1/* SPDX-License-Identifier: GPL-2.0 */
  2#ifndef _M68KNOMMU_IO_H
  3#define _M68KNOMMU_IO_H
  4
  5/*
  6 * Convert a physical memory address into a IO memory address.
  7 * For us this is trivially a type cast.
  8 */
  9#define iomem(a)	((void __iomem *) (a))
 10
 11/*
 12 * The non-MMU m68k and ColdFire IO and memory mapped hardware access
 13 * functions have always worked in CPU native endian. We need to define
 14 * that behavior here first before we include asm-generic/io.h.
 15 */
 16#define __raw_readb(addr) \
 17    ({ u8 __v = (*(__force volatile u8 *) (addr)); __v; })
 18#define __raw_readw(addr) \
 19    ({ u16 __v = (*(__force volatile u16 *) (addr)); __v; })
 20#define __raw_readl(addr) \
 21    ({ u32 __v = (*(__force volatile u32 *) (addr)); __v; })
 22
 23#define __raw_writeb(b, addr) (void)((*(__force volatile u8 *) (addr)) = (b))
 24#define __raw_writew(b, addr) (void)((*(__force volatile u16 *) (addr)) = (b))
 25#define __raw_writel(b, addr) (void)((*(__force volatile u32 *) (addr)) = (b))
 26
 27#if defined(CONFIG_COLDFIRE)
 28/*
 29 * For ColdFire platforms we may need to do some extra checks for what
 30 * type of address range we are accessing. Include the ColdFire platform
 31 * definitions so we can figure out if need to do something special.
 32 */
 33#include <asm/byteorder.h>
 34#include <asm/coldfire.h>
 35#include <asm/mcfsim.h>
 36#endif /* CONFIG_COLDFIRE */
 
 
 
 
 37
 38#if defined(IOMEMBASE)
 39/*
 40 * The ColdFire SoC internal peripherals are mapped into virtual address
 41 * space using the ACR registers of the cache control unit. This means we
 42 * are using a 1:1 physical:virtual mapping for them. We can quickly
 43 * determine if we are accessing an internal peripheral device given the
 44 * physical or vitrual address using the same range check. This check logic
 45 * applies just the same of there is no MMU but something like a PCI bus
 46 * is present.
 47 */
 48static int __cf_internalio(unsigned long addr)
 49{
 50	return (addr >= IOMEMBASE) && (addr <= IOMEMBASE + IOMEMSIZE - 1);
 51}
 52
 53static int cf_internalio(const volatile void __iomem *addr)
 54{
 55	return __cf_internalio((unsigned long) addr);
 56}
 57
 58/*
 59 * We need to treat built-in peripherals and bus based address ranges
 60 * differently. Local built-in peripherals (and the ColdFire SoC parts
 61 * have quite a lot of them) are always native endian - which is big
 62 * endian on m68k/ColdFire. Bus based address ranges, like the PCI bus,
 63 * are accessed little endian - so we need to byte swap those.
 64 */
 65#define readw readw
 66static inline u16 readw(const volatile void __iomem *addr)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 67{
 68	if (cf_internalio(addr))
 69		return __raw_readw(addr);
 70	return swab16(__raw_readw(addr));
 
 71}
 72
 73#define readl readl
 74static inline u32 readl(const volatile void __iomem *addr)
 75{
 76	if (cf_internalio(addr))
 77		return __raw_readl(addr);
 78	return swab32(__raw_readl(addr));
 
 79}
 80
 81#define writew writew
 82static inline void writew(u16 value, volatile void __iomem *addr)
 83{
 84	if (cf_internalio(addr))
 85		__raw_writew(value, addr);
 86	else
 87		__raw_writew(swab16(value), addr);
 88}
 89
 90#define writel writel
 91static inline void writel(u32 value, volatile void __iomem *addr)
 92{
 93	if (cf_internalio(addr))
 94		__raw_writel(value, addr);
 95	else
 96		__raw_writel(swab32(value), addr);
 97}
 98
 99#else
 
 
 
 
 
 
100
101#define readb __raw_readb
102#define readw __raw_readw
103#define readl __raw_readl
104#define writeb __raw_writeb
105#define writew __raw_writew
106#define writel __raw_writel
 
107
108#endif /* IOMEMBASE */
109
110#if defined(CONFIG_PCI)
111/*
112 * Support for PCI bus access uses the asm-generic access functions.
113 * We need to supply the base address and masks for the normal memory
114 * and IO address space mappings.
115 */
116#define PCI_MEM_PA	0xf0000000		/* Host physical address */
117#define PCI_MEM_BA	0xf0000000		/* Bus physical address */
118#define PCI_MEM_SIZE	0x08000000		/* 128 MB */
119#define PCI_MEM_MASK	(PCI_MEM_SIZE - 1)
120
121#define PCI_IO_PA	0xf8000000		/* Host physical address */
122#define PCI_IO_BA	0x00000000		/* Bus physical address */
123#define PCI_IO_SIZE	0x00010000		/* 64k */
124#define PCI_IO_MASK	(PCI_IO_SIZE - 1)
125
126#define HAVE_ARCH_PIO_SIZE
127#define PIO_OFFSET	0
128#define PIO_MASK	0xffff
129#define PIO_RESERVED	0x10000
130#define PCI_IOBASE	((void __iomem *) PCI_IO_PA)
131#define PCI_SPACE_LIMIT	PCI_IO_MASK
132#endif /* CONFIG_PCI */
133
134#include <asm/kmap.h>
135#include <asm/virtconvert.h>
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
136
137#endif /* _M68KNOMMU_IO_H */

 
  1#ifndef _M68KNOMMU_IO_H
  2#define _M68KNOMMU_IO_H
  3
  4#ifdef __KERNEL__
 
 
 
 
  5
  6#include <asm/virtconvert.h>
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  7
 
  8/*
  9 * These are for ISA/PCI shared memory _only_ and should never be used
 10 * on any other type of memory, including Zorro memory. They are meant to
 11 * access the bus in the bus byte order which is little-endian!.
 12 *
 13 * readX/writeX() are used to access memory mapped devices. On some
 14 * architectures the memory mapped IO stuff needs to be accessed
 15 * differently. On the m68k architecture, we just read/write the
 16 * memory location directly.
 17 */
 18/* ++roman: The assignments to temp. vars avoid that gcc sometimes generates
 19 * two accesses to memory, which may be undesirable for some devices.
 20 */
 21
 
 22/*
 23 * swap functions are sometimes needed to interface little-endian hardware
 
 
 
 
 
 
 24 */
 25static inline unsigned short _swapw(volatile unsigned short v)
 26{
 27    return ((v << 8) | (v >> 8));
 28}
 29
 30static inline unsigned int _swapl(volatile unsigned long v)
 31{
 32    return ((v << 24) | ((v & 0xff00) << 8) | ((v & 0xff0000) >> 8) | (v >> 24));
 33}
 34
 35#define readb(addr) \
 36    ({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; })
 37#define readw(addr) \
 38    ({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; })
 39#define readl(addr) \
 40    ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
 41
 42#define readb_relaxed(addr) readb(addr)
 43#define readw_relaxed(addr) readw(addr)
 44#define readl_relaxed(addr) readl(addr)
 45
 46#define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b))
 47#define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b))
 48#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b))
 49
 50#define __raw_readb readb
 51#define __raw_readw readw
 52#define __raw_readl readl
 53#define __raw_writeb writeb
 54#define __raw_writew writew
 55#define __raw_writel writel
 56
 57static inline void io_outsb(unsigned int addr, void *buf, int len)
 58{
 59	volatile unsigned char *ap = (volatile unsigned char *) addr;
 60	unsigned char *bp = (unsigned char *) buf;
 61	while (len--)
 62		*ap = *bp++;
 63}
 64
 65static inline void io_outsw(unsigned int addr, void *buf, int len)
 
 66{
 67	volatile unsigned short *ap = (volatile unsigned short *) addr;
 68	unsigned short *bp = (unsigned short *) buf;
 69	while (len--)
 70		*ap = _swapw(*bp++);
 71}
 72
 73static inline void io_outsl(unsigned int addr, void *buf, int len)
 
 74{
 75	volatile unsigned int *ap = (volatile unsigned int *) addr;
 76	unsigned int *bp = (unsigned int *) buf;
 77	while (len--)
 78		*ap = _swapl(*bp++);
 79}
 80
 81static inline void io_insb(unsigned int addr, void *buf, int len)
 
 82{
 83	volatile unsigned char *ap = (volatile unsigned char *) addr;
 84	unsigned char *bp = (unsigned char *) buf;
 85	while (len--)
 86		*bp++ = *ap;
 87}
 88
 89static inline void io_insw(unsigned int addr, void *buf, int len)
 90{
 91	volatile unsigned short *ap = (volatile unsigned short *) addr;
 92	unsigned short *bp = (unsigned short *) buf;
 93	while (len--)
 94		*bp++ = _swapw(*ap);
 95}
 96
 97static inline void io_insl(unsigned int addr, void *buf, int len)
 98{
 99	volatile unsigned int *ap = (volatile unsigned int *) addr;
100	unsigned int *bp = (unsigned int *) buf;
101	while (len--)
102		*bp++ = _swapl(*ap);
103}
104
105#define mmiowb()
106
 
107/*
108 *	make the short names macros so specific devices
109 *	can override them as required
110 */
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
111
112#define memset_io(a,b,c)	memset((void *)(a),(b),(c))
113#define memcpy_fromio(a,b,c)	memcpy((a),(void *)(b),(c))
114#define memcpy_toio(a,b,c)	memcpy((void *)(a),(b),(c))
115
116#define inb(addr)    readb(addr)
117#define inw(addr)    readw(addr)
118#define inl(addr)    readl(addr)
119#define outb(x,addr) ((void) writeb(x,addr))
120#define outw(x,addr) ((void) writew(x,addr))
121#define outl(x,addr) ((void) writel(x,addr))
122
123#define inb_p(addr)    inb(addr)
124#define inw_p(addr)    inw(addr)
125#define inl_p(addr)    inl(addr)
126#define outb_p(x,addr) outb(x,addr)
127#define outw_p(x,addr) outw(x,addr)
128#define outl_p(x,addr) outl(x,addr)
129
130#define outsb(a,b,l) io_outsb(a,b,l)
131#define outsw(a,b,l) io_outsw(a,b,l)
132#define outsl(a,b,l) io_outsl(a,b,l)
133
134#define insb(a,b,l) io_insb(a,b,l)
135#define insw(a,b,l) io_insw(a,b,l)
136#define insl(a,b,l) io_insl(a,b,l)
137
138#define IO_SPACE_LIMIT 0xffffffff
139
140
141/* Values for nocacheflag and cmode */
142#define IOMAP_FULL_CACHING		0
143#define IOMAP_NOCACHE_SER		1
144#define IOMAP_NOCACHE_NONSER		2
145#define IOMAP_WRITETHROUGH		3
146
147static inline void *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag)
148{
149	return (void *) physaddr;
150}
151static inline void *ioremap(unsigned long physaddr, unsigned long size)
152{
153	return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
154}
155static inline void *ioremap_nocache(unsigned long physaddr, unsigned long size)
156{
157	return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
158}
159static inline void *ioremap_writethrough(unsigned long physaddr, unsigned long size)
160{
161	return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
162}
163static inline void *ioremap_fullcache(unsigned long physaddr, unsigned long size)
164{
165	return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
166}
167
168#define	iounmap(addr)	do { } while(0)
169
170/*
171 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
172 * access
173 */
174#define xlate_dev_mem_ptr(p)	__va(p)
175
176/*
177 * Convert a virtual cached pointer to an uncached pointer
178 */
179#define xlate_dev_kmem_ptr(p)	p
180
181#endif /* __KERNEL__ */
182
183#endif /* _M68KNOMMU_IO_H */