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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2002 ARM Ltd.
4 * Copyright (C) 2008 STMicroelctronics.
5 * Copyright (C) 2009 ST-Ericsson.
6 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
7 *
8 * This file is based on arm realview platform
9 */
10#include <linux/init.h>
11#include <linux/errno.h>
12#include <linux/delay.h>
13#include <linux/device.h>
14#include <linux/smp.h>
15#include <linux/io.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18
19#include <asm/cacheflush.h>
20#include <asm/smp_plat.h>
21#include <asm/smp_scu.h>
22
23/* Magic triggers in backup RAM */
24#define UX500_CPU1_JUMPADDR_OFFSET 0x1FF4
25#define UX500_CPU1_WAKEMAGIC_OFFSET 0x1FF0
26
27static void __iomem *backupram;
28
29static void __init ux500_smp_prepare_cpus(unsigned int max_cpus)
30{
31 struct device_node *np;
32 static void __iomem *scu_base;
33 unsigned int ncores;
34 int i;
35
36 np = of_find_compatible_node(NULL, NULL, "ste,dbx500-backupram");
37 if (!np) {
38 pr_err("No backupram base address\n");
39 return;
40 }
41 backupram = of_iomap(np, 0);
42 of_node_put(np);
43 if (!backupram) {
44 pr_err("No backupram remap\n");
45 return;
46 }
47
48 np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
49 if (!np) {
50 pr_err("No SCU base address\n");
51 return;
52 }
53 scu_base = of_iomap(np, 0);
54 of_node_put(np);
55 if (!scu_base) {
56 pr_err("No SCU remap\n");
57 return;
58 }
59
60 scu_enable(scu_base);
61 ncores = scu_get_core_count(scu_base);
62 for (i = 0; i < ncores; i++)
63 set_cpu_possible(i, true);
64 iounmap(scu_base);
65}
66
67static int ux500_boot_secondary(unsigned int cpu, struct task_struct *idle)
68{
69 /*
70 * write the address of secondary startup into the backup ram register
71 * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the
72 * backup ram register at offset 0x1FF0, which is what boot rom code
73 * is waiting for. This will wake up the secondary core from WFE.
74 */
75 writel(__pa_symbol(secondary_startup),
76 backupram + UX500_CPU1_JUMPADDR_OFFSET);
77 writel(0xA1FEED01,
78 backupram + UX500_CPU1_WAKEMAGIC_OFFSET);
79
80 /* make sure write buffer is drained */
81 mb();
82 arch_send_wakeup_ipi_mask(cpumask_of(cpu));
83 return 0;
84}
85
86#ifdef CONFIG_HOTPLUG_CPU
87static void ux500_cpu_die(unsigned int cpu)
88{
89 wfi();
90}
91#endif
92
93static const struct smp_operations ux500_smp_ops __initconst = {
94 .smp_prepare_cpus = ux500_smp_prepare_cpus,
95 .smp_boot_secondary = ux500_boot_secondary,
96#ifdef CONFIG_HOTPLUG_CPU
97 .cpu_die = ux500_cpu_die,
98#endif
99};
100CPU_METHOD_OF_DECLARE(ux500_smp, "ste,dbx500-smp", &ux500_smp_ops);
1/*
2 * Copyright (C) 2002 ARM Ltd.
3 * Copyright (C) 2008 STMicroelctronics.
4 * Copyright (C) 2009 ST-Ericsson.
5 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
6 *
7 * This file is based on arm realview platform
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#include <linux/init.h>
14#include <linux/errno.h>
15#include <linux/delay.h>
16#include <linux/device.h>
17#include <linux/smp.h>
18#include <linux/io.h>
19
20#include <asm/cacheflush.h>
21#include <asm/hardware/gic.h>
22#include <asm/smp_scu.h>
23#include <mach/hardware.h>
24#include <mach/setup.h>
25
26/* This is called from headsmp.S to wakeup the secondary core */
27extern void u8500_secondary_startup(void);
28
29/*
30 * control for which core is the next to come out of the secondary
31 * boot "holding pen"
32 */
33volatile int pen_release = -1;
34
35/*
36 * Write pen_release in a way that is guaranteed to be visible to all
37 * observers, irrespective of whether they're taking part in coherency
38 * or not. This is necessary for the hotplug code to work reliably.
39 */
40static void write_pen_release(int val)
41{
42 pen_release = val;
43 smp_wmb();
44 __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
45 outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
46}
47
48static void __iomem *scu_base_addr(void)
49{
50 if (cpu_is_u5500())
51 return __io_address(U5500_SCU_BASE);
52 else if (cpu_is_u8500())
53 return __io_address(U8500_SCU_BASE);
54 else
55 ux500_unknown_soc();
56
57 return NULL;
58}
59
60static DEFINE_SPINLOCK(boot_lock);
61
62void __cpuinit platform_secondary_init(unsigned int cpu)
63{
64 /*
65 * if any interrupts are already enabled for the primary
66 * core (e.g. timer irq), then they will not have been enabled
67 * for us: do so
68 */
69 gic_secondary_init(0);
70
71 /*
72 * let the primary processor know we're out of the
73 * pen, then head off into the C entry point
74 */
75 write_pen_release(-1);
76
77 /*
78 * Synchronise with the boot thread.
79 */
80 spin_lock(&boot_lock);
81 spin_unlock(&boot_lock);
82}
83
84int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
85{
86 unsigned long timeout;
87
88 /*
89 * set synchronisation state between this boot processor
90 * and the secondary one
91 */
92 spin_lock(&boot_lock);
93
94 /*
95 * The secondary processor is waiting to be released from
96 * the holding pen - release it, then wait for it to flag
97 * that it has been released by resetting pen_release.
98 */
99 write_pen_release(cpu);
100
101 gic_raise_softirq(cpumask_of(cpu), 1);
102
103 timeout = jiffies + (1 * HZ);
104 while (time_before(jiffies, timeout)) {
105 if (pen_release == -1)
106 break;
107 }
108
109 /*
110 * now the secondary core is starting up let it run its
111 * calibrations, then wait for it to finish
112 */
113 spin_unlock(&boot_lock);
114
115 return pen_release != -1 ? -ENOSYS : 0;
116}
117
118static void __init wakeup_secondary(void)
119{
120 void __iomem *backupram;
121
122 if (cpu_is_u5500())
123 backupram = __io_address(U5500_BACKUPRAM0_BASE);
124 else if (cpu_is_u8500())
125 backupram = __io_address(U8500_BACKUPRAM0_BASE);
126 else
127 ux500_unknown_soc();
128
129 /*
130 * write the address of secondary startup into the backup ram register
131 * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the
132 * backup ram register at offset 0x1FF0, which is what boot rom code
133 * is waiting for. This would wake up the secondary core from WFE
134 */
135#define UX500_CPU1_JUMPADDR_OFFSET 0x1FF4
136 __raw_writel(virt_to_phys(u8500_secondary_startup),
137 backupram + UX500_CPU1_JUMPADDR_OFFSET);
138
139#define UX500_CPU1_WAKEMAGIC_OFFSET 0x1FF0
140 __raw_writel(0xA1FEED01,
141 backupram + UX500_CPU1_WAKEMAGIC_OFFSET);
142
143 /* make sure write buffer is drained */
144 mb();
145}
146
147/*
148 * Initialise the CPU possible map early - this describes the CPUs
149 * which may be present or become present in the system.
150 */
151void __init smp_init_cpus(void)
152{
153 void __iomem *scu_base = scu_base_addr();
154 unsigned int i, ncores;
155
156 ncores = scu_base ? scu_get_core_count(scu_base) : 1;
157
158 /* sanity check */
159 if (ncores > NR_CPUS) {
160 printk(KERN_WARNING
161 "U8500: no. of cores (%d) greater than configured "
162 "maximum of %d - clipping\n",
163 ncores, NR_CPUS);
164 ncores = NR_CPUS;
165 }
166
167 for (i = 0; i < ncores; i++)
168 set_cpu_possible(i, true);
169
170 set_smp_cross_call(gic_raise_softirq);
171}
172
173void __init platform_smp_prepare_cpus(unsigned int max_cpus)
174{
175
176 scu_enable(scu_base_addr());
177 wakeup_secondary();
178}