1/*
  2 * Copyright (C) ST-Ericsson SA 2010
  3 *
  4 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
  5 * License terms: GNU General Public License (GPL) version 2
  6 */
  7
  8#include <linux/platform_device.h>
  9#include <linux/io.h>
 10#include <linux/clk.h>
 11#include <linux/mfd/db8500-prcmu.h>
 12#include <linux/mfd/db5500-prcmu.h>
 13
 14#include <asm/cacheflush.h>
 15#include <asm/hardware/cache-l2x0.h>
 16#include <asm/hardware/gic.h>
 17#include <asm/mach/map.h>
 18#include <asm/localtimer.h>
 19
 20#include <plat/mtu.h>
 21#include <mach/hardware.h>
 22#include <mach/setup.h>
 23#include <mach/devices.h>
 24
 25#include "clock.h"
 26
 27void __iomem *_PRCMU_BASE;
 28
 29#ifdef CONFIG_CACHE_L2X0
 30static void __iomem *l2x0_base;
 31#endif
 32
 33void __init ux500_init_irq(void)
 34{
 35	void __iomem *dist_base;
 36	void __iomem *cpu_base;
 37
 38	if (cpu_is_u5500()) {
 39		dist_base = __io_address(U5500_GIC_DIST_BASE);
 40		cpu_base = __io_address(U5500_GIC_CPU_BASE);
 41	} else if (cpu_is_u8500()) {
 42		dist_base = __io_address(U8500_GIC_DIST_BASE);
 43		cpu_base = __io_address(U8500_GIC_CPU_BASE);
 44	} else
 45		ux500_unknown_soc();
 46
 47	gic_init(0, 29, dist_base, cpu_base);
 48
 49	/*
 50	 * Init clocks here so that they are available for system timer
 51	 * initialization.
 52	 */
 53	if (cpu_is_u5500())
 54		db5500_prcmu_early_init();
 55	if (cpu_is_u8500())
 56		prcmu_early_init();
 57	clk_init();
 58}
 59
 60#ifdef CONFIG_CACHE_L2X0
 61static inline void ux500_cache_wait(void __iomem *reg, unsigned long mask)
 62{
 63	/* wait for the operation to complete */
 64	while (readl_relaxed(reg) & mask)
 65		;
 66}
 67
 68static inline void ux500_cache_sync(void)
 69{
 70	void __iomem *base = l2x0_base;
 71
 72	writel_relaxed(0, base + L2X0_CACHE_SYNC);
 73	ux500_cache_wait(base + L2X0_CACHE_SYNC, 1);
 74}
 75
 76/*
 77 * The L2 cache cannot be turned off in the non-secure world.
 78 * Dummy until a secure service is in place.
 79 */
 80static void ux500_l2x0_disable(void)
 81{
 82}
 83
 84/*
 85 * This is only called when doing a kexec, just after turning off the L2
 86 * and L1 cache, and it is surrounded by a spinlock in the generic version.
 87 * However, we're not really turning off the L2 cache right now and the
 88 * PL310 does not support exclusive accesses (used to implement the spinlock).
 89 * So, the invalidation needs to be done without the spinlock.
 90 */
 91static void ux500_l2x0_inv_all(void)
 92{
 93	void __iomem *base = l2x0_base;
 94	uint32_t l2x0_way_mask = (1<<16) - 1;	/* Bitmask of active ways */
 95
 96	/* invalidate all ways */
 97	writel_relaxed(l2x0_way_mask, base + L2X0_INV_WAY);
 98	ux500_cache_wait(base + L2X0_INV_WAY, l2x0_way_mask);
 99	ux500_cache_sync();
100}
101
102static int ux500_l2x0_init(void)
103{
104	if (cpu_is_u5500())
105		l2x0_base = __io_address(U5500_L2CC_BASE);
106	else if (cpu_is_u8500())
107		l2x0_base = __io_address(U8500_L2CC_BASE);
108	else
109		ux500_unknown_soc();
110
111	/* 64KB way size, 8 way associativity, force WA */
112	l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);
113
114	/* Override invalidate function */
115	outer_cache.disable = ux500_l2x0_disable;
116	outer_cache.inv_all = ux500_l2x0_inv_all;
117
118	return 0;
119}
120early_initcall(ux500_l2x0_init);
121#endif
122
123static void __init ux500_timer_init(void)
124{
125#ifdef CONFIG_LOCAL_TIMERS
126	/* Setup the local timer base */
127	if (cpu_is_u5500())
128		twd_base = __io_address(U5500_TWD_BASE);
129	else if (cpu_is_u8500())
130		twd_base = __io_address(U8500_TWD_BASE);
131	else
132		ux500_unknown_soc();
133#endif
134	if (cpu_is_u5500())
135		mtu_base = __io_address(U5500_MTU0_BASE);
136	else if (cpu_is_u8500ed())
137		mtu_base = __io_address(U8500_MTU0_BASE_ED);
138	else if (cpu_is_u8500())
139		mtu_base = __io_address(U8500_MTU0_BASE);
140	else
141		ux500_unknown_soc();
142
143	nmdk_timer_init();
144}
145
146struct sys_timer ux500_timer = {
147	.init	= ux500_timer_init,
148};