1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * NVIDIA Tegra SoC device tree board support
  4 *
  5 * Copyright (C) 2011, 2013, NVIDIA Corporation
  6 * Copyright (C) 2010 Secret Lab Technologies, Ltd.
  7 * Copyright (C) 2010 Google, Inc.
  8 */
  9
 10#include <linux/clk.h>
 11#include <linux/clk/tegra.h>
 12#include <linux/dma-mapping.h>
 13#include <linux/init.h>
 14#include <linux/io.h>
 15#include <linux/irqchip.h>
 16#include <linux/irqdomain.h>
 17#include <linux/kernel.h>
 18#include <linux/of_address.h>
 19#include <linux/of_fdt.h>
 20#include <linux/of.h>
 21#include <linux/of_platform.h>
 22#include <linux/platform_device.h>
 23#include <linux/serial_8250.h>
 24#include <linux/slab.h>
 25#include <linux/sys_soc.h>
 26#include <linux/usb/tegra_usb_phy.h>
 27
 28#include <linux/firmware/trusted_foundations.h>
 29
 30#include <soc/tegra/fuse.h>
 31#include <soc/tegra/pmc.h>
 32
 33#include <asm/firmware.h>
 34#include <asm/hardware/cache-l2x0.h>
 35#include <asm/mach/arch.h>
 36#include <asm/mach/time.h>
 37#include <asm/mach-types.h>
 38#include <asm/psci.h>
 39#include <asm/setup.h>
 40
 41#include "board.h"
 42#include "common.h"
 43#include "iomap.h"
 44#include "pm.h"
 45#include "reset.h"
 46#include "sleep.h"
 47
 48/*
 49 * Storage for debug-macro.S's state.
 50 *
 51 * This must be in .data not .bss so that it gets initialized each time the
 52 * kernel is loaded. The data is declared here rather than debug-macro.S so
 53 * that multiple inclusions of debug-macro.S point at the same data.
 54 */
 55u32 tegra_uart_config[3] = {
 56	/* Debug UART initialization required */
 57	1,
 58	/* Debug UART physical address */
 59	0,
 60	/* Debug UART virtual address */
 61	0,
 62};
 63
 64static void __init tegra_init_early(void)
 65{
 66	of_register_trusted_foundations();
 67	tegra_cpu_reset_handler_init();
 68	call_firmware_op(l2x0_init);
 69}
 70
 71static void __init tegra_dt_init_irq(void)
 72{
 73	tegra_init_irq();
 74	irqchip_init();
 75}
 76
 77static void __init tegra_dt_init(void)
 78{
 79	struct device *parent = tegra_soc_device_register();
 80
 81	of_platform_default_populate(NULL, NULL, parent);
 82}
 83
 84static void __init tegra_dt_init_late(void)
 85{
 86	if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) &&
 87	    of_machine_is_compatible("compal,paz00"))
 88		tegra_paz00_wifikill_init();
 89
 90	if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) &&
 91	    of_machine_is_compatible("nvidia,tegra20"))
 92		platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0);
 93
 94	if (IS_ENABLED(CONFIG_ARM_TEGRA_CPUIDLE) && !psci_smp_available())
 95		platform_device_register_simple("tegra-cpuidle", -1, NULL, 0);
 96
 97	if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) &&
 98	    of_machine_is_compatible("nvidia,tegra30"))
 99		platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0);
100}
101
102static const char * const tegra_dt_board_compat[] = {
103	"nvidia,tegra124",
104	"nvidia,tegra114",
105	"nvidia,tegra30",
106	"nvidia,tegra20",
107	NULL
108};
109
110DT_MACHINE_START(TEGRA_DT, "NVIDIA Tegra SoC (Flattened Device Tree)")
111	.l2c_aux_val	= 0x3c400000,
112	.l2c_aux_mask	= 0xc20fc3ff,
113	.smp		= smp_ops(tegra_smp_ops),
114	.map_io		= tegra_map_common_io,
115	.init_early	= tegra_init_early,
116	.init_irq	= tegra_dt_init_irq,
117	.init_machine	= tegra_dt_init,
118	.init_late	= tegra_dt_init_late,
119	.dt_compat	= tegra_dt_board_compat,
120MACHINE_END