1// SPDX-License-Identifier: GPL-2.0-only
 2/*
 3 * OMAP3 Voltage Controller (VC) data
 4 *
 5 * Copyright (C) 2007, 2010 Texas Instruments, Inc.
 6 * Rajendra Nayak <rnayak@ti.com>
 7 * Lesly A M <x0080970@ti.com>
 8 * Thara Gopinath <thara@ti.com>
 9 *
10 * Copyright (C) 2008, 2011 Nokia Corporation
11 * Kalle Jokiniemi
12 * Paul Walmsley
 
 
 
 
13 */
14#include <linux/io.h>
15#include <linux/err.h>
16#include <linux/init.h>
17
18#include "common.h"
19
20#include "prm-regbits-34xx.h"
21#include "voltage.h"
22
23#include "vc.h"
24
25/*
26 * VC data common to 34xx/36xx chips
27 * XXX This stuff presumably belongs in the vc3xxx.c or vc.c file.
28 */
29static struct omap_vc_common omap3_vc_common = {
 
 
30	.bypass_val_reg	 = OMAP3_PRM_VC_BYPASS_VAL_OFFSET,
31	.data_shift	 = OMAP3430_DATA_SHIFT,
32	.slaveaddr_shift = OMAP3430_SLAVEADDR_SHIFT,
33	.regaddr_shift	 = OMAP3430_REGADDR_SHIFT,
34	.valid		 = OMAP3430_VALID_MASK,
35	.cmd_on_shift	 = OMAP3430_VC_CMD_ON_SHIFT,
36	.cmd_on_mask	 = OMAP3430_VC_CMD_ON_MASK,
37	.cmd_onlp_shift	 = OMAP3430_VC_CMD_ONLP_SHIFT,
38	.cmd_ret_shift	 = OMAP3430_VC_CMD_RET_SHIFT,
39	.cmd_off_shift	 = OMAP3430_VC_CMD_OFF_SHIFT,
40	.i2c_cfg_clear_mask = OMAP3430_SREN_MASK | OMAP3430_HSEN_MASK,
41	.i2c_cfg_hsen_mask = OMAP3430_HSEN_MASK,
42	.i2c_cfg_reg	 = OMAP3_PRM_VC_I2C_CFG_OFFSET,
43	.i2c_mcode_mask	 = OMAP3430_MCODE_MASK,
44};
45
46struct omap_vc_channel omap3_vc_mpu = {
47	.flags = OMAP_VC_CHANNEL_DEFAULT,
48	.common = &omap3_vc_common,
49	.smps_sa_reg	 = OMAP3_PRM_VC_SMPS_SA_OFFSET,
50	.smps_volra_reg	 = OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET,
51	.smps_cmdra_reg	 = OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET,
52	.cfg_channel_reg = OMAP3_PRM_VC_CH_CONF_OFFSET,
53	.cmdval_reg = OMAP3_PRM_VC_CMD_VAL_0_OFFSET,
 
54	.smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA0_MASK,
 
55	.smps_volra_mask = OMAP3430_VOLRA0_MASK,
56	.smps_cmdra_mask = OMAP3430_CMDRA0_MASK,
57	.cfg_channel_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT,
58};
59
60struct omap_vc_channel omap3_vc_core = {
61	.common = &omap3_vc_common,
62	.smps_sa_reg	 = OMAP3_PRM_VC_SMPS_SA_OFFSET,
63	.smps_volra_reg	 = OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET,
64	.smps_cmdra_reg	 = OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET,
65	.cfg_channel_reg = OMAP3_PRM_VC_CH_CONF_OFFSET,
66	.cmdval_reg = OMAP3_PRM_VC_CMD_VAL_1_OFFSET,
 
67	.smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA1_MASK,
 
68	.smps_volra_mask = OMAP3430_VOLRA1_MASK,
69	.smps_cmdra_mask = OMAP3430_CMDRA1_MASK,
70	.cfg_channel_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT,
71};
72
73/*
74 * Voltage levels for different operating modes: on, sleep, retention and off
75 */
76#define OMAP3_ON_VOLTAGE_UV		1200000
77#define OMAP3_ONLP_VOLTAGE_UV		1000000
78#define OMAP3_RET_VOLTAGE_UV		975000
79#define OMAP3_OFF_VOLTAGE_UV		600000
80
81struct omap_vc_param omap3_mpu_vc_data = {
82	.on		= OMAP3_ON_VOLTAGE_UV,
83	.onlp		= OMAP3_ONLP_VOLTAGE_UV,
84	.ret		= OMAP3_RET_VOLTAGE_UV,
85	.off		= OMAP3_OFF_VOLTAGE_UV,
86};
87
88struct omap_vc_param omap3_core_vc_data = {
89	.on		= OMAP3_ON_VOLTAGE_UV,
90	.onlp		= OMAP3_ONLP_VOLTAGE_UV,
91	.ret		= OMAP3_RET_VOLTAGE_UV,
92	.off		= OMAP3_OFF_VOLTAGE_UV,
93};

 
 1/*
 2 * OMAP3 Voltage Controller (VC) data
 3 *
 4 * Copyright (C) 2007, 2010 Texas Instruments, Inc.
 5 * Rajendra Nayak <rnayak@ti.com>
 6 * Lesly A M <x0080970@ti.com>
 7 * Thara Gopinath <thara@ti.com>
 8 *
 9 * Copyright (C) 2008, 2011 Nokia Corporation
10 * Kalle Jokiniemi
11 * Paul Walmsley
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17#include <linux/io.h>
18#include <linux/err.h>
19#include <linux/init.h>
20
21#include <plat/common.h>
22
23#include "prm-regbits-34xx.h"
24#include "voltage.h"
25
26#include "vc.h"
27
28/*
29 * VC data common to 34xx/36xx chips
30 * XXX This stuff presumably belongs in the vc3xxx.c or vc.c file.
31 */
32static struct omap_vc_common_data omap3_vc_common = {
33	.smps_sa_reg	 = OMAP3_PRM_VC_SMPS_SA_OFFSET,
34	.smps_volra_reg	 = OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET,
35	.bypass_val_reg	 = OMAP3_PRM_VC_BYPASS_VAL_OFFSET,
36	.data_shift	 = OMAP3430_DATA_SHIFT,
37	.slaveaddr_shift = OMAP3430_SLAVEADDR_SHIFT,
38	.regaddr_shift	 = OMAP3430_REGADDR_SHIFT,
39	.valid		 = OMAP3430_VALID_MASK,
40	.cmd_on_shift	 = OMAP3430_VC_CMD_ON_SHIFT,
41	.cmd_on_mask	 = OMAP3430_VC_CMD_ON_MASK,
42	.cmd_onlp_shift	 = OMAP3430_VC_CMD_ONLP_SHIFT,
43	.cmd_ret_shift	 = OMAP3430_VC_CMD_RET_SHIFT,
44	.cmd_off_shift	 = OMAP3430_VC_CMD_OFF_SHIFT,
 
 
 
 
45};
46
47struct omap_vc_instance_data omap3_vc1_data = {
48	.vc_common = &omap3_vc_common,
 
 
 
 
 
49	.cmdval_reg = OMAP3_PRM_VC_CMD_VAL_0_OFFSET,
50	.smps_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT,
51	.smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA0_MASK,
52	.smps_volra_shift = OMAP3430_VOLRA0_SHIFT,
53	.smps_volra_mask = OMAP3430_VOLRA0_MASK,
 
 
54};
55
56struct omap_vc_instance_data omap3_vc2_data = {
57	.vc_common = &omap3_vc_common,
 
 
 
 
58	.cmdval_reg = OMAP3_PRM_VC_CMD_VAL_1_OFFSET,
59	.smps_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT,
60	.smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA1_MASK,
61	.smps_volra_shift = OMAP3430_VOLRA1_SHIFT,
62	.smps_volra_mask = OMAP3430_VOLRA1_MASK,
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
63};