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1/*
2 * OMAP Smartreflex Defines and Routines
3 *
4 * Author: Thara Gopinath <thara@ti.com>
5 *
6 * Copyright (C) 2010 Texas Instruments, Inc.
7 * Thara Gopinath <thara@ti.com>
8 *
9 * Copyright (C) 2008 Nokia Corporation
10 * Kalle Jokiniemi
11 *
12 * Copyright (C) 2007 Texas Instruments, Inc.
13 * Lesly A M <x0080970@ti.com>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#ifndef __ASM_ARM_OMAP_SMARTREFLEX_H
21#define __ASM_ARM_OMAP_SMARTREFLEX_H
22
23#include <linux/platform_device.h>
24
25#include "voltage.h"
26
27/*
28 * Different Smartreflex IPs version. The v1 is the 65nm version used in
29 * OMAP3430. The v2 is the update for the 45nm version of the IP
30 * used in OMAP3630 and OMAP4430
31 */
32#define SR_TYPE_V1 1
33#define SR_TYPE_V2 2
34
35/* SMART REFLEX REG ADDRESS OFFSET */
36#define SRCONFIG 0x00
37#define SRSTATUS 0x04
38#define SENVAL 0x08
39#define SENMIN 0x0C
40#define SENMAX 0x10
41#define SENAVG 0x14
42#define AVGWEIGHT 0x18
43#define NVALUERECIPROCAL 0x1c
44#define SENERROR_V1 0x20
45#define ERRCONFIG_V1 0x24
46#define IRQ_EOI 0x20
47#define IRQSTATUS_RAW 0x24
48#define IRQSTATUS 0x28
49#define IRQENABLE_SET 0x2C
50#define IRQENABLE_CLR 0x30
51#define SENERROR_V2 0x34
52#define ERRCONFIG_V2 0x38
53
54/* Bit/Shift Positions */
55
56/* SRCONFIG */
57#define SRCONFIG_ACCUMDATA_SHIFT 22
58#define SRCONFIG_SRCLKLENGTH_SHIFT 12
59#define SRCONFIG_SENNENABLE_V1_SHIFT 5
60#define SRCONFIG_SENPENABLE_V1_SHIFT 3
61#define SRCONFIG_SENNENABLE_V2_SHIFT 1
62#define SRCONFIG_SENPENABLE_V2_SHIFT 0
63#define SRCONFIG_CLKCTRL_SHIFT 0
64
65#define SRCONFIG_ACCUMDATA_MASK (0x3ff << 22)
66
67#define SRCONFIG_SRENABLE BIT(11)
68#define SRCONFIG_SENENABLE BIT(10)
69#define SRCONFIG_ERRGEN_EN BIT(9)
70#define SRCONFIG_MINMAXAVG_EN BIT(8)
71#define SRCONFIG_DELAYCTRL BIT(2)
72
73/* AVGWEIGHT */
74#define AVGWEIGHT_SENPAVGWEIGHT_SHIFT 2
75#define AVGWEIGHT_SENNAVGWEIGHT_SHIFT 0
76
77/* NVALUERECIPROCAL */
78#define NVALUERECIPROCAL_SENPGAIN_SHIFT 20
79#define NVALUERECIPROCAL_SENNGAIN_SHIFT 16
80#define NVALUERECIPROCAL_RNSENP_SHIFT 8
81#define NVALUERECIPROCAL_RNSENN_SHIFT 0
82
83/* ERRCONFIG */
84#define ERRCONFIG_ERRWEIGHT_SHIFT 16
85#define ERRCONFIG_ERRMAXLIMIT_SHIFT 8
86#define ERRCONFIG_ERRMINLIMIT_SHIFT 0
87
88#define SR_ERRWEIGHT_MASK (0x07 << 16)
89#define SR_ERRMAXLIMIT_MASK (0xff << 8)
90#define SR_ERRMINLIMIT_MASK (0xff << 0)
91
92#define ERRCONFIG_VPBOUNDINTEN_V1 BIT(31)
93#define ERRCONFIG_VPBOUNDINTST_V1 BIT(30)
94#define ERRCONFIG_MCUACCUMINTEN BIT(29)
95#define ERRCONFIG_MCUACCUMINTST BIT(28)
96#define ERRCONFIG_MCUVALIDINTEN BIT(27)
97#define ERRCONFIG_MCUVALIDINTST BIT(26)
98#define ERRCONFIG_MCUBOUNDINTEN BIT(25)
99#define ERRCONFIG_MCUBOUNDINTST BIT(24)
100#define ERRCONFIG_MCUDISACKINTEN BIT(23)
101#define ERRCONFIG_VPBOUNDINTST_V2 BIT(23)
102#define ERRCONFIG_MCUDISACKINTST BIT(22)
103#define ERRCONFIG_VPBOUNDINTEN_V2 BIT(22)
104
105#define ERRCONFIG_STATUS_V1_MASK (ERRCONFIG_VPBOUNDINTST_V1 | \
106 ERRCONFIG_MCUACCUMINTST | \
107 ERRCONFIG_MCUVALIDINTST | \
108 ERRCONFIG_MCUBOUNDINTST | \
109 ERRCONFIG_MCUDISACKINTST)
110/* IRQSTATUS */
111#define IRQSTATUS_MCUACCUMINT BIT(3)
112#define IRQSTATUS_MCVALIDINT BIT(2)
113#define IRQSTATUS_MCBOUNDSINT BIT(1)
114#define IRQSTATUS_MCUDISABLEACKINT BIT(0)
115
116/* IRQENABLE_SET and IRQENABLE_CLEAR */
117#define IRQENABLE_MCUACCUMINT BIT(3)
118#define IRQENABLE_MCUVALIDINT BIT(2)
119#define IRQENABLE_MCUBOUNDSINT BIT(1)
120#define IRQENABLE_MCUDISABLEACKINT BIT(0)
121
122/* Common Bit values */
123
124#define SRCLKLENGTH_12MHZ_SYSCLK 0x3c
125#define SRCLKLENGTH_13MHZ_SYSCLK 0x41
126#define SRCLKLENGTH_19MHZ_SYSCLK 0x60
127#define SRCLKLENGTH_26MHZ_SYSCLK 0x82
128#define SRCLKLENGTH_38MHZ_SYSCLK 0xC0
129
130/*
131 * 3430 specific values. Maybe these should be passed from board file or
132 * pmic structures.
133 */
134#define OMAP3430_SR_ACCUMDATA 0x1f4
135
136#define OMAP3430_SR1_SENPAVGWEIGHT 0x03
137#define OMAP3430_SR1_SENNAVGWEIGHT 0x03
138
139#define OMAP3430_SR2_SENPAVGWEIGHT 0x01
140#define OMAP3430_SR2_SENNAVGWEIGHT 0x01
141
142#define OMAP3430_SR_ERRWEIGHT 0x04
143#define OMAP3430_SR_ERRMAXLIMIT 0x02
144
145/**
146 * struct omap_sr_pmic_data - Strucutre to be populated by pmic code to pass
147 * pmic specific info to smartreflex driver
148 *
149 * @sr_pmic_init: API to initialize smartreflex on the PMIC side.
150 */
151struct omap_sr_pmic_data {
152 void (*sr_pmic_init) (void);
153};
154
155#ifdef CONFIG_OMAP_SMARTREFLEX
156/*
157 * The smart reflex driver supports CLASS1 CLASS2 and CLASS3 SR.
158 * The smartreflex class driver should pass the class type.
159 * Should be used to populate the class_type field of the
160 * omap_smartreflex_class_data structure.
161 */
162#define SR_CLASS1 0x1
163#define SR_CLASS2 0x2
164#define SR_CLASS3 0x3
165
166/**
167 * struct omap_sr_class_data - Smartreflex class driver info
168 *
169 * @enable: API to enable a particular class smaartreflex.
170 * @disable: API to disable a particular class smartreflex.
171 * @configure: API to configure a particular class smartreflex.
172 * @notify: API to notify the class driver about an event in SR.
173 * Not needed for class3.
174 * @notify_flags: specify the events to be notified to the class driver
175 * @class_type: specify which smartreflex class.
176 * Can be used by the SR driver to take any class
177 * based decisions.
178 */
179struct omap_sr_class_data {
180 int (*enable)(struct voltagedomain *voltdm);
181 int (*disable)(struct voltagedomain *voltdm, int is_volt_reset);
182 int (*configure)(struct voltagedomain *voltdm);
183 int (*notify)(struct voltagedomain *voltdm, u32 status);
184 u8 notify_flags;
185 u8 class_type;
186};
187
188/**
189 * struct omap_sr_nvalue_table - Smartreflex n-target value info
190 *
191 * @efuse_offs: The offset of the efuse where n-target values are stored.
192 * @nvalue: The n-target value.
193 */
194struct omap_sr_nvalue_table {
195 u32 efuse_offs;
196 u32 nvalue;
197};
198
199/**
200 * struct omap_sr_data - Smartreflex platform data.
201 *
202 * @ip_type: Smartreflex IP type.
203 * @senp_mod: SENPENABLE value for the sr
204 * @senn_mod: SENNENABLE value for sr
205 * @nvalue_count: Number of distinct nvalues in the nvalue table
206 * @enable_on_init: whether this sr module needs to enabled at
207 * boot up or not.
208 * @nvalue_table: table containing the efuse offsets and nvalues
209 * corresponding to them.
210 * @voltdm: Pointer to the voltage domain associated with the SR
211 */
212struct omap_sr_data {
213 int ip_type;
214 u32 senp_mod;
215 u32 senn_mod;
216 int nvalue_count;
217 bool enable_on_init;
218 struct omap_sr_nvalue_table *nvalue_table;
219 struct voltagedomain *voltdm;
220};
221
222/* Smartreflex module enable/disable interface */
223void omap_sr_enable(struct voltagedomain *voltdm);
224void omap_sr_disable(struct voltagedomain *voltdm);
225void omap_sr_disable_reset_volt(struct voltagedomain *voltdm);
226
227/* API to register the pmic specific data with the smartreflex driver. */
228void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data);
229
230/* Smartreflex driver hooks to be called from Smartreflex class driver */
231int sr_enable(struct voltagedomain *voltdm, unsigned long volt);
232void sr_disable(struct voltagedomain *voltdm);
233int sr_configure_errgen(struct voltagedomain *voltdm);
234int sr_configure_minmax(struct voltagedomain *voltdm);
235
236/* API to register the smartreflex class driver with the smartreflex driver */
237int sr_register_class(struct omap_sr_class_data *class_data);
238#else
239static inline void omap_sr_enable(struct voltagedomain *voltdm) {}
240static inline void omap_sr_disable(struct voltagedomain *voltdm) {}
241static inline void omap_sr_disable_reset_volt(
242 struct voltagedomain *voltdm) {}
243static inline void omap_sr_register_pmic(
244 struct omap_sr_pmic_data *pmic_data) {}
245#endif
246#endif