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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * OMAP3 Power Management Routines
4 *
5 * Copyright (C) 2006-2008 Nokia Corporation
6 * Tony Lindgren <tony@atomide.com>
7 * Jouni Hogander
8 *
9 * Copyright (C) 2007 Texas Instruments, Inc.
10 * Rajendra Nayak <rnayak@ti.com>
11 *
12 * Copyright (C) 2005 Texas Instruments, Inc.
13 * Richard Woodruff <r-woodruff2@ti.com>
14 *
15 * Based on pm.c for omap1
16 */
17
18#include <linux/cpu_pm.h>
19#include <linux/pm.h>
20#include <linux/suspend.h>
21#include <linux/interrupt.h>
22#include <linux/module.h>
23#include <linux/list.h>
24#include <linux/err.h>
25#include <linux/clk.h>
26#include <linux/delay.h>
27#include <linux/slab.h>
28#include <linux/of.h>
29#include <linux/cpuidle.h>
30
31#include <trace/events/power.h>
32
33#include <asm/fncpy.h>
34#include <asm/suspend.h>
35#include <asm/system_misc.h>
36
37#include "clockdomain.h"
38#include "powerdomain.h"
39#include "soc.h"
40#include "common.h"
41#include "cm3xxx.h"
42#include "cm-regbits-34xx.h"
43#include "prm-regbits-34xx.h"
44#include "prm3xxx.h"
45#include "pm.h"
46#include "sdrc.h"
47#include "omap-secure.h"
48#include "sram.h"
49#include "control.h"
50#include "vc.h"
51
52/* pm34xx errata defined in pm.h */
53u16 pm34xx_errata;
54
55struct power_state {
56 struct powerdomain *pwrdm;
57 u32 next_state;
58#ifdef CONFIG_SUSPEND
59 u32 saved_state;
60#endif
61 struct list_head node;
62};
63
64static LIST_HEAD(pwrst_list);
65
66void (*omap3_do_wfi_sram)(void);
67
68static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
69static struct powerdomain *core_pwrdm, *per_pwrdm;
70
71static void omap3_core_save_context(void)
72{
73 omap3_ctrl_save_padconf();
74
75 /*
76 * Force write last pad into memory, as this can fail in some
77 * cases according to errata 1.157, 1.185
78 */
79 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
80 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
81
82 /* Save the Interrupt controller context */
83 omap_intc_save_context();
84 /* Save the system control module context, padconf already save above*/
85 omap3_control_save_context();
86}
87
88static void omap3_core_restore_context(void)
89{
90 /* Restore the control module context, padconf restored by h/w */
91 omap3_control_restore_context();
92 /* Restore the interrupt controller context */
93 omap_intc_restore_context();
94}
95
96/*
97 * FIXME: This function should be called before entering off-mode after
98 * OMAP3 secure services have been accessed. Currently it is only called
99 * once during boot sequence, but this works as we are not using secure
100 * services.
101 */
102static void omap3_save_secure_ram_context(void)
103{
104 u32 ret;
105 int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
106
107 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
108 /*
109 * MPU next state must be set to POWER_ON temporarily,
110 * otherwise the WFI executed inside the ROM code
111 * will hang the system.
112 */
113 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
114 ret = omap3_save_secure_ram(omap3_secure_ram_storage,
115 OMAP3_SAVE_SECURE_RAM_SZ);
116 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
117 /* Following is for error tracking, it should not happen */
118 if (ret) {
119 pr_err("save_secure_sram() returns %08x\n", ret);
120 while (1)
121 ;
122 }
123 }
124}
125
126static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
127{
128 int c;
129
130 c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, OMAP3430_ST_IO_MASK |
131 OMAP3430_ST_IO_CHAIN_MASK);
132
133 return c ? IRQ_HANDLED : IRQ_NONE;
134}
135
136static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
137{
138 int c;
139
140 /*
141 * Clear all except ST_IO and ST_IO_CHAIN for wkup module,
142 * these are handled in a separate handler to avoid acking
143 * IO events before parsing in mux code
144 */
145 c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, ~(OMAP3430_ST_IO_MASK |
146 OMAP3430_ST_IO_CHAIN_MASK));
147 c += omap_prm_clear_mod_irqs(CORE_MOD, 1, ~0);
148 c += omap_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, ~0);
149 if (omap_rev() > OMAP3430_REV_ES1_0) {
150 c += omap_prm_clear_mod_irqs(CORE_MOD, 3, ~0);
151 c += omap_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, ~0);
152 }
153
154 return c ? IRQ_HANDLED : IRQ_NONE;
155}
156
157static void omap34xx_save_context(u32 *save)
158{
159 u32 val;
160
161 /* Read Auxiliary Control Register */
162 asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
163 *save++ = 1;
164 *save++ = val;
165
166 /* Read L2 AUX ctrl register */
167 asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
168 *save++ = 1;
169 *save++ = val;
170}
171
172static int omap34xx_do_sram_idle(unsigned long save_state)
173{
174 omap34xx_cpu_suspend(save_state);
175 return 0;
176}
177
178__cpuidle void omap_sram_idle(bool rcuidle)
179{
180 /* Variable to tell what needs to be saved and restored
181 * in omap_sram_idle*/
182 /* save_state = 0 => Nothing to save and restored */
183 /* save_state = 1 => Only L1 and logic lost */
184 /* save_state = 2 => Only L2 lost */
185 /* save_state = 3 => L1, L2 and logic lost */
186 int save_state = 0;
187 int mpu_next_state = PWRDM_POWER_ON;
188 int per_next_state = PWRDM_POWER_ON;
189 int core_next_state = PWRDM_POWER_ON;
190 u32 sdrc_pwr = 0;
191 int error;
192
193 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
194 switch (mpu_next_state) {
195 case PWRDM_POWER_ON:
196 case PWRDM_POWER_RET:
197 /* No need to save context */
198 save_state = 0;
199 break;
200 case PWRDM_POWER_OFF:
201 save_state = 3;
202 break;
203 default:
204 /* Invalid state */
205 pr_err("Invalid mpu state in sram_idle\n");
206 return;
207 }
208
209 /* NEON control */
210 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
211 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
212
213 /* Enable IO-PAD and IO-CHAIN wakeups */
214 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
215 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
216
217 pwrdm_pre_transition(NULL);
218
219 /* PER */
220 if (per_next_state == PWRDM_POWER_OFF) {
221 error = cpu_cluster_pm_enter();
222 if (error)
223 return;
224 }
225
226 /* CORE */
227 if (core_next_state < PWRDM_POWER_ON) {
228 if (core_next_state == PWRDM_POWER_OFF) {
229 omap3_core_save_context();
230 omap3_cm_save_context();
231 }
232 }
233
234 /* Configure PMIC signaling for I2C4 or sys_off_mode */
235 omap3_vc_set_pmic_signaling(core_next_state);
236
237 omap3_intc_prepare_idle();
238
239 /*
240 * On EMU/HS devices ROM code restores a SRDC value
241 * from scratchpad which has automatic self refresh on timeout
242 * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
243 * Hence store/restore the SDRC_POWER register here.
244 */
245 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
246 (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
247 omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
248 core_next_state == PWRDM_POWER_OFF)
249 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
250
251 /*
252 * omap3_arm_context is the location where some ARM context
253 * get saved. The rest is placed on the stack, and restored
254 * from there before resuming.
255 */
256 if (save_state)
257 omap34xx_save_context(omap3_arm_context);
258
259 if (rcuidle)
260 ct_cpuidle_enter();
261
262 if (save_state == 1 || save_state == 3)
263 cpu_suspend(save_state, omap34xx_do_sram_idle);
264 else
265 omap34xx_do_sram_idle(save_state);
266
267 if (rcuidle)
268 ct_cpuidle_exit();
269
270 /* Restore normal SDRC POWER settings */
271 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
272 (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
273 omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
274 core_next_state == PWRDM_POWER_OFF)
275 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
276
277 /* CORE */
278 if (core_next_state < PWRDM_POWER_ON &&
279 pwrdm_read_prev_pwrst(core_pwrdm) == PWRDM_POWER_OFF) {
280 omap3_core_restore_context();
281 omap3_cm_restore_context();
282 omap3_sram_restore_context();
283 omap2_sms_restore_context();
284 } else {
285 /*
286 * In off-mode resume path above, omap3_core_restore_context
287 * also handles the INTC autoidle restore done here so limit
288 * this to non-off mode resume paths so we don't do it twice.
289 */
290 omap3_intc_resume_idle();
291 }
292
293 pwrdm_post_transition(NULL);
294
295 /* PER */
296 if (per_next_state == PWRDM_POWER_OFF)
297 cpu_cluster_pm_exit();
298}
299
300static void omap3_pm_idle(void)
301{
302 if (omap_irq_pending())
303 return;
304
305 omap3_do_wfi();
306}
307
308#ifdef CONFIG_SUSPEND
309static int omap3_pm_suspend(void)
310{
311 struct power_state *pwrst;
312 int state, ret = 0;
313
314 /* Read current next_pwrsts */
315 list_for_each_entry(pwrst, &pwrst_list, node)
316 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
317 /* Set ones wanted by suspend */
318 list_for_each_entry(pwrst, &pwrst_list, node) {
319 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
320 goto restore;
321 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
322 goto restore;
323 }
324
325 omap3_intc_suspend();
326
327 omap_sram_idle(false);
328
329restore:
330 /* Restore next_pwrsts */
331 list_for_each_entry(pwrst, &pwrst_list, node) {
332 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
333 if (state > pwrst->next_state) {
334 pr_info("Powerdomain (%s) didn't enter target state %d\n",
335 pwrst->pwrdm->name, pwrst->next_state);
336 ret = -1;
337 }
338 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
339 }
340 if (ret)
341 pr_err("Could not enter target state in pm_suspend\n");
342 else
343 pr_info("Successfully put all powerdomains to target state\n");
344
345 return ret;
346}
347#else
348#define omap3_pm_suspend NULL
349#endif /* CONFIG_SUSPEND */
350
351static void __init prcm_setup_regs(void)
352{
353 omap3_ctrl_init();
354
355 omap3_prm_init_pm(cpu_is_omap3630(), omap3_has_iva());
356}
357
358void omap3_pm_off_mode_enable(int enable)
359{
360 struct power_state *pwrst;
361 u32 state;
362
363 if (enable)
364 state = PWRDM_POWER_OFF;
365 else
366 state = PWRDM_POWER_RET;
367
368 list_for_each_entry(pwrst, &pwrst_list, node) {
369 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
370 pwrst->pwrdm == core_pwrdm &&
371 state == PWRDM_POWER_OFF) {
372 pwrst->next_state = PWRDM_POWER_RET;
373 pr_warn("%s: Core OFF disabled due to errata i583\n",
374 __func__);
375 } else {
376 pwrst->next_state = state;
377 }
378 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
379 }
380}
381
382int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
383{
384 struct power_state *pwrst;
385
386 list_for_each_entry(pwrst, &pwrst_list, node) {
387 if (pwrst->pwrdm == pwrdm)
388 return pwrst->next_state;
389 }
390 return -EINVAL;
391}
392
393int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
394{
395 struct power_state *pwrst;
396
397 list_for_each_entry(pwrst, &pwrst_list, node) {
398 if (pwrst->pwrdm == pwrdm) {
399 pwrst->next_state = state;
400 return 0;
401 }
402 }
403 return -EINVAL;
404}
405
406static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
407{
408 struct power_state *pwrst;
409
410 if (!pwrdm->pwrsts)
411 return 0;
412
413 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
414 if (!pwrst)
415 return -ENOMEM;
416 pwrst->pwrdm = pwrdm;
417
418 if (enable_off_mode)
419 pwrst->next_state = PWRDM_POWER_OFF;
420 else
421 pwrst->next_state = PWRDM_POWER_RET;
422
423 list_add(&pwrst->node, &pwrst_list);
424
425 if (pwrdm_has_hdwr_sar(pwrdm))
426 pwrdm_enable_hdwr_sar(pwrdm);
427
428 return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
429}
430
431/*
432 * Push functions to SRAM
433 *
434 * The minimum set of functions is pushed to SRAM for execution:
435 * - omap3_do_wfi for erratum i581 WA,
436 */
437void omap_push_sram_idle(void)
438{
439 omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
440}
441
442static void __init pm_errata_configure(void)
443{
444 if (cpu_is_omap3630()) {
445 pm34xx_errata |= PM_RTA_ERRATUM_i608;
446 /* Enable the l2 cache toggling in sleep logic */
447 enable_omap3630_toggle_l2_on_restore();
448 if (omap_rev() < OMAP3630_REV_ES1_2)
449 pm34xx_errata |= (PM_SDRC_WAKEUP_ERRATUM_i583 |
450 PM_PER_MEMORIES_ERRATUM_i582);
451 } else if (cpu_is_omap34xx()) {
452 pm34xx_errata |= PM_PER_MEMORIES_ERRATUM_i582;
453 }
454}
455
456static void __init omap3_pm_check_pmic(void)
457{
458 struct device_node *np;
459
460 np = of_find_compatible_node(NULL, NULL, "ti,twl4030-power-idle");
461 if (!np)
462 np = of_find_compatible_node(NULL, NULL, "ti,twl4030-power-idle-osc-off");
463
464 if (np) {
465 of_node_put(np);
466 enable_off_mode = 1;
467 } else {
468 enable_off_mode = 0;
469 }
470}
471
472int __init omap3_pm_init(void)
473{
474 struct power_state *pwrst, *tmp;
475 struct clockdomain *neon_clkdm, *mpu_clkdm, *per_clkdm, *wkup_clkdm;
476 int ret;
477
478 if (!omap3_has_io_chain_ctrl())
479 pr_warn("PM: no software I/O chain control; some wakeups may be lost\n");
480
481 pm_errata_configure();
482
483 /* XXX prcm_setup_regs needs to be before enabling hw
484 * supervised mode for powerdomains */
485 prcm_setup_regs();
486
487 ret = request_irq(omap_prcm_event_to_irq("wkup"),
488 _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL);
489
490 if (ret) {
491 pr_err("pm: Failed to request pm_wkup irq\n");
492 goto err1;
493 }
494
495 /* IO interrupt is shared with mux code */
496 ret = request_irq(omap_prcm_event_to_irq("io"),
497 _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
498 omap3_pm_init);
499
500 if (ret) {
501 pr_err("pm: Failed to request pm_io irq\n");
502 goto err2;
503 }
504
505 omap3_pm_check_pmic();
506
507 ret = pwrdm_for_each(pwrdms_setup, NULL);
508 if (ret) {
509 pr_err("Failed to setup powerdomains\n");
510 goto err3;
511 }
512
513 (void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
514
515 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
516 if (mpu_pwrdm == NULL) {
517 pr_err("Failed to get mpu_pwrdm\n");
518 ret = -EINVAL;
519 goto err3;
520 }
521
522 neon_pwrdm = pwrdm_lookup("neon_pwrdm");
523 per_pwrdm = pwrdm_lookup("per_pwrdm");
524 core_pwrdm = pwrdm_lookup("core_pwrdm");
525
526 neon_clkdm = clkdm_lookup("neon_clkdm");
527 mpu_clkdm = clkdm_lookup("mpu_clkdm");
528 per_clkdm = clkdm_lookup("per_clkdm");
529 wkup_clkdm = clkdm_lookup("wkup_clkdm");
530
531 omap_common_suspend_init(omap3_pm_suspend);
532
533 arm_pm_idle = omap3_pm_idle;
534 omap3_idle_init();
535
536 /*
537 * RTA is disabled during initialization as per erratum i608
538 * it is safer to disable RTA by the bootloader, but we would like
539 * to be doubly sure here and prevent any mishaps.
540 */
541 if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
542 omap3630_ctrl_disable_rta();
543
544 /*
545 * The UART3/4 FIFO and the sidetone memory in McBSP2/3 are
546 * not correctly reset when the PER powerdomain comes back
547 * from OFF or OSWR when the CORE powerdomain is kept active.
548 * See OMAP36xx Erratum i582 "PER Domain reset issue after
549 * Domain-OFF/OSWR Wakeup". This wakeup dependency is not a
550 * complete workaround. The kernel must also prevent the PER
551 * powerdomain from going to OSWR/OFF while the CORE
552 * powerdomain is not going to OSWR/OFF. And if PER last
553 * power state was off while CORE last power state was ON, the
554 * UART3/4 and McBSP2/3 SIDETONE devices need to run a
555 * self-test using their loopback tests; if that fails, those
556 * devices are unusable until the PER/CORE can complete a transition
557 * from ON to OSWR/OFF and then back to ON.
558 *
559 * XXX Technically this workaround is only needed if off-mode
560 * or OSWR is enabled.
561 */
562 if (IS_PM34XX_ERRATUM(PM_PER_MEMORIES_ERRATUM_i582))
563 clkdm_add_wkdep(per_clkdm, wkup_clkdm);
564
565 clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
566 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
567 omap3_secure_ram_storage =
568 kmalloc(OMAP3_SAVE_SECURE_RAM_SZ, GFP_KERNEL);
569 if (!omap3_secure_ram_storage)
570 pr_err("Memory allocation failed when allocating for secure sram context\n");
571
572 local_irq_disable();
573
574 omap3_save_secure_ram_context();
575
576 local_irq_enable();
577 }
578
579 omap3_save_scratchpad_contents();
580 return ret;
581
582err3:
583 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
584 list_del(&pwrst->node);
585 kfree(pwrst);
586 }
587 free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init);
588err2:
589 free_irq(omap_prcm_event_to_irq("wkup"), NULL);
590err1:
591 return ret;
592}
1/*
2 * OMAP3 Power Management Routines
3 *
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
6 * Jouni Hogander
7 *
8 * Copyright (C) 2007 Texas Instruments, Inc.
9 * Rajendra Nayak <rnayak@ti.com>
10 *
11 * Copyright (C) 2005 Texas Instruments, Inc.
12 * Richard Woodruff <r-woodruff2@ti.com>
13 *
14 * Based on pm.c for omap1
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#include <linux/pm.h>
22#include <linux/suspend.h>
23#include <linux/interrupt.h>
24#include <linux/module.h>
25#include <linux/list.h>
26#include <linux/err.h>
27#include <linux/gpio.h>
28#include <linux/clk.h>
29#include <linux/delay.h>
30#include <linux/slab.h>
31#include <linux/console.h>
32#include <trace/events/power.h>
33
34#include <asm/suspend.h>
35
36#include <plat/sram.h>
37#include "clockdomain.h"
38#include "powerdomain.h"
39#include <plat/serial.h>
40#include <plat/sdrc.h>
41#include <plat/prcm.h>
42#include <plat/gpmc.h>
43#include <plat/dma.h>
44
45#include "cm2xxx_3xxx.h"
46#include "cm-regbits-34xx.h"
47#include "prm-regbits-34xx.h"
48
49#include "prm2xxx_3xxx.h"
50#include "pm.h"
51#include "sdrc.h"
52#include "control.h"
53
54#ifdef CONFIG_SUSPEND
55static suspend_state_t suspend_state = PM_SUSPEND_ON;
56static inline bool is_suspending(void)
57{
58 return (suspend_state != PM_SUSPEND_ON);
59}
60#else
61static inline bool is_suspending(void)
62{
63 return false;
64}
65#endif
66
67/* pm34xx errata defined in pm.h */
68u16 pm34xx_errata;
69
70struct power_state {
71 struct powerdomain *pwrdm;
72 u32 next_state;
73#ifdef CONFIG_SUSPEND
74 u32 saved_state;
75#endif
76 struct list_head node;
77};
78
79static LIST_HEAD(pwrst_list);
80
81static int (*_omap_save_secure_sram)(u32 *addr);
82void (*omap3_do_wfi_sram)(void);
83
84static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
85static struct powerdomain *core_pwrdm, *per_pwrdm;
86static struct powerdomain *cam_pwrdm;
87
88static inline void omap3_per_save_context(void)
89{
90 omap_gpio_save_context();
91}
92
93static inline void omap3_per_restore_context(void)
94{
95 omap_gpio_restore_context();
96}
97
98static void omap3_enable_io_chain(void)
99{
100 int timeout = 0;
101
102 if (omap_rev() >= OMAP3430_REV_ES3_1) {
103 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
104 PM_WKEN);
105 /* Do a readback to assure write has been done */
106 omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
107
108 while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
109 OMAP3430_ST_IO_CHAIN_MASK)) {
110 timeout++;
111 if (timeout > 1000) {
112 printk(KERN_ERR "Wake up daisy chain "
113 "activation failed.\n");
114 return;
115 }
116 omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
117 WKUP_MOD, PM_WKEN);
118 }
119 }
120}
121
122static void omap3_disable_io_chain(void)
123{
124 if (omap_rev() >= OMAP3430_REV_ES3_1)
125 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
126 PM_WKEN);
127}
128
129static void omap3_core_save_context(void)
130{
131 omap3_ctrl_save_padconf();
132
133 /*
134 * Force write last pad into memory, as this can fail in some
135 * cases according to errata 1.157, 1.185
136 */
137 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
138 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
139
140 /* Save the Interrupt controller context */
141 omap_intc_save_context();
142 /* Save the GPMC context */
143 omap3_gpmc_save_context();
144 /* Save the system control module context, padconf already save above*/
145 omap3_control_save_context();
146 omap_dma_global_context_save();
147}
148
149static void omap3_core_restore_context(void)
150{
151 /* Restore the control module context, padconf restored by h/w */
152 omap3_control_restore_context();
153 /* Restore the GPMC context */
154 omap3_gpmc_restore_context();
155 /* Restore the interrupt controller context */
156 omap_intc_restore_context();
157 omap_dma_global_context_restore();
158}
159
160/*
161 * FIXME: This function should be called before entering off-mode after
162 * OMAP3 secure services have been accessed. Currently it is only called
163 * once during boot sequence, but this works as we are not using secure
164 * services.
165 */
166static void omap3_save_secure_ram_context(void)
167{
168 u32 ret;
169 int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
170
171 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
172 /*
173 * MPU next state must be set to POWER_ON temporarily,
174 * otherwise the WFI executed inside the ROM code
175 * will hang the system.
176 */
177 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
178 ret = _omap_save_secure_sram((u32 *)
179 __pa(omap3_secure_ram_storage));
180 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
181 /* Following is for error tracking, it should not happen */
182 if (ret) {
183 printk(KERN_ERR "save_secure_sram() returns %08x\n",
184 ret);
185 while (1)
186 ;
187 }
188 }
189}
190
191/*
192 * PRCM Interrupt Handler Helper Function
193 *
194 * The purpose of this function is to clear any wake-up events latched
195 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
196 * may occur whilst attempting to clear a PM_WKST_x register and thus
197 * set another bit in this register. A while loop is used to ensure
198 * that any peripheral wake-up events occurring while attempting to
199 * clear the PM_WKST_x are detected and cleared.
200 */
201static int prcm_clear_mod_irqs(s16 module, u8 regs)
202{
203 u32 wkst, fclk, iclk, clken;
204 u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
205 u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
206 u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
207 u16 grpsel_off = (regs == 3) ?
208 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
209 int c = 0;
210
211 wkst = omap2_prm_read_mod_reg(module, wkst_off);
212 wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
213 if (wkst) {
214 iclk = omap2_cm_read_mod_reg(module, iclk_off);
215 fclk = omap2_cm_read_mod_reg(module, fclk_off);
216 while (wkst) {
217 clken = wkst;
218 omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
219 /*
220 * For USBHOST, we don't know whether HOST1 or
221 * HOST2 woke us up, so enable both f-clocks
222 */
223 if (module == OMAP3430ES2_USBHOST_MOD)
224 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
225 omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
226 omap2_prm_write_mod_reg(wkst, module, wkst_off);
227 wkst = omap2_prm_read_mod_reg(module, wkst_off);
228 c++;
229 }
230 omap2_cm_write_mod_reg(iclk, module, iclk_off);
231 omap2_cm_write_mod_reg(fclk, module, fclk_off);
232 }
233
234 return c;
235}
236
237static int _prcm_int_handle_wakeup(void)
238{
239 int c;
240
241 c = prcm_clear_mod_irqs(WKUP_MOD, 1);
242 c += prcm_clear_mod_irqs(CORE_MOD, 1);
243 c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
244 if (omap_rev() > OMAP3430_REV_ES1_0) {
245 c += prcm_clear_mod_irqs(CORE_MOD, 3);
246 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
247 }
248
249 return c;
250}
251
252/*
253 * PRCM Interrupt Handler
254 *
255 * The PRM_IRQSTATUS_MPU register indicates if there are any pending
256 * interrupts from the PRCM for the MPU. These bits must be cleared in
257 * order to clear the PRCM interrupt. The PRCM interrupt handler is
258 * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
259 * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
260 * register indicates that a wake-up event is pending for the MPU and
261 * this bit can only be cleared if the all the wake-up events latched
262 * in the various PM_WKST_x registers have been cleared. The interrupt
263 * handler is implemented using a do-while loop so that if a wake-up
264 * event occurred during the processing of the prcm interrupt handler
265 * (setting a bit in the corresponding PM_WKST_x register and thus
266 * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
267 * this would be handled.
268 */
269static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
270{
271 u32 irqenable_mpu, irqstatus_mpu;
272 int c = 0;
273
274 irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD,
275 OMAP3_PRM_IRQENABLE_MPU_OFFSET);
276 irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
277 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
278 irqstatus_mpu &= irqenable_mpu;
279
280 do {
281 if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK |
282 OMAP3430_IO_ST_MASK)) {
283 c = _prcm_int_handle_wakeup();
284
285 /*
286 * Is the MPU PRCM interrupt handler racing with the
287 * IVA2 PRCM interrupt handler ?
288 */
289 WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
290 "but no wakeup sources are marked\n");
291 } else {
292 /* XXX we need to expand our PRCM interrupt handler */
293 WARN(1, "prcm: WARNING: PRCM interrupt received, but "
294 "no code to handle it (%08x)\n", irqstatus_mpu);
295 }
296
297 omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
298 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
299
300 irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
301 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
302 irqstatus_mpu &= irqenable_mpu;
303
304 } while (irqstatus_mpu);
305
306 return IRQ_HANDLED;
307}
308
309static void omap34xx_save_context(u32 *save)
310{
311 u32 val;
312
313 /* Read Auxiliary Control Register */
314 asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
315 *save++ = 1;
316 *save++ = val;
317
318 /* Read L2 AUX ctrl register */
319 asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
320 *save++ = 1;
321 *save++ = val;
322}
323
324static int omap34xx_do_sram_idle(unsigned long save_state)
325{
326 omap34xx_cpu_suspend(save_state);
327 return 0;
328}
329
330void omap_sram_idle(void)
331{
332 /* Variable to tell what needs to be saved and restored
333 * in omap_sram_idle*/
334 /* save_state = 0 => Nothing to save and restored */
335 /* save_state = 1 => Only L1 and logic lost */
336 /* save_state = 2 => Only L2 lost */
337 /* save_state = 3 => L1, L2 and logic lost */
338 int save_state = 0;
339 int mpu_next_state = PWRDM_POWER_ON;
340 int per_next_state = PWRDM_POWER_ON;
341 int core_next_state = PWRDM_POWER_ON;
342 int per_going_off;
343 int core_prev_state, per_prev_state;
344 u32 sdrc_pwr = 0;
345
346 pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
347 pwrdm_clear_all_prev_pwrst(neon_pwrdm);
348 pwrdm_clear_all_prev_pwrst(core_pwrdm);
349 pwrdm_clear_all_prev_pwrst(per_pwrdm);
350
351 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
352 switch (mpu_next_state) {
353 case PWRDM_POWER_ON:
354 case PWRDM_POWER_RET:
355 /* No need to save context */
356 save_state = 0;
357 break;
358 case PWRDM_POWER_OFF:
359 save_state = 3;
360 break;
361 default:
362 /* Invalid state */
363 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
364 return;
365 }
366 pwrdm_pre_transition();
367
368 /* NEON control */
369 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
370 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
371
372 /* Enable IO-PAD and IO-CHAIN wakeups */
373 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
374 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
375 if (omap3_has_io_wakeup() &&
376 (per_next_state < PWRDM_POWER_ON ||
377 core_next_state < PWRDM_POWER_ON)) {
378 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
379 omap3_enable_io_chain();
380 }
381
382 /* Block console output in case it is on one of the OMAP UARTs */
383 if (!is_suspending())
384 if (per_next_state < PWRDM_POWER_ON ||
385 core_next_state < PWRDM_POWER_ON)
386 if (!console_trylock())
387 goto console_still_active;
388
389 /* PER */
390 if (per_next_state < PWRDM_POWER_ON) {
391 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
392 omap_uart_prepare_idle(2);
393 omap_uart_prepare_idle(3);
394 omap2_gpio_prepare_for_idle(per_going_off);
395 if (per_next_state == PWRDM_POWER_OFF)
396 omap3_per_save_context();
397 }
398
399 /* CORE */
400 if (core_next_state < PWRDM_POWER_ON) {
401 omap_uart_prepare_idle(0);
402 omap_uart_prepare_idle(1);
403 if (core_next_state == PWRDM_POWER_OFF) {
404 omap3_core_save_context();
405 omap3_cm_save_context();
406 }
407 }
408
409 omap3_intc_prepare_idle();
410
411 /*
412 * On EMU/HS devices ROM code restores a SRDC value
413 * from scratchpad which has automatic self refresh on timeout
414 * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
415 * Hence store/restore the SDRC_POWER register here.
416 */
417 if (omap_rev() >= OMAP3430_REV_ES3_0 &&
418 omap_type() != OMAP2_DEVICE_TYPE_GP &&
419 core_next_state == PWRDM_POWER_OFF)
420 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
421
422 /*
423 * omap3_arm_context is the location where some ARM context
424 * get saved. The rest is placed on the stack, and restored
425 * from there before resuming.
426 */
427 if (save_state)
428 omap34xx_save_context(omap3_arm_context);
429 if (save_state == 1 || save_state == 3)
430 cpu_suspend(save_state, omap34xx_do_sram_idle);
431 else
432 omap34xx_do_sram_idle(save_state);
433
434 /* Restore normal SDRC POWER settings */
435 if (omap_rev() >= OMAP3430_REV_ES3_0 &&
436 omap_type() != OMAP2_DEVICE_TYPE_GP &&
437 core_next_state == PWRDM_POWER_OFF)
438 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
439
440 /* CORE */
441 if (core_next_state < PWRDM_POWER_ON) {
442 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
443 if (core_prev_state == PWRDM_POWER_OFF) {
444 omap3_core_restore_context();
445 omap3_cm_restore_context();
446 omap3_sram_restore_context();
447 omap2_sms_restore_context();
448 }
449 omap_uart_resume_idle(0);
450 omap_uart_resume_idle(1);
451 if (core_next_state == PWRDM_POWER_OFF)
452 omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
453 OMAP3430_GR_MOD,
454 OMAP3_PRM_VOLTCTRL_OFFSET);
455 }
456 omap3_intc_resume_idle();
457
458 /* PER */
459 if (per_next_state < PWRDM_POWER_ON) {
460 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
461 omap2_gpio_resume_after_idle();
462 if (per_prev_state == PWRDM_POWER_OFF)
463 omap3_per_restore_context();
464 omap_uart_resume_idle(2);
465 omap_uart_resume_idle(3);
466 }
467
468 if (!is_suspending())
469 console_unlock();
470
471console_still_active:
472 /* Disable IO-PAD and IO-CHAIN wakeup */
473 if (omap3_has_io_wakeup() &&
474 (per_next_state < PWRDM_POWER_ON ||
475 core_next_state < PWRDM_POWER_ON)) {
476 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
477 PM_WKEN);
478 omap3_disable_io_chain();
479 }
480
481 pwrdm_post_transition();
482
483 clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
484}
485
486int omap3_can_sleep(void)
487{
488 if (!omap_uart_can_sleep())
489 return 0;
490 return 1;
491}
492
493static void omap3_pm_idle(void)
494{
495 local_irq_disable();
496 local_fiq_disable();
497
498 if (!omap3_can_sleep())
499 goto out;
500
501 if (omap_irq_pending() || need_resched())
502 goto out;
503
504 trace_power_start(POWER_CSTATE, 1, smp_processor_id());
505 trace_cpu_idle(1, smp_processor_id());
506
507 omap_sram_idle();
508
509 trace_power_end(smp_processor_id());
510 trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
511
512out:
513 local_fiq_enable();
514 local_irq_enable();
515}
516
517#ifdef CONFIG_SUSPEND
518static int omap3_pm_suspend(void)
519{
520 struct power_state *pwrst;
521 int state, ret = 0;
522
523 /* Read current next_pwrsts */
524 list_for_each_entry(pwrst, &pwrst_list, node)
525 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
526 /* Set ones wanted by suspend */
527 list_for_each_entry(pwrst, &pwrst_list, node) {
528 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
529 goto restore;
530 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
531 goto restore;
532 }
533
534 omap_uart_prepare_suspend();
535 omap3_intc_suspend();
536
537 omap_sram_idle();
538
539restore:
540 /* Restore next_pwrsts */
541 list_for_each_entry(pwrst, &pwrst_list, node) {
542 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
543 if (state > pwrst->next_state) {
544 printk(KERN_INFO "Powerdomain (%s) didn't enter "
545 "target state %d\n",
546 pwrst->pwrdm->name, pwrst->next_state);
547 ret = -1;
548 }
549 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
550 }
551 if (ret)
552 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
553 else
554 printk(KERN_INFO "Successfully put all powerdomains "
555 "to target state\n");
556
557 return ret;
558}
559
560static int omap3_pm_enter(suspend_state_t unused)
561{
562 int ret = 0;
563
564 switch (suspend_state) {
565 case PM_SUSPEND_STANDBY:
566 case PM_SUSPEND_MEM:
567 ret = omap3_pm_suspend();
568 break;
569 default:
570 ret = -EINVAL;
571 }
572
573 return ret;
574}
575
576/* Hooks to enable / disable UART interrupts during suspend */
577static int omap3_pm_begin(suspend_state_t state)
578{
579 disable_hlt();
580 suspend_state = state;
581 omap_uart_enable_irqs(0);
582 return 0;
583}
584
585static void omap3_pm_end(void)
586{
587 suspend_state = PM_SUSPEND_ON;
588 omap_uart_enable_irqs(1);
589 enable_hlt();
590 return;
591}
592
593static const struct platform_suspend_ops omap_pm_ops = {
594 .begin = omap3_pm_begin,
595 .end = omap3_pm_end,
596 .enter = omap3_pm_enter,
597 .valid = suspend_valid_only_mem,
598};
599#endif /* CONFIG_SUSPEND */
600
601
602/**
603 * omap3_iva_idle(): ensure IVA is in idle so it can be put into
604 * retention
605 *
606 * In cases where IVA2 is activated by bootcode, it may prevent
607 * full-chip retention or off-mode because it is not idle. This
608 * function forces the IVA2 into idle state so it can go
609 * into retention/off and thus allow full-chip retention/off.
610 *
611 **/
612static void __init omap3_iva_idle(void)
613{
614 /* ensure IVA2 clock is disabled */
615 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
616
617 /* if no clock activity, nothing else to do */
618 if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
619 OMAP3430_CLKACTIVITY_IVA2_MASK))
620 return;
621
622 /* Reset IVA2 */
623 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
624 OMAP3430_RST2_IVA2_MASK |
625 OMAP3430_RST3_IVA2_MASK,
626 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
627
628 /* Enable IVA2 clock */
629 omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
630 OMAP3430_IVA2_MOD, CM_FCLKEN);
631
632 /* Set IVA2 boot mode to 'idle' */
633 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
634 OMAP343X_CONTROL_IVA2_BOOTMOD);
635
636 /* Un-reset IVA2 */
637 omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
638
639 /* Disable IVA2 clock */
640 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
641
642 /* Reset IVA2 */
643 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
644 OMAP3430_RST2_IVA2_MASK |
645 OMAP3430_RST3_IVA2_MASK,
646 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
647}
648
649static void __init omap3_d2d_idle(void)
650{
651 u16 mask, padconf;
652
653 /* In a stand alone OMAP3430 where there is not a stacked
654 * modem for the D2D Idle Ack and D2D MStandby must be pulled
655 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
656 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
657 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
658 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
659 padconf |= mask;
660 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
661
662 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
663 padconf |= mask;
664 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
665
666 /* reset modem */
667 omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
668 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
669 CORE_MOD, OMAP2_RM_RSTCTRL);
670 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
671}
672
673static void __init prcm_setup_regs(void)
674{
675 u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
676 OMAP3630_EN_UART4_MASK : 0;
677 u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
678 OMAP3630_GRPSEL_UART4_MASK : 0;
679
680 /* XXX This should be handled by hwmod code or SCM init code */
681 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
682
683 /*
684 * Enable control of expternal oscillator through
685 * sys_clkreq. In the long run clock framework should
686 * take care of this.
687 */
688 omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
689 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
690 OMAP3430_GR_MOD,
691 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
692
693 /* setup wakup source */
694 omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
695 OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
696 WKUP_MOD, PM_WKEN);
697 /* No need to write EN_IO, that is always enabled */
698 omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
699 OMAP3430_GRPSEL_GPT1_MASK |
700 OMAP3430_GRPSEL_GPT12_MASK,
701 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
702 /* For some reason IO doesn't generate wakeup event even if
703 * it is selected to mpu wakeup goup */
704 omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
705 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
706
707 /* Enable PM_WKEN to support DSS LPR */
708 omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
709 OMAP3430_DSS_MOD, PM_WKEN);
710
711 /* Enable wakeups in PER */
712 omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
713 OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
714 OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
715 OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
716 OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
717 OMAP3430_EN_MCBSP4_MASK,
718 OMAP3430_PER_MOD, PM_WKEN);
719 /* and allow them to wake up MPU */
720 omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
721 OMAP3430_GRPSEL_GPIO2_MASK |
722 OMAP3430_GRPSEL_GPIO3_MASK |
723 OMAP3430_GRPSEL_GPIO4_MASK |
724 OMAP3430_GRPSEL_GPIO5_MASK |
725 OMAP3430_GRPSEL_GPIO6_MASK |
726 OMAP3430_GRPSEL_UART3_MASK |
727 OMAP3430_GRPSEL_MCBSP2_MASK |
728 OMAP3430_GRPSEL_MCBSP3_MASK |
729 OMAP3430_GRPSEL_MCBSP4_MASK,
730 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
731
732 /* Don't attach IVA interrupts */
733 omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
734 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
735 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
736 omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
737
738 /* Clear any pending 'reset' flags */
739 omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
740 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
741 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
742 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
743 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
744 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
745 omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
746
747 /* Clear any pending PRCM interrupts */
748 omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
749
750 omap3_iva_idle();
751 omap3_d2d_idle();
752}
753
754void omap3_pm_off_mode_enable(int enable)
755{
756 struct power_state *pwrst;
757 u32 state;
758
759 if (enable)
760 state = PWRDM_POWER_OFF;
761 else
762 state = PWRDM_POWER_RET;
763
764 list_for_each_entry(pwrst, &pwrst_list, node) {
765 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
766 pwrst->pwrdm == core_pwrdm &&
767 state == PWRDM_POWER_OFF) {
768 pwrst->next_state = PWRDM_POWER_RET;
769 pr_warn("%s: Core OFF disabled due to errata i583\n",
770 __func__);
771 } else {
772 pwrst->next_state = state;
773 }
774 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
775 }
776}
777
778int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
779{
780 struct power_state *pwrst;
781
782 list_for_each_entry(pwrst, &pwrst_list, node) {
783 if (pwrst->pwrdm == pwrdm)
784 return pwrst->next_state;
785 }
786 return -EINVAL;
787}
788
789int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
790{
791 struct power_state *pwrst;
792
793 list_for_each_entry(pwrst, &pwrst_list, node) {
794 if (pwrst->pwrdm == pwrdm) {
795 pwrst->next_state = state;
796 return 0;
797 }
798 }
799 return -EINVAL;
800}
801
802static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
803{
804 struct power_state *pwrst;
805
806 if (!pwrdm->pwrsts)
807 return 0;
808
809 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
810 if (!pwrst)
811 return -ENOMEM;
812 pwrst->pwrdm = pwrdm;
813 pwrst->next_state = PWRDM_POWER_RET;
814 list_add(&pwrst->node, &pwrst_list);
815
816 if (pwrdm_has_hdwr_sar(pwrdm))
817 pwrdm_enable_hdwr_sar(pwrdm);
818
819 return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
820}
821
822/*
823 * Enable hw supervised mode for all clockdomains if it's
824 * supported. Initiate sleep transition for other clockdomains, if
825 * they are not used
826 */
827static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
828{
829 if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
830 clkdm_allow_idle(clkdm);
831 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
832 atomic_read(&clkdm->usecount) == 0)
833 clkdm_sleep(clkdm);
834 return 0;
835}
836
837/*
838 * Push functions to SRAM
839 *
840 * The minimum set of functions is pushed to SRAM for execution:
841 * - omap3_do_wfi for erratum i581 WA,
842 * - save_secure_ram_context for security extensions.
843 */
844void omap_push_sram_idle(void)
845{
846 omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
847
848 if (omap_type() != OMAP2_DEVICE_TYPE_GP)
849 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
850 save_secure_ram_context_sz);
851}
852
853static void __init pm_errata_configure(void)
854{
855 if (cpu_is_omap3630()) {
856 pm34xx_errata |= PM_RTA_ERRATUM_i608;
857 /* Enable the l2 cache toggling in sleep logic */
858 enable_omap3630_toggle_l2_on_restore();
859 if (omap_rev() < OMAP3630_REV_ES1_2)
860 pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
861 }
862}
863
864static int __init omap3_pm_init(void)
865{
866 struct power_state *pwrst, *tmp;
867 struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
868 int ret;
869
870 if (!cpu_is_omap34xx())
871 return -ENODEV;
872
873 pm_errata_configure();
874
875 /* XXX prcm_setup_regs needs to be before enabling hw
876 * supervised mode for powerdomains */
877 prcm_setup_regs();
878
879 ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
880 (irq_handler_t)prcm_interrupt_handler,
881 IRQF_DISABLED, "prcm", NULL);
882 if (ret) {
883 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
884 INT_34XX_PRCM_MPU_IRQ);
885 goto err1;
886 }
887
888 ret = pwrdm_for_each(pwrdms_setup, NULL);
889 if (ret) {
890 printk(KERN_ERR "Failed to setup powerdomains\n");
891 goto err2;
892 }
893
894 (void) clkdm_for_each(clkdms_setup, NULL);
895
896 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
897 if (mpu_pwrdm == NULL) {
898 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
899 goto err2;
900 }
901
902 neon_pwrdm = pwrdm_lookup("neon_pwrdm");
903 per_pwrdm = pwrdm_lookup("per_pwrdm");
904 core_pwrdm = pwrdm_lookup("core_pwrdm");
905 cam_pwrdm = pwrdm_lookup("cam_pwrdm");
906
907 neon_clkdm = clkdm_lookup("neon_clkdm");
908 mpu_clkdm = clkdm_lookup("mpu_clkdm");
909 per_clkdm = clkdm_lookup("per_clkdm");
910 core_clkdm = clkdm_lookup("core_clkdm");
911
912#ifdef CONFIG_SUSPEND
913 suspend_set_ops(&omap_pm_ops);
914#endif /* CONFIG_SUSPEND */
915
916 pm_idle = omap3_pm_idle;
917 omap3_idle_init();
918
919 /*
920 * RTA is disabled during initialization as per erratum i608
921 * it is safer to disable RTA by the bootloader, but we would like
922 * to be doubly sure here and prevent any mishaps.
923 */
924 if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
925 omap3630_ctrl_disable_rta();
926
927 clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
928 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
929 omap3_secure_ram_storage =
930 kmalloc(0x803F, GFP_KERNEL);
931 if (!omap3_secure_ram_storage)
932 printk(KERN_ERR "Memory allocation failed when"
933 "allocating for secure sram context\n");
934
935 local_irq_disable();
936 local_fiq_disable();
937
938 omap_dma_global_context_save();
939 omap3_save_secure_ram_context();
940 omap_dma_global_context_restore();
941
942 local_irq_enable();
943 local_fiq_enable();
944 }
945
946 omap3_save_scratchpad_contents();
947err1:
948 return ret;
949err2:
950 free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
951 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
952 list_del(&pwrst->node);
953 kfree(pwrst);
954 }
955 return ret;
956}
957
958late_initcall(omap3_pm_init);