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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * omap_hwmod_2xxx_3xxx_ipblock_data.c - common IP block data for OMAP2/3
4 *
5 * Copyright (C) 2011 Nokia Corporation
6 * Copyright (C) 2012 Texas Instruments, Inc.
7 * Paul Walmsley
8 */
9
10#include <linux/dmaengine.h>
11#include <linux/omap-dma.h>
12
13#include "omap_hwmod.h"
14#include "hdq1w.h"
15
16#include "omap_hwmod_common_data.h"
17
18/* UART */
19
20static struct omap_hwmod_class_sysconfig omap2_uart_sysc = {
21 .rev_offs = 0x50,
22 .sysc_offs = 0x54,
23 .syss_offs = 0x58,
24 .sysc_flags = (SYSC_HAS_SIDLEMODE |
25 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
26 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
27 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
28 .sysc_fields = &omap_hwmod_sysc_type1,
29};
30
31struct omap_hwmod_class omap2_uart_class = {
32 .name = "uart",
33 .sysc = &omap2_uart_sysc,
34};
35
36/*
37 * 'venc' class
38 * video encoder
39 */
40
41struct omap_hwmod_class omap2_venc_hwmod_class = {
42 .name = "venc",
43};
44
45/*
46 * omap_hwmod class data
47 */
48
49struct omap_hwmod_class l3_hwmod_class = {
50 .name = "l3",
51};
52
53struct omap_hwmod_class l4_hwmod_class = {
54 .name = "l4",
55};
56
57struct omap_hwmod_class mpu_hwmod_class = {
58 .name = "mpu",
59};
60
61struct omap_hwmod_class iva_hwmod_class = {
62 .name = "iva",
63};
64
65static struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = {
66 .rev_offs = 0x0,
67 .sysc_offs = 0x14,
68 .syss_offs = 0x18,
69 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
70 SYSS_HAS_RESET_STATUS),
71 .sysc_fields = &omap_hwmod_sysc_type1,
72};
73
74struct omap_hwmod_class omap2_hdq1w_class = {
75 .name = "hdq1w",
76 .sysc = &omap2_hdq1w_sysc,
77 .reset = &omap_hdq1w_reset,
78};
1/*
2 * omap_hwmod_2xxx_3xxx_ipblock_data.c - common IP block data for OMAP2/3
3 *
4 * Copyright (C) 2011 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <plat/omap_hwmod.h>
12#include <plat/serial.h>
13#include <plat/dma.h>
14
15#include <mach/irqs.h>
16
17#include "omap_hwmod_common_data.h"
18
19/* UART */
20
21static struct omap_hwmod_class_sysconfig omap2_uart_sysc = {
22 .rev_offs = 0x50,
23 .sysc_offs = 0x54,
24 .syss_offs = 0x58,
25 .sysc_flags = (SYSC_HAS_SIDLEMODE |
26 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
27 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
28 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
29 .sysc_fields = &omap_hwmod_sysc_type1,
30};
31
32struct omap_hwmod_class omap2_uart_class = {
33 .name = "uart",
34 .sysc = &omap2_uart_sysc,
35};
36
37/*
38 * 'dss' class
39 * display sub-system
40 */
41
42static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {
43 .rev_offs = 0x0000,
44 .sysc_offs = 0x0010,
45 .syss_offs = 0x0014,
46 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
47 .sysc_fields = &omap_hwmod_sysc_type1,
48};
49
50struct omap_hwmod_class omap2_dss_hwmod_class = {
51 .name = "dss",
52 .sysc = &omap2_dss_sysc,
53};
54
55/*
56 * 'dispc' class
57 * display controller
58 */
59
60static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
61 .rev_offs = 0x0000,
62 .sysc_offs = 0x0010,
63 .syss_offs = 0x0014,
64 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
65 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
66 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
67 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
68 .sysc_fields = &omap_hwmod_sysc_type1,
69};
70
71struct omap_hwmod_class omap2_dispc_hwmod_class = {
72 .name = "dispc",
73 .sysc = &omap2_dispc_sysc,
74};
75
76/*
77 * 'rfbi' class
78 * remote frame buffer interface
79 */
80
81static struct omap_hwmod_class_sysconfig omap2_rfbi_sysc = {
82 .rev_offs = 0x0000,
83 .sysc_offs = 0x0010,
84 .syss_offs = 0x0014,
85 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
86 SYSC_HAS_AUTOIDLE),
87 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
88 .sysc_fields = &omap_hwmod_sysc_type1,
89};
90
91struct omap_hwmod_class omap2_rfbi_hwmod_class = {
92 .name = "rfbi",
93 .sysc = &omap2_rfbi_sysc,
94};
95
96/*
97 * 'venc' class
98 * video encoder
99 */
100
101struct omap_hwmod_class omap2_venc_hwmod_class = {
102 .name = "venc",
103};
104
105
106/* Common DMA request line data */
107struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = {
108 { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
109 { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
110 { .dma_req = -1 }
111};
112
113struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = {
114 { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
115 { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
116 { .dma_req = -1 }
117};
118
119struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = {
120 { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
121 { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
122 { .dma_req = -1 }
123};
124
125struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = {
126 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
127 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
128 { .dma_req = -1 }
129};
130
131struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = {
132 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
133 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
134 { .dma_req = -1 }
135};
136
137struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[] = {
138 { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
139 { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
140 { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
141 { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
142 { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
143 { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
144 { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
145 { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
146 { .dma_req = -1 }
147};
148
149struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[] = {
150 { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
151 { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
152 { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
153 { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
154 { .dma_req = -1 }
155};
156
157struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[] = {
158 { .name = "rx", .dma_req = 32 },
159 { .name = "tx", .dma_req = 31 },
160 { .dma_req = -1 }
161};
162
163struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[] = {
164 { .name = "rx", .dma_req = 34 },
165 { .name = "tx", .dma_req = 33 },
166 { .dma_req = -1 }
167};
168
169struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[] = {
170 { .name = "rx", .dma_req = 18 },
171 { .name = "tx", .dma_req = 17 },
172 { .dma_req = -1 }
173};
174
175/* Other IP block data */
176
177
178/*
179 * omap_hwmod class data
180 */
181
182struct omap_hwmod_class l3_hwmod_class = {
183 .name = "l3"
184};
185
186struct omap_hwmod_class l4_hwmod_class = {
187 .name = "l4"
188};
189
190struct omap_hwmod_class mpu_hwmod_class = {
191 .name = "mpu"
192};
193
194struct omap_hwmod_class iva_hwmod_class = {
195 .name = "iva"
196};
197
198/* Common MPU IRQ line data */
199
200struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = {
201 { .irq = 37, },
202 { .irq = -1 }
203};
204
205struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[] = {
206 { .irq = 38, },
207 { .irq = -1 }
208};
209
210struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[] = {
211 { .irq = 39, },
212 { .irq = -1 }
213};
214
215struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[] = {
216 { .irq = 40, },
217 { .irq = -1 }
218};
219
220struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[] = {
221 { .irq = 41, },
222 { .irq = -1 }
223};
224
225struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[] = {
226 { .irq = 42, },
227 { .irq = -1 }
228};
229
230struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[] = {
231 { .irq = 43, },
232 { .irq = -1 }
233};
234
235struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[] = {
236 { .irq = 44, },
237 { .irq = -1 }
238};
239
240struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[] = {
241 { .irq = 45, },
242 { .irq = -1 }
243};
244
245struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[] = {
246 { .irq = 46, },
247 { .irq = -1 }
248};
249
250struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = {
251 { .irq = 47, },
252 { .irq = -1 }
253};
254
255struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = {
256 { .irq = INT_24XX_UART1_IRQ, },
257 { .irq = -1 }
258};
259
260struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = {
261 { .irq = INT_24XX_UART2_IRQ, },
262 { .irq = -1 }
263};
264
265struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = {
266 { .irq = INT_24XX_UART3_IRQ, },
267 { .irq = -1 }
268};
269
270struct omap_hwmod_irq_info omap2_dispc_irqs[] = {
271 { .irq = 25 },
272 { .irq = -1 }
273};
274
275struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = {
276 { .irq = INT_24XX_I2C1_IRQ, },
277 { .irq = -1 }
278};
279
280struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = {
281 { .irq = INT_24XX_I2C2_IRQ, },
282 { .irq = -1 }
283};
284
285struct omap_hwmod_irq_info omap2_gpio1_irqs[] = {
286 { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
287 { .irq = -1 }
288};
289
290struct omap_hwmod_irq_info omap2_gpio2_irqs[] = {
291 { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
292 { .irq = -1 }
293};
294
295struct omap_hwmod_irq_info omap2_gpio3_irqs[] = {
296 { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
297 { .irq = -1 }
298};
299
300struct omap_hwmod_irq_info omap2_gpio4_irqs[] = {
301 { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
302 { .irq = -1 }
303};
304
305struct omap_hwmod_irq_info omap2_dma_system_irqs[] = {
306 { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
307 { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
308 { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
309 { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
310 { .irq = -1 }
311};
312
313struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[] = {
314 { .irq = 65 },
315 { .irq = -1 }
316};
317
318struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = {
319 { .irq = 66 },
320 { .irq = -1 }
321};
322