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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/arch/arm/mach-omap2/io.c
4 *
5 * OMAP2 I/O mapping code
6 *
7 * Copyright (C) 2005 Nokia Corporation
8 * Copyright (C) 2007-2009 Texas Instruments
9 *
10 * Author:
11 * Juha Yrjola <juha.yrjola@nokia.com>
12 * Syed Khasim <x0khasim@ti.com>
13 *
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
15 */
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/io.h>
20#include <linux/clk.h>
21
22#include <asm/tlb.h>
23#include <asm/mach/map.h>
24
25#include <linux/omap-dma.h>
26
27#include "omap_hwmod.h"
28#include "soc.h"
29#include "iomap.h"
30#include "voltage.h"
31#include "powerdomain.h"
32#include "clockdomain.h"
33#include "common.h"
34#include "clock.h"
35#include "sdrc.h"
36#include "control.h"
37#include "sram.h"
38#include "cm2xxx.h"
39#include "cm3xxx.h"
40#include "cm33xx.h"
41#include "cm44xx.h"
42#include "prm.h"
43#include "cm.h"
44#include "prcm_mpu44xx.h"
45#include "prminst44xx.h"
46#include "prm2xxx.h"
47#include "prm3xxx.h"
48#include "prm33xx.h"
49#include "prm44xx.h"
50#include "opp2xxx.h"
51#include "omap-secure.h"
52
53/*
54 * omap_clk_soc_init: points to a function that does the SoC-specific
55 * clock initializations
56 */
57static int (*omap_clk_soc_init)(void);
58
59/*
60 * The machine specific code may provide the extra mapping besides the
61 * default mapping provided here.
62 */
63
64#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
65static struct map_desc omap24xx_io_desc[] __initdata = {
66 {
67 .virtual = L3_24XX_VIRT,
68 .pfn = __phys_to_pfn(L3_24XX_PHYS),
69 .length = L3_24XX_SIZE,
70 .type = MT_DEVICE
71 },
72 {
73 .virtual = L4_24XX_VIRT,
74 .pfn = __phys_to_pfn(L4_24XX_PHYS),
75 .length = L4_24XX_SIZE,
76 .type = MT_DEVICE
77 },
78};
79
80#ifdef CONFIG_SOC_OMAP2420
81static struct map_desc omap242x_io_desc[] __initdata = {
82 {
83 .virtual = DSP_MEM_2420_VIRT,
84 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
85 .length = DSP_MEM_2420_SIZE,
86 .type = MT_DEVICE
87 },
88 {
89 .virtual = DSP_IPI_2420_VIRT,
90 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
91 .length = DSP_IPI_2420_SIZE,
92 .type = MT_DEVICE
93 },
94 {
95 .virtual = DSP_MMU_2420_VIRT,
96 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
97 .length = DSP_MMU_2420_SIZE,
98 .type = MT_DEVICE
99 },
100};
101
102#endif
103
104#ifdef CONFIG_SOC_OMAP2430
105static struct map_desc omap243x_io_desc[] __initdata = {
106 {
107 .virtual = L4_WK_243X_VIRT,
108 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
109 .length = L4_WK_243X_SIZE,
110 .type = MT_DEVICE
111 },
112 {
113 .virtual = OMAP243X_GPMC_VIRT,
114 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
115 .length = OMAP243X_GPMC_SIZE,
116 .type = MT_DEVICE
117 },
118 {
119 .virtual = OMAP243X_SDRC_VIRT,
120 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
121 .length = OMAP243X_SDRC_SIZE,
122 .type = MT_DEVICE
123 },
124 {
125 .virtual = OMAP243X_SMS_VIRT,
126 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
127 .length = OMAP243X_SMS_SIZE,
128 .type = MT_DEVICE
129 },
130};
131#endif
132#endif
133
134#ifdef CONFIG_ARCH_OMAP3
135static struct map_desc omap34xx_io_desc[] __initdata = {
136 {
137 .virtual = L3_34XX_VIRT,
138 .pfn = __phys_to_pfn(L3_34XX_PHYS),
139 .length = L3_34XX_SIZE,
140 .type = MT_DEVICE
141 },
142 {
143 .virtual = L4_34XX_VIRT,
144 .pfn = __phys_to_pfn(L4_34XX_PHYS),
145 .length = L4_34XX_SIZE,
146 .type = MT_DEVICE
147 },
148 {
149 .virtual = OMAP34XX_GPMC_VIRT,
150 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
151 .length = OMAP34XX_GPMC_SIZE,
152 .type = MT_DEVICE
153 },
154 {
155 .virtual = OMAP343X_SMS_VIRT,
156 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
157 .length = OMAP343X_SMS_SIZE,
158 .type = MT_DEVICE
159 },
160 {
161 .virtual = OMAP343X_SDRC_VIRT,
162 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
163 .length = OMAP343X_SDRC_SIZE,
164 .type = MT_DEVICE
165 },
166 {
167 .virtual = L4_PER_34XX_VIRT,
168 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
169 .length = L4_PER_34XX_SIZE,
170 .type = MT_DEVICE
171 },
172 {
173 .virtual = L4_EMU_34XX_VIRT,
174 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
175 .length = L4_EMU_34XX_SIZE,
176 .type = MT_DEVICE
177 },
178};
179#endif
180
181#ifdef CONFIG_SOC_TI81XX
182static struct map_desc omapti81xx_io_desc[] __initdata = {
183 {
184 .virtual = L4_34XX_VIRT,
185 .pfn = __phys_to_pfn(L4_34XX_PHYS),
186 .length = L4_34XX_SIZE,
187 .type = MT_DEVICE
188 }
189};
190#endif
191
192#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
193static struct map_desc omapam33xx_io_desc[] __initdata = {
194 {
195 .virtual = L4_34XX_VIRT,
196 .pfn = __phys_to_pfn(L4_34XX_PHYS),
197 .length = L4_34XX_SIZE,
198 .type = MT_DEVICE
199 },
200 {
201 .virtual = L4_WK_AM33XX_VIRT,
202 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
203 .length = L4_WK_AM33XX_SIZE,
204 .type = MT_DEVICE
205 }
206};
207#endif
208
209#ifdef CONFIG_ARCH_OMAP4
210static struct map_desc omap44xx_io_desc[] __initdata = {
211 {
212 .virtual = L3_44XX_VIRT,
213 .pfn = __phys_to_pfn(L3_44XX_PHYS),
214 .length = L3_44XX_SIZE,
215 .type = MT_DEVICE,
216 },
217 {
218 .virtual = L4_44XX_VIRT,
219 .pfn = __phys_to_pfn(L4_44XX_PHYS),
220 .length = L4_44XX_SIZE,
221 .type = MT_DEVICE,
222 },
223 {
224 .virtual = L4_PER_44XX_VIRT,
225 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
226 .length = L4_PER_44XX_SIZE,
227 .type = MT_DEVICE,
228 },
229};
230#endif
231
232#ifdef CONFIG_SOC_OMAP5
233static struct map_desc omap54xx_io_desc[] __initdata = {
234 {
235 .virtual = L3_54XX_VIRT,
236 .pfn = __phys_to_pfn(L3_54XX_PHYS),
237 .length = L3_54XX_SIZE,
238 .type = MT_DEVICE,
239 },
240 {
241 .virtual = L4_54XX_VIRT,
242 .pfn = __phys_to_pfn(L4_54XX_PHYS),
243 .length = L4_54XX_SIZE,
244 .type = MT_DEVICE,
245 },
246 {
247 .virtual = L4_WK_54XX_VIRT,
248 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
249 .length = L4_WK_54XX_SIZE,
250 .type = MT_DEVICE,
251 },
252 {
253 .virtual = L4_PER_54XX_VIRT,
254 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
255 .length = L4_PER_54XX_SIZE,
256 .type = MT_DEVICE,
257 },
258};
259#endif
260
261#ifdef CONFIG_SOC_DRA7XX
262static struct map_desc dra7xx_io_desc[] __initdata = {
263 {
264 .virtual = L4_CFG_MPU_DRA7XX_VIRT,
265 .pfn = __phys_to_pfn(L4_CFG_MPU_DRA7XX_PHYS),
266 .length = L4_CFG_MPU_DRA7XX_SIZE,
267 .type = MT_DEVICE,
268 },
269 {
270 .virtual = L3_MAIN_SN_DRA7XX_VIRT,
271 .pfn = __phys_to_pfn(L3_MAIN_SN_DRA7XX_PHYS),
272 .length = L3_MAIN_SN_DRA7XX_SIZE,
273 .type = MT_DEVICE,
274 },
275 {
276 .virtual = L4_PER1_DRA7XX_VIRT,
277 .pfn = __phys_to_pfn(L4_PER1_DRA7XX_PHYS),
278 .length = L4_PER1_DRA7XX_SIZE,
279 .type = MT_DEVICE,
280 },
281 {
282 .virtual = L4_PER2_DRA7XX_VIRT,
283 .pfn = __phys_to_pfn(L4_PER2_DRA7XX_PHYS),
284 .length = L4_PER2_DRA7XX_SIZE,
285 .type = MT_DEVICE,
286 },
287 {
288 .virtual = L4_PER3_DRA7XX_VIRT,
289 .pfn = __phys_to_pfn(L4_PER3_DRA7XX_PHYS),
290 .length = L4_PER3_DRA7XX_SIZE,
291 .type = MT_DEVICE,
292 },
293 {
294 .virtual = L4_CFG_DRA7XX_VIRT,
295 .pfn = __phys_to_pfn(L4_CFG_DRA7XX_PHYS),
296 .length = L4_CFG_DRA7XX_SIZE,
297 .type = MT_DEVICE,
298 },
299 {
300 .virtual = L4_WKUP_DRA7XX_VIRT,
301 .pfn = __phys_to_pfn(L4_WKUP_DRA7XX_PHYS),
302 .length = L4_WKUP_DRA7XX_SIZE,
303 .type = MT_DEVICE,
304 },
305};
306#endif
307
308#ifdef CONFIG_SOC_OMAP2420
309void __init omap242x_map_io(void)
310{
311 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
312 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
313}
314#endif
315
316#ifdef CONFIG_SOC_OMAP2430
317void __init omap243x_map_io(void)
318{
319 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
320 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
321}
322#endif
323
324#ifdef CONFIG_ARCH_OMAP3
325void __init omap3_map_io(void)
326{
327 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
328}
329#endif
330
331#ifdef CONFIG_SOC_TI81XX
332void __init ti81xx_map_io(void)
333{
334 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
335}
336#endif
337
338#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
339void __init am33xx_map_io(void)
340{
341 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
342}
343#endif
344
345#ifdef CONFIG_ARCH_OMAP4
346void __init omap4_map_io(void)
347{
348 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
349 omap_barriers_init();
350}
351#endif
352
353#ifdef CONFIG_SOC_OMAP5
354void __init omap5_map_io(void)
355{
356 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
357 omap_barriers_init();
358}
359#endif
360
361#ifdef CONFIG_SOC_DRA7XX
362void __init dra7xx_map_io(void)
363{
364 iotable_init(dra7xx_io_desc, ARRAY_SIZE(dra7xx_io_desc));
365 omap_barriers_init();
366}
367#endif
368/*
369 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
370 *
371 * Sets the CORE DPLL3 M2 divider to the same value that it's at
372 * currently. This has the effect of setting the SDRC SDRAM AC timing
373 * registers to the values currently defined by the kernel. Currently
374 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
375 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
376 * or passes along the return value of clk_set_rate().
377 */
378static int __init _omap2_init_reprogram_sdrc(void)
379{
380 struct clk *dpll3_m2_ck;
381 int v = -EINVAL;
382 long rate;
383
384 if (!cpu_is_omap34xx())
385 return 0;
386
387 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
388 if (IS_ERR(dpll3_m2_ck))
389 return -EINVAL;
390
391 rate = clk_get_rate(dpll3_m2_ck);
392 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
393 v = clk_set_rate(dpll3_m2_ck, rate);
394 if (v)
395 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
396
397 clk_put(dpll3_m2_ck);
398
399 return v;
400}
401
402#ifdef CONFIG_OMAP_HWMOD
403static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
404{
405 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
406}
407
408static void __init __maybe_unused omap_hwmod_init_postsetup(void)
409{
410 u8 postsetup_state = _HWMOD_STATE_DEFAULT;
411
412 /* Set the default postsetup state for all hwmods */
413 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
414}
415#else
416static inline void omap_hwmod_init_postsetup(void)
417{
418}
419#endif
420
421#ifdef CONFIG_SOC_OMAP2420
422void __init omap2420_init_early(void)
423{
424 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
425 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
426 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
427 omap2_control_base_init();
428 omap2xxx_check_revision();
429 omap2_prcm_base_init();
430 omap2xxx_voltagedomains_init();
431 omap242x_powerdomains_init();
432 omap242x_clockdomains_init();
433 omap2420_hwmod_init();
434 omap_hwmod_init_postsetup();
435 omap_clk_soc_init = omap2420_dt_clk_init;
436 rate_table = omap2420_rate_table;
437}
438#endif
439
440#ifdef CONFIG_SOC_OMAP2430
441void __init omap2430_init_early(void)
442{
443 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
444 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
445 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
446 omap2_control_base_init();
447 omap2xxx_check_revision();
448 omap2_prcm_base_init();
449 omap2xxx_voltagedomains_init();
450 omap243x_powerdomains_init();
451 omap243x_clockdomains_init();
452 omap2430_hwmod_init();
453 omap_hwmod_init_postsetup();
454 omap_clk_soc_init = omap2430_dt_clk_init;
455 rate_table = omap2430_rate_table;
456}
457#endif
458
459/*
460 * Currently only board-omap3beagle.c should call this because of the
461 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
462 */
463#ifdef CONFIG_ARCH_OMAP3
464static void __init omap3_init_early(void)
465{
466 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
467 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
468 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
469 omap2_control_base_init();
470 omap3xxx_check_revision();
471 omap3xxx_check_features();
472 omap2_prcm_base_init();
473 omap3xxx_voltagedomains_init();
474 omap3xxx_powerdomains_init();
475 omap3xxx_clockdomains_init();
476 omap3xxx_hwmod_init();
477 omap_hwmod_init_postsetup();
478 omap_secure_init();
479}
480
481void __init omap3430_init_early(void)
482{
483 omap3_init_early();
484 omap_clk_soc_init = omap3430_dt_clk_init;
485}
486
487void __init omap3630_init_early(void)
488{
489 omap3_init_early();
490 omap_clk_soc_init = omap3630_dt_clk_init;
491}
492
493void __init am35xx_init_early(void)
494{
495 omap3_init_early();
496 omap_clk_soc_init = am35xx_dt_clk_init;
497}
498
499void __init omap3_init_late(void)
500{
501 omap_pm_soc_init = omap3_pm_init;
502}
503
504void __init ti81xx_init_late(void)
505{
506 omap_pm_soc_init = omap_pm_nop_init;
507}
508#endif
509
510#ifdef CONFIG_SOC_TI81XX
511void __init ti814x_init_early(void)
512{
513 omap2_set_globals_tap(TI814X_CLASS,
514 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
515 omap2_control_base_init();
516 omap3xxx_check_revision();
517 ti81xx_check_features();
518 omap2_prcm_base_init();
519 omap3xxx_voltagedomains_init();
520 omap3xxx_powerdomains_init();
521 ti814x_clockdomains_init();
522 dm814x_hwmod_init();
523 omap_hwmod_init_postsetup();
524 omap_clk_soc_init = dm814x_dt_clk_init;
525 omap_secure_init();
526}
527
528void __init ti816x_init_early(void)
529{
530 omap2_set_globals_tap(TI816X_CLASS,
531 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
532 omap2_control_base_init();
533 omap3xxx_check_revision();
534 ti81xx_check_features();
535 omap2_prcm_base_init();
536 omap3xxx_voltagedomains_init();
537 omap3xxx_powerdomains_init();
538 ti816x_clockdomains_init();
539 dm816x_hwmod_init();
540 omap_hwmod_init_postsetup();
541 omap_clk_soc_init = dm816x_dt_clk_init;
542 omap_secure_init();
543}
544#endif
545
546#ifdef CONFIG_SOC_AM33XX
547void __init am33xx_init_early(void)
548{
549 omap2_set_globals_tap(AM335X_CLASS,
550 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
551 omap2_control_base_init();
552 omap3xxx_check_revision();
553 am33xx_check_features();
554 omap2_prcm_base_init();
555 am33xx_powerdomains_init();
556 am33xx_clockdomains_init();
557 omap_clk_soc_init = am33xx_dt_clk_init;
558 omap_secure_init();
559}
560
561void __init am33xx_init_late(void)
562{
563 omap_pm_soc_init = amx3_common_pm_init;
564}
565#endif
566
567#ifdef CONFIG_SOC_AM43XX
568void __init am43xx_init_early(void)
569{
570 omap2_set_globals_tap(AM335X_CLASS,
571 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
572 omap2_control_base_init();
573 omap3xxx_check_revision();
574 am33xx_check_features();
575 omap2_prcm_base_init();
576 am43xx_powerdomains_init();
577 am43xx_clockdomains_init();
578 omap_l2_cache_init();
579 omap_clk_soc_init = am43xx_dt_clk_init;
580 omap_secure_init();
581}
582
583void __init am43xx_init_late(void)
584{
585 omap_pm_soc_init = amx3_common_pm_init;
586}
587#endif
588
589#ifdef CONFIG_ARCH_OMAP4
590void __init omap4430_init_early(void)
591{
592 omap2_set_globals_tap(OMAP443X_CLASS,
593 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
594 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
595 omap2_control_base_init();
596 omap4xxx_check_revision();
597 omap4xxx_check_features();
598 omap2_prcm_base_init();
599 omap4_sar_ram_init();
600 omap4_mpuss_early_init();
601 omap4_pm_init_early();
602 omap44xx_voltagedomains_init();
603 omap44xx_powerdomains_init();
604 omap44xx_clockdomains_init();
605 omap_l2_cache_init();
606 omap_clk_soc_init = omap4xxx_dt_clk_init;
607 omap_secure_init();
608}
609
610void __init omap4430_init_late(void)
611{
612 omap_pm_soc_init = omap4_pm_init;
613}
614#endif
615
616#ifdef CONFIG_SOC_OMAP5
617void __init omap5_init_early(void)
618{
619 omap2_set_globals_tap(OMAP54XX_CLASS,
620 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
621 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
622 omap2_control_base_init();
623 omap2_prcm_base_init();
624 omap5xxx_check_revision();
625 omap4_sar_ram_init();
626 omap4_mpuss_early_init();
627 omap4_pm_init_early();
628 omap54xx_voltagedomains_init();
629 omap54xx_powerdomains_init();
630 omap54xx_clockdomains_init();
631 omap_clk_soc_init = omap5xxx_dt_clk_init;
632 omap_secure_init();
633}
634
635void __init omap5_init_late(void)
636{
637 omap_pm_soc_init = omap4_pm_init;
638}
639#endif
640
641#ifdef CONFIG_SOC_DRA7XX
642void __init dra7xx_init_early(void)
643{
644 omap2_set_globals_tap(DRA7XX_CLASS,
645 OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
646 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
647 omap2_control_base_init();
648 omap4_pm_init_early();
649 omap2_prcm_base_init();
650 dra7xxx_check_revision();
651 dra7xx_powerdomains_init();
652 dra7xx_clockdomains_init();
653 omap_clk_soc_init = dra7xx_dt_clk_init;
654 omap_secure_init();
655}
656
657void __init dra7xx_init_late(void)
658{
659 omap_pm_soc_init = omap4_pm_init;
660}
661#endif
662
663
664void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
665 struct omap_sdrc_params *sdrc_cs1)
666{
667 omap_sram_init();
668
669 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
670 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
671 _omap2_init_reprogram_sdrc();
672 }
673}
674
675int __init omap_clk_init(void)
676{
677 int ret = 0;
678
679 if (!omap_clk_soc_init)
680 return 0;
681
682 ti_clk_init_features();
683
684 omap2_clk_setup_ll_ops();
685
686 ret = omap_control_init();
687 if (ret)
688 return ret;
689
690 ret = omap_prcm_init();
691 if (ret)
692 return ret;
693
694 of_clk_init(NULL);
695
696 ti_dt_clk_init_retry_clks();
697
698 ti_dt_clockdomains_setup();
699
700 ret = omap_clk_soc_init();
701
702 return ret;
703}
1/*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments
8 *
9 * Author:
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
12 *
13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/io.h>
24#include <linux/clk.h>
25#include <linux/omapfb.h>
26
27#include <asm/tlb.h>
28
29#include <asm/mach/map.h>
30
31#include <plat/sram.h>
32#include <plat/sdrc.h>
33#include <plat/serial.h>
34
35#include "clock2xxx.h"
36#include "clock3xxx.h"
37#include "clock44xx.h"
38#include "io.h"
39
40#include <plat/omap-pm.h>
41#include "powerdomain.h"
42
43#include "clockdomain.h"
44#include <plat/omap_hwmod.h>
45#include <plat/multi.h>
46
47/*
48 * The machine specific code may provide the extra mapping besides the
49 * default mapping provided here.
50 */
51
52#ifdef CONFIG_ARCH_OMAP2
53static struct map_desc omap24xx_io_desc[] __initdata = {
54 {
55 .virtual = L3_24XX_VIRT,
56 .pfn = __phys_to_pfn(L3_24XX_PHYS),
57 .length = L3_24XX_SIZE,
58 .type = MT_DEVICE
59 },
60 {
61 .virtual = L4_24XX_VIRT,
62 .pfn = __phys_to_pfn(L4_24XX_PHYS),
63 .length = L4_24XX_SIZE,
64 .type = MT_DEVICE
65 },
66};
67
68#ifdef CONFIG_SOC_OMAP2420
69static struct map_desc omap242x_io_desc[] __initdata = {
70 {
71 .virtual = DSP_MEM_2420_VIRT,
72 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
73 .length = DSP_MEM_2420_SIZE,
74 .type = MT_DEVICE
75 },
76 {
77 .virtual = DSP_IPI_2420_VIRT,
78 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
79 .length = DSP_IPI_2420_SIZE,
80 .type = MT_DEVICE
81 },
82 {
83 .virtual = DSP_MMU_2420_VIRT,
84 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
85 .length = DSP_MMU_2420_SIZE,
86 .type = MT_DEVICE
87 },
88};
89
90#endif
91
92#ifdef CONFIG_SOC_OMAP2430
93static struct map_desc omap243x_io_desc[] __initdata = {
94 {
95 .virtual = L4_WK_243X_VIRT,
96 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
97 .length = L4_WK_243X_SIZE,
98 .type = MT_DEVICE
99 },
100 {
101 .virtual = OMAP243X_GPMC_VIRT,
102 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
103 .length = OMAP243X_GPMC_SIZE,
104 .type = MT_DEVICE
105 },
106 {
107 .virtual = OMAP243X_SDRC_VIRT,
108 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
109 .length = OMAP243X_SDRC_SIZE,
110 .type = MT_DEVICE
111 },
112 {
113 .virtual = OMAP243X_SMS_VIRT,
114 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
115 .length = OMAP243X_SMS_SIZE,
116 .type = MT_DEVICE
117 },
118};
119#endif
120#endif
121
122#ifdef CONFIG_ARCH_OMAP3
123static struct map_desc omap34xx_io_desc[] __initdata = {
124 {
125 .virtual = L3_34XX_VIRT,
126 .pfn = __phys_to_pfn(L3_34XX_PHYS),
127 .length = L3_34XX_SIZE,
128 .type = MT_DEVICE
129 },
130 {
131 .virtual = L4_34XX_VIRT,
132 .pfn = __phys_to_pfn(L4_34XX_PHYS),
133 .length = L4_34XX_SIZE,
134 .type = MT_DEVICE
135 },
136 {
137 .virtual = OMAP34XX_GPMC_VIRT,
138 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
139 .length = OMAP34XX_GPMC_SIZE,
140 .type = MT_DEVICE
141 },
142 {
143 .virtual = OMAP343X_SMS_VIRT,
144 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
145 .length = OMAP343X_SMS_SIZE,
146 .type = MT_DEVICE
147 },
148 {
149 .virtual = OMAP343X_SDRC_VIRT,
150 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
151 .length = OMAP343X_SDRC_SIZE,
152 .type = MT_DEVICE
153 },
154 {
155 .virtual = L4_PER_34XX_VIRT,
156 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
157 .length = L4_PER_34XX_SIZE,
158 .type = MT_DEVICE
159 },
160 {
161 .virtual = L4_EMU_34XX_VIRT,
162 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
163 .length = L4_EMU_34XX_SIZE,
164 .type = MT_DEVICE
165 },
166#if defined(CONFIG_DEBUG_LL) && \
167 (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3))
168 {
169 .virtual = ZOOM_UART_VIRT,
170 .pfn = __phys_to_pfn(ZOOM_UART_BASE),
171 .length = SZ_1M,
172 .type = MT_DEVICE
173 },
174#endif
175};
176#endif
177
178#ifdef CONFIG_SOC_OMAPTI816X
179static struct map_desc omapti816x_io_desc[] __initdata = {
180 {
181 .virtual = L4_34XX_VIRT,
182 .pfn = __phys_to_pfn(L4_34XX_PHYS),
183 .length = L4_34XX_SIZE,
184 .type = MT_DEVICE
185 },
186};
187#endif
188
189#ifdef CONFIG_ARCH_OMAP4
190static struct map_desc omap44xx_io_desc[] __initdata = {
191 {
192 .virtual = L3_44XX_VIRT,
193 .pfn = __phys_to_pfn(L3_44XX_PHYS),
194 .length = L3_44XX_SIZE,
195 .type = MT_DEVICE,
196 },
197 {
198 .virtual = L4_44XX_VIRT,
199 .pfn = __phys_to_pfn(L4_44XX_PHYS),
200 .length = L4_44XX_SIZE,
201 .type = MT_DEVICE,
202 },
203 {
204 .virtual = OMAP44XX_GPMC_VIRT,
205 .pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS),
206 .length = OMAP44XX_GPMC_SIZE,
207 .type = MT_DEVICE,
208 },
209 {
210 .virtual = OMAP44XX_EMIF1_VIRT,
211 .pfn = __phys_to_pfn(OMAP44XX_EMIF1_PHYS),
212 .length = OMAP44XX_EMIF1_SIZE,
213 .type = MT_DEVICE,
214 },
215 {
216 .virtual = OMAP44XX_EMIF2_VIRT,
217 .pfn = __phys_to_pfn(OMAP44XX_EMIF2_PHYS),
218 .length = OMAP44XX_EMIF2_SIZE,
219 .type = MT_DEVICE,
220 },
221 {
222 .virtual = OMAP44XX_DMM_VIRT,
223 .pfn = __phys_to_pfn(OMAP44XX_DMM_PHYS),
224 .length = OMAP44XX_DMM_SIZE,
225 .type = MT_DEVICE,
226 },
227 {
228 .virtual = L4_PER_44XX_VIRT,
229 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
230 .length = L4_PER_44XX_SIZE,
231 .type = MT_DEVICE,
232 },
233 {
234 .virtual = L4_EMU_44XX_VIRT,
235 .pfn = __phys_to_pfn(L4_EMU_44XX_PHYS),
236 .length = L4_EMU_44XX_SIZE,
237 .type = MT_DEVICE,
238 },
239};
240#endif
241
242static void __init _omap2_map_common_io(void)
243{
244 /* Normally devicemaps_init() would flush caches and tlb after
245 * mdesc->map_io(), but we must also do it here because of the CPU
246 * revision check below.
247 */
248 local_flush_tlb_all();
249 flush_cache_all();
250
251 omap2_check_revision();
252 omap_sram_init();
253}
254
255#ifdef CONFIG_SOC_OMAP2420
256void __init omap242x_map_common_io(void)
257{
258 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
259 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
260 _omap2_map_common_io();
261}
262#endif
263
264#ifdef CONFIG_SOC_OMAP2430
265void __init omap243x_map_common_io(void)
266{
267 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
268 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
269 _omap2_map_common_io();
270}
271#endif
272
273#ifdef CONFIG_ARCH_OMAP3
274void __init omap34xx_map_common_io(void)
275{
276 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
277 _omap2_map_common_io();
278}
279#endif
280
281#ifdef CONFIG_SOC_OMAPTI816X
282void __init omapti816x_map_common_io(void)
283{
284 iotable_init(omapti816x_io_desc, ARRAY_SIZE(omapti816x_io_desc));
285 _omap2_map_common_io();
286}
287#endif
288
289#ifdef CONFIG_ARCH_OMAP4
290void __init omap44xx_map_common_io(void)
291{
292 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
293 _omap2_map_common_io();
294}
295#endif
296
297/*
298 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
299 *
300 * Sets the CORE DPLL3 M2 divider to the same value that it's at
301 * currently. This has the effect of setting the SDRC SDRAM AC timing
302 * registers to the values currently defined by the kernel. Currently
303 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
304 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
305 * or passes along the return value of clk_set_rate().
306 */
307static int __init _omap2_init_reprogram_sdrc(void)
308{
309 struct clk *dpll3_m2_ck;
310 int v = -EINVAL;
311 long rate;
312
313 if (!cpu_is_omap34xx())
314 return 0;
315
316 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
317 if (IS_ERR(dpll3_m2_ck))
318 return -EINVAL;
319
320 rate = clk_get_rate(dpll3_m2_ck);
321 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
322 v = clk_set_rate(dpll3_m2_ck, rate);
323 if (v)
324 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
325
326 clk_put(dpll3_m2_ck);
327
328 return v;
329}
330
331static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
332{
333 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
334}
335
336/* See irq.c, omap4-common.c and entry-macro.S */
337void __iomem *omap_irq_base;
338
339void __init omap2_init_common_infrastructure(void)
340{
341 u8 postsetup_state;
342
343 if (cpu_is_omap242x()) {
344 omap2xxx_powerdomains_init();
345 omap2xxx_clockdomains_init();
346 omap2420_hwmod_init();
347 } else if (cpu_is_omap243x()) {
348 omap2xxx_powerdomains_init();
349 omap2xxx_clockdomains_init();
350 omap2430_hwmod_init();
351 } else if (cpu_is_omap34xx()) {
352 omap3xxx_powerdomains_init();
353 omap3xxx_clockdomains_init();
354 omap3xxx_hwmod_init();
355 } else if (cpu_is_omap44xx()) {
356 omap44xx_powerdomains_init();
357 omap44xx_clockdomains_init();
358 omap44xx_hwmod_init();
359 } else {
360 pr_err("Could not init hwmod data - unknown SoC\n");
361 }
362
363 /* Set the default postsetup state for all hwmods */
364#ifdef CONFIG_PM_RUNTIME
365 postsetup_state = _HWMOD_STATE_IDLE;
366#else
367 postsetup_state = _HWMOD_STATE_ENABLED;
368#endif
369 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
370
371 /*
372 * Set the default postsetup state for unusual modules (like
373 * MPU WDT).
374 *
375 * The postsetup_state is not actually used until
376 * omap_hwmod_late_init(), so boards that desire full watchdog
377 * coverage of kernel initialization can reprogram the
378 * postsetup_state between the calls to
379 * omap2_init_common_infra() and omap2_init_common_devices().
380 *
381 * XXX ideally we could detect whether the MPU WDT was currently
382 * enabled here and make this conditional
383 */
384 postsetup_state = _HWMOD_STATE_DISABLED;
385 omap_hwmod_for_each_by_class("wd_timer",
386 _set_hwmod_postsetup_state,
387 &postsetup_state);
388
389 omap_pm_if_early_init();
390
391 if (cpu_is_omap2420())
392 omap2420_clk_init();
393 else if (cpu_is_omap2430())
394 omap2430_clk_init();
395 else if (cpu_is_omap34xx())
396 omap3xxx_clk_init();
397 else if (cpu_is_omap44xx())
398 omap4xxx_clk_init();
399 else
400 pr_err("Could not init clock framework - unknown SoC\n");
401}
402
403void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
404 struct omap_sdrc_params *sdrc_cs1)
405{
406 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
407 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
408 _omap2_init_reprogram_sdrc();
409 }
410
411}
412
413/*
414 * NOTE: Please use ioremap + __raw_read/write where possible instead of these
415 */
416
417u8 omap_readb(u32 pa)
418{
419 return __raw_readb(OMAP2_L4_IO_ADDRESS(pa));
420}
421EXPORT_SYMBOL(omap_readb);
422
423u16 omap_readw(u32 pa)
424{
425 return __raw_readw(OMAP2_L4_IO_ADDRESS(pa));
426}
427EXPORT_SYMBOL(omap_readw);
428
429u32 omap_readl(u32 pa)
430{
431 return __raw_readl(OMAP2_L4_IO_ADDRESS(pa));
432}
433EXPORT_SYMBOL(omap_readl);
434
435void omap_writeb(u8 v, u32 pa)
436{
437 __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa));
438}
439EXPORT_SYMBOL(omap_writeb);
440
441void omap_writew(u16 v, u32 pa)
442{
443 __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
444}
445EXPORT_SYMBOL(omap_writew);
446
447void omap_writel(u32 v, u32 pa)
448{
449 __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa));
450}
451EXPORT_SYMBOL(omap_writel);