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1/*
2 * linux/arch/arm/mach-omap2/hsmmc.c
3 *
4 * Copyright (C) 2007-2008 Texas Instruments
5 * Copyright (C) 2008 Nokia Corporation
6 * Author: Texas Instruments
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12#include <linux/kernel.h>
13#include <linux/slab.h>
14#include <linux/string.h>
15#include <linux/delay.h>
16#include <linux/gpio.h>
17#include <mach/hardware.h>
18#include <plat/mmc.h>
19#include <plat/omap-pm.h>
20#include <plat/mux.h>
21#include <plat/omap_device.h>
22
23#include "mux.h"
24#include "hsmmc.h"
25#include "control.h"
26
27#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
28
29static u16 control_pbias_offset;
30static u16 control_devconf1_offset;
31static u16 control_mmc1;
32
33#define HSMMC_NAME_LEN 9
34
35#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
36
37static int hsmmc_get_context_loss(struct device *dev)
38{
39 return omap_pm_get_dev_context_loss_count(dev);
40}
41
42#else
43#define hsmmc_get_context_loss NULL
44#endif
45
46static void omap_hsmmc1_before_set_reg(struct device *dev, int slot,
47 int power_on, int vdd)
48{
49 u32 reg, prog_io;
50 struct omap_mmc_platform_data *mmc = dev->platform_data;
51
52 if (mmc->slots[0].remux)
53 mmc->slots[0].remux(dev, slot, power_on);
54
55 /*
56 * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
57 * card with Vcc regulator (from twl4030 or whatever). OMAP has both
58 * 1.8V and 3.0V modes, controlled by the PBIAS register.
59 *
60 * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
61 * is most naturally TWL VSIM; those pins also use PBIAS.
62 *
63 * FIXME handle VMMC1A as needed ...
64 */
65 if (power_on) {
66 if (cpu_is_omap2430()) {
67 reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
68 if ((1 << vdd) >= MMC_VDD_30_31)
69 reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE;
70 else
71 reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
72 omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
73 }
74
75 if (mmc->slots[0].internal_clock) {
76 reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
77 reg |= OMAP2_MMCSDIO1ADPCLKISEL;
78 omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
79 }
80
81 reg = omap_ctrl_readl(control_pbias_offset);
82 if (cpu_is_omap3630()) {
83 /* Set MMC I/O to 52Mhz */
84 prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
85 prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL;
86 omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);
87 } else {
88 reg |= OMAP2_PBIASSPEEDCTRL0;
89 }
90 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
91 omap_ctrl_writel(reg, control_pbias_offset);
92 } else {
93 reg = omap_ctrl_readl(control_pbias_offset);
94 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
95 omap_ctrl_writel(reg, control_pbias_offset);
96 }
97}
98
99static void omap_hsmmc1_after_set_reg(struct device *dev, int slot,
100 int power_on, int vdd)
101{
102 u32 reg;
103
104 /* 100ms delay required for PBIAS configuration */
105 msleep(100);
106
107 if (power_on) {
108 reg = omap_ctrl_readl(control_pbias_offset);
109 reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
110 if ((1 << vdd) <= MMC_VDD_165_195)
111 reg &= ~OMAP2_PBIASLITEVMODE0;
112 else
113 reg |= OMAP2_PBIASLITEVMODE0;
114 omap_ctrl_writel(reg, control_pbias_offset);
115 } else {
116 reg = omap_ctrl_readl(control_pbias_offset);
117 reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
118 OMAP2_PBIASLITEVMODE0);
119 omap_ctrl_writel(reg, control_pbias_offset);
120 }
121}
122
123static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
124 int power_on, int vdd)
125{
126 u32 reg;
127
128 /*
129 * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
130 * card with Vcc regulator (from twl4030 or whatever). OMAP has both
131 * 1.8V and 3.0V modes, controlled by the PBIAS register.
132 *
133 * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
134 * is most naturally TWL VSIM; those pins also use PBIAS.
135 *
136 * FIXME handle VMMC1A as needed ...
137 */
138 reg = omap4_ctrl_pad_readl(control_pbias_offset);
139 reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
140 OMAP4_MMC1_PWRDNZ_MASK);
141 omap4_ctrl_pad_writel(reg, control_pbias_offset);
142}
143
144static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
145 int power_on, int vdd)
146{
147 u32 reg;
148 unsigned long timeout;
149
150 if (power_on) {
151 reg = omap4_ctrl_pad_readl(control_pbias_offset);
152 reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK;
153 if ((1 << vdd) <= MMC_VDD_165_195)
154 reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK;
155 else
156 reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK;
157 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
158 OMAP4_MMC1_PWRDNZ_MASK);
159 omap4_ctrl_pad_writel(reg, control_pbias_offset);
160
161 timeout = jiffies + msecs_to_jiffies(5);
162 do {
163 reg = omap4_ctrl_pad_readl(control_pbias_offset);
164 if (!(reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK))
165 break;
166 usleep_range(100, 200);
167 } while (!time_after(jiffies, timeout));
168
169 if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) {
170 pr_err("Pbias Voltage is not same as LDO\n");
171 /* Caution : On VMODE_ERROR Power Down MMC IO */
172 reg &= ~(OMAP4_MMC1_PWRDNZ_MASK);
173 omap4_ctrl_pad_writel(reg, control_pbias_offset);
174 }
175 } else {
176 reg = omap4_ctrl_pad_readl(control_pbias_offset);
177 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
178 OMAP4_MMC1_PWRDNZ_MASK |
179 OMAP4_MMC1_PBIASLITE_VMODE_MASK);
180 omap4_ctrl_pad_writel(reg, control_pbias_offset);
181 }
182}
183
184static void hsmmc23_before_set_reg(struct device *dev, int slot,
185 int power_on, int vdd)
186{
187 struct omap_mmc_platform_data *mmc = dev->platform_data;
188
189 if (mmc->slots[0].remux)
190 mmc->slots[0].remux(dev, slot, power_on);
191
192 if (power_on) {
193 /* Only MMC2 supports a CLKIN */
194 if (mmc->slots[0].internal_clock) {
195 u32 reg;
196
197 reg = omap_ctrl_readl(control_devconf1_offset);
198 reg |= OMAP2_MMCSDIO2ADPCLKISEL;
199 omap_ctrl_writel(reg, control_devconf1_offset);
200 }
201 }
202}
203
204static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
205 int vdd)
206{
207 return 0;
208}
209
210static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
211 int controller_nr)
212{
213 if (gpio_is_valid(mmc_controller->slots[0].switch_pin))
214 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
215 OMAP_PIN_INPUT_PULLUP);
216 if (gpio_is_valid(mmc_controller->slots[0].gpio_wp))
217 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
218 OMAP_PIN_INPUT_PULLUP);
219 if (cpu_is_omap34xx()) {
220 if (controller_nr == 0) {
221 omap_mux_init_signal("sdmmc1_clk",
222 OMAP_PIN_INPUT_PULLUP);
223 omap_mux_init_signal("sdmmc1_cmd",
224 OMAP_PIN_INPUT_PULLUP);
225 omap_mux_init_signal("sdmmc1_dat0",
226 OMAP_PIN_INPUT_PULLUP);
227 if (mmc_controller->slots[0].caps &
228 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
229 omap_mux_init_signal("sdmmc1_dat1",
230 OMAP_PIN_INPUT_PULLUP);
231 omap_mux_init_signal("sdmmc1_dat2",
232 OMAP_PIN_INPUT_PULLUP);
233 omap_mux_init_signal("sdmmc1_dat3",
234 OMAP_PIN_INPUT_PULLUP);
235 }
236 if (mmc_controller->slots[0].caps &
237 MMC_CAP_8_BIT_DATA) {
238 omap_mux_init_signal("sdmmc1_dat4",
239 OMAP_PIN_INPUT_PULLUP);
240 omap_mux_init_signal("sdmmc1_dat5",
241 OMAP_PIN_INPUT_PULLUP);
242 omap_mux_init_signal("sdmmc1_dat6",
243 OMAP_PIN_INPUT_PULLUP);
244 omap_mux_init_signal("sdmmc1_dat7",
245 OMAP_PIN_INPUT_PULLUP);
246 }
247 }
248 if (controller_nr == 1) {
249 /* MMC2 */
250 omap_mux_init_signal("sdmmc2_clk",
251 OMAP_PIN_INPUT_PULLUP);
252 omap_mux_init_signal("sdmmc2_cmd",
253 OMAP_PIN_INPUT_PULLUP);
254 omap_mux_init_signal("sdmmc2_dat0",
255 OMAP_PIN_INPUT_PULLUP);
256
257 /*
258 * For 8 wire configurations, Lines DAT4, 5, 6 and 7
259 * need to be muxed in the board-*.c files
260 */
261 if (mmc_controller->slots[0].caps &
262 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
263 omap_mux_init_signal("sdmmc2_dat1",
264 OMAP_PIN_INPUT_PULLUP);
265 omap_mux_init_signal("sdmmc2_dat2",
266 OMAP_PIN_INPUT_PULLUP);
267 omap_mux_init_signal("sdmmc2_dat3",
268 OMAP_PIN_INPUT_PULLUP);
269 }
270 if (mmc_controller->slots[0].caps &
271 MMC_CAP_8_BIT_DATA) {
272 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
273 OMAP_PIN_INPUT_PULLUP);
274 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
275 OMAP_PIN_INPUT_PULLUP);
276 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
277 OMAP_PIN_INPUT_PULLUP);
278 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
279 OMAP_PIN_INPUT_PULLUP);
280 }
281 }
282
283 /*
284 * For MMC3 the pins need to be muxed in the board-*.c files
285 */
286 }
287}
288
289static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
290 struct omap_mmc_platform_data *mmc)
291{
292 char *hc_name;
293
294 hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL);
295 if (!hc_name) {
296 pr_err("Cannot allocate memory for controller slot name\n");
297 kfree(hc_name);
298 return -ENOMEM;
299 }
300
301 if (c->name)
302 strncpy(hc_name, c->name, HSMMC_NAME_LEN);
303 else
304 snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i",
305 c->mmc, 1);
306 mmc->slots[0].name = hc_name;
307 mmc->nr_slots = 1;
308 mmc->slots[0].caps = c->caps;
309 mmc->slots[0].internal_clock = !c->ext_clock;
310 mmc->dma_mask = 0xffffffff;
311 if (cpu_is_omap44xx())
312 mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
313 else
314 mmc->reg_offset = 0;
315
316 mmc->get_context_loss_count = hsmmc_get_context_loss;
317
318 mmc->slots[0].switch_pin = c->gpio_cd;
319 mmc->slots[0].gpio_wp = c->gpio_wp;
320
321 mmc->slots[0].remux = c->remux;
322 mmc->slots[0].init_card = c->init_card;
323
324 if (c->cover_only)
325 mmc->slots[0].cover = 1;
326
327 if (c->nonremovable)
328 mmc->slots[0].nonremovable = 1;
329
330 if (c->power_saving)
331 mmc->slots[0].power_saving = 1;
332
333 if (c->no_off)
334 mmc->slots[0].no_off = 1;
335
336 if (c->no_off_init)
337 mmc->slots[0].no_regulator_off_init = c->no_off_init;
338
339 if (c->vcc_aux_disable_is_sleep)
340 mmc->slots[0].vcc_aux_disable_is_sleep = 1;
341
342 /*
343 * NOTE: MMC slots should have a Vcc regulator set up.
344 * This may be from a TWL4030-family chip, another
345 * controllable regulator, or a fixed supply.
346 *
347 * temporary HACK: ocr_mask instead of fixed supply
348 */
349 mmc->slots[0].ocr_mask = c->ocr_mask;
350
351 if (cpu_is_omap3517() || cpu_is_omap3505())
352 mmc->slots[0].set_power = nop_mmc_set_power;
353 else
354 mmc->slots[0].features |= HSMMC_HAS_PBIAS;
355
356 if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
357 mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
358
359 switch (c->mmc) {
360 case 1:
361 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
362 /* on-chip level shifting via PBIAS0/PBIAS1 */
363 if (cpu_is_omap44xx()) {
364 mmc->slots[0].before_set_reg =
365 omap4_hsmmc1_before_set_reg;
366 mmc->slots[0].after_set_reg =
367 omap4_hsmmc1_after_set_reg;
368 } else {
369 mmc->slots[0].before_set_reg =
370 omap_hsmmc1_before_set_reg;
371 mmc->slots[0].after_set_reg =
372 omap_hsmmc1_after_set_reg;
373 }
374 }
375
376 /* OMAP3630 HSMMC1 supports only 4-bit */
377 if (cpu_is_omap3630() &&
378 (c->caps & MMC_CAP_8_BIT_DATA)) {
379 c->caps &= ~MMC_CAP_8_BIT_DATA;
380 c->caps |= MMC_CAP_4_BIT_DATA;
381 mmc->slots[0].caps = c->caps;
382 }
383 break;
384 case 2:
385 if (c->ext_clock)
386 c->transceiver = 1;
387 if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
388 c->caps &= ~MMC_CAP_8_BIT_DATA;
389 c->caps |= MMC_CAP_4_BIT_DATA;
390 }
391 /* FALLTHROUGH */
392 case 3:
393 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
394 /* off-chip level shifting, or none */
395 mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
396 mmc->slots[0].after_set_reg = NULL;
397 }
398 break;
399 case 4:
400 case 5:
401 mmc->slots[0].before_set_reg = NULL;
402 mmc->slots[0].after_set_reg = NULL;
403 break;
404 default:
405 pr_err("MMC%d configuration not supported!\n", c->mmc);
406 kfree(hc_name);
407 return -ENODEV;
408 }
409 return 0;
410}
411
412static struct omap_device_pm_latency omap_hsmmc_latency[] = {
413 [0] = {
414 .deactivate_func = omap_device_idle_hwmods,
415 .activate_func = omap_device_enable_hwmods,
416 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
417 },
418 /*
419 * XXX There should also be an entry here to power off/on the
420 * MMC regulators/PBIAS cells, etc.
421 */
422};
423
424#define MAX_OMAP_MMC_HWMOD_NAME_LEN 16
425
426void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
427{
428 struct omap_hwmod *oh;
429 struct omap_device *od;
430 struct omap_device_pm_latency *ohl;
431 char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
432 struct omap_mmc_platform_data *mmc_data;
433 struct omap_mmc_dev_attr *mmc_dev_attr;
434 char *name;
435 int l;
436 int ohl_cnt = 0;
437
438 mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
439 if (!mmc_data) {
440 pr_err("Cannot allocate memory for mmc device!\n");
441 goto done;
442 }
443
444 if (omap_hsmmc_pdata_init(hsmmcinfo, mmc_data) < 0) {
445 pr_err("%s fails!\n", __func__);
446 goto done;
447 }
448 omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
449
450 name = "omap_hsmmc";
451 ohl = omap_hsmmc_latency;
452 ohl_cnt = ARRAY_SIZE(omap_hsmmc_latency);
453
454 l = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
455 "mmc%d", ctrl_nr);
456 WARN(l >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
457 "String buffer overflow in MMC%d device setup\n", ctrl_nr);
458 oh = omap_hwmod_lookup(oh_name);
459 if (!oh) {
460 pr_err("Could not look up %s\n", oh_name);
461 kfree(mmc_data->slots[0].name);
462 goto done;
463 }
464
465 if (oh->dev_attr != NULL) {
466 mmc_dev_attr = oh->dev_attr;
467 mmc_data->controller_flags = mmc_dev_attr->flags;
468 }
469
470 od = omap_device_build(name, ctrl_nr - 1, oh, mmc_data,
471 sizeof(struct omap_mmc_platform_data), ohl, ohl_cnt, false);
472 if (IS_ERR(od)) {
473 WARN(1, "Can't build omap_device for %s:%s.\n", name, oh->name);
474 kfree(mmc_data->slots[0].name);
475 goto done;
476 }
477 /*
478 * return device handle to board setup code
479 * required to populate for regulator framework structure
480 */
481 hsmmcinfo->dev = &od->pdev.dev;
482
483done:
484 kfree(mmc_data);
485}
486
487void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
488{
489 u32 reg;
490
491 if (!cpu_is_omap44xx()) {
492 if (cpu_is_omap2430()) {
493 control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
494 control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
495 } else {
496 control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
497 control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
498 }
499 } else {
500 control_pbias_offset =
501 OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
502 control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
503 reg = omap4_ctrl_pad_readl(control_mmc1);
504 reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
505 OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
506 reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
507 OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
508 reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK|
509 OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
510 OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
511 omap4_ctrl_pad_writel(reg, control_mmc1);
512 }
513
514 for (; controllers->mmc; controllers++)
515 omap_init_hsmmc(controllers, controllers->mmc);
516
517}
518
519#endif