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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * OMAP2+ DMA driver
4 *
5 * Copyright (C) 2003 - 2008 Nokia Corporation
6 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
7 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
8 * Graphics DMA and LCD DMA graphics tranformations
9 * by Imre Deak <imre.deak@nokia.com>
10 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
12 *
13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
15 *
16 * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
17 * Converted DMA library into platform driver
18 * - G, Manjunath Kondaiah <manjugk@ti.com>
19 */
20
21#include <linux/err.h>
22#include <linux/io.h>
23#include <linux/slab.h>
24#include <linux/module.h>
25#include <linux/init.h>
26#include <linux/device.h>
27#include <linux/dma-mapping.h>
28#include <linux/dmaengine.h>
29#include <linux/of.h>
30#include <linux/omap-dma.h>
31
32#include "soc.h"
33#include "common.h"
34
35static const struct omap_dma_reg reg_map[] = {
36 [REVISION] = { 0x0000, 0x00, OMAP_DMA_REG_32BIT },
37 [GCR] = { 0x0078, 0x00, OMAP_DMA_REG_32BIT },
38 [IRQSTATUS_L0] = { 0x0008, 0x00, OMAP_DMA_REG_32BIT },
39 [IRQSTATUS_L1] = { 0x000c, 0x00, OMAP_DMA_REG_32BIT },
40 [IRQSTATUS_L2] = { 0x0010, 0x00, OMAP_DMA_REG_32BIT },
41 [IRQSTATUS_L3] = { 0x0014, 0x00, OMAP_DMA_REG_32BIT },
42 [IRQENABLE_L0] = { 0x0018, 0x00, OMAP_DMA_REG_32BIT },
43 [IRQENABLE_L1] = { 0x001c, 0x00, OMAP_DMA_REG_32BIT },
44 [IRQENABLE_L2] = { 0x0020, 0x00, OMAP_DMA_REG_32BIT },
45 [IRQENABLE_L3] = { 0x0024, 0x00, OMAP_DMA_REG_32BIT },
46 [SYSSTATUS] = { 0x0028, 0x00, OMAP_DMA_REG_32BIT },
47 [OCP_SYSCONFIG] = { 0x002c, 0x00, OMAP_DMA_REG_32BIT },
48 [CAPS_0] = { 0x0064, 0x00, OMAP_DMA_REG_32BIT },
49 [CAPS_2] = { 0x006c, 0x00, OMAP_DMA_REG_32BIT },
50 [CAPS_3] = { 0x0070, 0x00, OMAP_DMA_REG_32BIT },
51 [CAPS_4] = { 0x0074, 0x00, OMAP_DMA_REG_32BIT },
52
53 /* Common register offsets */
54 [CCR] = { 0x0080, 0x60, OMAP_DMA_REG_32BIT },
55 [CLNK_CTRL] = { 0x0084, 0x60, OMAP_DMA_REG_32BIT },
56 [CICR] = { 0x0088, 0x60, OMAP_DMA_REG_32BIT },
57 [CSR] = { 0x008c, 0x60, OMAP_DMA_REG_32BIT },
58 [CSDP] = { 0x0090, 0x60, OMAP_DMA_REG_32BIT },
59 [CEN] = { 0x0094, 0x60, OMAP_DMA_REG_32BIT },
60 [CFN] = { 0x0098, 0x60, OMAP_DMA_REG_32BIT },
61 [CSEI] = { 0x00a4, 0x60, OMAP_DMA_REG_32BIT },
62 [CSFI] = { 0x00a8, 0x60, OMAP_DMA_REG_32BIT },
63 [CDEI] = { 0x00ac, 0x60, OMAP_DMA_REG_32BIT },
64 [CDFI] = { 0x00b0, 0x60, OMAP_DMA_REG_32BIT },
65 [CSAC] = { 0x00b4, 0x60, OMAP_DMA_REG_32BIT },
66 [CDAC] = { 0x00b8, 0x60, OMAP_DMA_REG_32BIT },
67
68 /* Channel specific register offsets */
69 [CSSA] = { 0x009c, 0x60, OMAP_DMA_REG_32BIT },
70 [CDSA] = { 0x00a0, 0x60, OMAP_DMA_REG_32BIT },
71 [CCEN] = { 0x00bc, 0x60, OMAP_DMA_REG_32BIT },
72 [CCFN] = { 0x00c0, 0x60, OMAP_DMA_REG_32BIT },
73 [COLOR] = { 0x00c4, 0x60, OMAP_DMA_REG_32BIT },
74
75 /* OMAP4 specific registers */
76 [CDP] = { 0x00d0, 0x60, OMAP_DMA_REG_32BIT },
77 [CNDP] = { 0x00d4, 0x60, OMAP_DMA_REG_32BIT },
78 [CCDN] = { 0x00d8, 0x60, OMAP_DMA_REG_32BIT },
79};
80
81static unsigned configure_dma_errata(void)
82{
83 unsigned errata = 0;
84
85 /*
86 * Errata applicable for OMAP2430ES1.0 and all omap2420
87 *
88 * I.
89 * Erratum ID: Not Available
90 * Inter Frame DMA buffering issue DMA will wrongly
91 * buffer elements if packing and bursting is enabled. This might
92 * result in data gets stalled in FIFO at the end of the block.
93 * Workaround: DMA channels must have BUFFERING_DISABLED bit set to
94 * guarantee no data will stay in the DMA FIFO in case inter frame
95 * buffering occurs
96 *
97 * II.
98 * Erratum ID: Not Available
99 * DMA may hang when several channels are used in parallel
100 * In the following configuration, DMA channel hanging can occur:
101 * a. Channel i, hardware synchronized, is enabled
102 * b. Another channel (Channel x), software synchronized, is enabled.
103 * c. Channel i is disabled before end of transfer
104 * d. Channel i is reenabled.
105 * e. Steps 1 to 4 are repeated a certain number of times.
106 * f. A third channel (Channel y), software synchronized, is enabled.
107 * Channel x and Channel y may hang immediately after step 'f'.
108 * Workaround:
109 * For any channel used - make sure NextLCH_ID is set to the value j.
110 */
111 if (cpu_is_omap2420() || (cpu_is_omap2430() &&
112 (omap_type() == OMAP2430_REV_ES1_0))) {
113
114 SET_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING);
115 SET_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS);
116 }
117
118 /*
119 * Erratum ID: i378: OMAP2+: sDMA Channel is not disabled
120 * after a transaction error.
121 * Workaround: SW should explicitely disable the channel.
122 */
123 if (cpu_class_is_omap2())
124 SET_DMA_ERRATA(DMA_ERRATA_i378);
125
126 /*
127 * Erratum ID: i541: sDMA FIFO draining does not finish
128 * If sDMA channel is disabled on the fly, sDMA enters standby even
129 * through FIFO Drain is still in progress
130 * Workaround: Put sDMA in NoStandby more before a logical channel is
131 * disabled, then put it back to SmartStandby right after the channel
132 * finishes FIFO draining.
133 */
134 if (cpu_is_omap34xx())
135 SET_DMA_ERRATA(DMA_ERRATA_i541);
136
137 /*
138 * Erratum ID: i88 : Special programming model needed to disable DMA
139 * before end of block.
140 * Workaround: software must ensure that the DMA is configured in No
141 * Standby mode(DMAx_OCP_SYSCONFIG.MIDLEMODE = "01")
142 */
143 if (omap_type() == OMAP3430_REV_ES1_0)
144 SET_DMA_ERRATA(DMA_ERRATA_i88);
145
146 /*
147 * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
148 * read before the DMA controller finished disabling the channel.
149 */
150 SET_DMA_ERRATA(DMA_ERRATA_3_3);
151
152 /*
153 * Erratum ID: Not Available
154 * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
155 * after secure sram context save and restore.
156 * Work around: Hence we need to manually clear those IRQs to avoid
157 * spurious interrupts. This affects only secure devices.
158 */
159 if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
160 SET_DMA_ERRATA(DMA_ROMCODE_BUG);
161
162 return errata;
163}
164
165static const struct dma_slave_map omap24xx_sdma_dt_map[] = {
166 /* external DMA requests when tusb6010 is used */
167 { "musb-hdrc.1.auto", "dmareq0", SDMA_FILTER_PARAM(2) },
168 { "musb-hdrc.1.auto", "dmareq1", SDMA_FILTER_PARAM(3) },
169 { "musb-hdrc.1.auto", "dmareq2", SDMA_FILTER_PARAM(14) }, /* OMAP2420 only */
170 { "musb-hdrc.1.auto", "dmareq3", SDMA_FILTER_PARAM(15) }, /* OMAP2420 only */
171 { "musb-hdrc.1.auto", "dmareq4", SDMA_FILTER_PARAM(16) }, /* OMAP2420 only */
172 { "musb-hdrc.1.auto", "dmareq5", SDMA_FILTER_PARAM(64) }, /* OMAP2420 only */
173};
174
175static struct omap_dma_dev_attr dma_attr = {
176 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
177 IS_CSSA_32 | IS_CDSA_32,
178 .lch_count = 32,
179};
180
181struct omap_system_dma_plat_info dma_plat_info = {
182 .reg_map = reg_map,
183 .channel_stride = 0x60,
184 .dma_attr = &dma_attr,
185};
186
187/* One time initializations */
188static int __init omap2_system_dma_init(void)
189{
190 dma_plat_info.errata = configure_dma_errata();
191
192 if (soc_is_omap24xx()) {
193 /* DMA slave map for drivers not yet converted to DT */
194 dma_plat_info.slave_map = omap24xx_sdma_dt_map;
195 dma_plat_info.slavecnt = ARRAY_SIZE(omap24xx_sdma_dt_map);
196 }
197
198 if (!soc_is_omap242x())
199 dma_attr.dev_caps |= IS_RW_PRIORITY;
200
201 if (soc_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
202 dma_attr.dev_caps |= HS_CHANNELS_RESERVED;
203
204 return 0;
205}
206omap_arch_initcall(omap2_system_dma_init);
1/*
2 * OMAP2+ DMA driver
3 *
4 * Copyright (C) 2003 - 2008 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
11 *
12 * Copyright (C) 2009 Texas Instruments
13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
14 *
15 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
16 * Converted DMA library into platform driver
17 * - G, Manjunath Kondaiah <manjugk@ti.com>
18 *
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License version 2 as
21 * published by the Free Software Foundation.
22 */
23
24#include <linux/err.h>
25#include <linux/io.h>
26#include <linux/slab.h>
27#include <linux/module.h>
28#include <linux/init.h>
29#include <linux/device.h>
30
31#include <plat/omap_hwmod.h>
32#include <plat/omap_device.h>
33#include <plat/dma.h>
34
35#define OMAP2_DMA_STRIDE 0x60
36
37static u32 errata;
38static u8 dma_stride;
39
40static struct omap_dma_dev_attr *d;
41
42static enum omap_reg_offsets dma_common_ch_start, dma_common_ch_end;
43
44static u16 reg_map[] = {
45 [REVISION] = 0x00,
46 [GCR] = 0x78,
47 [IRQSTATUS_L0] = 0x08,
48 [IRQSTATUS_L1] = 0x0c,
49 [IRQSTATUS_L2] = 0x10,
50 [IRQSTATUS_L3] = 0x14,
51 [IRQENABLE_L0] = 0x18,
52 [IRQENABLE_L1] = 0x1c,
53 [IRQENABLE_L2] = 0x20,
54 [IRQENABLE_L3] = 0x24,
55 [SYSSTATUS] = 0x28,
56 [OCP_SYSCONFIG] = 0x2c,
57 [CAPS_0] = 0x64,
58 [CAPS_2] = 0x6c,
59 [CAPS_3] = 0x70,
60 [CAPS_4] = 0x74,
61
62 /* Common register offsets */
63 [CCR] = 0x80,
64 [CLNK_CTRL] = 0x84,
65 [CICR] = 0x88,
66 [CSR] = 0x8c,
67 [CSDP] = 0x90,
68 [CEN] = 0x94,
69 [CFN] = 0x98,
70 [CSEI] = 0xa4,
71 [CSFI] = 0xa8,
72 [CDEI] = 0xac,
73 [CDFI] = 0xb0,
74 [CSAC] = 0xb4,
75 [CDAC] = 0xb8,
76
77 /* Channel specific register offsets */
78 [CSSA] = 0x9c,
79 [CDSA] = 0xa0,
80 [CCEN] = 0xbc,
81 [CCFN] = 0xc0,
82 [COLOR] = 0xc4,
83
84 /* OMAP4 specific registers */
85 [CDP] = 0xd0,
86 [CNDP] = 0xd4,
87 [CCDN] = 0xd8,
88};
89
90static struct omap_device_pm_latency omap2_dma_latency[] = {
91 {
92 .deactivate_func = omap_device_idle_hwmods,
93 .activate_func = omap_device_enable_hwmods,
94 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
95 },
96};
97
98static void __iomem *dma_base;
99static inline void dma_write(u32 val, int reg, int lch)
100{
101 u8 stride;
102 u32 offset;
103
104 stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
105 offset = reg_map[reg] + (stride * lch);
106 __raw_writel(val, dma_base + offset);
107}
108
109static inline u32 dma_read(int reg, int lch)
110{
111 u8 stride;
112 u32 offset, val;
113
114 stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
115 offset = reg_map[reg] + (stride * lch);
116 val = __raw_readl(dma_base + offset);
117 return val;
118}
119
120static inline void omap2_disable_irq_lch(int lch)
121{
122 u32 val;
123
124 val = dma_read(IRQENABLE_L0, lch);
125 val &= ~(1 << lch);
126 dma_write(val, IRQENABLE_L0, lch);
127}
128
129static void omap2_clear_dma(int lch)
130{
131 int i = dma_common_ch_start;
132
133 for (; i <= dma_common_ch_end; i += 1)
134 dma_write(0, i, lch);
135}
136
137static void omap2_show_dma_caps(void)
138{
139 u8 revision = dma_read(REVISION, 0) & 0xff;
140 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
141 revision >> 4, revision & 0xf);
142 return;
143}
144
145static u32 configure_dma_errata(void)
146{
147
148 /*
149 * Errata applicable for OMAP2430ES1.0 and all omap2420
150 *
151 * I.
152 * Erratum ID: Not Available
153 * Inter Frame DMA buffering issue DMA will wrongly
154 * buffer elements if packing and bursting is enabled. This might
155 * result in data gets stalled in FIFO at the end of the block.
156 * Workaround: DMA channels must have BUFFERING_DISABLED bit set to
157 * guarantee no data will stay in the DMA FIFO in case inter frame
158 * buffering occurs
159 *
160 * II.
161 * Erratum ID: Not Available
162 * DMA may hang when several channels are used in parallel
163 * In the following configuration, DMA channel hanging can occur:
164 * a. Channel i, hardware synchronized, is enabled
165 * b. Another channel (Channel x), software synchronized, is enabled.
166 * c. Channel i is disabled before end of transfer
167 * d. Channel i is reenabled.
168 * e. Steps 1 to 4 are repeated a certain number of times.
169 * f. A third channel (Channel y), software synchronized, is enabled.
170 * Channel x and Channel y may hang immediately after step 'f'.
171 * Workaround:
172 * For any channel used - make sure NextLCH_ID is set to the value j.
173 */
174 if (cpu_is_omap2420() || (cpu_is_omap2430() &&
175 (omap_type() == OMAP2430_REV_ES1_0))) {
176
177 SET_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING);
178 SET_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS);
179 }
180
181 /*
182 * Erratum ID: i378: OMAP2+: sDMA Channel is not disabled
183 * after a transaction error.
184 * Workaround: SW should explicitely disable the channel.
185 */
186 if (cpu_class_is_omap2())
187 SET_DMA_ERRATA(DMA_ERRATA_i378);
188
189 /*
190 * Erratum ID: i541: sDMA FIFO draining does not finish
191 * If sDMA channel is disabled on the fly, sDMA enters standby even
192 * through FIFO Drain is still in progress
193 * Workaround: Put sDMA in NoStandby more before a logical channel is
194 * disabled, then put it back to SmartStandby right after the channel
195 * finishes FIFO draining.
196 */
197 if (cpu_is_omap34xx())
198 SET_DMA_ERRATA(DMA_ERRATA_i541);
199
200 /*
201 * Erratum ID: i88 : Special programming model needed to disable DMA
202 * before end of block.
203 * Workaround: software must ensure that the DMA is configured in No
204 * Standby mode(DMAx_OCP_SYSCONFIG.MIDLEMODE = "01")
205 */
206 if (omap_type() == OMAP3430_REV_ES1_0)
207 SET_DMA_ERRATA(DMA_ERRATA_i88);
208
209 /*
210 * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
211 * read before the DMA controller finished disabling the channel.
212 */
213 SET_DMA_ERRATA(DMA_ERRATA_3_3);
214
215 /*
216 * Erratum ID: Not Available
217 * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
218 * after secure sram context save and restore.
219 * Work around: Hence we need to manually clear those IRQs to avoid
220 * spurious interrupts. This affects only secure devices.
221 */
222 if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
223 SET_DMA_ERRATA(DMA_ROMCODE_BUG);
224
225 return errata;
226}
227
228/* One time initializations */
229static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
230{
231 struct omap_device *od;
232 struct omap_system_dma_plat_info *p;
233 struct resource *mem;
234 char *name = "omap_dma_system";
235
236 dma_stride = OMAP2_DMA_STRIDE;
237 dma_common_ch_start = CSDP;
238 if (cpu_is_omap3630() || cpu_is_omap4430())
239 dma_common_ch_end = CCDN;
240 else
241 dma_common_ch_end = CCFN;
242
243 p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL);
244 if (!p) {
245 pr_err("%s: Unable to allocate pdata for %s:%s\n",
246 __func__, name, oh->name);
247 return -ENOMEM;
248 }
249
250 p->dma_attr = (struct omap_dma_dev_attr *)oh->dev_attr;
251 p->disable_irq_lch = omap2_disable_irq_lch;
252 p->show_dma_caps = omap2_show_dma_caps;
253 p->clear_dma = omap2_clear_dma;
254 p->dma_write = dma_write;
255 p->dma_read = dma_read;
256
257 p->clear_lch_regs = NULL;
258
259 p->errata = configure_dma_errata();
260
261 od = omap_device_build(name, 0, oh, p, sizeof(*p),
262 omap2_dma_latency, ARRAY_SIZE(omap2_dma_latency), 0);
263 kfree(p);
264 if (IS_ERR(od)) {
265 pr_err("%s: Can't build omap_device for %s:%s.\n",
266 __func__, name, oh->name);
267 return PTR_ERR(od);
268 }
269
270 mem = platform_get_resource(&od->pdev, IORESOURCE_MEM, 0);
271 if (!mem) {
272 dev_err(&od->pdev.dev, "%s: no mem resource\n", __func__);
273 return -EINVAL;
274 }
275 dma_base = ioremap(mem->start, resource_size(mem));
276 if (!dma_base) {
277 dev_err(&od->pdev.dev, "%s: ioremap fail\n", __func__);
278 return -ENOMEM;
279 }
280
281 d = oh->dev_attr;
282 d->chan = kzalloc(sizeof(struct omap_dma_lch) *
283 (d->lch_count), GFP_KERNEL);
284
285 if (!d->chan) {
286 dev_err(&od->pdev.dev, "%s: kzalloc fail\n", __func__);
287 return -ENOMEM;
288 }
289 return 0;
290}
291
292static int __init omap2_system_dma_init(void)
293{
294 return omap_hwmod_for_each_by_class("dma",
295 omap2_system_dma_init_dev, NULL);
296}
297arch_initcall(omap2_system_dma_init);