1/*
   2 * OMAP4 Clock data
   3 *
   4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
   5 * Copyright (C) 2009-2010 Nokia Corporation
   6 *
   7 * Paul Walmsley (paul@pwsan.com)
   8 * Rajendra Nayak (rnayak@ti.com)
   9 * Benoit Cousson (b-cousson@ti.com)
  10 *
  11 * This file is automatically generated from the OMAP hardware databases.
  12 * We respectfully ask that any modifications to this file be coordinated
  13 * with the public linux-omap@vger.kernel.org mailing list and the
  14 * authors above to ensure that the autogeneration scripts are kept
  15 * up-to-date with the file contents.
  16 *
  17 * This program is free software; you can redistribute it and/or modify
  18 * it under the terms of the GNU General Public License version 2 as
  19 * published by the Free Software Foundation.
  20 *
  21 * XXX Some of the ES1 clocks have been removed/changed; once support
  22 * is added for discriminating clocks by ES level, these should be added back
  23 * in.
  24 */
  25
  26#include <linux/kernel.h>
  27#include <linux/list.h>
  28#include <linux/clk.h>
  29#include <plat/clkdev_omap.h>
  30
  31#include "clock.h"
  32#include "clock44xx.h"
  33#include "cm1_44xx.h"
  34#include "cm2_44xx.h"
  35#include "cm-regbits-44xx.h"
  36#include "prm44xx.h"
  37#include "prm-regbits-44xx.h"
  38#include "control.h"
  39#include "scrm44xx.h"
  40
  41/* OMAP4 modulemode control */
  42#define OMAP4430_MODULEMODE_HWCTRL			0
  43#define OMAP4430_MODULEMODE_SWCTRL			1
  44
  45/* Root clocks */
  46
  47static struct clk extalt_clkin_ck = {
  48	.name		= "extalt_clkin_ck",
  49	.rate		= 59000000,
  50	.ops		= &clkops_null,
  51};
  52
  53static struct clk pad_clks_ck = {
  54	.name		= "pad_clks_ck",
  55	.rate		= 12000000,
  56	.ops		= &clkops_omap2_dflt,
  57	.enable_reg	= OMAP4430_CM_CLKSEL_ABE,
  58	.enable_bit	= OMAP4430_PAD_CLKS_GATE_SHIFT,
  59};
  60
  61static struct clk pad_slimbus_core_clks_ck = {
  62	.name		= "pad_slimbus_core_clks_ck",
  63	.rate		= 12000000,
  64	.ops		= &clkops_null,
  65};
  66
  67static struct clk secure_32k_clk_src_ck = {
  68	.name		= "secure_32k_clk_src_ck",
  69	.rate		= 32768,
  70	.ops		= &clkops_null,
  71};
  72
  73static struct clk slimbus_clk = {
  74	.name		= "slimbus_clk",
  75	.rate		= 12000000,
  76	.ops		= &clkops_omap2_dflt,
  77	.enable_reg	= OMAP4430_CM_CLKSEL_ABE,
  78	.enable_bit	= OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
  79};
  80
  81static struct clk sys_32k_ck = {
  82	.name		= "sys_32k_ck",
  83	.rate		= 32768,
  84	.ops		= &clkops_null,
  85};
  86
  87static struct clk virt_12000000_ck = {
  88	.name		= "virt_12000000_ck",
  89	.ops		= &clkops_null,
  90	.rate		= 12000000,
  91};
  92
  93static struct clk virt_13000000_ck = {
  94	.name		= "virt_13000000_ck",
  95	.ops		= &clkops_null,
  96	.rate		= 13000000,
  97};
  98
  99static struct clk virt_16800000_ck = {
 100	.name		= "virt_16800000_ck",
 101	.ops		= &clkops_null,
 102	.rate		= 16800000,
 103};
 104
 105static struct clk virt_19200000_ck = {
 106	.name		= "virt_19200000_ck",
 107	.ops		= &clkops_null,
 108	.rate		= 19200000,
 109};
 110
 111static struct clk virt_26000000_ck = {
 112	.name		= "virt_26000000_ck",
 113	.ops		= &clkops_null,
 114	.rate		= 26000000,
 115};
 116
 117static struct clk virt_27000000_ck = {
 118	.name		= "virt_27000000_ck",
 119	.ops		= &clkops_null,
 120	.rate		= 27000000,
 121};
 122
 123static struct clk virt_38400000_ck = {
 124	.name		= "virt_38400000_ck",
 125	.ops		= &clkops_null,
 126	.rate		= 38400000,
 127};
 128
 129static const struct clksel_rate div_1_0_rates[] = {
 130	{ .div = 1, .val = 0, .flags = RATE_IN_4430 },
 131	{ .div = 0 },
 132};
 133
 134static const struct clksel_rate div_1_1_rates[] = {
 135	{ .div = 1, .val = 1, .flags = RATE_IN_4430 },
 136	{ .div = 0 },
 137};
 138
 139static const struct clksel_rate div_1_2_rates[] = {
 140	{ .div = 1, .val = 2, .flags = RATE_IN_4430 },
 141	{ .div = 0 },
 142};
 143
 144static const struct clksel_rate div_1_3_rates[] = {
 145	{ .div = 1, .val = 3, .flags = RATE_IN_4430 },
 146	{ .div = 0 },
 147};
 148
 149static const struct clksel_rate div_1_4_rates[] = {
 150	{ .div = 1, .val = 4, .flags = RATE_IN_4430 },
 151	{ .div = 0 },
 152};
 153
 154static const struct clksel_rate div_1_5_rates[] = {
 155	{ .div = 1, .val = 5, .flags = RATE_IN_4430 },
 156	{ .div = 0 },
 157};
 158
 159static const struct clksel_rate div_1_6_rates[] = {
 160	{ .div = 1, .val = 6, .flags = RATE_IN_4430 },
 161	{ .div = 0 },
 162};
 163
 164static const struct clksel_rate div_1_7_rates[] = {
 165	{ .div = 1, .val = 7, .flags = RATE_IN_4430 },
 166	{ .div = 0 },
 167};
 168
 169static const struct clksel sys_clkin_sel[] = {
 170	{ .parent = &virt_12000000_ck, .rates = div_1_1_rates },
 171	{ .parent = &virt_13000000_ck, .rates = div_1_2_rates },
 172	{ .parent = &virt_16800000_ck, .rates = div_1_3_rates },
 173	{ .parent = &virt_19200000_ck, .rates = div_1_4_rates },
 174	{ .parent = &virt_26000000_ck, .rates = div_1_5_rates },
 175	{ .parent = &virt_27000000_ck, .rates = div_1_6_rates },
 176	{ .parent = &virt_38400000_ck, .rates = div_1_7_rates },
 177	{ .parent = NULL },
 178};
 179
 180static struct clk sys_clkin_ck = {
 181	.name		= "sys_clkin_ck",
 182	.rate		= 38400000,
 183	.clksel		= sys_clkin_sel,
 184	.init		= &omap2_init_clksel_parent,
 185	.clksel_reg	= OMAP4430_CM_SYS_CLKSEL,
 186	.clksel_mask	= OMAP4430_SYS_CLKSEL_MASK,
 187	.ops		= &clkops_null,
 188	.recalc		= &omap2_clksel_recalc,
 189};
 190
 191static struct clk tie_low_clock_ck = {
 192	.name		= "tie_low_clock_ck",
 193	.rate		= 0,
 194	.ops		= &clkops_null,
 195};
 196
 197static struct clk utmi_phy_clkout_ck = {
 198	.name		= "utmi_phy_clkout_ck",
 199	.rate		= 60000000,
 200	.ops		= &clkops_null,
 201};
 202
 203static struct clk xclk60mhsp1_ck = {
 204	.name		= "xclk60mhsp1_ck",
 205	.rate		= 60000000,
 206	.ops		= &clkops_null,
 207};
 208
 209static struct clk xclk60mhsp2_ck = {
 210	.name		= "xclk60mhsp2_ck",
 211	.rate		= 60000000,
 212	.ops		= &clkops_null,
 213};
 214
 215static struct clk xclk60motg_ck = {
 216	.name		= "xclk60motg_ck",
 217	.rate		= 60000000,
 218	.ops		= &clkops_null,
 219};
 220
 221/* Module clocks and DPLL outputs */
 222
 223static const struct clksel abe_dpll_bypass_clk_mux_sel[] = {
 224	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 225	{ .parent = &sys_32k_ck, .rates = div_1_1_rates },
 226	{ .parent = NULL },
 227};
 228
 229static struct clk abe_dpll_bypass_clk_mux_ck = {
 230	.name		= "abe_dpll_bypass_clk_mux_ck",
 231	.parent		= &sys_clkin_ck,
 232	.ops		= &clkops_null,
 233	.recalc		= &followparent_recalc,
 234};
 235
 236static struct clk abe_dpll_refclk_mux_ck = {
 237	.name		= "abe_dpll_refclk_mux_ck",
 238	.parent		= &sys_clkin_ck,
 239	.clksel		= abe_dpll_bypass_clk_mux_sel,
 240	.init		= &omap2_init_clksel_parent,
 241	.clksel_reg	= OMAP4430_CM_ABE_PLL_REF_CLKSEL,
 242	.clksel_mask	= OMAP4430_CLKSEL_0_0_MASK,
 243	.ops		= &clkops_null,
 244	.recalc		= &omap2_clksel_recalc,
 245};
 246
 247/* DPLL_ABE */
 248static struct dpll_data dpll_abe_dd = {
 249	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_ABE,
 250	.clk_bypass	= &abe_dpll_bypass_clk_mux_ck,
 251	.clk_ref	= &abe_dpll_refclk_mux_ck,
 252	.control_reg	= OMAP4430_CM_CLKMODE_DPLL_ABE,
 253	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 254	.autoidle_reg	= OMAP4430_CM_AUTOIDLE_DPLL_ABE,
 255	.idlest_reg	= OMAP4430_CM_IDLEST_DPLL_ABE,
 256	.mult_mask	= OMAP4430_DPLL_MULT_MASK,
 257	.div1_mask	= OMAP4430_DPLL_DIV_MASK,
 258	.enable_mask	= OMAP4430_DPLL_EN_MASK,
 259	.autoidle_mask	= OMAP4430_AUTO_DPLL_MODE_MASK,
 260	.idlest_mask	= OMAP4430_ST_DPLL_CLK_MASK,
 261	.max_multiplier	= 2047,
 262	.max_divider	= 128,
 263	.min_divider	= 1,
 264};
 265
 266
 267static struct clk dpll_abe_ck = {
 268	.name		= "dpll_abe_ck",
 269	.parent		= &abe_dpll_refclk_mux_ck,
 270	.dpll_data	= &dpll_abe_dd,
 271	.init		= &omap2_init_dpll_parent,
 272	.ops		= &clkops_omap3_noncore_dpll_ops,
 273	.recalc		= &omap3_dpll_recalc,
 274	.round_rate	= &omap2_dpll_round_rate,
 275	.set_rate	= &omap3_noncore_dpll_set_rate,
 276};
 277
 278static struct clk dpll_abe_x2_ck = {
 279	.name		= "dpll_abe_x2_ck",
 280	.parent		= &dpll_abe_ck,
 281	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_ABE,
 282	.flags		= CLOCK_CLKOUTX2,
 283	.ops		= &clkops_omap4_dpllmx_ops,
 284	.recalc		= &omap3_clkoutx2_recalc,
 285};
 286
 287static const struct clksel_rate div31_1to31_rates[] = {
 288	{ .div = 1, .val = 1, .flags = RATE_IN_4430 },
 289	{ .div = 2, .val = 2, .flags = RATE_IN_4430 },
 290	{ .div = 3, .val = 3, .flags = RATE_IN_4430 },
 291	{ .div = 4, .val = 4, .flags = RATE_IN_4430 },
 292	{ .div = 5, .val = 5, .flags = RATE_IN_4430 },
 293	{ .div = 6, .val = 6, .flags = RATE_IN_4430 },
 294	{ .div = 7, .val = 7, .flags = RATE_IN_4430 },
 295	{ .div = 8, .val = 8, .flags = RATE_IN_4430 },
 296	{ .div = 9, .val = 9, .flags = RATE_IN_4430 },
 297	{ .div = 10, .val = 10, .flags = RATE_IN_4430 },
 298	{ .div = 11, .val = 11, .flags = RATE_IN_4430 },
 299	{ .div = 12, .val = 12, .flags = RATE_IN_4430 },
 300	{ .div = 13, .val = 13, .flags = RATE_IN_4430 },
 301	{ .div = 14, .val = 14, .flags = RATE_IN_4430 },
 302	{ .div = 15, .val = 15, .flags = RATE_IN_4430 },
 303	{ .div = 16, .val = 16, .flags = RATE_IN_4430 },
 304	{ .div = 17, .val = 17, .flags = RATE_IN_4430 },
 305	{ .div = 18, .val = 18, .flags = RATE_IN_4430 },
 306	{ .div = 19, .val = 19, .flags = RATE_IN_4430 },
 307	{ .div = 20, .val = 20, .flags = RATE_IN_4430 },
 308	{ .div = 21, .val = 21, .flags = RATE_IN_4430 },
 309	{ .div = 22, .val = 22, .flags = RATE_IN_4430 },
 310	{ .div = 23, .val = 23, .flags = RATE_IN_4430 },
 311	{ .div = 24, .val = 24, .flags = RATE_IN_4430 },
 312	{ .div = 25, .val = 25, .flags = RATE_IN_4430 },
 313	{ .div = 26, .val = 26, .flags = RATE_IN_4430 },
 314	{ .div = 27, .val = 27, .flags = RATE_IN_4430 },
 315	{ .div = 28, .val = 28, .flags = RATE_IN_4430 },
 316	{ .div = 29, .val = 29, .flags = RATE_IN_4430 },
 317	{ .div = 30, .val = 30, .flags = RATE_IN_4430 },
 318	{ .div = 31, .val = 31, .flags = RATE_IN_4430 },
 319	{ .div = 0 },
 320};
 321
 322static const struct clksel dpll_abe_m2x2_div[] = {
 323	{ .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates },
 324	{ .parent = NULL },
 325};
 326
 327static struct clk dpll_abe_m2x2_ck = {
 328	.name		= "dpll_abe_m2x2_ck",
 329	.parent		= &dpll_abe_x2_ck,
 330	.clksel		= dpll_abe_m2x2_div,
 331	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_ABE,
 332	.clksel_mask	= OMAP4430_DPLL_CLKOUT_DIV_MASK,
 333	.ops		= &clkops_omap4_dpllmx_ops,
 334	.recalc		= &omap2_clksel_recalc,
 335	.round_rate	= &omap2_clksel_round_rate,
 336	.set_rate	= &omap2_clksel_set_rate,
 337};
 338
 339static struct clk abe_24m_fclk = {
 340	.name		= "abe_24m_fclk",
 341	.parent		= &dpll_abe_m2x2_ck,
 342	.ops		= &clkops_null,
 343	.fixed_div	= 8,
 344	.recalc		= &omap_fixed_divisor_recalc,
 345};
 346
 347static const struct clksel_rate div3_1to4_rates[] = {
 348	{ .div = 1, .val = 0, .flags = RATE_IN_4430 },
 349	{ .div = 2, .val = 1, .flags = RATE_IN_4430 },
 350	{ .div = 4, .val = 2, .flags = RATE_IN_4430 },
 351	{ .div = 0 },
 352};
 353
 354static const struct clksel abe_clk_div[] = {
 355	{ .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates },
 356	{ .parent = NULL },
 357};
 358
 359static struct clk abe_clk = {
 360	.name		= "abe_clk",
 361	.parent		= &dpll_abe_m2x2_ck,
 362	.clksel		= abe_clk_div,
 363	.clksel_reg	= OMAP4430_CM_CLKSEL_ABE,
 364	.clksel_mask	= OMAP4430_CLKSEL_OPP_MASK,
 365	.ops		= &clkops_null,
 366	.recalc		= &omap2_clksel_recalc,
 367	.round_rate	= &omap2_clksel_round_rate,
 368	.set_rate	= &omap2_clksel_set_rate,
 369};
 370
 371static const struct clksel_rate div2_1to2_rates[] = {
 372	{ .div = 1, .val = 0, .flags = RATE_IN_4430 },
 373	{ .div = 2, .val = 1, .flags = RATE_IN_4430 },
 374	{ .div = 0 },
 375};
 376
 377static const struct clksel aess_fclk_div[] = {
 378	{ .parent = &abe_clk, .rates = div2_1to2_rates },
 379	{ .parent = NULL },
 380};
 381
 382static struct clk aess_fclk = {
 383	.name		= "aess_fclk",
 384	.parent		= &abe_clk,
 385	.clksel		= aess_fclk_div,
 386	.clksel_reg	= OMAP4430_CM1_ABE_AESS_CLKCTRL,
 387	.clksel_mask	= OMAP4430_CLKSEL_AESS_FCLK_MASK,
 388	.ops		= &clkops_null,
 389	.recalc		= &omap2_clksel_recalc,
 390	.round_rate	= &omap2_clksel_round_rate,
 391	.set_rate	= &omap2_clksel_set_rate,
 392};
 393
 394static struct clk dpll_abe_m3x2_ck = {
 395	.name		= "dpll_abe_m3x2_ck",
 396	.parent		= &dpll_abe_x2_ck,
 397	.clksel		= dpll_abe_m2x2_div,
 398	.clksel_reg	= OMAP4430_CM_DIV_M3_DPLL_ABE,
 399	.clksel_mask	= OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
 400	.ops		= &clkops_omap4_dpllmx_ops,
 401	.recalc		= &omap2_clksel_recalc,
 402	.round_rate	= &omap2_clksel_round_rate,
 403	.set_rate	= &omap2_clksel_set_rate,
 404};
 405
 406static const struct clksel core_hsd_byp_clk_mux_sel[] = {
 407	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 408	{ .parent = &dpll_abe_m3x2_ck, .rates = div_1_1_rates },
 409	{ .parent = NULL },
 410};
 411
 412static struct clk core_hsd_byp_clk_mux_ck = {
 413	.name		= "core_hsd_byp_clk_mux_ck",
 414	.parent		= &sys_clkin_ck,
 415	.clksel		= core_hsd_byp_clk_mux_sel,
 416	.init		= &omap2_init_clksel_parent,
 417	.clksel_reg	= OMAP4430_CM_CLKSEL_DPLL_CORE,
 418	.clksel_mask	= OMAP4430_DPLL_BYP_CLKSEL_MASK,
 419	.ops		= &clkops_null,
 420	.recalc		= &omap2_clksel_recalc,
 421};
 422
 423/* DPLL_CORE */
 424static struct dpll_data dpll_core_dd = {
 425	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_CORE,
 426	.clk_bypass	= &core_hsd_byp_clk_mux_ck,
 427	.clk_ref	= &sys_clkin_ck,
 428	.control_reg	= OMAP4430_CM_CLKMODE_DPLL_CORE,
 429	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 430	.autoidle_reg	= OMAP4430_CM_AUTOIDLE_DPLL_CORE,
 431	.idlest_reg	= OMAP4430_CM_IDLEST_DPLL_CORE,
 432	.mult_mask	= OMAP4430_DPLL_MULT_MASK,
 433	.div1_mask	= OMAP4430_DPLL_DIV_MASK,
 434	.enable_mask	= OMAP4430_DPLL_EN_MASK,
 435	.autoidle_mask	= OMAP4430_AUTO_DPLL_MODE_MASK,
 436	.idlest_mask	= OMAP4430_ST_DPLL_CLK_MASK,
 437	.max_multiplier	= 2047,
 438	.max_divider	= 128,
 439	.min_divider	= 1,
 440};
 441
 442
 443static struct clk dpll_core_ck = {
 444	.name		= "dpll_core_ck",
 445	.parent		= &sys_clkin_ck,
 446	.dpll_data	= &dpll_core_dd,
 447	.init		= &omap2_init_dpll_parent,
 448	.ops		= &clkops_omap3_core_dpll_ops,
 449	.recalc		= &omap3_dpll_recalc,
 450};
 451
 452static struct clk dpll_core_x2_ck = {
 453	.name		= "dpll_core_x2_ck",
 454	.parent		= &dpll_core_ck,
 455	.flags		= CLOCK_CLKOUTX2,
 456	.ops		= &clkops_null,
 457	.recalc		= &omap3_clkoutx2_recalc,
 458};
 459
 460static const struct clksel dpll_core_m6x2_div[] = {
 461	{ .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
 462	{ .parent = NULL },
 463};
 464
 465static struct clk dpll_core_m6x2_ck = {
 466	.name		= "dpll_core_m6x2_ck",
 467	.parent		= &dpll_core_x2_ck,
 468	.clksel		= dpll_core_m6x2_div,
 469	.clksel_reg	= OMAP4430_CM_DIV_M6_DPLL_CORE,
 470	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
 471	.ops		= &clkops_omap4_dpllmx_ops,
 472	.recalc		= &omap2_clksel_recalc,
 473	.round_rate	= &omap2_clksel_round_rate,
 474	.set_rate	= &omap2_clksel_set_rate,
 475};
 476
 477static const struct clksel dbgclk_mux_sel[] = {
 478	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 479	{ .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
 480	{ .parent = NULL },
 481};
 482
 483static struct clk dbgclk_mux_ck = {
 484	.name		= "dbgclk_mux_ck",
 485	.parent		= &sys_clkin_ck,
 486	.ops		= &clkops_null,
 487	.recalc		= &followparent_recalc,
 488};
 489
 490static const struct clksel dpll_core_m2_div[] = {
 491	{ .parent = &dpll_core_ck, .rates = div31_1to31_rates },
 492	{ .parent = NULL },
 493};
 494
 495static struct clk dpll_core_m2_ck = {
 496	.name		= "dpll_core_m2_ck",
 497	.parent		= &dpll_core_ck,
 498	.clksel		= dpll_core_m2_div,
 499	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_CORE,
 500	.clksel_mask	= OMAP4430_DPLL_CLKOUT_DIV_MASK,
 501	.ops		= &clkops_omap4_dpllmx_ops,
 502	.recalc		= &omap2_clksel_recalc,
 503	.round_rate	= &omap2_clksel_round_rate,
 504	.set_rate	= &omap2_clksel_set_rate,
 505};
 506
 507static struct clk ddrphy_ck = {
 508	.name		= "ddrphy_ck",
 509	.parent		= &dpll_core_m2_ck,
 510	.ops		= &clkops_null,
 511	.fixed_div	= 2,
 512	.recalc		= &omap_fixed_divisor_recalc,
 513};
 514
 515static struct clk dpll_core_m5x2_ck = {
 516	.name		= "dpll_core_m5x2_ck",
 517	.parent		= &dpll_core_x2_ck,
 518	.clksel		= dpll_core_m6x2_div,
 519	.clksel_reg	= OMAP4430_CM_DIV_M5_DPLL_CORE,
 520	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
 521	.ops		= &clkops_omap4_dpllmx_ops,
 522	.recalc		= &omap2_clksel_recalc,
 523	.round_rate	= &omap2_clksel_round_rate,
 524	.set_rate	= &omap2_clksel_set_rate,
 525};
 526
 527static const struct clksel div_core_div[] = {
 528	{ .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates },
 529	{ .parent = NULL },
 530};
 531
 532static struct clk div_core_ck = {
 533	.name		= "div_core_ck",
 534	.parent		= &dpll_core_m5x2_ck,
 535	.clksel		= div_core_div,
 536	.clksel_reg	= OMAP4430_CM_CLKSEL_CORE,
 537	.clksel_mask	= OMAP4430_CLKSEL_CORE_MASK,
 538	.ops		= &clkops_null,
 539	.recalc		= &omap2_clksel_recalc,
 540	.round_rate	= &omap2_clksel_round_rate,
 541	.set_rate	= &omap2_clksel_set_rate,
 542};
 543
 544static const struct clksel_rate div4_1to8_rates[] = {
 545	{ .div = 1, .val = 0, .flags = RATE_IN_4430 },
 546	{ .div = 2, .val = 1, .flags = RATE_IN_4430 },
 547	{ .div = 4, .val = 2, .flags = RATE_IN_4430 },
 548	{ .div = 8, .val = 3, .flags = RATE_IN_4430 },
 549	{ .div = 0 },
 550};
 551
 552static const struct clksel div_iva_hs_clk_div[] = {
 553	{ .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates },
 554	{ .parent = NULL },
 555};
 556
 557static struct clk div_iva_hs_clk = {
 558	.name		= "div_iva_hs_clk",
 559	.parent		= &dpll_core_m5x2_ck,
 560	.clksel		= div_iva_hs_clk_div,
 561	.clksel_reg	= OMAP4430_CM_BYPCLK_DPLL_IVA,
 562	.clksel_mask	= OMAP4430_CLKSEL_0_1_MASK,
 563	.ops		= &clkops_null,
 564	.recalc		= &omap2_clksel_recalc,
 565	.round_rate	= &omap2_clksel_round_rate,
 566	.set_rate	= &omap2_clksel_set_rate,
 567};
 568
 569static struct clk div_mpu_hs_clk = {
 570	.name		= "div_mpu_hs_clk",
 571	.parent		= &dpll_core_m5x2_ck,
 572	.clksel		= div_iva_hs_clk_div,
 573	.clksel_reg	= OMAP4430_CM_BYPCLK_DPLL_MPU,
 574	.clksel_mask	= OMAP4430_CLKSEL_0_1_MASK,
 575	.ops		= &clkops_null,
 576	.recalc		= &omap2_clksel_recalc,
 577	.round_rate	= &omap2_clksel_round_rate,
 578	.set_rate	= &omap2_clksel_set_rate,
 579};
 580
 581static struct clk dpll_core_m4x2_ck = {
 582	.name		= "dpll_core_m4x2_ck",
 583	.parent		= &dpll_core_x2_ck,
 584	.clksel		= dpll_core_m6x2_div,
 585	.clksel_reg	= OMAP4430_CM_DIV_M4_DPLL_CORE,
 586	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
 587	.ops		= &clkops_omap4_dpllmx_ops,
 588	.recalc		= &omap2_clksel_recalc,
 589	.round_rate	= &omap2_clksel_round_rate,
 590	.set_rate	= &omap2_clksel_set_rate,
 591};
 592
 593static struct clk dll_clk_div_ck = {
 594	.name		= "dll_clk_div_ck",
 595	.parent		= &dpll_core_m4x2_ck,
 596	.ops		= &clkops_null,
 597	.fixed_div	= 2,
 598	.recalc		= &omap_fixed_divisor_recalc,
 599};
 600
 601static const struct clksel dpll_abe_m2_div[] = {
 602	{ .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
 603	{ .parent = NULL },
 604};
 605
 606static struct clk dpll_abe_m2_ck = {
 607	.name		= "dpll_abe_m2_ck",
 608	.parent		= &dpll_abe_ck,
 609	.clksel		= dpll_abe_m2_div,
 610	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_ABE,
 611	.clksel_mask	= OMAP4430_DPLL_CLKOUT_DIV_MASK,
 612	.ops		= &clkops_omap4_dpllmx_ops,
 613	.recalc		= &omap2_clksel_recalc,
 614	.round_rate	= &omap2_clksel_round_rate,
 615	.set_rate	= &omap2_clksel_set_rate,
 616};
 617
 618static struct clk dpll_core_m3x2_ck = {
 619	.name		= "dpll_core_m3x2_ck",
 620	.parent		= &dpll_core_x2_ck,
 621	.clksel		= dpll_core_m6x2_div,
 622	.clksel_reg	= OMAP4430_CM_DIV_M3_DPLL_CORE,
 623	.clksel_mask	= OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
 624	.ops		= &clkops_omap2_dflt,
 625	.recalc		= &omap2_clksel_recalc,
 626	.round_rate	= &omap2_clksel_round_rate,
 627	.set_rate	= &omap2_clksel_set_rate,
 628	.enable_reg	= OMAP4430_CM_DIV_M3_DPLL_CORE,
 629	.enable_bit	= OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
 630};
 631
 632static struct clk dpll_core_m7x2_ck = {
 633	.name		= "dpll_core_m7x2_ck",
 634	.parent		= &dpll_core_x2_ck,
 635	.clksel		= dpll_core_m6x2_div,
 636	.clksel_reg	= OMAP4430_CM_DIV_M7_DPLL_CORE,
 637	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
 638	.ops		= &clkops_omap4_dpllmx_ops,
 639	.recalc		= &omap2_clksel_recalc,
 640	.round_rate	= &omap2_clksel_round_rate,
 641	.set_rate	= &omap2_clksel_set_rate,
 642};
 643
 644static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
 645	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 646	{ .parent = &div_iva_hs_clk, .rates = div_1_1_rates },
 647	{ .parent = NULL },
 648};
 649
 650static struct clk iva_hsd_byp_clk_mux_ck = {
 651	.name		= "iva_hsd_byp_clk_mux_ck",
 652	.parent		= &sys_clkin_ck,
 653	.clksel		= iva_hsd_byp_clk_mux_sel,
 654	.init		= &omap2_init_clksel_parent,
 655	.clksel_reg	= OMAP4430_CM_CLKSEL_DPLL_IVA,
 656	.clksel_mask	= OMAP4430_DPLL_BYP_CLKSEL_MASK,
 657	.ops		= &clkops_null,
 658	.recalc		= &omap2_clksel_recalc,
 659};
 660
 661/* DPLL_IVA */
 662static struct dpll_data dpll_iva_dd = {
 663	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_IVA,
 664	.clk_bypass	= &iva_hsd_byp_clk_mux_ck,
 665	.clk_ref	= &sys_clkin_ck,
 666	.control_reg	= OMAP4430_CM_CLKMODE_DPLL_IVA,
 667	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 668	.autoidle_reg	= OMAP4430_CM_AUTOIDLE_DPLL_IVA,
 669	.idlest_reg	= OMAP4430_CM_IDLEST_DPLL_IVA,
 670	.mult_mask	= OMAP4430_DPLL_MULT_MASK,
 671	.div1_mask	= OMAP4430_DPLL_DIV_MASK,
 672	.enable_mask	= OMAP4430_DPLL_EN_MASK,
 673	.autoidle_mask	= OMAP4430_AUTO_DPLL_MODE_MASK,
 674	.idlest_mask	= OMAP4430_ST_DPLL_CLK_MASK,
 675	.max_multiplier	= 2047,
 676	.max_divider	= 128,
 677	.min_divider	= 1,
 678};
 679
 680
 681static struct clk dpll_iva_ck = {
 682	.name		= "dpll_iva_ck",
 683	.parent		= &sys_clkin_ck,
 684	.dpll_data	= &dpll_iva_dd,
 685	.init		= &omap2_init_dpll_parent,
 686	.ops		= &clkops_omap3_noncore_dpll_ops,
 687	.recalc		= &omap3_dpll_recalc,
 688	.round_rate	= &omap2_dpll_round_rate,
 689	.set_rate	= &omap3_noncore_dpll_set_rate,
 690};
 691
 692static struct clk dpll_iva_x2_ck = {
 693	.name		= "dpll_iva_x2_ck",
 694	.parent		= &dpll_iva_ck,
 695	.flags		= CLOCK_CLKOUTX2,
 696	.ops		= &clkops_null,
 697	.recalc		= &omap3_clkoutx2_recalc,
 698};
 699
 700static const struct clksel dpll_iva_m4x2_div[] = {
 701	{ .parent = &dpll_iva_x2_ck, .rates = div31_1to31_rates },
 702	{ .parent = NULL },
 703};
 704
 705static struct clk dpll_iva_m4x2_ck = {
 706	.name		= "dpll_iva_m4x2_ck",
 707	.parent		= &dpll_iva_x2_ck,
 708	.clksel		= dpll_iva_m4x2_div,
 709	.clksel_reg	= OMAP4430_CM_DIV_M4_DPLL_IVA,
 710	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
 711	.ops		= &clkops_omap4_dpllmx_ops,
 712	.recalc		= &omap2_clksel_recalc,
 713	.round_rate	= &omap2_clksel_round_rate,
 714	.set_rate	= &omap2_clksel_set_rate,
 715};
 716
 717static struct clk dpll_iva_m5x2_ck = {
 718	.name		= "dpll_iva_m5x2_ck",
 719	.parent		= &dpll_iva_x2_ck,
 720	.clksel		= dpll_iva_m4x2_div,
 721	.clksel_reg	= OMAP4430_CM_DIV_M5_DPLL_IVA,
 722	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
 723	.ops		= &clkops_omap4_dpllmx_ops,
 724	.recalc		= &omap2_clksel_recalc,
 725	.round_rate	= &omap2_clksel_round_rate,
 726	.set_rate	= &omap2_clksel_set_rate,
 727};
 728
 729/* DPLL_MPU */
 730static struct dpll_data dpll_mpu_dd = {
 731	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_MPU,
 732	.clk_bypass	= &div_mpu_hs_clk,
 733	.clk_ref	= &sys_clkin_ck,
 734	.control_reg	= OMAP4430_CM_CLKMODE_DPLL_MPU,
 735	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 736	.autoidle_reg	= OMAP4430_CM_AUTOIDLE_DPLL_MPU,
 737	.idlest_reg	= OMAP4430_CM_IDLEST_DPLL_MPU,
 738	.mult_mask	= OMAP4430_DPLL_MULT_MASK,
 739	.div1_mask	= OMAP4430_DPLL_DIV_MASK,
 740	.enable_mask	= OMAP4430_DPLL_EN_MASK,
 741	.autoidle_mask	= OMAP4430_AUTO_DPLL_MODE_MASK,
 742	.idlest_mask	= OMAP4430_ST_DPLL_CLK_MASK,
 743	.max_multiplier	= 2047,
 744	.max_divider	= 128,
 745	.min_divider	= 1,
 746};
 747
 748
 749static struct clk dpll_mpu_ck = {
 750	.name		= "dpll_mpu_ck",
 751	.parent		= &sys_clkin_ck,
 752	.dpll_data	= &dpll_mpu_dd,
 753	.init		= &omap2_init_dpll_parent,
 754	.ops		= &clkops_omap3_noncore_dpll_ops,
 755	.recalc		= &omap3_dpll_recalc,
 756	.round_rate	= &omap2_dpll_round_rate,
 757	.set_rate	= &omap3_noncore_dpll_set_rate,
 758};
 759
 760static const struct clksel dpll_mpu_m2_div[] = {
 761	{ .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
 762	{ .parent = NULL },
 763};
 764
 765static struct clk dpll_mpu_m2_ck = {
 766	.name		= "dpll_mpu_m2_ck",
 767	.parent		= &dpll_mpu_ck,
 768	.clksel		= dpll_mpu_m2_div,
 769	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_MPU,
 770	.clksel_mask	= OMAP4430_DPLL_CLKOUT_DIV_MASK,
 771	.ops		= &clkops_omap4_dpllmx_ops,
 772	.recalc		= &omap2_clksel_recalc,
 773	.round_rate	= &omap2_clksel_round_rate,
 774	.set_rate	= &omap2_clksel_set_rate,
 775};
 776
 777static struct clk per_hs_clk_div_ck = {
 778	.name		= "per_hs_clk_div_ck",
 779	.parent		= &dpll_abe_m3x2_ck,
 780	.ops		= &clkops_null,
 781	.fixed_div	= 2,
 782	.recalc		= &omap_fixed_divisor_recalc,
 783};
 784
 785static const struct clksel per_hsd_byp_clk_mux_sel[] = {
 786	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 787	{ .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates },
 788	{ .parent = NULL },
 789};
 790
 791static struct clk per_hsd_byp_clk_mux_ck = {
 792	.name		= "per_hsd_byp_clk_mux_ck",
 793	.parent		= &sys_clkin_ck,
 794	.clksel		= per_hsd_byp_clk_mux_sel,
 795	.init		= &omap2_init_clksel_parent,
 796	.clksel_reg	= OMAP4430_CM_CLKSEL_DPLL_PER,
 797	.clksel_mask	= OMAP4430_DPLL_BYP_CLKSEL_MASK,
 798	.ops		= &clkops_null,
 799	.recalc		= &omap2_clksel_recalc,
 800};
 801
 802/* DPLL_PER */
 803static struct dpll_data dpll_per_dd = {
 804	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_PER,
 805	.clk_bypass	= &per_hsd_byp_clk_mux_ck,
 806	.clk_ref	= &sys_clkin_ck,
 807	.control_reg	= OMAP4430_CM_CLKMODE_DPLL_PER,
 808	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 809	.autoidle_reg	= OMAP4430_CM_AUTOIDLE_DPLL_PER,
 810	.idlest_reg	= OMAP4430_CM_IDLEST_DPLL_PER,
 811	.mult_mask	= OMAP4430_DPLL_MULT_MASK,
 812	.div1_mask	= OMAP4430_DPLL_DIV_MASK,
 813	.enable_mask	= OMAP4430_DPLL_EN_MASK,
 814	.autoidle_mask	= OMAP4430_AUTO_DPLL_MODE_MASK,
 815	.idlest_mask	= OMAP4430_ST_DPLL_CLK_MASK,
 816	.max_multiplier	= 2047,
 817	.max_divider	= 128,
 818	.min_divider	= 1,
 819};
 820
 821
 822static struct clk dpll_per_ck = {
 823	.name		= "dpll_per_ck",
 824	.parent		= &sys_clkin_ck,
 825	.dpll_data	= &dpll_per_dd,
 826	.init		= &omap2_init_dpll_parent,
 827	.ops		= &clkops_omap3_noncore_dpll_ops,
 828	.recalc		= &omap3_dpll_recalc,
 829	.round_rate	= &omap2_dpll_round_rate,
 830	.set_rate	= &omap3_noncore_dpll_set_rate,
 831};
 832
 833static const struct clksel dpll_per_m2_div[] = {
 834	{ .parent = &dpll_per_ck, .rates = div31_1to31_rates },
 835	{ .parent = NULL },
 836};
 837
 838static struct clk dpll_per_m2_ck = {
 839	.name		= "dpll_per_m2_ck",
 840	.parent		= &dpll_per_ck,
 841	.clksel		= dpll_per_m2_div,
 842	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_PER,
 843	.clksel_mask	= OMAP4430_DPLL_CLKOUT_DIV_MASK,
 844	.ops		= &clkops_omap4_dpllmx_ops,
 845	.recalc		= &omap2_clksel_recalc,
 846	.round_rate	= &omap2_clksel_round_rate,
 847	.set_rate	= &omap2_clksel_set_rate,
 848};
 849
 850static struct clk dpll_per_x2_ck = {
 851	.name		= "dpll_per_x2_ck",
 852	.parent		= &dpll_per_ck,
 853	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_PER,
 854	.flags		= CLOCK_CLKOUTX2,
 855	.ops		= &clkops_omap4_dpllmx_ops,
 856	.recalc		= &omap3_clkoutx2_recalc,
 857};
 858
 859static const struct clksel dpll_per_m2x2_div[] = {
 860	{ .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
 861	{ .parent = NULL },
 862};
 863
 864static struct clk dpll_per_m2x2_ck = {
 865	.name		= "dpll_per_m2x2_ck",
 866	.parent		= &dpll_per_x2_ck,
 867	.clksel		= dpll_per_m2x2_div,
 868	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_PER,
 869	.clksel_mask	= OMAP4430_DPLL_CLKOUT_DIV_MASK,
 870	.ops		= &clkops_omap4_dpllmx_ops,
 871	.recalc		= &omap2_clksel_recalc,
 872	.round_rate	= &omap2_clksel_round_rate,
 873	.set_rate	= &omap2_clksel_set_rate,
 874};
 875
 876static struct clk dpll_per_m3x2_ck = {
 877	.name		= "dpll_per_m3x2_ck",
 878	.parent		= &dpll_per_x2_ck,
 879	.clksel		= dpll_per_m2x2_div,
 880	.clksel_reg	= OMAP4430_CM_DIV_M3_DPLL_PER,
 881	.clksel_mask	= OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
 882	.ops		= &clkops_omap2_dflt,
 883	.recalc		= &omap2_clksel_recalc,
 884	.round_rate	= &omap2_clksel_round_rate,
 885	.set_rate	= &omap2_clksel_set_rate,
 886	.enable_reg	= OMAP4430_CM_DIV_M3_DPLL_PER,
 887	.enable_bit	= OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
 888};
 889
 890static struct clk dpll_per_m4x2_ck = {
 891	.name		= "dpll_per_m4x2_ck",
 892	.parent		= &dpll_per_x2_ck,
 893	.clksel		= dpll_per_m2x2_div,
 894	.clksel_reg	= OMAP4430_CM_DIV_M4_DPLL_PER,
 895	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
 896	.ops		= &clkops_omap4_dpllmx_ops,
 897	.recalc		= &omap2_clksel_recalc,
 898	.round_rate	= &omap2_clksel_round_rate,
 899	.set_rate	= &omap2_clksel_set_rate,
 900};
 901
 902static struct clk dpll_per_m5x2_ck = {
 903	.name		= "dpll_per_m5x2_ck",
 904	.parent		= &dpll_per_x2_ck,
 905	.clksel		= dpll_per_m2x2_div,
 906	.clksel_reg	= OMAP4430_CM_DIV_M5_DPLL_PER,
 907	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
 908	.ops		= &clkops_omap4_dpllmx_ops,
 909	.recalc		= &omap2_clksel_recalc,
 910	.round_rate	= &omap2_clksel_round_rate,
 911	.set_rate	= &omap2_clksel_set_rate,
 912};
 913
 914static struct clk dpll_per_m6x2_ck = {
 915	.name		= "dpll_per_m6x2_ck",
 916	.parent		= &dpll_per_x2_ck,
 917	.clksel		= dpll_per_m2x2_div,
 918	.clksel_reg	= OMAP4430_CM_DIV_M6_DPLL_PER,
 919	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
 920	.ops		= &clkops_omap4_dpllmx_ops,
 921	.recalc		= &omap2_clksel_recalc,
 922	.round_rate	= &omap2_clksel_round_rate,
 923	.set_rate	= &omap2_clksel_set_rate,
 924};
 925
 926static struct clk dpll_per_m7x2_ck = {
 927	.name		= "dpll_per_m7x2_ck",
 928	.parent		= &dpll_per_x2_ck,
 929	.clksel		= dpll_per_m2x2_div,
 930	.clksel_reg	= OMAP4430_CM_DIV_M7_DPLL_PER,
 931	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
 932	.ops		= &clkops_omap4_dpllmx_ops,
 933	.recalc		= &omap2_clksel_recalc,
 934	.round_rate	= &omap2_clksel_round_rate,
 935	.set_rate	= &omap2_clksel_set_rate,
 936};
 937
 938static struct clk usb_hs_clk_div_ck = {
 939	.name		= "usb_hs_clk_div_ck",
 940	.parent		= &dpll_abe_m3x2_ck,
 941	.ops		= &clkops_null,
 942	.fixed_div	= 3,
 943	.recalc		= &omap_fixed_divisor_recalc,
 944};
 945
 946/* DPLL_USB */
 947static struct dpll_data dpll_usb_dd = {
 948	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_USB,
 949	.clk_bypass	= &usb_hs_clk_div_ck,
 950	.flags		= DPLL_J_TYPE,
 951	.clk_ref	= &sys_clkin_ck,
 952	.control_reg	= OMAP4430_CM_CLKMODE_DPLL_USB,
 953	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 954	.autoidle_reg	= OMAP4430_CM_AUTOIDLE_DPLL_USB,
 955	.idlest_reg	= OMAP4430_CM_IDLEST_DPLL_USB,
 956	.mult_mask	= OMAP4430_DPLL_MULT_MASK,
 957	.div1_mask	= OMAP4430_DPLL_DIV_MASK,
 958	.enable_mask	= OMAP4430_DPLL_EN_MASK,
 959	.autoidle_mask	= OMAP4430_AUTO_DPLL_MODE_MASK,
 960	.idlest_mask	= OMAP4430_ST_DPLL_CLK_MASK,
 961	.sddiv_mask	= OMAP4430_DPLL_SD_DIV_MASK,
 962	.max_multiplier	= 4095,
 963	.max_divider	= 256,
 964	.min_divider	= 1,
 965};
 966
 967
 968static struct clk dpll_usb_ck = {
 969	.name		= "dpll_usb_ck",
 970	.parent		= &sys_clkin_ck,
 971	.dpll_data	= &dpll_usb_dd,
 972	.init		= &omap2_init_dpll_parent,
 973	.ops		= &clkops_omap3_noncore_dpll_ops,
 974	.recalc		= &omap3_dpll_recalc,
 975	.round_rate	= &omap2_dpll_round_rate,
 976	.set_rate	= &omap3_noncore_dpll_set_rate,
 977};
 978
 979static struct clk dpll_usb_clkdcoldo_ck = {
 980	.name		= "dpll_usb_clkdcoldo_ck",
 981	.parent		= &dpll_usb_ck,
 982	.clksel_reg	= OMAP4430_CM_CLKDCOLDO_DPLL_USB,
 983	.ops		= &clkops_omap4_dpllmx_ops,
 984	.recalc		= &followparent_recalc,
 985};
 986
 987static const struct clksel dpll_usb_m2_div[] = {
 988	{ .parent = &dpll_usb_ck, .rates = div31_1to31_rates },
 989	{ .parent = NULL },
 990};
 991
 992static struct clk dpll_usb_m2_ck = {
 993	.name		= "dpll_usb_m2_ck",
 994	.parent		= &dpll_usb_ck,
 995	.clksel		= dpll_usb_m2_div,
 996	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_USB,
 997	.clksel_mask	= OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK,
 998	.ops		= &clkops_omap4_dpllmx_ops,
 999	.recalc		= &omap2_clksel_recalc,
1000	.round_rate	= &omap2_clksel_round_rate,
1001	.set_rate	= &omap2_clksel_set_rate,
1002};
1003
1004static const struct clksel ducati_clk_mux_sel[] = {
1005	{ .parent = &div_core_ck, .rates = div_1_0_rates },
1006	{ .parent = &dpll_per_m6x2_ck, .rates = div_1_1_rates },
1007	{ .parent = NULL },
1008};
1009
1010static struct clk ducati_clk_mux_ck = {
1011	.name		= "ducati_clk_mux_ck",
1012	.parent		= &div_core_ck,
1013	.clksel		= ducati_clk_mux_sel,
1014	.init		= &omap2_init_clksel_parent,
1015	.clksel_reg	= OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT,
1016	.clksel_mask	= OMAP4430_CLKSEL_0_0_MASK,
1017	.ops		= &clkops_null,
1018	.recalc		= &omap2_clksel_recalc,
1019};
1020
1021static struct clk func_12m_fclk = {
1022	.name		= "func_12m_fclk",
1023	.parent		= &dpll_per_m2x2_ck,
1024	.ops		= &clkops_null,
1025	.fixed_div	= 16,
1026	.recalc		= &omap_fixed_divisor_recalc,
1027};
1028
1029static struct clk func_24m_clk = {
1030	.name		= "func_24m_clk",
1031	.parent		= &dpll_per_m2_ck,
1032	.ops		= &clkops_null,
1033	.fixed_div	= 4,
1034	.recalc		= &omap_fixed_divisor_recalc,
1035};
1036
1037static struct clk func_24mc_fclk = {
1038	.name		= "func_24mc_fclk",
1039	.parent		= &dpll_per_m2x2_ck,
1040	.ops		= &clkops_null,
1041	.fixed_div	= 8,
1042	.recalc		= &omap_fixed_divisor_recalc,
1043};
1044
1045static const struct clksel_rate div2_4to8_rates[] = {
1046	{ .div = 4, .val = 0, .flags = RATE_IN_4430 },
1047	{ .div = 8, .val = 1, .flags = RATE_IN_4430 },
1048	{ .div = 0 },
1049};
1050
1051static const struct clksel func_48m_fclk_div[] = {
1052	{ .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates },
1053	{ .parent = NULL },
1054};
1055
1056static struct clk func_48m_fclk = {
1057	.name		= "func_48m_fclk",
1058	.parent		= &dpll_per_m2x2_ck,
1059	.clksel		= func_48m_fclk_div,
1060	.clksel_reg	= OMAP4430_CM_SCALE_FCLK,
1061	.clksel_mask	= OMAP4430_SCALE_FCLK_MASK,
1062	.ops		= &clkops_null,
1063	.recalc		= &omap2_clksel_recalc,
1064	.round_rate	= &omap2_clksel_round_rate,
1065	.set_rate	= &omap2_clksel_set_rate,
1066};
1067
1068static struct clk func_48mc_fclk = {
1069	.name		= "func_48mc_fclk",
1070	.parent		= &dpll_per_m2x2_ck,
1071	.ops		= &clkops_null,
1072	.fixed_div	= 4,
1073	.recalc		= &omap_fixed_divisor_recalc,
1074};
1075
1076static const struct clksel_rate div2_2to4_rates[] = {
1077	{ .div = 2, .val = 0, .flags = RATE_IN_4430 },
1078	{ .div = 4, .val = 1, .flags = RATE_IN_4430 },
1079	{ .div = 0 },
1080};
1081
1082static const struct clksel func_64m_fclk_div[] = {
1083	{ .parent = &dpll_per_m4x2_ck, .rates = div2_2to4_rates },
1084	{ .parent = NULL },
1085};
1086
1087static struct clk func_64m_fclk = {
1088	.name		= "func_64m_fclk",
1089	.parent		= &dpll_per_m4x2_ck,
1090	.clksel		= func_64m_fclk_div,
1091	.clksel_reg	= OMAP4430_CM_SCALE_FCLK,
1092	.clksel_mask	= OMAP4430_SCALE_FCLK_MASK,
1093	.ops		= &clkops_null,
1094	.recalc		= &omap2_clksel_recalc,
1095	.round_rate	= &omap2_clksel_round_rate,
1096	.set_rate	= &omap2_clksel_set_rate,
1097};
1098
1099static const struct clksel func_96m_fclk_div[] = {
1100	{ .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates },
1101	{ .parent = NULL },
1102};
1103
1104static struct clk func_96m_fclk = {
1105	.name		= "func_96m_fclk",
1106	.parent		= &dpll_per_m2x2_ck,
1107	.clksel		= func_96m_fclk_div,
1108	.clksel_reg	= OMAP4430_CM_SCALE_FCLK,
1109	.clksel_mask	= OMAP4430_SCALE_FCLK_MASK,
1110	.ops		= &clkops_null,
1111	.recalc		= &omap2_clksel_recalc,
1112	.round_rate	= &omap2_clksel_round_rate,
1113	.set_rate	= &omap2_clksel_set_rate,
1114};
1115
1116static const struct clksel_rate div2_1to8_rates[] = {
1117	{ .div = 1, .val = 0, .flags = RATE_IN_4430 },
1118	{ .div = 8, .val = 1, .flags = RATE_IN_4430 },
1119	{ .div = 0 },
1120};
1121
1122static const struct clksel init_60m_fclk_div[] = {
1123	{ .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates },
1124	{ .parent = NULL },
1125};
1126
1127static struct clk init_60m_fclk = {
1128	.name		= "init_60m_fclk",
1129	.parent		= &dpll_usb_m2_ck,
1130	.clksel		= init_60m_fclk_div,
1131	.clksel_reg	= OMAP4430_CM_CLKSEL_USB_60MHZ,
1132	.clksel_mask	= OMAP4430_CLKSEL_0_0_MASK,
1133	.ops		= &clkops_null,
1134	.recalc		= &omap2_clksel_recalc,
1135	.round_rate	= &omap2_clksel_round_rate,
1136	.set_rate	= &omap2_clksel_set_rate,
1137};
1138
1139static const struct clksel l3_div_div[] = {
1140	{ .parent = &div_core_ck, .rates = div2_1to2_rates },
1141	{ .parent = NULL },
1142};
1143
1144static struct clk l3_div_ck = {
1145	.name		= "l3_div_ck",
1146	.parent		= &div_core_ck,
1147	.clksel		= l3_div_div,
1148	.clksel_reg	= OMAP4430_CM_CLKSEL_CORE,
1149	.clksel_mask	= OMAP4430_CLKSEL_L3_MASK,
1150	.ops		= &clkops_null,
1151	.recalc		= &omap2_clksel_recalc,
1152	.round_rate	= &omap2_clksel_round_rate,
1153	.set_rate	= &omap2_clksel_set_rate,
1154};
1155
1156static const struct clksel l4_div_div[] = {
1157	{ .parent = &l3_div_ck, .rates = div2_1to2_rates },
1158	{ .parent = NULL },
1159};
1160
1161static struct clk l4_div_ck = {
1162	.name		= "l4_div_ck",
1163	.parent		= &l3_div_ck,
1164	.clksel		= l4_div_div,
1165	.clksel_reg	= OMAP4430_CM_CLKSEL_CORE,
1166	.clksel_mask	= OMAP4430_CLKSEL_L4_MASK,
1167	.ops		= &clkops_null,
1168	.recalc		= &omap2_clksel_recalc,
1169	.round_rate	= &omap2_clksel_round_rate,
1170	.set_rate	= &omap2_clksel_set_rate,
1171};
1172
1173static struct clk lp_clk_div_ck = {
1174	.name		= "lp_clk_div_ck",
1175	.parent		= &dpll_abe_m2x2_ck,
1176	.ops		= &clkops_null,
1177	.fixed_div	= 16,
1178	.recalc		= &omap_fixed_divisor_recalc,
1179};
1180
1181static const struct clksel l4_wkup_clk_mux_sel[] = {
1182	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1183	{ .parent = &lp_clk_div_ck, .rates = div_1_1_rates },
1184	{ .parent = NULL },
1185};
1186
1187static struct clk l4_wkup_clk_mux_ck = {
1188	.name		= "l4_wkup_clk_mux_ck",
1189	.parent		= &sys_clkin_ck,
1190	.clksel		= l4_wkup_clk_mux_sel,
1191	.init		= &omap2_init_clksel_parent,
1192	.clksel_reg	= OMAP4430_CM_L4_WKUP_CLKSEL,
1193	.clksel_mask	= OMAP4430_CLKSEL_0_0_MASK,
1194	.ops		= &clkops_null,
1195	.recalc		= &omap2_clksel_recalc,
1196};
1197
1198static struct clk ocp_abe_iclk = {
1199	.name		= "ocp_abe_iclk",
1200	.parent		= &aess_fclk,
1201	.ops		= &clkops_null,
1202	.recalc		= &followparent_recalc,
1203};
1204
1205static struct clk per_abe_24m_fclk = {
1206	.name		= "per_abe_24m_fclk",
1207	.parent		= &dpll_abe_m2_ck,
1208	.ops		= &clkops_null,
1209	.fixed_div	= 4,
1210	.recalc		= &omap_fixed_divisor_recalc,
1211};
1212
1213static const struct clksel per_abe_nc_fclk_div[] = {
1214	{ .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
1215	{ .parent = NULL },
1216};
1217
1218static struct clk per_abe_nc_fclk = {
1219	.name		= "per_abe_nc_fclk",
1220	.parent		= &dpll_abe_m2_ck,
1221	.clksel		= per_abe_nc_fclk_div,
1222	.clksel_reg	= OMAP4430_CM_SCALE_FCLK,
1223	.clksel_mask	= OMAP4430_SCALE_FCLK_MASK,
1224	.ops		= &clkops_null,
1225	.recalc		= &omap2_clksel_recalc,
1226	.round_rate	= &omap2_clksel_round_rate,
1227	.set_rate	= &omap2_clksel_set_rate,
1228};
1229
1230static const struct clksel pmd_stm_clock_mux_sel[] = {
1231	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1232	{ .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
1233	{ .parent = &tie_low_clock_ck, .rates = div_1_2_rates },
1234	{ .parent = NULL },
1235};
1236
1237static struct clk pmd_stm_clock_mux_ck = {
1238	.name		= "pmd_stm_clock_mux_ck",
1239	.parent		= &sys_clkin_ck,
1240	.ops		= &clkops_null,
1241	.recalc		= &followparent_recalc,
1242};
1243
1244static struct clk pmd_trace_clk_mux_ck = {
1245	.name		= "pmd_trace_clk_mux_ck",
1246	.parent		= &sys_clkin_ck,
1247	.ops		= &clkops_null,
1248	.recalc		= &followparent_recalc,
1249};
1250
1251static const struct clksel syc_clk_div_div[] = {
1252	{ .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
1253	{ .parent = NULL },
1254};
1255
1256static struct clk syc_clk_div_ck = {
1257	.name		= "syc_clk_div_ck",
1258	.parent		= &sys_clkin_ck,
1259	.clksel		= syc_clk_div_div,
1260	.clksel_reg	= OMAP4430_CM_ABE_DSS_SYS_CLKSEL,
1261	.clksel_mask	= OMAP4430_CLKSEL_0_0_MASK,
1262	.ops		= &clkops_null,
1263	.recalc		= &omap2_clksel_recalc,
1264	.round_rate	= &omap2_clksel_round_rate,
1265	.set_rate	= &omap2_clksel_set_rate,
1266};
1267
1268/* Leaf clocks controlled by modules */
1269
1270static struct clk aes1_fck = {
1271	.name		= "aes1_fck",
1272	.ops		= &clkops_omap2_dflt,
1273	.enable_reg	= OMAP4430_CM_L4SEC_AES1_CLKCTRL,
1274	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
1275	.clkdm_name	= "l4_secure_clkdm",
1276	.parent		= &l3_div_ck,
1277	.recalc		= &followparent_recalc,
1278};
1279
1280static struct clk aes2_fck = {
1281	.name		= "aes2_fck",
1282	.ops		= &clkops_omap2_dflt,
1283	.enable_reg	= OMAP4430_CM_L4SEC_AES2_CLKCTRL,
1284	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
1285	.clkdm_name	= "l4_secure_clkdm",
1286	.parent		= &l3_div_ck,
1287	.recalc		= &followparent_recalc,
1288};
1289
1290static struct clk aess_fck = {
1291	.name		= "aess_fck",
1292	.ops		= &clkops_omap2_dflt,
1293	.enable_reg	= OMAP4430_CM1_ABE_AESS_CLKCTRL,
1294	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
1295	.clkdm_name	= "abe_clkdm",
1296	.parent		= &aess_fclk,
1297	.recalc		= &followparent_recalc,
1298};
1299
1300static struct clk bandgap_fclk = {
1301	.name		= "bandgap_fclk",
1302	.ops		= &clkops_omap2_dflt,
1303	.enable_reg	= OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1304	.enable_bit	= OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT,
1305	.clkdm_name	= "l4_wkup_clkdm",
1306	.parent		= &sys_32k_ck,
1307	.recalc		= &followparent_recalc,
1308};
1309
1310static struct clk des3des_fck = {
1311	.name		= "des3des_fck",
1312	.ops		= &clkops_omap2_dflt,
1313	.enable_reg	= OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
1314	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
1315	.clkdm_name	= "l4_secure_clkdm",
1316	.parent		= &l4_div_ck,
1317	.recalc		= &followparent_recalc,
1318};
1319
1320static const struct clksel dmic_sync_mux_sel[] = {
1321	{ .parent = &abe_24m_fclk, .rates = div_1_0_rates },
1322	{ .parent = &syc_clk_div_ck, .rates = div_1_1_rates },
1323	{ .parent = &func_24m_clk, .rates = div_1_2_rates },
1324	{ .parent = NULL },
1325};
1326
1327static struct clk dmic_sync_mux_ck = {
1328	.name		= "dmic_sync_mux_ck",
1329	.parent		= &abe_24m_fclk,
1330	.clksel		= dmic_sync_mux_sel,
1331	.init		= &omap2_init_clksel_parent,
1332	.clksel_reg	= OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1333	.clksel_mask	= OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1334	.ops		= &clkops_null,
1335	.recalc		= &omap2_clksel_recalc,
1336};
1337
1338static const struct clksel func_dmic_abe_gfclk_sel[] = {
1339	{ .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
1340	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
1341	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
1342	{ .parent = NULL },
1343};
1344
1345/* Merged func_dmic_abe_gfclk into dmic */
1346static struct clk dmic_fck = {
1347	.name		= "dmic_fck",
1348	.parent		= &dmic_sync_mux_ck,
1349	.clksel		= func_dmic_abe_gfclk_sel,
1350	.init		= &omap2_init_clksel_parent,
1351	.clksel_reg	= OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1352	.clksel_mask	= OMAP4430_CLKSEL_SOURCE_MASK,
1353	.ops		= &clkops_omap2_dflt,
1354	.recalc		= &omap2_clksel_recalc,
1355	.enable_reg	= OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1356	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
1357	.clkdm_name	= "abe_clkdm",
1358};
1359
1360static struct clk dsp_fck = {
1361	.name		= "dsp_fck",
1362	.ops		= &clkops_omap2_dflt,
1363	.enable_reg	= OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1364	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
1365	.clkdm_name	= "tesla_clkdm",
1366	.parent		= &dpll_iva_m4x2_ck,
1367	.recalc		= &followparent_recalc,
1368};
1369
1370static struct clk dss_sys_clk = {
1371	.name		= "dss_sys_clk",
1372	.ops		= &clkops_omap2_dflt,
1373	.enable_reg	= OMAP4430_CM_DSS_DSS_CLKCTRL,
1374	.enable_bit	= OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT,
1375	.clkdm_name	= "l3_dss_clkdm",
1376	.parent		= &syc_clk_div_ck,
1377	.recalc		= &followparent_recalc,
1378};
1379
1380static struct clk dss_tv_clk = {
1381	.name		= "dss_tv_clk",
1382	.ops		= &clkops_omap2_dflt,
1383	.enable_reg	= OMAP4430_CM_DSS_DSS_CLKCTRL,
1384	.enable_bit	= OMAP4430_OPTFCLKEN_TV_CLK_SHIFT,
1385	.clkdm_name	= "l3_dss_clkdm",
1386	.parent		= &extalt_clkin_ck,
1387	.recalc		= &followparent_recalc,
1388};
1389
1390static struct clk dss_dss_clk = {
1391	.name		= "dss_dss_clk",
1392	.ops		= &clkops_omap2_dflt,
1393	.enable_reg	= OMAP4430_CM_DSS_DSS_CLKCTRL,
1394	.enable_bit	= OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
1395	.clkdm_name	= "l3_dss_clkdm",
1396	.parent		= &dpll_per_m5x2_ck,
1397	.recalc		= &followparent_recalc,
1398};
1399
1400static const struct clksel_rate div3_8to32_rates[] = {
1401	{ .div = 8, .val = 0, .flags = RATE_IN_44XX },
1402	{ .div = 16, .val = 1, .flags = RATE_IN_44XX },
1403	{ .div = 32, .val = 2, .flags = RATE_IN_44XX },
1404	{ .div = 0 },
1405};
1406
1407static const struct clksel div_ts_div[] = {
1408	{ .parent = &l4_wkup_clk_mux_ck, .rates = div3_8to32_rates },
1409	{ .parent = NULL },
1410};
1411
1412static struct clk div_ts_ck = {
1413	.name		= "div_ts_ck",
1414	.parent		= &l4_wkup_clk_mux_ck,
1415	.clksel		= div_ts_div,
1416	.clksel_reg	= OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1417	.clksel_mask	= OMAP4430_CLKSEL_24_25_MASK,
1418	.ops		= &clkops_null,
1419	.recalc		= &omap2_clksel_recalc,
1420	.round_rate	= &omap2_clksel_round_rate,
1421	.set_rate	= &omap2_clksel_set_rate,
1422};
1423
1424static struct clk bandgap_ts_fclk = {
1425	.name		= "bandgap_ts_fclk",
1426	.ops		= &clkops_omap2_dflt,
1427	.enable_reg	= OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1428	.enable_bit	= OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
1429	.clkdm_name	= "l4_wkup_clkdm",
1430	.parent		= &div_ts_ck,
1431	.recalc		= &followparent_recalc,
1432};
1433
1434static struct clk dss_48mhz_clk = {
1435	.name		= "dss_48mhz_clk",
1436	.ops		= &clkops_omap2_dflt,
1437	.enable_reg	= OMAP4430_CM_DSS_DSS_CLKCTRL,
1438	.enable_bit	= OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
1439	.clkdm_name	= "l3_dss_clkdm",
1440	.parent		= &func_48mc_fclk,
1441	.recalc		= &followparent_recalc,
1442};
1443
1444static struct clk dss_fck = {
1445	.name		= "dss_fck",
1446	.ops		= &clkops_omap2_dflt,
1447	.enable_reg	= OMAP4430_CM_DSS_DSS_CLKCTRL,
1448	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
1449	.clkdm_name	= "l3_dss_clkdm",
1450	.parent		= &l3_div_ck,
1451	.recalc		= &followparent_recalc,
1452};
1453
1454static struct clk efuse_ctrl_cust_fck = {
1455	.name		= "efuse_ctrl_cust_fck",
1456	.ops		= &clkops_omap2_dflt,
1457	.enable_reg	= OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
1458	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
1459	.clkdm_name	= "l4_cefuse_clkdm",
1460	.parent		= &sys_clkin_ck,
1461	.recalc		= &followparent_recalc,
1462};
1463
1464static struct clk emif1_fck = {
1465	.name		= "emif1_fck",
1466	.ops		= &clkops_omap2_dflt,
1467	.enable_reg	= OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
1468	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
1469	.flags		= ENABLE_ON_INIT,
1470	.clkdm_name	= "l3_emif_clkdm",
1471	.parent		= &ddrphy_ck,
1472	.recalc		= &followparent_recalc,
1473};
1474
1475static struct clk emif2_fck = {
1476	.name		= "emif2_fck",
1477	.ops		= &clkops_omap2_dflt,
1478	.enable_reg	= OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
1479	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
1480	.flags		= ENABLE_ON_INIT,
1481	.clkdm_name	= "l3_emif_clkdm",
1482	.parent		= &ddrphy_ck,
1483	.recalc		= &followparent_recalc,
1484};
1485
1486static const struct clksel fdif_fclk_div[] = {
1487	{ .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates },
1488	{ .parent = NULL },
1489};
1490
1491/* Merged fdif_fclk into fdif */
1492static struct clk fdif_fck = {
1493	.name		= "fdif_fck",
1494	.parent		= &dpll_per_m4x2_ck,
1495	.clksel		= fdif_fclk_div,
1496	.clksel_reg	= OMAP4430_CM_CAM_FDIF_CLKCTRL,
1497	.clksel_mask	= OMAP4430_CLKSEL_FCLK_MASK,
1498	.ops		= &clkops_omap2_dflt,
1499	.recalc		= &omap2_clksel_recalc,
1500	.round_rate	= &omap2_clksel_round_rate,
1501	.set_rate	= &omap2_clksel_set_rate,
1502	.enable_reg	= OMAP4430_CM_CAM_FDIF_CLKCTRL,
1503	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
1504	.clkdm_name	= "iss_clkdm",
1505};
1506
1507static struct clk fpka_fck = {
1508	.name		= "fpka_fck",
1509	.ops		= &clkops_omap2_dflt,
1510	.enable_reg	= OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
1511	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
1512	.clkdm_name	= "l4_secure_clkdm",
1513	.parent		= &l4_div_ck,
1514	.recalc		= &followparent_recalc,
1515};
1516
1517static struct clk gpio1_dbclk = {
1518	.name		= "gpio1_dbclk",
1519	.ops		= &clkops_omap2_dflt,
1520	.enable_reg	= OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1521	.enable_bit	= OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1522	.clkdm_name	= "l4_wkup_clkdm",
1523	.parent		= &sys_32k_ck,
1524	.recalc		= &followparent_recalc,
1525};
1526
1527static struct clk gpio1_ick = {
1528	.name		= "gpio1_ick",
1529	.ops		= &clkops_omap2_dflt,
1530	.enable_reg	= OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1531	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
1532	.clkdm_name	= "l4_wkup_clkdm",
1533	.parent		= &l4_wkup_clk_mux_ck,
1534	.recalc		= &followparent_recalc,
1535};
1536
1537static struct clk gpio2_dbclk = {
1538	.name		= "gpio2_dbclk",
1539	.ops		= &clkops_omap2_dflt,
1540	.enable_reg	= OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1541	.enable_bit	= OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1542	.clkdm_name	= "l4_per_clkdm",
1543	.parent		= &sys_32k_ck,
1544	.recalc		= &followparent_recalc,
1545};
1546
1547static struct clk gpio2_ick = {
1548	.name		= "gpio2_ick",
1549	.ops		= &clkops_omap2_dflt,
1550	.enable_reg	= OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1551	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
1552	.clkdm_name	= "l4_per_clkdm",
1553	.parent		= &l4_div_ck,
1554	.recalc		= &followparent_recalc,
1555};
1556
1557static struct clk gpio3_dbclk = {
1558	.name		= "gpio3_dbclk",
1559	.ops		= &clkops_omap2_dflt,
1560	.enable_reg	= OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1561	.enable_bit	= OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1562	.clkdm_name	= "l4_per_clkdm",
1563	.parent		= &sys_32k_ck,
1564	.recalc		= &followparent_recalc,
1565};
1566
1567static struct clk gpio3_ick = {
1568	.name		= "gpio3_ick",
1569	.ops		= &clkops_omap2_dflt,
1570	.enable_reg	= OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1571	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
1572	.clkdm_name	= "l4_per_clkdm",
1573	.parent		= &l4_div_ck,
1574	.recalc		= &followparent_recalc,
1575};
1576
1577static struct clk gpio4_dbclk = {
1578	.name		= "gpio4_dbclk",
1579	.ops		= &clkops_omap2_dflt,
1580	.enable_reg	= OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1581	.enable_bit	= OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1582	.clkdm_name	= "l4_per_clkdm",
1583	.parent		= &sys_32k_ck,
1584	.recalc		= &followparent_recalc,
1585};
1586
1587static struct clk gpio4_ick = {
1588	.name		= "gpio4_ick",
1589	.ops		= &clkops_omap2_dflt,
1590	.enable_reg	= OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1591	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
1592	.clkdm_name	= "l4_per_clkdm",
1593	.parent		= &l4_div_ck,
1594	.recalc		= &followparent_recalc,
1595};
1596
1597static struct clk gpio5_dbclk = {
1598	.name		= "gpio5_dbclk",
1599	.ops		= &clkops_omap2_dflt,
1600	.enable_reg	= OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1601	.enable_bit	= OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1602	.clkdm_name	= "l4_per_clkdm",
1603	.parent		= &sys_32k_ck,
1604	.recalc		= &followparent_recalc,
1605};
1606
1607static struct clk gpio5_ick = {
1608	.name		= "gpio5_ick",
1609	.ops		= &clkops_omap2_dflt,
1610	.enable_reg	= OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1611	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
1612	.clkdm_name	= "l4_per_clkdm",
1613	.parent		= &l4_div_ck,
1614	.recalc		= &followparent_recalc,
1615};
1616
1617static struct clk gpio6_dbclk = {
1618	.name		= "gpio6_dbclk",
1619	.ops		= &clkops_omap2_dflt,
1620	.enable_reg	= OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1621	.enable_bit	= OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1622	.clkdm_name	= "l4_per_clkdm",
1623	.parent		= &sys_32k_ck,
1624	.recalc		= &followparent_recalc,
1625};
1626
1627static struct clk gpio6_ick = {
1628	.name		= "gpio6_ick",
1629	.ops		= &clkops_omap2_dflt,
1630	.enable_reg	= OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1631	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
1632	.clkdm_name	= "l4_per_clkdm",
1633	.parent		= &l4_div_ck,
1634	.recalc		= &followparent_recalc,
1635};
1636
1637static struct clk gpmc_ick = {
1638	.name		= "gpmc_ick",
1639	.ops		= &clkops_omap2_dflt,
1640	.enable_reg	= OMAP4430_CM_L3_2_GPMC_CLKCTRL,
1641	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
1642	.flags		= ENABLE_ON_INIT,
1643	.clkdm_name	= "l3_2_clkdm",
1644	.parent		= &l3_div_ck,
1645	.recalc		= &followparent_recalc,
1646};
1647
1648static const struct clksel sgx_clk_mux_sel[] = {
1649	{ .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
1650	{ .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
1651	{ .parent = NULL },
1652};
1653
1654/* Merged sgx_clk_mux into gpu */
1655static struct clk gpu_fck = {
1656	.name		= "gpu_fck",
1657	.parent		= &dpll_core_m7x2_ck,
1658	.clksel		= sgx_clk_mux_sel,
1659	.init		= &omap2_init_clksel_parent,
1660	.clksel_reg	= OMAP4430_CM_GFX_GFX_CLKCTRL,
1661	.clksel_mask	= OMAP4430_CLKSEL_SGX_FCLK_MASK,
1662	.ops		= &clkops_omap2_dflt,
1663	.recalc		= &omap2_clksel_recalc,
1664	.enable_reg	= OMAP4430_CM_GFX_GFX_CLKCTRL,
1665	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
1666	.clkdm_name	= "l3_gfx_clkdm",
1667};
1668
1669static struct clk hdq1w_fck = {
1670	.name		= "hdq1w_fck",
1671	.ops		= &clkops_omap2_dflt,
1672	.enable_reg	= OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
1673	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
1674	.clkdm_name	= "l4_per_clkdm",
1675	.parent		= &func_12m_fclk,
1676	.recalc		= &followparent_recalc,
1677};
1678
1679static const struct clksel hsi_fclk_div[] = {
1680	{ .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
1681	{ .parent = NULL },
1682};
1683
1684/* Merged hsi_fclk into hsi */
1685static struct clk hsi_fck = {
1686	.name		= "hsi_fck",
1687	.parent		= &dpll_per_m2x2_ck,
1688	.clksel		= hsi_fclk_div,
1689	.clksel_reg	= OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1690	.clksel_mask	= OMAP4430_CLKSEL_24_25_MASK,
1691	.ops		= &clkops_omap2_dflt,
1692	.recalc		= &omap2_clksel_recalc,
1693	.round_rate	= &omap2_clksel_round_rate,
1694	.set_rate	= &omap2_clksel_set_rate,
1695	.enable_reg	= OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1696	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
1697	.clkdm_name	= "l3_init_clkdm",
1698};
1699
1700static struct clk i2c1_fck = {
1701	.name		= "i2c1_fck",
1702	.ops		= &clkops_omap2_dflt,
1703	.enable_reg	= OMAP4430_CM_L4PER_I2C1_CLKCTRL,
1704	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
1705	.clkdm_name	= "l4_per_clkdm",
1706	.parent		= &func_96m_fclk,
1707	.recalc		= &followparent_recalc,
1708};
1709
1710static struct clk i2c2_fck = {
1711	.name		= "i2c2_fck",
1712	.ops		= &clkops_omap2_dflt,
1713	.enable_reg	= OMAP4430_CM_L4PER_I2C2_CLKCTRL,
1714	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
1715	.clkdm_name	= "l4_per_clkdm",
1716	.parent		= &func_96m_fclk,
1717	.recalc		= &followparent_recalc,
1718};
1719
1720static struct clk i2c3_fck = {
1721	.name		= "i2c3_fck",
1722	.ops		= &clkops_omap2_dflt,
1723	.enable_reg	= OMAP4430_CM_L4PER_I2C3_CLKCTRL,
1724	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
1725	.clkdm_name	= "l4_per_clkdm",
1726	.parent		= &func_96m_fclk,
1727	.recalc		= &followparent_recalc,
1728};
1729
1730static struct clk i2c4_fck = {
1731	.name		= "i2c4_fck",
1732	.ops		= &clkops_omap2_dflt,
1733	.enable_reg	= OMAP4430_CM_L4PER_I2C4_CLKCTRL,
1734	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
1735	.clkdm_name	= "l4_per_clkdm",
1736	.parent		= &func_96m_fclk,
1737	.recalc		= &followparent_recalc,
1738};
1739
1740static struct clk ipu_fck = {
1741	.name		= "ipu_fck",
1742	.ops		= &clkops_omap2_dflt,
1743	.enable_reg	= OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
1744	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
1745	.clkdm_name	= "ducati_clkdm",
1746	.parent		= &ducati_clk_mux_ck,
1747	.recalc		= &followparent_recalc,
1748};
1749
1750static struct clk iss_ctrlclk = {
1751	.name		= "iss_ctrlclk",
1752	.ops		= &clkops_omap2_dflt,
1753	.enable_reg	= OMAP4430_CM_CAM_ISS_CLKCTRL,
1754	.enable_bit	= OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
1755	.clkdm_name	= "iss_clkdm",
1756	.parent		= &func_96m_fclk,
1757	.recalc		= &followparent_recalc,
1758};
1759
1760static struct clk iss_fck = {
1761	.name		= "iss_fck",
1762	.ops		= &clkops_omap2_dflt,
1763	.enable_reg	= OMAP4430_CM_CAM_ISS_CLKCTRL,
1764	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
1765	.clkdm_name	= "iss_clkdm",
1766	.parent		= &ducati_clk_mux_ck,
1767	.recalc		= &followparent_recalc,
1768};
1769
1770static struct clk iva_fck = {
1771	.name		= "iva_fck",
1772	.ops		= &clkops_omap2_dflt,
1773	.enable_reg	= OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
1774	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
1775	.clkdm_name	= "ivahd_clkdm",
1776	.parent		= &dpll_iva_m5x2_ck,
1777	.recalc		= &followparent_recalc,
1778};
1779
1780static struct clk kbd_fck = {
1781	.name		= "kbd_fck",
1782	.ops		= &clkops_omap2_dflt,
1783	.enable_reg	= OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
1784	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
1785	.clkdm_name	= "l4_wkup_clkdm",
1786	.parent		= &sys_32k_ck,
1787	.recalc		= &followparent_recalc,
1788};
1789
1790static struct clk l3_instr_ick = {
1791	.name		= "l3_instr_ick",
1792	.ops		= &clkops_omap2_dflt,
1793	.enable_reg	= OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
1794	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
1795	.flags		= ENABLE_ON_INIT,
1796	.clkdm_name	= "l3_instr_clkdm",
1797	.parent		= &l3_div_ck,
1798	.recalc		= &followparent_recalc,
1799};
1800
1801static struct clk l3_main_3_ick = {
1802	.name		= "l3_main_3_ick",
1803	.ops		= &clkops_omap2_dflt,
1804	.enable_reg	= OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
1805	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
1806	.flags		= ENABLE_ON_INIT,
1807	.clkdm_name	= "l3_instr_clkdm",
1808	.parent		= &l3_div_ck,
1809	.recalc		= &followparent_recalc,
1810};
1811
1812static struct clk mcasp_sync_mux_ck = {
1813	.name		= "mcasp_sync_mux_ck",
1814	.parent		= &abe_24m_fclk,
1815	.clksel		= dmic_sync_mux_sel,
1816	.init		= &omap2_init_clksel_parent,
1817	.clksel_reg	= OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1818	.clksel_mask	= OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1819	.ops		= &clkops_null,
1820	.recalc		= &omap2_clksel_recalc,
1821};
1822
1823static const struct clksel func_mcasp_abe_gfclk_sel[] = {
1824	{ .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
1825	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
1826	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
1827	{ .parent = NULL },
1828};
1829
1830/* Merged func_mcasp_abe_gfclk into mcasp */
1831static struct clk mcasp_fck = {
1832	.name		= "mcasp_fck",
1833	.parent		= &mcasp_sync_mux_ck,
1834	.clksel		= func_mcasp_abe_gfclk_sel,
1835	.init		= &omap2_init_clksel_parent,
1836	.clksel_reg	= OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1837	.clksel_mask	= OMAP4430_CLKSEL_SOURCE_MASK,
1838	.ops		= &clkops_omap2_dflt,
1839	.recalc		= &omap2_clksel_recalc,
1840	.enable_reg	= OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1841	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
1842	.clkdm_name	= "abe_clkdm",
1843};
1844
1845static struct clk mcbsp1_sync_mux_ck = {
1846	.name		= "mcbsp1_sync_mux_ck",
1847	.parent		= &abe_24m_fclk,
1848	.clksel		= dmic_sync_mux_sel,
1849	.init		= &omap2_init_clksel_parent,
1850	.clksel_reg	= OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1851	.clksel_mask	= OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1852	.ops		= &clkops_null,
1853	.recalc		= &omap2_clksel_recalc,
1854};
1855
1856static const struct clksel func_mcbsp1_gfclk_sel[] = {
1857	{ .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
1858	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
1859	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
1860	{ .parent = NULL },
1861};
1862
1863/* Merged func_mcbsp1_gfclk into mcbsp1 */
1864static struct clk mcbsp1_fck = {
1865	.name		= "mcbsp1_fck",
1866	.parent		= &mcbsp1_sync_mux_ck,
1867	.clksel		= func_mcbsp1_gfclk_sel,
1868	.init		= &omap2_init_clksel_parent,
1869	.clksel_reg	= OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1870	.clksel_mask	= OMAP4430_CLKSEL_SOURCE_MASK,
1871	.ops		= &clkops_omap2_dflt,
1872	.recalc		= &omap2_clksel_recalc,
1873	.enable_reg	= OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1874	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
1875	.clkdm_name	= "abe_clkdm",
1876};
1877
1878static struct clk mcbsp2_sync_mux_ck = {
1879	.name		= "mcbsp2_sync_mux_ck",
1880	.parent		= &abe_24m_fclk,
1881	.clksel		= dmic_sync_mux_sel,
1882	.init		= &omap2_init_clksel_parent,
1883	.clksel_reg	= OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1884	.clksel_mask	= OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1885	.ops		= &clkops_null,
1886	.recalc		= &omap2_clksel_recalc,
1887};
1888
1889static const struct clksel func_mcbsp2_gfclk_sel[] = {
1890	{ .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
1891	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
1892	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
1893	{ .parent = NULL },
1894};
1895
1896/* Merged func_mcbsp2_gfclk into mcbsp2 */
1897static struct clk mcbsp2_fck = {
1898	.name		= "mcbsp2_fck",
1899	.parent		= &mcbsp2_sync_mux_ck,
1900	.clksel		= func_mcbsp2_gfclk_sel,
1901	.init		= &omap2_init_clksel_parent,
1902	.clksel_reg	= OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1903	.clksel_mask	= OMAP4430_CLKSEL_SOURCE_MASK,
1904	.ops		= &clkops_omap2_dflt,
1905	.recalc		= &omap2_clksel_recalc,
1906	.enable_reg	= OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1907	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
1908	.clkdm_name	= "abe_clkdm",
1909};
1910
1911static struct clk mcbsp3_sync_mux_ck = {
1912	.name		= "mcbsp3_sync_mux_ck",
1913	.parent		= &abe_24m_fclk,
1914	.clksel		= dmic_sync_mux_sel,
1915	.init		= &omap2_init_clksel_parent,
1916	.clksel_reg	= OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1917	.clksel_mask	= OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1918	.ops		= &clkops_null,
1919	.recalc		= &omap2_clksel_recalc,
1920};
1921
1922static const struct clksel func_mcbsp3_gfclk_sel[] = {
1923	{ .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
1924	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
1925	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
1926	{ .parent = NULL },
1927};
1928
1929/* Merged func_mcbsp3_gfclk into mcbsp3 */
1930static struct clk mcbsp3_fck = {
1931	.name		= "mcbsp3_fck",
1932	.parent		= &mcbsp3_sync_mux_ck,
1933	.clksel		= func_mcbsp3_gfclk_sel,
1934	.init		= &omap2_init_clksel_parent,
1935	.clksel_reg	= OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1936	.clksel_mask	= OMAP4430_CLKSEL_SOURCE_MASK,
1937	.ops		= &clkops_omap2_dflt,
1938	.recalc		= &omap2_clksel_recalc,
1939	.enable_reg	= OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1940	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
1941	.clkdm_name	= "abe_clkdm",
1942};
1943
1944static const struct clksel mcbsp4_sync_mux_sel[] = {
1945	{ .parent = &func_96m_fclk, .rates = div_1_0_rates },
1946	{ .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
1947	{ .parent = NULL },
1948};
1949
1950static struct clk mcbsp4_sync_mux_ck = {
1951	.name		= "mcbsp4_sync_mux_ck",
1952	.parent		= &func_96m_fclk,
1953	.clksel		= mcbsp4_sync_mux_sel,
1954	.init		= &omap2_init_clksel_parent,
1955	.clksel_reg	= OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1956	.clksel_mask	= OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1957	.ops		= &clkops_null,
1958	.recalc		= &omap2_clksel_recalc,
1959};
1960
1961static const struct clksel per_mcbsp4_gfclk_sel[] = {
1962	{ .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
1963	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
1964	{ .parent = NULL },
1965};
1966
1967/* Merged per_mcbsp4_gfclk into mcbsp4 */
1968static struct clk mcbsp4_fck = {
1969	.name		= "mcbsp4_fck",
1970	.parent		= &mcbsp4_sync_mux_ck,
1971	.clksel		= per_mcbsp4_gfclk_sel,
1972	.init		= &omap2_init_clksel_parent,
1973	.clksel_reg	= OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1974	.clksel_mask	= OMAP4430_CLKSEL_SOURCE_24_24_MASK,
1975	.ops		= &clkops_omap2_dflt,
1976	.recalc		= &omap2_clksel_recalc,
1977	.enable_reg	= OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1978	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
1979	.clkdm_name	= "l4_per_clkdm",
1980};
1981
1982static struct clk mcpdm_fck = {
1983	.name		= "mcpdm_fck",
1984	.ops		= &clkops_omap2_dflt,
1985	.enable_reg	= OMAP4430_CM1_ABE_PDM_CLKCTRL,
1986	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
1987	.clkdm_name	= "abe_clkdm",
1988	.parent		= &pad_clks_ck,
1989	.recalc		= &followparent_recalc,
1990};
1991
1992static struct clk mcspi1_fck = {
1993	.name		= "mcspi1_fck",
1994	.ops		= &clkops_omap2_dflt,
1995	.enable_reg	= OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
1996	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
1997	.clkdm_name	= "l4_per_clkdm",
1998	.parent		= &func_48m_fclk,
1999	.recalc		= &followparent_recalc,
2000};
2001
2002static struct clk mcspi2_fck = {
2003	.name		= "mcspi2_fck",
2004	.ops		= &clkops_omap2_dflt,
2005	.enable_reg	= OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
2006	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
2007	.clkdm_name	= "l4_per_clkdm",
2008	.parent		= &func_48m_fclk,
2009	.recalc		= &followparent_recalc,
2010};
2011
2012static struct clk mcspi3_fck = {
2013	.name		= "mcspi3_fck",
2014	.ops		= &clkops_omap2_dflt,
2015	.enable_reg	= OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
2016	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
2017	.clkdm_name	= "l4_per_clkdm",
2018	.parent		= &func_48m_fclk,
2019	.recalc		= &followparent_recalc,
2020};
2021
2022static struct clk mcspi4_fck = {
2023	.name		= "mcspi4_fck",
2024	.ops		= &clkops_omap2_dflt,
2025	.enable_reg	= OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
2026	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
2027	.clkdm_name	= "l4_per_clkdm",
2028	.parent		= &func_48m_fclk,
2029	.recalc		= &followparent_recalc,
2030};
2031
2032static const struct clksel hsmmc1_fclk_sel[] = {
2033	{ .parent = &func_64m_fclk, .rates = div_1_0_rates },
2034	{ .parent = &func_96m_fclk, .rates = div_1_1_rates },
2035	{ .parent = NULL },
2036};
2037
2038/* Merged hsmmc1_fclk into mmc1 */
2039static struct clk mmc1_fck = {
2040	.name		= "mmc1_fck",
2041	.parent		= &func_64m_fclk,
2042	.clksel		= hsmmc1_fclk_sel,
2043	.init		= &omap2_init_clksel_parent,
2044	.clksel_reg	= OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2045	.clksel_mask	= OMAP4430_CLKSEL_MASK,
2046	.ops		= &clkops_omap2_dflt,
2047	.recalc		= &omap2_clksel_recalc,
2048	.enable_reg	= OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2049	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
2050	.clkdm_name	= "l3_init_clkdm",
2051};
2052
2053/* Merged hsmmc2_fclk into mmc2 */
2054static struct clk mmc2_fck = {
2055	.name		= "mmc2_fck",
2056	.parent		= &func_64m_fclk,
2057	.clksel		= hsmmc1_fclk_sel,
2058	.init		= &omap2_init_clksel_parent,
2059	.clksel_reg	= OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2060	.clksel_mask	= OMAP4430_CLKSEL_MASK,
2061	.ops		= &clkops_omap2_dflt,
2062	.recalc		= &omap2_clksel_recalc,
2063	.enable_reg	= OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2064	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
2065	.clkdm_name	= "l3_init_clkdm",
2066};
2067
2068static struct clk mmc3_fck = {
2069	.name		= "mmc3_fck",
2070	.ops		= &clkops_omap2_dflt,
2071	.enable_reg	= OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
2072	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
2073	.clkdm_name	= "l4_per_clkdm",
2074	.parent		= &func_48m_fclk,
2075	.recalc		= &followparent_recalc,
2076};
2077
2078static struct clk mmc4_fck = {
2079	.name		= "mmc4_fck",
2080	.ops		= &clkops_omap2_dflt,
2081	.enable_reg	= OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
2082	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
2083	.clkdm_name	= "l4_per_clkdm",
2084	.parent		= &func_48m_fclk,
2085	.recalc		= &followparent_recalc,
2086};
2087
2088static struct clk mmc5_fck = {
2089	.name		= "mmc5_fck",
2090	.ops		= &clkops_omap2_dflt,
2091	.enable_reg	= OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
2092	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
2093	.clkdm_name	= "l4_per_clkdm",
2094	.parent		= &func_48m_fclk,
2095	.recalc		= &followparent_recalc,
2096};
2097
2098static struct clk ocp2scp_usb_phy_phy_48m = {
2099	.name		= "ocp2scp_usb_phy_phy_48m",
2100	.ops		= &clkops_omap2_dflt,
2101	.enable_reg	= OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2102	.enable_bit	= OMAP4430_OPTFCLKEN_PHY_48M_SHIFT,
2103	.clkdm_name	= "l3_init_clkdm",
2104	.parent		= &func_48m_fclk,
2105	.recalc		= &followparent_recalc,
2106};
2107
2108static struct clk ocp2scp_usb_phy_ick = {
2109	.name		= "ocp2scp_usb_phy_ick",
2110	.ops		= &clkops_omap2_dflt,
2111	.enable_reg	= OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2112	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
2113	.clkdm_name	= "l3_init_clkdm",
2114	.parent		= &l4_div_ck,
2115	.recalc		= &followparent_recalc,
2116};
2117
2118static struct clk ocp_wp_noc_ick = {
2119	.name		= "ocp_wp_noc_ick",
2120	.ops		= &clkops_omap2_dflt,
2121	.enable_reg	= OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
2122	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
2123	.flags		= ENABLE_ON_INIT,
2124	.clkdm_name	= "l3_instr_clkdm",
2125	.parent		= &l3_div_ck,
2126	.recalc		= &followparent_recalc,
2127};
2128
2129static struct clk rng_ick = {
2130	.name		= "rng_ick",
2131	.ops		= &clkops_omap2_dflt,
2132	.enable_reg	= OMAP4430_CM_L4SEC_RNG_CLKCTRL,
2133	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
2134	.clkdm_name	= "l4_secure_clkdm",
2135	.parent		= &l4_div_ck,
2136	.recalc		= &followparent_recalc,
2137};
2138
2139static struct clk sha2md5_fck = {
2140	.name		= "sha2md5_fck",
2141	.ops		= &clkops_omap2_dflt,
2142	.enable_reg	= OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
2143	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
2144	.clkdm_name	= "l4_secure_clkdm",
2145	.parent		= &l3_div_ck,
2146	.recalc		= &followparent_recalc,
2147};
2148
2149static struct clk sl2if_ick = {
2150	.name		= "sl2if_ick",
2151	.ops		= &clkops_omap2_dflt,
2152	.enable_reg	= OMAP4430_CM_IVAHD_SL2_CLKCTRL,
2153	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
2154	.clkdm_name	= "ivahd_clkdm",
2155	.parent		= &dpll_iva_m5x2_ck,
2156	.recalc		= &followparent_recalc,
2157};
2158
2159static struct clk slimbus1_fclk_1 = {
2160	.name		= "slimbus1_fclk_1",
2161	.ops		= &clkops_omap2_dflt,
2162	.enable_reg	= OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2163	.enable_bit	= OMAP4430_OPTFCLKEN_FCLK1_SHIFT,
2164	.clkdm_name	= "abe_clkdm",
2165	.parent		= &func_24m_clk,
2166	.recalc		= &followparent_recalc,
2167};
2168
2169static struct clk slimbus1_fclk_0 = {
2170	.name		= "slimbus1_fclk_0",
2171	.ops		= &clkops_omap2_dflt,
2172	.enable_reg	= OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2173	.enable_bit	= OMAP4430_OPTFCLKEN_FCLK0_SHIFT,
2174	.clkdm_name	= "abe_clkdm",
2175	.parent		= &abe_24m_fclk,
2176	.recalc		= &followparent_recalc,
2177};
2178
2179static struct clk slimbus1_fclk_2 = {
2180	.name		= "slimbus1_fclk_2",
2181	.ops		= &clkops_omap2_dflt,
2182	.enable_reg	= OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2183	.enable_bit	= OMAP4430_OPTFCLKEN_FCLK2_SHIFT,
2184	.clkdm_name	= "abe_clkdm",
2185	.parent		= &pad_clks_ck,
2186	.recalc		= &followparent_recalc,
2187};
2188
2189static struct clk slimbus1_slimbus_clk = {
2190	.name		= "slimbus1_slimbus_clk",
2191	.ops		= &clkops_omap2_dflt,
2192	.enable_reg	= OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2193	.enable_bit	= OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT,
2194	.clkdm_name	= "abe_clkdm",
2195	.parent		= &slimbus_clk,
2196	.recalc		= &followparent_recalc,
2197};
2198
2199static struct clk slimbus1_fck = {
2200	.name		= "slimbus1_fck",
2201	.ops		= &clkops_omap2_dflt,
2202	.enable_reg	= OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2203	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
2204	.clkdm_name	= "abe_clkdm",
2205	.parent		= &ocp_abe_iclk,
2206	.recalc		= &followparent_recalc,
2207};
2208
2209static struct clk slimbus2_fclk_1 = {
2210	.name		= "slimbus2_fclk_1",
2211	.ops		= &clkops_omap2_dflt,
2212	.enable_reg	= OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2213	.enable_bit	= OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT,
2214	.clkdm_name	= "l4_per_clkdm",
2215	.parent		= &per_abe_24m_fclk,
2216	.recalc		= &followparent_recalc,
2217};
2218
2219static struct clk slimbus2_fclk_0 = {
2220	.name		= "slimbus2_fclk_0",
2221	.ops		= &clkops_omap2_dflt,
2222	.enable_reg	= OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2223	.enable_bit	= OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT,
2224	.clkdm_name	= "l4_per_clkdm",
2225	.parent		= &func_24mc_fclk,
2226	.recalc		= &followparent_recalc,
2227};
2228
2229static struct clk slimbus2_slimbus_clk = {
2230	.name		= "slimbus2_slimbus_clk",
2231	.ops		= &clkops_omap2_dflt,
2232	.enable_reg	= OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2233	.enable_bit	= OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT,
2234	.clkdm_name	= "l4_per_clkdm",
2235	.parent		= &pad_slimbus_core_clks_ck,
2236	.recalc		= &followparent_recalc,
2237};
2238
2239static struct clk slimbus2_fck = {
2240	.name		= "slimbus2_fck",
2241	.ops		= &clkops_omap2_dflt,
2242	.enable_reg	= OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2243	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
2244	.clkdm_name	= "l4_per_clkdm",
2245	.parent		= &l4_div_ck,
2246	.recalc		= &followparent_recalc,
2247};
2248
2249static struct clk smartreflex_core_fck = {
2250	.name		= "smartreflex_core_fck",
2251	.ops		= &clkops_omap2_dflt,
2252	.enable_reg	= OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
2253	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
2254	.clkdm_name	= "l4_ao_clkdm",
2255	.parent		= &l4_wkup_clk_mux_ck,
2256	.recalc		= &followparent_recalc,
2257};
2258
2259static struct clk smartreflex_iva_fck = {
2260	.name		= "smartreflex_iva_fck",
2261	.ops		= &clkops_omap2_dflt,
2262	.enable_reg	= OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
2263	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
2264	.clkdm_name	= "l4_ao_clkdm",
2265	.parent		= &l4_wkup_clk_mux_ck,
2266	.recalc		= &followparent_recalc,
2267};
2268
2269static struct clk smartreflex_mpu_fck = {
2270	.name		= "smartreflex_mpu_fck",
2271	.ops		= &clkops_omap2_dflt,
2272	.enable_reg	= OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
2273	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
2274	.clkdm_name	= "l4_ao_clkdm",
2275	.parent		= &l4_wkup_clk_mux_ck,
2276	.recalc		= &followparent_recalc,
2277};
2278
2279/* Merged dmt1_clk_mux into timer1 */
2280static struct clk timer1_fck = {
2281	.name		= "timer1_fck",
2282	.parent		= &sys_clkin_ck,
2283	.clksel		= abe_dpll_bypass_clk_mux_sel,
2284	.init		= &omap2_init_clksel_parent,
2285	.clksel_reg	= OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2286	.clksel_mask	= OMAP4430_CLKSEL_MASK,
2287	.ops		= &clkops_omap2_dflt,
2288	.recalc		= &omap2_clksel_recalc,
2289	.enable_reg	= OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2290	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
2291	.clkdm_name	= "l4_wkup_clkdm",
2292};
2293
2294/* Merged cm2_dm10_mux into timer10 */
2295static struct clk timer10_fck = {
2296	.name		= "timer10_fck",
2297	.parent		= &sys_clkin_ck,
2298	.clksel		= abe_dpll_bypass_clk_mux_sel,
2299	.init		= &omap2_init_clksel_parent,
2300	.clksel_reg	= OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2301	.clksel_mask	= OMAP4430_CLKSEL_MASK,
2302	.ops		= &clkops_omap2_dflt,
2303	.recalc		= &omap2_clksel_recalc,
2304	.enable_reg	= OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2305	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
2306	.clkdm_name	= "l4_per_clkdm",
2307};
2308
2309/* Merged cm2_dm11_mux into timer11 */
2310static struct clk timer11_fck = {
2311	.name		= "timer11_fck",
2312	.parent		= &sys_clkin_ck,
2313	.clksel		= abe_dpll_bypass_clk_mux_sel,
2314	.init		= &omap2_init_clksel_parent,
2315	.clksel_reg	= OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2316	.clksel_mask	= OMAP4430_CLKSEL_MASK,
2317	.ops		= &clkops_omap2_dflt,
2318	.recalc		= &omap2_clksel_recalc,
2319	.enable_reg	= OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2320	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
2321	.clkdm_name	= "l4_per_clkdm",
2322};
2323
2324/* Merged cm2_dm2_mux into timer2 */
2325static struct clk timer2_fck = {
2326	.name		= "timer2_fck",
2327	.parent		= &sys_clkin_ck,
2328	.clksel		= abe_dpll_bypass_clk_mux_sel,
2329	.init		= &omap2_init_clksel_parent,
2330	.clksel_reg	= OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2331	.clksel_mask	= OMAP4430_CLKSEL_MASK,
2332	.ops		= &clkops_omap2_dflt,
2333	.recalc		= &omap2_clksel_recalc,
2334	.enable_reg	= OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2335	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
2336	.clkdm_name	= "l4_per_clkdm",
2337};
2338
2339/* Merged cm2_dm3_mux into timer3 */
2340static struct clk timer3_fck = {
2341	.name		= "timer3_fck",
2342	.parent		= &sys_clkin_ck,
2343	.clksel		= abe_dpll_bypass_clk_mux_sel,
2344	.init		= &omap2_init_clksel_parent,
2345	.clksel_reg	= OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2346	.clksel_mask	= OMAP4430_CLKSEL_MASK,
2347	.ops		= &clkops_omap2_dflt,
2348	.recalc		= &omap2_clksel_recalc,
2349	.enable_reg	= OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2350	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
2351	.clkdm_name	= "l4_per_clkdm",
2352};
2353
2354/* Merged cm2_dm4_mux into timer4 */
2355static struct clk timer4_fck = {
2356	.name		= "timer4_fck",
2357	.parent		= &sys_clkin_ck,
2358	.clksel		= abe_dpll_bypass_clk_mux_sel,
2359	.init		= &omap2_init_clksel_parent,
2360	.clksel_reg	= OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2361	.clksel_mask	= OMAP4430_CLKSEL_MASK,
2362	.ops		= &clkops_omap2_dflt,
2363	.recalc		= &omap2_clksel_recalc,
2364	.enable_reg	= OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2365	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
2366	.clkdm_name	= "l4_per_clkdm",
2367};
2368
2369static const struct clksel timer5_sync_mux_sel[] = {
2370	{ .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
2371	{ .parent = &sys_32k_ck, .rates = div_1_1_rates },
2372	{ .parent = NULL },
2373};
2374
2375/* Merged timer5_sync_mux into timer5 */
2376static struct clk timer5_fck = {
2377	.name		= "timer5_fck",
2378	.parent		= &syc_clk_div_ck,
2379	.clksel		= timer5_sync_mux_sel,
2380	.init		= &omap2_init_clksel_parent,
2381	.clksel_reg	= OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2382	.clksel_mask	= OMAP4430_CLKSEL_MASK,
2383	.ops		= &clkops_omap2_dflt,
2384	.recalc		= &omap2_clksel_recalc,
2385	.enable_reg	= OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2386	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
2387	.clkdm_name	= "abe_clkdm",
2388};
2389
2390/* Merged timer6_sync_mux into timer6 */
2391static struct clk timer6_fck = {
2392	.name		= "timer6_fck",
2393	.parent		= &syc_clk_div_ck,
2394	.clksel		= timer5_sync_mux_sel,
2395	.init		= &omap2_init_clksel_parent,
2396	.clksel_reg	= OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2397	.clksel_mask	= OMAP4430_CLKSEL_MASK,
2398	.ops		= &clkops_omap2_dflt,
2399	.recalc		= &omap2_clksel_recalc,
2400	.enable_reg	= OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2401	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
2402	.clkdm_name	= "abe_clkdm",
2403};
2404
2405/* Merged timer7_sync_mux into timer7 */
2406static struct clk timer7_fck = {
2407	.name		= "timer7_fck",
2408	.parent		= &syc_clk_div_ck,
2409	.clksel		= timer5_sync_mux_sel,
2410	.init		= &omap2_init_clksel_parent,
2411	.clksel_reg	= OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2412	.clksel_mask	= OMAP4430_CLKSEL_MASK,
2413	.ops		= &clkops_omap2_dflt,
2414	.recalc		= &omap2_clksel_recalc,
2415	.enable_reg	= OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2416	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
2417	.clkdm_name	= "abe_clkdm",
2418};
2419
2420/* Merged timer8_sync_mux into timer8 */
2421static struct clk timer8_fck = {
2422	.name		= "timer8_fck",
2423	.parent		= &syc_clk_div_ck,
2424	.clksel		= timer5_sync_mux_sel,
2425	.init		= &omap2_init_clksel_parent,
2426	.clksel_reg	= OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2427	.clksel_mask	= OMAP4430_CLKSEL_MASK,
2428	.ops		= &clkops_omap2_dflt,
2429	.recalc		= &omap2_clksel_recalc,
2430	.enable_reg	= OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2431	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
2432	.clkdm_name	= "abe_clkdm",
2433};
2434
2435/* Merged cm2_dm9_mux into timer9 */
2436static struct clk timer9_fck = {
2437	.name		= "timer9_fck",
2438	.parent		= &sys_clkin_ck,
2439	.clksel		= abe_dpll_bypass_clk_mux_sel,
2440	.init		= &omap2_init_clksel_parent,
2441	.clksel_reg	= OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2442	.clksel_mask	= OMAP4430_CLKSEL_MASK,
2443	.ops		= &clkops_omap2_dflt,
2444	.recalc		= &omap2_clksel_recalc,
2445	.enable_reg	= OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2446	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
2447	.clkdm_name	= "l4_per_clkdm",
2448};
2449
2450static struct clk uart1_fck = {
2451	.name		= "uart1_fck",
2452	.ops		= &clkops_omap2_dflt,
2453	.enable_reg	= OMAP4430_CM_L4PER_UART1_CLKCTRL,
2454	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
2455	.clkdm_name	= "l4_per_clkdm",
2456	.parent		= &func_48m_fclk,
2457	.recalc		= &followparent_recalc,
2458};
2459
2460static struct clk uart2_fck = {
2461	.name		= "uart2_fck",
2462	.ops		= &clkops_omap2_dflt,
2463	.enable_reg	= OMAP4430_CM_L4PER_UART2_CLKCTRL,
2464	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
2465	.clkdm_name	= "l4_per_clkdm",
2466	.parent		= &func_48m_fclk,
2467	.recalc		= &followparent_recalc,
2468};
2469
2470static struct clk uart3_fck = {
2471	.name		= "uart3_fck",
2472	.ops		= &clkops_omap2_dflt,
2473	.enable_reg	= OMAP4430_CM_L4PER_UART3_CLKCTRL,
2474	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
2475	.clkdm_name	= "l4_per_clkdm",
2476	.parent		= &func_48m_fclk,
2477	.recalc		= &followparent_recalc,
2478};
2479
2480static struct clk uart4_fck = {
2481	.name		= "uart4_fck",
2482	.ops		= &clkops_omap2_dflt,
2483	.enable_reg	= OMAP4430_CM_L4PER_UART4_CLKCTRL,
2484	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
2485	.clkdm_name	= "l4_per_clkdm",
2486	.parent		= &func_48m_fclk,
2487	.recalc		= &followparent_recalc,
2488};
2489
2490static struct clk usb_host_fs_fck = {
2491	.name		= "usb_host_fs_fck",
2492	.ops		= &clkops_omap2_dflt,
2493	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
2494	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
2495	.clkdm_name	= "l3_init_clkdm",
2496	.parent		= &func_48mc_fclk,
2497	.recalc		= &followparent_recalc,
2498};
2499
2500static const struct clksel utmi_p1_gfclk_sel[] = {
2501	{ .parent = &init_60m_fclk, .rates = div_1_0_rates },
2502	{ .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
2503	{ .parent = NULL },
2504};
2505
2506static struct clk utmi_p1_gfclk = {
2507	.name		= "utmi_p1_gfclk",
2508	.parent		= &init_60m_fclk,
2509	.clksel		= utmi_p1_gfclk_sel,
2510	.init		= &omap2_init_clksel_parent,
2511	.clksel_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2512	.clksel_mask	= OMAP4430_CLKSEL_UTMI_P1_MASK,
2513	.ops		= &clkops_null,
2514	.recalc		= &omap2_clksel_recalc,
2515};
2516
2517static struct clk usb_host_hs_utmi_p1_clk = {
2518	.name		= "usb_host_hs_utmi_p1_clk",
2519	.ops		= &clkops_omap2_dflt,
2520	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2521	.enable_bit	= OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT,
2522	.clkdm_name	= "l3_init_clkdm",
2523	.parent		= &utmi_p1_gfclk,
2524	.recalc		= &followparent_recalc,
2525};
2526
2527static const struct clksel utmi_p2_gfclk_sel[] = {
2528	{ .parent = &init_60m_fclk, .rates = div_1_0_rates },
2529	{ .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
2530	{ .parent = NULL },
2531};
2532
2533static struct clk utmi_p2_gfclk = {
2534	.name		= "utmi_p2_gfclk",
2535	.parent		= &init_60m_fclk,
2536	.clksel		= utmi_p2_gfclk_sel,
2537	.init		= &omap2_init_clksel_parent,
2538	.clksel_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2539	.clksel_mask	= OMAP4430_CLKSEL_UTMI_P2_MASK,
2540	.ops		= &clkops_null,
2541	.recalc		= &omap2_clksel_recalc,
2542};
2543
2544static struct clk usb_host_hs_utmi_p2_clk = {
2545	.name		= "usb_host_hs_utmi_p2_clk",
2546	.ops		= &clkops_omap2_dflt,
2547	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2548	.enable_bit	= OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT,
2549	.clkdm_name	= "l3_init_clkdm",
2550	.parent		= &utmi_p2_gfclk,
2551	.recalc		= &followparent_recalc,
2552};
2553
2554static struct clk usb_host_hs_utmi_p3_clk = {
2555	.name		= "usb_host_hs_utmi_p3_clk",
2556	.ops		= &clkops_omap2_dflt,
2557	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2558	.enable_bit	= OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
2559	.clkdm_name	= "l3_init_clkdm",
2560	.parent		= &init_60m_fclk,
2561	.recalc		= &followparent_recalc,
2562};
2563
2564static struct clk usb_host_hs_hsic480m_p1_clk = {
2565	.name		= "usb_host_hs_hsic480m_p1_clk",
2566	.ops		= &clkops_omap2_dflt,
2567	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2568	.enable_bit	= OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT,
2569	.clkdm_name	= "l3_init_clkdm",
2570	.parent		= &dpll_usb_m2_ck,
2571	.recalc		= &followparent_recalc,
2572};
2573
2574static struct clk usb_host_hs_hsic60m_p1_clk = {
2575	.name		= "usb_host_hs_hsic60m_p1_clk",
2576	.ops		= &clkops_omap2_dflt,
2577	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2578	.enable_bit	= OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
2579	.clkdm_name	= "l3_init_clkdm",
2580	.parent		= &init_60m_fclk,
2581	.recalc		= &followparent_recalc,
2582};
2583
2584static struct clk usb_host_hs_hsic60m_p2_clk = {
2585	.name		= "usb_host_hs_hsic60m_p2_clk",
2586	.ops		= &clkops_omap2_dflt,
2587	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2588	.enable_bit	= OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
2589	.clkdm_name	= "l3_init_clkdm",
2590	.parent		= &init_60m_fclk,
2591	.recalc		= &followparent_recalc,
2592};
2593
2594static struct clk usb_host_hs_hsic480m_p2_clk = {
2595	.name		= "usb_host_hs_hsic480m_p2_clk",
2596	.ops		= &clkops_omap2_dflt,
2597	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2598	.enable_bit	= OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT,
2599	.clkdm_name	= "l3_init_clkdm",
2600	.parent		= &dpll_usb_m2_ck,
2601	.recalc		= &followparent_recalc,
2602};
2603
2604static struct clk usb_host_hs_func48mclk = {
2605	.name		= "usb_host_hs_func48mclk",
2606	.ops		= &clkops_omap2_dflt,
2607	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2608	.enable_bit	= OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT,
2609	.clkdm_name	= "l3_init_clkdm",
2610	.parent		= &func_48mc_fclk,
2611	.recalc		= &followparent_recalc,
2612};
2613
2614static struct clk usb_host_hs_fck = {
2615	.name		= "usb_host_hs_fck",
2616	.ops		= &clkops_omap2_dflt,
2617	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2618	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
2619	.clkdm_name	= "l3_init_clkdm",
2620	.parent		= &init_60m_fclk,
2621	.recalc		= &followparent_recalc,
2622};
2623
2624static const struct clksel otg_60m_gfclk_sel[] = {
2625	{ .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
2626	{ .parent = &xclk60motg_ck, .rates = div_1_1_rates },
2627	{ .parent = NULL },
2628};
2629
2630static struct clk otg_60m_gfclk = {
2631	.name		= "otg_60m_gfclk",
2632	.parent		= &utmi_phy_clkout_ck,
2633	.clksel		= otg_60m_gfclk_sel,
2634	.init		= &omap2_init_clksel_parent,
2635	.clksel_reg	= OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2636	.clksel_mask	= OMAP4430_CLKSEL_60M_MASK,
2637	.ops		= &clkops_null,
2638	.recalc		= &omap2_clksel_recalc,
2639};
2640
2641static struct clk usb_otg_hs_xclk = {
2642	.name		= "usb_otg_hs_xclk",
2643	.ops		= &clkops_omap2_dflt,
2644	.enable_reg	= OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2645	.enable_bit	= OMAP4430_OPTFCLKEN_XCLK_SHIFT,
2646	.clkdm_name	= "l3_init_clkdm",
2647	.parent		= &otg_60m_gfclk,
2648	.recalc		= &followparent_recalc,
2649};
2650
2651static struct clk usb_otg_hs_ick = {
2652	.name		= "usb_otg_hs_ick",
2653	.ops		= &clkops_omap2_dflt,
2654	.enable_reg	= OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2655	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
2656	.clkdm_name	= "l3_init_clkdm",
2657	.parent		= &l3_div_ck,
2658	.recalc		= &followparent_recalc,
2659};
2660
2661static struct clk usb_phy_cm_clk32k = {
2662	.name		= "usb_phy_cm_clk32k",
2663	.ops		= &clkops_omap2_dflt,
2664	.enable_reg	= OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
2665	.enable_bit	= OMAP4430_OPTFCLKEN_CLK32K_SHIFT,
2666	.clkdm_name	= "l4_ao_clkdm",
2667	.parent		= &sys_32k_ck,
2668	.recalc		= &followparent_recalc,
2669};
2670
2671static struct clk usb_tll_hs_usb_ch2_clk = {
2672	.name		= "usb_tll_hs_usb_ch2_clk",
2673	.ops		= &clkops_omap2_dflt,
2674	.enable_reg	= OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2675	.enable_bit	= OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT,
2676	.clkdm_name	= "l3_init_clkdm",
2677	.parent		= &init_60m_fclk,
2678	.recalc		= &followparent_recalc,
2679};
2680
2681static struct clk usb_tll_hs_usb_ch0_clk = {
2682	.name		= "usb_tll_hs_usb_ch0_clk",
2683	.ops		= &clkops_omap2_dflt,
2684	.enable_reg	= OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2685	.enable_bit	= OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT,
2686	.clkdm_name	= "l3_init_clkdm",
2687	.parent		= &init_60m_fclk,
2688	.recalc		= &followparent_recalc,
2689};
2690
2691static struct clk usb_tll_hs_usb_ch1_clk = {
2692	.name		= "usb_tll_hs_usb_ch1_clk",
2693	.ops		= &clkops_omap2_dflt,
2694	.enable_reg	= OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2695	.enable_bit	= OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT,
2696	.clkdm_name	= "l3_init_clkdm",
2697	.parent		= &init_60m_fclk,
2698	.recalc		= &followparent_recalc,
2699};
2700
2701static struct clk usb_tll_hs_ick = {
2702	.name		= "usb_tll_hs_ick",
2703	.ops		= &clkops_omap2_dflt,
2704	.enable_reg	= OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2705	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
2706	.clkdm_name	= "l3_init_clkdm",
2707	.parent		= &l4_div_ck,
2708	.recalc		= &followparent_recalc,
2709};
2710
2711static const struct clksel_rate div2_14to18_rates[] = {
2712	{ .div = 14, .val = 0, .flags = RATE_IN_4430 },
2713	{ .div = 18, .val = 1, .flags = RATE_IN_4430 },
2714	{ .div = 0 },
2715};
2716
2717static const struct clksel usim_fclk_div[] = {
2718	{ .parent = &dpll_per_m4x2_ck, .rates = div2_14to18_rates },
2719	{ .parent = NULL },
2720};
2721
2722static struct clk usim_ck = {
2723	.name		= "usim_ck",
2724	.parent		= &dpll_per_m4x2_ck,
2725	.clksel		= usim_fclk_div,
2726	.clksel_reg	= OMAP4430_CM_WKUP_USIM_CLKCTRL,
2727	.clksel_mask	= OMAP4430_CLKSEL_DIV_MASK,
2728	.ops		= &clkops_null,
2729	.recalc		= &omap2_clksel_recalc,
2730	.round_rate	= &omap2_clksel_round_rate,
2731	.set_rate	= &omap2_clksel_set_rate,
2732};
2733
2734static struct clk usim_fclk = {
2735	.name		= "usim_fclk",
2736	.ops		= &clkops_omap2_dflt,
2737	.enable_reg	= OMAP4430_CM_WKUP_USIM_CLKCTRL,
2738	.enable_bit	= OMAP4430_OPTFCLKEN_FCLK_SHIFT,
2739	.clkdm_name	= "l4_wkup_clkdm",
2740	.parent		= &usim_ck,
2741	.recalc		= &followparent_recalc,
2742};
2743
2744static struct clk usim_fck = {
2745	.name		= "usim_fck",
2746	.ops		= &clkops_omap2_dflt,
2747	.enable_reg	= OMAP4430_CM_WKUP_USIM_CLKCTRL,
2748	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
2749	.clkdm_name	= "l4_wkup_clkdm",
2750	.parent		= &sys_32k_ck,
2751	.recalc		= &followparent_recalc,
2752};
2753
2754static struct clk wd_timer2_fck = {
2755	.name		= "wd_timer2_fck",
2756	.ops		= &clkops_omap2_dflt,
2757	.enable_reg	= OMAP4430_CM_WKUP_WDT2_CLKCTRL,
2758	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
2759	.clkdm_name	= "l4_wkup_clkdm",
2760	.parent		= &sys_32k_ck,
2761	.recalc		= &followparent_recalc,
2762};
2763
2764static struct clk wd_timer3_fck = {
2765	.name		= "wd_timer3_fck",
2766	.ops		= &clkops_omap2_dflt,
2767	.enable_reg	= OMAP4430_CM1_ABE_WDT3_CLKCTRL,
2768	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
2769	.clkdm_name	= "abe_clkdm",
2770	.parent		= &sys_32k_ck,
2771	.recalc		= &followparent_recalc,
2772};
2773
2774/* Remaining optional clocks */
2775static const struct clksel stm_clk_div_div[] = {
2776	{ .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
2777	{ .parent = NULL },
2778};
2779
2780static struct clk stm_clk_div_ck = {
2781	.name		= "stm_clk_div_ck",
2782	.parent		= &pmd_stm_clock_mux_ck,
2783	.clksel		= stm_clk_div_div,
2784	.clksel_reg	= OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2785	.clksel_mask	= OMAP4430_CLKSEL_PMD_STM_CLK_MASK,
2786	.ops		= &clkops_null,
2787	.recalc		= &omap2_clksel_recalc,
2788	.round_rate	= &omap2_clksel_round_rate,
2789	.set_rate	= &omap2_clksel_set_rate,
2790};
2791
2792static const struct clksel trace_clk_div_div[] = {
2793	{ .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
2794	{ .parent = NULL },
2795};
2796
2797static struct clk trace_clk_div_ck = {
2798	.name		= "trace_clk_div_ck",
2799	.parent		= &pmd_trace_clk_mux_ck,
2800	.clksel		= trace_clk_div_div,
2801	.clksel_reg	= OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2802	.clksel_mask	= OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
2803	.ops		= &clkops_null,
2804	.recalc		= &omap2_clksel_recalc,
2805	.round_rate	= &omap2_clksel_round_rate,
2806	.set_rate	= &omap2_clksel_set_rate,
2807};
2808
2809/* SCRM aux clk nodes */
2810
2811static const struct clksel auxclk_src_sel[] = {
2812	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
2813	{ .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
2814	{ .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
2815	{ .parent = NULL },
2816};
2817
2818static const struct clksel_rate div16_1to16_rates[] = {
2819	{ .div = 1, .val = 0, .flags = RATE_IN_4430 },
2820	{ .div = 2, .val = 1, .flags = RATE_IN_4430 },
2821	{ .div = 3, .val = 2, .flags = RATE_IN_4430 },
2822	{ .div = 4, .val = 3, .flags = RATE_IN_4430 },
2823	{ .div = 5, .val = 4, .flags = RATE_IN_4430 },
2824	{ .div = 6, .val = 5, .flags = RATE_IN_4430 },
2825	{ .div = 7, .val = 6, .flags = RATE_IN_4430 },
2826	{ .div = 8, .val = 7, .flags = RATE_IN_4430 },
2827	{ .div = 9, .val = 8, .flags = RATE_IN_4430 },
2828	{ .div = 10, .val = 9, .flags = RATE_IN_4430 },
2829	{ .div = 11, .val = 10, .flags = RATE_IN_4430 },
2830	{ .div = 12, .val = 11, .flags = RATE_IN_4430 },
2831	{ .div = 13, .val = 12, .flags = RATE_IN_4430 },
2832	{ .div = 14, .val = 13, .flags = RATE_IN_4430 },
2833	{ .div = 15, .val = 14, .flags = RATE_IN_4430 },
2834	{ .div = 16, .val = 15, .flags = RATE_IN_4430 },
2835	{ .div = 0 },
2836};
2837
2838static struct clk auxclk0_src_ck = {
2839	.name		= "auxclk0_src_ck",
2840	.parent		= &sys_clkin_ck,
2841	.init		= &omap2_init_clksel_parent,
2842	.ops		= &clkops_omap2_dflt,
2843	.clksel		= auxclk_src_sel,
2844	.clksel_reg	= OMAP4_SCRM_AUXCLK0,
2845	.clksel_mask	= OMAP4_SRCSELECT_MASK,
2846	.recalc		= &omap2_clksel_recalc,
2847	.enable_reg	= OMAP4_SCRM_AUXCLK0,
2848	.enable_bit	= OMAP4_ENABLE_SHIFT,
2849};
2850
2851static const struct clksel auxclk0_sel[] = {
2852	{ .parent = &auxclk0_src_ck, .rates = div16_1to16_rates },
2853	{ .parent = NULL },
2854};
2855
2856static struct clk auxclk0_ck = {
2857	.name		= "auxclk0_ck",
2858	.parent		= &auxclk0_src_ck,
2859	.clksel		= auxclk0_sel,
2860	.clksel_reg	= OMAP4_SCRM_AUXCLK0,
2861	.clksel_mask	= OMAP4_CLKDIV_MASK,
2862	.ops		= &clkops_null,
2863	.recalc		= &omap2_clksel_recalc,
2864	.round_rate	= &omap2_clksel_round_rate,
2865	.set_rate	= &omap2_clksel_set_rate,
2866};
2867
2868static struct clk auxclk1_src_ck = {
2869	.name		= "auxclk1_src_ck",
2870	.parent		= &sys_clkin_ck,
2871	.init		= &omap2_init_clksel_parent,
2872	.ops		= &clkops_omap2_dflt,
2873	.clksel		= auxclk_src_sel,
2874	.clksel_reg	= OMAP4_SCRM_AUXCLK1,
2875	.clksel_mask	= OMAP4_SRCSELECT_MASK,
2876	.recalc		= &omap2_clksel_recalc,
2877	.enable_reg	= OMAP4_SCRM_AUXCLK1,
2878	.enable_bit	= OMAP4_ENABLE_SHIFT,
2879};
2880
2881static const struct clksel auxclk1_sel[] = {
2882	{ .parent = &auxclk1_src_ck, .rates = div16_1to16_rates },
2883	{ .parent = NULL },
2884};
2885
2886static struct clk auxclk1_ck = {
2887	.name		= "auxclk1_ck",
2888	.parent		= &auxclk1_src_ck,
2889	.clksel		= auxclk1_sel,
2890	.clksel_reg	= OMAP4_SCRM_AUXCLK1,
2891	.clksel_mask	= OMAP4_CLKDIV_MASK,
2892	.ops		= &clkops_null,
2893	.recalc		= &omap2_clksel_recalc,
2894	.round_rate	= &omap2_clksel_round_rate,
2895	.set_rate	= &omap2_clksel_set_rate,
2896};
2897
2898static struct clk auxclk2_src_ck = {
2899	.name		= "auxclk2_src_ck",
2900	.parent		= &sys_clkin_ck,
2901	.init		= &omap2_init_clksel_parent,
2902	.ops		= &clkops_omap2_dflt,
2903	.clksel		= auxclk_src_sel,
2904	.clksel_reg	= OMAP4_SCRM_AUXCLK2,
2905	.clksel_mask	= OMAP4_SRCSELECT_MASK,
2906	.recalc		= &omap2_clksel_recalc,
2907	.enable_reg	= OMAP4_SCRM_AUXCLK2,
2908	.enable_bit	= OMAP4_ENABLE_SHIFT,
2909};
2910
2911static const struct clksel auxclk2_sel[] = {
2912	{ .parent = &auxclk2_src_ck, .rates = div16_1to16_rates },
2913	{ .parent = NULL },
2914};
2915
2916static struct clk auxclk2_ck = {
2917	.name		= "auxclk2_ck",
2918	.parent		= &auxclk2_src_ck,
2919	.clksel		= auxclk2_sel,
2920	.clksel_reg	= OMAP4_SCRM_AUXCLK2,
2921	.clksel_mask	= OMAP4_CLKDIV_MASK,
2922	.ops		= &clkops_null,
2923	.recalc		= &omap2_clksel_recalc,
2924	.round_rate	= &omap2_clksel_round_rate,
2925	.set_rate	= &omap2_clksel_set_rate,
2926};
2927
2928static struct clk auxclk3_src_ck = {
2929	.name		= "auxclk3_src_ck",
2930	.parent		= &sys_clkin_ck,
2931	.init		= &omap2_init_clksel_parent,
2932	.ops		= &clkops_omap2_dflt,
2933	.clksel		= auxclk_src_sel,
2934	.clksel_reg	= OMAP4_SCRM_AUXCLK3,
2935	.clksel_mask	= OMAP4_SRCSELECT_MASK,
2936	.recalc		= &omap2_clksel_recalc,
2937	.enable_reg	= OMAP4_SCRM_AUXCLK3,
2938	.enable_bit	= OMAP4_ENABLE_SHIFT,
2939};
2940
2941static const struct clksel auxclk3_sel[] = {
2942	{ .parent = &auxclk3_src_ck, .rates = div16_1to16_rates },
2943	{ .parent = NULL },
2944};
2945
2946static struct clk auxclk3_ck = {
2947	.name		= "auxclk3_ck",
2948	.parent		= &auxclk3_src_ck,
2949	.clksel		= auxclk3_sel,
2950	.clksel_reg	= OMAP4_SCRM_AUXCLK3,
2951	.clksel_mask	= OMAP4_CLKDIV_MASK,
2952	.ops		= &clkops_null,
2953	.recalc		= &omap2_clksel_recalc,
2954	.round_rate	= &omap2_clksel_round_rate,
2955	.set_rate	= &omap2_clksel_set_rate,
2956};
2957
2958static struct clk auxclk4_src_ck = {
2959	.name		= "auxclk4_src_ck",
2960	.parent		= &sys_clkin_ck,
2961	.init		= &omap2_init_clksel_parent,
2962	.ops		= &clkops_omap2_dflt,
2963	.clksel		= auxclk_src_sel,
2964	.clksel_reg	= OMAP4_SCRM_AUXCLK4,
2965	.clksel_mask	= OMAP4_SRCSELECT_MASK,
2966	.recalc		= &omap2_clksel_recalc,
2967	.enable_reg	= OMAP4_SCRM_AUXCLK4,
2968	.enable_bit	= OMAP4_ENABLE_SHIFT,
2969};
2970
2971static const struct clksel auxclk4_sel[] = {
2972	{ .parent = &auxclk4_src_ck, .rates = div16_1to16_rates },
2973	{ .parent = NULL },
2974};
2975
2976static struct clk auxclk4_ck = {
2977	.name		= "auxclk4_ck",
2978	.parent		= &auxclk4_src_ck,
2979	.clksel		= auxclk4_sel,
2980	.clksel_reg	= OMAP4_SCRM_AUXCLK4,
2981	.clksel_mask	= OMAP4_CLKDIV_MASK,
2982	.ops		= &clkops_null,
2983	.recalc		= &omap2_clksel_recalc,
2984	.round_rate	= &omap2_clksel_round_rate,
2985	.set_rate	= &omap2_clksel_set_rate,
2986};
2987
2988static struct clk auxclk5_src_ck = {
2989	.name		= "auxclk5_src_ck",
2990	.parent		= &sys_clkin_ck,
2991	.init		= &omap2_init_clksel_parent,
2992	.ops		= &clkops_omap2_dflt,
2993	.clksel		= auxclk_src_sel,
2994	.clksel_reg	= OMAP4_SCRM_AUXCLK5,
2995	.clksel_mask	= OMAP4_SRCSELECT_MASK,
2996	.recalc		= &omap2_clksel_recalc,
2997	.enable_reg	= OMAP4_SCRM_AUXCLK5,
2998	.enable_bit	= OMAP4_ENABLE_SHIFT,
2999};
3000
3001static const struct clksel auxclk5_sel[] = {
3002	{ .parent = &auxclk5_src_ck, .rates = div16_1to16_rates },
3003	{ .parent = NULL },
3004};
3005
3006static struct clk auxclk5_ck = {
3007	.name		= "auxclk5_ck",
3008	.parent		= &auxclk5_src_ck,
3009	.clksel		= auxclk5_sel,
3010	.clksel_reg	= OMAP4_SCRM_AUXCLK5,
3011	.clksel_mask	= OMAP4_CLKDIV_MASK,
3012	.ops		= &clkops_null,
3013	.recalc		= &omap2_clksel_recalc,
3014	.round_rate	= &omap2_clksel_round_rate,
3015	.set_rate	= &omap2_clksel_set_rate,
3016};
3017
3018static const struct clksel auxclkreq_sel[] = {
3019	{ .parent = &auxclk0_ck, .rates = div_1_0_rates },
3020	{ .parent = &auxclk1_ck, .rates = div_1_1_rates },
3021	{ .parent = &auxclk2_ck, .rates = div_1_2_rates },
3022	{ .parent = &auxclk3_ck, .rates = div_1_3_rates },
3023	{ .parent = &auxclk4_ck, .rates = div_1_4_rates },
3024	{ .parent = &auxclk5_ck, .rates = div_1_5_rates },
3025	{ .parent = NULL },
3026};
3027
3028static struct clk auxclkreq0_ck = {
3029	.name		= "auxclkreq0_ck",
3030	.parent		= &auxclk0_ck,
3031	.init		= &omap2_init_clksel_parent,
3032	.ops		= &clkops_null,
3033	.clksel         = auxclkreq_sel,
3034	.clksel_reg	= OMAP4_SCRM_AUXCLKREQ0,
3035	.clksel_mask	= OMAP4_MAPPING_MASK,
3036	.recalc		= &omap2_clksel_recalc,
3037};
3038
3039static struct clk auxclkreq1_ck = {
3040	.name		= "auxclkreq1_ck",
3041	.parent		= &auxclk1_ck,
3042	.init		= &omap2_init_clksel_parent,
3043	.ops		= &clkops_null,
3044	.clksel         = auxclkreq_sel,
3045	.clksel_reg	= OMAP4_SCRM_AUXCLKREQ1,
3046	.clksel_mask	= OMAP4_MAPPING_MASK,
3047	.recalc		= &omap2_clksel_recalc,
3048};
3049
3050static struct clk auxclkreq2_ck = {
3051	.name		= "auxclkreq2_ck",
3052	.parent		= &auxclk2_ck,
3053	.init		= &omap2_init_clksel_parent,
3054	.ops		= &clkops_null,
3055	.clksel         = auxclkreq_sel,
3056	.clksel_reg	= OMAP4_SCRM_AUXCLKREQ2,
3057	.clksel_mask	= OMAP4_MAPPING_MASK,
3058	.recalc		= &omap2_clksel_recalc,
3059};
3060
3061static struct clk auxclkreq3_ck = {
3062	.name		= "auxclkreq3_ck",
3063	.parent		= &auxclk3_ck,
3064	.init		= &omap2_init_clksel_parent,
3065	.ops		= &clkops_null,
3066	.clksel         = auxclkreq_sel,
3067	.clksel_reg	= OMAP4_SCRM_AUXCLKREQ3,
3068	.clksel_mask	= OMAP4_MAPPING_MASK,
3069	.recalc		= &omap2_clksel_recalc,
3070};
3071
3072static struct clk auxclkreq4_ck = {
3073	.name		= "auxclkreq4_ck",
3074	.parent		= &auxclk4_ck,
3075	.init		= &omap2_init_clksel_parent,
3076	.ops		= &clkops_null,
3077	.clksel         = auxclkreq_sel,
3078	.clksel_reg	= OMAP4_SCRM_AUXCLKREQ4,
3079	.clksel_mask	= OMAP4_MAPPING_MASK,
3080	.recalc		= &omap2_clksel_recalc,
3081};
3082
3083static struct clk auxclkreq5_ck = {
3084	.name		= "auxclkreq5_ck",
3085	.parent		= &auxclk5_ck,
3086	.init		= &omap2_init_clksel_parent,
3087	.ops		= &clkops_null,
3088	.clksel         = auxclkreq_sel,
3089	.clksel_reg	= OMAP4_SCRM_AUXCLKREQ5,
3090	.clksel_mask	= OMAP4_MAPPING_MASK,
3091	.recalc		= &omap2_clksel_recalc,
3092};
3093
3094/*
3095 * clkdev
3096 */
3097
3098static struct omap_clk omap44xx_clks[] = {
3099	CLK(NULL,	"extalt_clkin_ck",		&extalt_clkin_ck,	CK_443X),
3100	CLK(NULL,	"pad_clks_ck",			&pad_clks_ck,	CK_443X),
3101	CLK(NULL,	"pad_slimbus_core_clks_ck",	&pad_slimbus_core_clks_ck,	CK_443X),
3102	CLK(NULL,	"secure_32k_clk_src_ck",	&secure_32k_clk_src_ck,	CK_443X),
3103	CLK(NULL,	"slimbus_clk",			&slimbus_clk,	CK_443X),
3104	CLK(NULL,	"sys_32k_ck",			&sys_32k_ck,	CK_443X),
3105	CLK(NULL,	"virt_12000000_ck",		&virt_12000000_ck,	CK_443X),
3106	CLK(NULL,	"virt_13000000_ck",		&virt_13000000_ck,	CK_443X),
3107	CLK(NULL,	"virt_16800000_ck",		&virt_16800000_ck,	CK_443X),
3108	CLK(NULL,	"virt_19200000_ck",		&virt_19200000_ck,	CK_443X),
3109	CLK(NULL,	"virt_26000000_ck",		&virt_26000000_ck,	CK_443X),
3110	CLK(NULL,	"virt_27000000_ck",		&virt_27000000_ck,	CK_443X),
3111	CLK(NULL,	"virt_38400000_ck",		&virt_38400000_ck,	CK_443X),
3112	CLK(NULL,	"sys_clkin_ck",			&sys_clkin_ck,	CK_443X),
3113	CLK(NULL,	"tie_low_clock_ck",		&tie_low_clock_ck,	CK_443X),
3114	CLK(NULL,	"utmi_phy_clkout_ck",		&utmi_phy_clkout_ck,	CK_443X),
3115	CLK(NULL,	"xclk60mhsp1_ck",		&xclk60mhsp1_ck,	CK_443X),
3116	CLK(NULL,	"xclk60mhsp2_ck",		&xclk60mhsp2_ck,	CK_443X),
3117	CLK(NULL,	"xclk60motg_ck",		&xclk60motg_ck,	CK_443X),
3118	CLK(NULL,	"abe_dpll_bypass_clk_mux_ck",	&abe_dpll_bypass_clk_mux_ck,	CK_443X),
3119	CLK(NULL,	"abe_dpll_refclk_mux_ck",	&abe_dpll_refclk_mux_ck,	CK_443X),
3120	CLK(NULL,	"dpll_abe_ck",			&dpll_abe_ck,	CK_443X),
3121	CLK(NULL,	"dpll_abe_x2_ck",		&dpll_abe_x2_ck,	CK_443X),
3122	CLK(NULL,	"dpll_abe_m2x2_ck",		&dpll_abe_m2x2_ck,	CK_443X),
3123	CLK(NULL,	"abe_24m_fclk",			&abe_24m_fclk,	CK_443X),
3124	CLK(NULL,	"abe_clk",			&abe_clk,	CK_443X),
3125	CLK(NULL,	"aess_fclk",			&aess_fclk,	CK_443X),
3126	CLK(NULL,	"dpll_abe_m3x2_ck",		&dpll_abe_m3x2_ck,	CK_443X),
3127	CLK(NULL,	"core_hsd_byp_clk_mux_ck",	&core_hsd_byp_clk_mux_ck,	CK_443X),
3128	CLK(NULL,	"dpll_core_ck",			&dpll_core_ck,	CK_443X),
3129	CLK(NULL,	"dpll_core_x2_ck",		&dpll_core_x2_ck,	CK_443X),
3130	CLK(NULL,	"dpll_core_m6x2_ck",		&dpll_core_m6x2_ck,	CK_443X),
3131	CLK(NULL,	"dbgclk_mux_ck",		&dbgclk_mux_ck,	CK_443X),
3132	CLK(NULL,	"dpll_core_m2_ck",		&dpll_core_m2_ck,	CK_443X),
3133	CLK(NULL,	"ddrphy_ck",			&ddrphy_ck,	CK_443X),
3134	CLK(NULL,	"dpll_core_m5x2_ck",		&dpll_core_m5x2_ck,	CK_443X),
3135	CLK(NULL,	"div_core_ck",			&div_core_ck,	CK_443X),
3136	CLK(NULL,	"div_iva_hs_clk",		&div_iva_hs_clk,	CK_443X),
3137	CLK(NULL,	"div_mpu_hs_clk",		&div_mpu_hs_clk,	CK_443X),
3138	CLK(NULL,	"dpll_core_m4x2_ck",		&dpll_core_m4x2_ck,	CK_443X),
3139	CLK(NULL,	"dll_clk_div_ck",		&dll_clk_div_ck,	CK_443X),
3140	CLK(NULL,	"dpll_abe_m2_ck",		&dpll_abe_m2_ck,	CK_443X),
3141	CLK(NULL,	"dpll_core_m3x2_ck",		&dpll_core_m3x2_ck,	CK_443X),
3142	CLK(NULL,	"dpll_core_m7x2_ck",		&dpll_core_m7x2_ck,	CK_443X),
3143	CLK(NULL,	"iva_hsd_byp_clk_mux_ck",	&iva_hsd_byp_clk_mux_ck,	CK_443X),
3144	CLK(NULL,	"dpll_iva_ck",			&dpll_iva_ck,	CK_443X),
3145	CLK(NULL,	"dpll_iva_x2_ck",		&dpll_iva_x2_ck,	CK_443X),
3146	CLK(NULL,	"dpll_iva_m4x2_ck",		&dpll_iva_m4x2_ck,	CK_443X),
3147	CLK(NULL,	"dpll_iva_m5x2_ck",		&dpll_iva_m5x2_ck,	CK_443X),
3148	CLK(NULL,	"dpll_mpu_ck",			&dpll_mpu_ck,	CK_443X),
3149	CLK(NULL,	"dpll_mpu_m2_ck",		&dpll_mpu_m2_ck,	CK_443X),
3150	CLK(NULL,	"per_hs_clk_div_ck",		&per_hs_clk_div_ck,	CK_443X),
3151	CLK(NULL,	"per_hsd_byp_clk_mux_ck",	&per_hsd_byp_clk_mux_ck,	CK_443X),
3152	CLK(NULL,	"dpll_per_ck",			&dpll_per_ck,	CK_443X),
3153	CLK(NULL,	"dpll_per_m2_ck",		&dpll_per_m2_ck,	CK_443X),
3154	CLK(NULL,	"dpll_per_x2_ck",		&dpll_per_x2_ck,	CK_443X),
3155	CLK(NULL,	"dpll_per_m2x2_ck",		&dpll_per_m2x2_ck,	CK_443X),
3156	CLK(NULL,	"dpll_per_m3x2_ck",		&dpll_per_m3x2_ck,	CK_443X),
3157	CLK(NULL,	"dpll_per_m4x2_ck",		&dpll_per_m4x2_ck,	CK_443X),
3158	CLK(NULL,	"dpll_per_m5x2_ck",		&dpll_per_m5x2_ck,	CK_443X),
3159	CLK(NULL,	"dpll_per_m6x2_ck",		&dpll_per_m6x2_ck,	CK_443X),
3160	CLK(NULL,	"dpll_per_m7x2_ck",		&dpll_per_m7x2_ck,	CK_443X),
3161	CLK(NULL,	"usb_hs_clk_div_ck",		&usb_hs_clk_div_ck,	CK_443X),
3162	CLK(NULL,	"dpll_usb_ck",			&dpll_usb_ck,	CK_443X),
3163	CLK(NULL,	"dpll_usb_clkdcoldo_ck",	&dpll_usb_clkdcoldo_ck,	CK_443X),
3164	CLK(NULL,	"dpll_usb_m2_ck",		&dpll_usb_m2_ck,	CK_443X),
3165	CLK(NULL,	"ducati_clk_mux_ck",		&ducati_clk_mux_ck,	CK_443X),
3166	CLK(NULL,	"func_12m_fclk",		&func_12m_fclk,	CK_443X),
3167	CLK(NULL,	"func_24m_clk",			&func_24m_clk,	CK_443X),
3168	CLK(NULL,	"func_24mc_fclk",		&func_24mc_fclk,	CK_443X),
3169	CLK(NULL,	"func_48m_fclk",		&func_48m_fclk,	CK_443X),
3170	CLK(NULL,	"func_48mc_fclk",		&func_48mc_fclk,	CK_443X),
3171	CLK(NULL,	"func_64m_fclk",		&func_64m_fclk,	CK_443X),
3172	CLK(NULL,	"func_96m_fclk",		&func_96m_fclk,	CK_443X),
3173	CLK(NULL,	"init_60m_fclk",		&init_60m_fclk,	CK_443X),
3174	CLK(NULL,	"l3_div_ck",			&l3_div_ck,	CK_443X),
3175	CLK(NULL,	"l4_div_ck",			&l4_div_ck,	CK_443X),
3176	CLK(NULL,	"lp_clk_div_ck",		&lp_clk_div_ck,	CK_443X),
3177	CLK(NULL,	"l4_wkup_clk_mux_ck",		&l4_wkup_clk_mux_ck,	CK_443X),
3178	CLK(NULL,	"ocp_abe_iclk",			&ocp_abe_iclk,	CK_443X),
3179	CLK(NULL,	"per_abe_24m_fclk",		&per_abe_24m_fclk,	CK_443X),
3180	CLK(NULL,	"per_abe_nc_fclk",		&per_abe_nc_fclk,	CK_443X),
3181	CLK(NULL,	"pmd_stm_clock_mux_ck",		&pmd_stm_clock_mux_ck,	CK_443X),
3182	CLK(NULL,	"pmd_trace_clk_mux_ck",		&pmd_trace_clk_mux_ck,	CK_443X),
3183	CLK(NULL,	"syc_clk_div_ck",		&syc_clk_div_ck,	CK_443X),
3184	CLK(NULL,	"aes1_fck",			&aes1_fck,	CK_443X),
3185	CLK(NULL,	"aes2_fck",			&aes2_fck,	CK_443X),
3186	CLK(NULL,	"aess_fck",			&aess_fck,	CK_443X),
3187	CLK(NULL,	"bandgap_fclk",			&bandgap_fclk,	CK_443X),
3188	CLK(NULL,	"bandgap_ts_fclk",		&bandgap_ts_fclk,	CK_446X),
3189	CLK(NULL,	"des3des_fck",			&des3des_fck,	CK_443X),
3190	CLK(NULL,	"div_ts_ck",			&div_ts_ck,	CK_446X),
3191	CLK(NULL,	"dmic_sync_mux_ck",		&dmic_sync_mux_ck,	CK_443X),
3192	CLK(NULL,	"dmic_fck",			&dmic_fck,	CK_443X),
3193	CLK(NULL,	"dsp_fck",			&dsp_fck,	CK_443X),
3194	CLK(NULL,	"dss_sys_clk",			&dss_sys_clk,	CK_443X),
3195	CLK(NULL,	"dss_tv_clk",			&dss_tv_clk,	CK_443X),
3196	CLK(NULL,	"dss_48mhz_clk",		&dss_48mhz_clk,	CK_443X),
3197	CLK(NULL,	"dss_dss_clk",			&dss_dss_clk,	CK_443X),
3198	CLK("omapdss_dss",	"ick",				&dss_fck,	CK_443X),
3199	CLK(NULL,	"efuse_ctrl_cust_fck",		&efuse_ctrl_cust_fck,	CK_443X),
3200	CLK(NULL,	"emif1_fck",			&emif1_fck,	CK_443X),
3201	CLK(NULL,	"emif2_fck",			&emif2_fck,	CK_443X),
3202	CLK(NULL,	"fdif_fck",			&fdif_fck,	CK_443X),
3203	CLK(NULL,	"fpka_fck",			&fpka_fck,	CK_443X),
3204	CLK(NULL,	"gpio1_dbclk",			&gpio1_dbclk,	CK_443X),
3205	CLK(NULL,	"gpio1_ick",			&gpio1_ick,	CK_443X),
3206	CLK(NULL,	"gpio2_dbclk",			&gpio2_dbclk,	CK_443X),
3207	CLK(NULL,	"gpio2_ick",			&gpio2_ick,	CK_443X),
3208	CLK(NULL,	"gpio3_dbclk",			&gpio3_dbclk,	CK_443X),
3209	CLK(NULL,	"gpio3_ick",			&gpio3_ick,	CK_443X),
3210	CLK(NULL,	"gpio4_dbclk",			&gpio4_dbclk,	CK_443X),
3211	CLK(NULL,	"gpio4_ick",			&gpio4_ick,	CK_443X),
3212	CLK(NULL,	"gpio5_dbclk",			&gpio5_dbclk,	CK_443X),
3213	CLK(NULL,	"gpio5_ick",			&gpio5_ick,	CK_443X),
3214	CLK(NULL,	"gpio6_dbclk",			&gpio6_dbclk,	CK_443X),
3215	CLK(NULL,	"gpio6_ick",			&gpio6_ick,	CK_443X),
3216	CLK(NULL,	"gpmc_ick",			&gpmc_ick,	CK_443X),
3217	CLK(NULL,	"gpu_fck",			&gpu_fck,	CK_443X),
3218	CLK(NULL,	"hdq1w_fck",			&hdq1w_fck,	CK_443X),
3219	CLK(NULL,	"hsi_fck",			&hsi_fck,	CK_443X),
3220	CLK(NULL,	"i2c1_fck",			&i2c1_fck,	CK_443X),
3221	CLK(NULL,	"i2c2_fck",			&i2c2_fck,	CK_443X),
3222	CLK(NULL,	"i2c3_fck",			&i2c3_fck,	CK_443X),
3223	CLK(NULL,	"i2c4_fck",			&i2c4_fck,	CK_443X),
3224	CLK(NULL,	"ipu_fck",			&ipu_fck,	CK_443X),
3225	CLK(NULL,	"iss_ctrlclk",			&iss_ctrlclk,	CK_443X),
3226	CLK(NULL,	"iss_fck",			&iss_fck,	CK_443X),
3227	CLK(NULL,	"iva_fck",			&iva_fck,	CK_443X),
3228	CLK(NULL,	"kbd_fck",			&kbd_fck,	CK_443X),
3229	CLK(NULL,	"l3_instr_ick",			&l3_instr_ick,	CK_443X),
3230	CLK(NULL,	"l3_main_3_ick",		&l3_main_3_ick,	CK_443X),
3231	CLK(NULL,	"mcasp_sync_mux_ck",		&mcasp_sync_mux_ck,	CK_443X),
3232	CLK(NULL,	"mcasp_fck",			&mcasp_fck,	CK_443X),
3233	CLK(NULL,	"mcbsp1_sync_mux_ck",		&mcbsp1_sync_mux_ck,	CK_443X),
3234	CLK(NULL,	"mcbsp1_fck",			&mcbsp1_fck,	CK_443X),
3235	CLK(NULL,	"mcbsp2_sync_mux_ck",		&mcbsp2_sync_mux_ck,	CK_443X),
3236	CLK(NULL,	"mcbsp2_fck",			&mcbsp2_fck,	CK_443X),
3237	CLK(NULL,	"mcbsp3_sync_mux_ck",		&mcbsp3_sync_mux_ck,	CK_443X),
3238	CLK(NULL,	"mcbsp3_fck",			&mcbsp3_fck,	CK_443X),
3239	CLK(NULL,	"mcbsp4_sync_mux_ck",		&mcbsp4_sync_mux_ck,	CK_443X),
3240	CLK(NULL,	"mcbsp4_fck",			&mcbsp4_fck,	CK_443X),
3241	CLK(NULL,	"mcpdm_fck",			&mcpdm_fck,	CK_443X),
3242	CLK(NULL,	"mcspi1_fck",			&mcspi1_fck,	CK_443X),
3243	CLK(NULL,	"mcspi2_fck",			&mcspi2_fck,	CK_443X),
3244	CLK(NULL,	"mcspi3_fck",			&mcspi3_fck,	CK_443X),
3245	CLK(NULL,	"mcspi4_fck",			&mcspi4_fck,	CK_443X),
3246	CLK(NULL,	"mmc1_fck",			&mmc1_fck,	CK_443X),
3247	CLK(NULL,	"mmc2_fck",			&mmc2_fck,	CK_443X),
3248	CLK(NULL,	"mmc3_fck",			&mmc3_fck,	CK_443X),
3249	CLK(NULL,	"mmc4_fck",			&mmc4_fck,	CK_443X),
3250	CLK(NULL,	"mmc5_fck",			&mmc5_fck,	CK_443X),
3251	CLK(NULL,	"ocp2scp_usb_phy_phy_48m",	&ocp2scp_usb_phy_phy_48m,	CK_443X),
3252	CLK(NULL,	"ocp2scp_usb_phy_ick",		&ocp2scp_usb_phy_ick,	CK_443X),
3253	CLK(NULL,	"ocp_wp_noc_ick",		&ocp_wp_noc_ick,	CK_443X),
3254	CLK("omap_rng",	"ick",				&rng_ick,	CK_443X),
3255	CLK(NULL,	"sha2md5_fck",			&sha2md5_fck,	CK_443X),
3256	CLK(NULL,	"sl2if_ick",			&sl2if_ick,	CK_443X),
3257	CLK(NULL,	"slimbus1_fclk_1",		&slimbus1_fclk_1,	CK_443X),
3258	CLK(NULL,	"slimbus1_fclk_0",		&slimbus1_fclk_0,	CK_443X),
3259	CLK(NULL,	"slimbus1_fclk_2",		&slimbus1_fclk_2,	CK_443X),
3260	CLK(NULL,	"slimbus1_slimbus_clk",		&slimbus1_slimbus_clk,	CK_443X),
3261	CLK(NULL,	"slimbus1_fck",			&slimbus1_fck,	CK_443X),
3262	CLK(NULL,	"slimbus2_fclk_1",		&slimbus2_fclk_1,	CK_443X),
3263	CLK(NULL,	"slimbus2_fclk_0",		&slimbus2_fclk_0,	CK_443X),
3264	CLK(NULL,	"slimbus2_slimbus_clk",		&slimbus2_slimbus_clk,	CK_443X),
3265	CLK(NULL,	"slimbus2_fck",			&slimbus2_fck,	CK_443X),
3266	CLK(NULL,	"smartreflex_core_fck",		&smartreflex_core_fck,	CK_443X),
3267	CLK(NULL,	"smartreflex_iva_fck",		&smartreflex_iva_fck,	CK_443X),
3268	CLK(NULL,	"smartreflex_mpu_fck",		&smartreflex_mpu_fck,	CK_443X),
3269	CLK(NULL,	"gpt1_fck",			&timer1_fck,	CK_443X),
3270	CLK(NULL,	"gpt10_fck",			&timer10_fck,	CK_443X),
3271	CLK(NULL,	"gpt11_fck",			&timer11_fck,	CK_443X),
3272	CLK(NULL,	"gpt2_fck",			&timer2_fck,	CK_443X),
3273	CLK(NULL,	"gpt3_fck",			&timer3_fck,	CK_443X),
3274	CLK(NULL,	"gpt4_fck",			&timer4_fck,	CK_443X),
3275	CLK(NULL,	"gpt5_fck",			&timer5_fck,	CK_443X),
3276	CLK(NULL,	"gpt6_fck",			&timer6_fck,	CK_443X),
3277	CLK(NULL,	"gpt7_fck",			&timer7_fck,	CK_443X),
3278	CLK(NULL,	"gpt8_fck",			&timer8_fck,	CK_443X),
3279	CLK(NULL,	"gpt9_fck",			&timer9_fck,	CK_443X),
3280	CLK(NULL,	"uart1_fck",			&uart1_fck,	CK_443X),
3281	CLK(NULL,	"uart2_fck",			&uart2_fck,	CK_443X),
3282	CLK(NULL,	"uart3_fck",			&uart3_fck,	CK_443X),
3283	CLK(NULL,	"uart4_fck",			&uart4_fck,	CK_443X),
3284	CLK("usbhs-omap.0",	"fs_fck",		&usb_host_fs_fck,	CK_443X),
3285	CLK(NULL,	"utmi_p1_gfclk",		&utmi_p1_gfclk,	CK_443X),
3286	CLK(NULL,	"usb_host_hs_utmi_p1_clk",	&usb_host_hs_utmi_p1_clk,	CK_443X),
3287	CLK(NULL,	"utmi_p2_gfclk",		&utmi_p2_gfclk,	CK_443X),
3288	CLK(NULL,	"usb_host_hs_utmi_p2_clk",	&usb_host_hs_utmi_p2_clk,	CK_443X),
3289	CLK(NULL,	"usb_host_hs_utmi_p3_clk",	&usb_host_hs_utmi_p3_clk,	CK_443X),
3290	CLK(NULL,	"usb_host_hs_hsic480m_p1_clk",	&usb_host_hs_hsic480m_p1_clk,	CK_443X),
3291	CLK(NULL,	"usb_host_hs_hsic60m_p1_clk",	&usb_host_hs_hsic60m_p1_clk,	CK_443X),
3292	CLK(NULL,	"usb_host_hs_hsic60m_p2_clk",	&usb_host_hs_hsic60m_p2_clk,	CK_443X),
3293	CLK(NULL,	"usb_host_hs_hsic480m_p2_clk",	&usb_host_hs_hsic480m_p2_clk,	CK_443X),
3294	CLK(NULL,	"usb_host_hs_func48mclk",	&usb_host_hs_func48mclk,	CK_443X),
3295	CLK("usbhs-omap.0",	"hs_fck",		&usb_host_hs_fck,	CK_443X),
3296	CLK(NULL,	"otg_60m_gfclk",		&otg_60m_gfclk,	CK_443X),
3297	CLK(NULL,	"usb_otg_hs_xclk",		&usb_otg_hs_xclk,	CK_443X),
3298	CLK("musb-omap2430",	"ick",				&usb_otg_hs_ick,	CK_443X),
3299	CLK(NULL,	"usb_phy_cm_clk32k",		&usb_phy_cm_clk32k,	CK_443X),
3300	CLK(NULL,	"usb_tll_hs_usb_ch2_clk",	&usb_tll_hs_usb_ch2_clk,	CK_443X),
3301	CLK(NULL,	"usb_tll_hs_usb_ch0_clk",	&usb_tll_hs_usb_ch0_clk,	CK_443X),
3302	CLK(NULL,	"usb_tll_hs_usb_ch1_clk",	&usb_tll_hs_usb_ch1_clk,	CK_443X),
3303	CLK("usbhs-omap.0",	"usbtll_ick",		&usb_tll_hs_ick,	CK_443X),
3304	CLK(NULL,	"usim_ck",			&usim_ck,	CK_443X),
3305	CLK(NULL,	"usim_fclk",			&usim_fclk,	CK_443X),
3306	CLK(NULL,	"usim_fck",			&usim_fck,	CK_443X),
3307	CLK(NULL,	"wd_timer2_fck",		&wd_timer2_fck,	CK_443X),
3308	CLK(NULL,	"wd_timer3_fck",		&wd_timer3_fck,	CK_443X),
3309	CLK(NULL,	"stm_clk_div_ck",		&stm_clk_div_ck,	CK_443X),
3310	CLK(NULL,	"trace_clk_div_ck",		&trace_clk_div_ck,	CK_443X),
3311	CLK(NULL,	"auxclk0_src_ck",		&auxclk0_src_ck,	CK_443X),
3312	CLK(NULL,	"auxclk0_ck",			&auxclk0_ck,	CK_443X),
3313	CLK(NULL,	"auxclkreq0_ck",		&auxclkreq0_ck,	CK_443X),
3314	CLK(NULL,	"auxclk1_src_ck",		&auxclk1_src_ck,	CK_443X),
3315	CLK(NULL,	"auxclk1_ck",			&auxclk1_ck,	CK_443X),
3316	CLK(NULL,	"auxclkreq1_ck",		&auxclkreq1_ck,	CK_443X),
3317	CLK(NULL,	"auxclk2_src_ck",		&auxclk2_src_ck,	CK_443X),
3318	CLK(NULL,	"auxclk2_ck",			&auxclk2_ck,	CK_443X),
3319	CLK(NULL,	"auxclkreq2_ck",		&auxclkreq2_ck,	CK_443X),
3320	CLK(NULL,	"auxclk3_src_ck",		&auxclk3_src_ck,	CK_443X),
3321	CLK(NULL,	"auxclk3_ck",			&auxclk3_ck,	CK_443X),
3322	CLK(NULL,	"auxclkreq3_ck",		&auxclkreq3_ck,	CK_443X),
3323	CLK(NULL,	"auxclk4_src_ck",		&auxclk4_src_ck,	CK_443X),
3324	CLK(NULL,	"auxclk4_ck",			&auxclk4_ck,	CK_443X),
3325	CLK(NULL,	"auxclkreq4_ck",		&auxclkreq4_ck,	CK_443X),
3326	CLK(NULL,	"auxclk5_src_ck",		&auxclk5_src_ck,	CK_443X),
3327	CLK(NULL,	"auxclk5_ck",			&auxclk5_ck,	CK_443X),
3328	CLK(NULL,	"auxclkreq5_ck",		&auxclkreq5_ck,	CK_443X),
3329	CLK(NULL,	"gpmc_ck",			&dummy_ck,	CK_443X),
3330	CLK(NULL,	"gpt1_ick",			&dummy_ck,	CK_443X),
3331	CLK(NULL,	"gpt2_ick",			&dummy_ck,	CK_443X),
3332	CLK(NULL,	"gpt3_ick",			&dummy_ck,	CK_443X),
3333	CLK(NULL,	"gpt4_ick",			&dummy_ck,	CK_443X),
3334	CLK(NULL,	"gpt5_ick",			&dummy_ck,	CK_443X),
3335	CLK(NULL,	"gpt6_ick",			&dummy_ck,	CK_443X),
3336	CLK(NULL,	"gpt7_ick",			&dummy_ck,	CK_443X),
3337	CLK(NULL,	"gpt8_ick",			&dummy_ck,	CK_443X),
3338	CLK(NULL,	"gpt9_ick",			&dummy_ck,	CK_443X),
3339	CLK(NULL,	"gpt10_ick",			&dummy_ck,	CK_443X),
3340	CLK(NULL,	"gpt11_ick",			&dummy_ck,	CK_443X),
3341	CLK("omap_i2c.1",	"ick",				&dummy_ck,	CK_443X),
3342	CLK("omap_i2c.2",	"ick",				&dummy_ck,	CK_443X),
3343	CLK("omap_i2c.3",	"ick",				&dummy_ck,	CK_443X),
3344	CLK("omap_i2c.4",	"ick",				&dummy_ck,	CK_443X),
3345	CLK(NULL,	"mailboxes_ick",		&dummy_ck,	CK_443X),
3346	CLK("omap_hsmmc.0",	"ick",				&dummy_ck,	CK_443X),
3347	CLK("omap_hsmmc.1",	"ick",				&dummy_ck,	CK_443X),
3348	CLK("omap_hsmmc.2",	"ick",				&dummy_ck,	CK_443X),
3349	CLK("omap_hsmmc.3",	"ick",				&dummy_ck,	CK_443X),
3350	CLK("omap_hsmmc.4",	"ick",				&dummy_ck,	CK_443X),
3351	CLK("omap-mcbsp.1",	"ick",				&dummy_ck,	CK_443X),
3352	CLK("omap-mcbsp.2",	"ick",				&dummy_ck,	CK_443X),
3353	CLK("omap-mcbsp.3",	"ick",				&dummy_ck,	CK_443X),
3354	CLK("omap-mcbsp.4",	"ick",				&dummy_ck,	CK_443X),
3355	CLK("omap2_mcspi.1",	"ick",				&dummy_ck,	CK_443X),
3356	CLK("omap2_mcspi.2",	"ick",				&dummy_ck,	CK_443X),
3357	CLK("omap2_mcspi.3",	"ick",				&dummy_ck,	CK_443X),
3358	CLK("omap2_mcspi.4",	"ick",				&dummy_ck,	CK_443X),
3359	CLK(NULL,	"uart1_ick",			&dummy_ck,	CK_443X),
3360	CLK(NULL,	"uart2_ick",			&dummy_ck,	CK_443X),
3361	CLK(NULL,	"uart3_ick",			&dummy_ck,	CK_443X),
3362	CLK(NULL,	"uart4_ick",			&dummy_ck,	CK_443X),
3363	CLK("usbhs-omap.0",	"usbhost_ick",		&dummy_ck,		CK_443X),
3364	CLK("usbhs-omap.0",	"usbtll_fck",		&dummy_ck,	CK_443X),
3365	CLK("omap_wdt",	"ick",				&dummy_ck,	CK_443X),
3366};
3367
3368int __init omap4xxx_clk_init(void)
3369{
3370	struct omap_clk *c;
3371	u32 cpu_clkflg;
3372
3373	if (cpu_is_omap44xx()) {
3374		cpu_mask = RATE_IN_4430;
3375		cpu_clkflg = CK_443X;
3376	} else if (cpu_is_omap446x()) {
3377		cpu_mask = RATE_IN_4460;
3378		cpu_clkflg = CK_446X;
3379	} else {
3380		return 0;
3381	}
3382
3383	clk_init(&omap2_clk_functions);
3384
3385	/*
3386	 * Must stay commented until all OMAP SoC drivers are
3387	 * converted to runtime PM, or drivers may start crashing
3388	 *
3389	 * omap2_clk_disable_clkdm_control();
3390	 */
3391
3392	for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
3393									  c++)
3394		clk_preinit(c->lk.clk);
3395
3396	for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
3397									  c++)
3398		if (c->cpu & cpu_clkflg) {
3399			clkdev_add(&c->lk);
3400			clk_register(c->lk.clk);
3401			omap2_init_clk_clkdm(c->lk.clk);
3402		}
3403
3404	/* Disable autoidle on all clocks; let the PM code enable it later */
3405	omap_clk_disable_autoidle_all();
3406
3407	recalculate_root_clocks();
3408
3409	/*
3410	 * Only enable those clocks we will need, let the drivers
3411	 * enable other clocks as necessary
3412	 */
3413	clk_enable_init_clocks();
3414
3415	return 0;
3416}