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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * linux/arch/arm/mach-omap2/clock.h
4 *
5 * Copyright (C) 2005-2009 Texas Instruments, Inc.
6 * Copyright (C) 2004-2011 Nokia Corporation
7 *
8 * Contacts:
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Paul Walmsley
11 */
12
13#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
14#define __ARCH_ARM_MACH_OMAP2_CLOCK_H
15
16#include <linux/kernel.h>
17#include <linux/list.h>
18
19#include <linux/clkdev.h>
20#include <linux/clk-provider.h>
21#include <linux/clk/ti.h>
22
23/* struct clksel_rate.flags possibilities */
24#define RATE_IN_242X (1 << 0)
25#define RATE_IN_243X (1 << 1)
26#define RATE_IN_3430ES1 (1 << 2) /* 3430ES1 rates only */
27#define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */
28#define RATE_IN_36XX (1 << 4)
29#define RATE_IN_4430 (1 << 5)
30#define RATE_IN_TI816X (1 << 6)
31#define RATE_IN_4460 (1 << 7)
32#define RATE_IN_AM33XX (1 << 8)
33#define RATE_IN_TI814X (1 << 9)
34
35#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
36#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
37#define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX)
38#define RATE_IN_44XX (RATE_IN_4430 | RATE_IN_4460)
39
40/* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
41#define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX)
42
43/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
44#define CORE_CLK_SRC_32K 0x0
45#define CORE_CLK_SRC_DPLL 0x1
46#define CORE_CLK_SRC_DPLL_X2 0x2
47
48/* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */
49#define OMAP2XXX_EN_DPLL_LPBYPASS 0x1
50#define OMAP2XXX_EN_DPLL_FRBYPASS 0x2
51#define OMAP2XXX_EN_DPLL_LOCKED 0x3
52
53/* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
54#define OMAP3XXX_EN_DPLL_LPBYPASS 0x5
55#define OMAP3XXX_EN_DPLL_FRBYPASS 0x6
56#define OMAP3XXX_EN_DPLL_LOCKED 0x7
57
58/* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
59#define OMAP4XXX_EN_DPLL_MNBYPASS 0x4
60#define OMAP4XXX_EN_DPLL_LPBYPASS 0x5
61#define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
62#define OMAP4XXX_EN_DPLL_LOCKED 0x7
63
64extern struct ti_clk_ll_ops omap_clk_ll_ops;
65
66int __init omap2_clk_setup_ll_ops(void);
67
68void __init ti_clk_init_features(void);
69#endif
1/*
2 * linux/arch/arm/mach-omap2/clock.h
3 *
4 * Copyright (C) 2005-2009 Texas Instruments, Inc.
5 * Copyright (C) 2004-2011 Nokia Corporation
6 *
7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
17#define __ARCH_ARM_MACH_OMAP2_CLOCK_H
18
19#include <linux/kernel.h>
20
21#include <plat/clock.h>
22
23/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
24#define CORE_CLK_SRC_32K 0x0
25#define CORE_CLK_SRC_DPLL 0x1
26#define CORE_CLK_SRC_DPLL_X2 0x2
27
28/* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */
29#define OMAP2XXX_EN_DPLL_LPBYPASS 0x1
30#define OMAP2XXX_EN_DPLL_FRBYPASS 0x2
31#define OMAP2XXX_EN_DPLL_LOCKED 0x3
32
33/* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
34#define OMAP3XXX_EN_DPLL_LPBYPASS 0x5
35#define OMAP3XXX_EN_DPLL_FRBYPASS 0x6
36#define OMAP3XXX_EN_DPLL_LOCKED 0x7
37
38/* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
39#define OMAP4XXX_EN_DPLL_MNBYPASS 0x4
40#define OMAP4XXX_EN_DPLL_LPBYPASS 0x5
41#define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
42#define OMAP4XXX_EN_DPLL_LOCKED 0x7
43
44/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
45#define DPLL_LOW_POWER_STOP 0x1
46#define DPLL_LOW_POWER_BYPASS 0x5
47#define DPLL_LOCKED 0x7
48
49/* DPLL Type and DCO Selection Flags */
50#define DPLL_J_TYPE 0x1
51
52int omap2_clk_enable(struct clk *clk);
53void omap2_clk_disable(struct clk *clk);
54long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
55int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
56int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
57long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
58unsigned long omap3_dpll_recalc(struct clk *clk);
59unsigned long omap3_clkoutx2_recalc(struct clk *clk);
60void omap3_dpll_allow_idle(struct clk *clk);
61void omap3_dpll_deny_idle(struct clk *clk);
62u32 omap3_dpll_autoidle_read(struct clk *clk);
63int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
64int omap3_noncore_dpll_enable(struct clk *clk);
65void omap3_noncore_dpll_disable(struct clk *clk);
66int omap4_dpllmx_gatectrl_read(struct clk *clk);
67void omap4_dpllmx_allow_gatectrl(struct clk *clk);
68void omap4_dpllmx_deny_gatectrl(struct clk *clk);
69
70#ifdef CONFIG_OMAP_RESET_CLOCKS
71void omap2_clk_disable_unused(struct clk *clk);
72#else
73#define omap2_clk_disable_unused NULL
74#endif
75
76void omap2_init_clk_clkdm(struct clk *clk);
77void __init omap2_clk_disable_clkdm_control(void);
78
79/* clkt_clksel.c public functions */
80u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
81 u32 *new_div);
82void omap2_init_clksel_parent(struct clk *clk);
83unsigned long omap2_clksel_recalc(struct clk *clk);
84long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
85int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
86int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent);
87
88/* clkt_iclk.c public functions */
89extern void omap2_clkt_iclk_allow_idle(struct clk *clk);
90extern void omap2_clkt_iclk_deny_idle(struct clk *clk);
91
92u32 omap2_get_dpll_rate(struct clk *clk);
93void omap2_init_dpll_parent(struct clk *clk);
94
95int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
96
97
98#ifdef CONFIG_ARCH_OMAP2
99void omap2xxx_clk_prepare_for_reboot(void);
100#else
101static inline void omap2xxx_clk_prepare_for_reboot(void)
102{
103}
104#endif
105
106#ifdef CONFIG_ARCH_OMAP3
107void omap3_clk_prepare_for_reboot(void);
108#else
109static inline void omap3_clk_prepare_for_reboot(void)
110{
111}
112#endif
113
114#ifdef CONFIG_ARCH_OMAP4
115void omap4_clk_prepare_for_reboot(void);
116#else
117static inline void omap4_clk_prepare_for_reboot(void)
118{
119}
120#endif
121
122int omap2_dflt_clk_enable(struct clk *clk);
123void omap2_dflt_clk_disable(struct clk *clk);
124void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
125 u8 *other_bit);
126void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
127 u8 *idlest_bit, u8 *idlest_val);
128int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
129void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
130 const char *core_ck_name,
131 const char *mpu_ck_name);
132
133extern u8 cpu_mask;
134
135extern const struct clkops clkops_omap2_dflt_wait;
136extern const struct clkops clkops_dummy;
137extern const struct clkops clkops_omap2_dflt;
138
139extern struct clk_functions omap2_clk_functions;
140extern struct clk *vclk, *sclk;
141
142extern const struct clksel_rate gpt_32k_rates[];
143extern const struct clksel_rate gpt_sys_rates[];
144extern const struct clksel_rate gfx_l3_rates[];
145extern const struct clksel_rate dsp_ick_rates[];
146
147#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_CPU_FREQ)
148extern void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
149extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
150#else
151#define omap2_clk_init_cpufreq_table 0
152#define omap2_clk_exit_cpufreq_table 0
153#endif
154
155extern const struct clkops clkops_omap2_iclk_dflt_wait;
156extern const struct clkops clkops_omap2_iclk_dflt;
157extern const struct clkops clkops_omap2_iclk_idle_only;
158extern const struct clkops clkops_omap2_mdmclk_dflt_wait;
159extern const struct clkops clkops_omap2xxx_dpll_ops;
160extern const struct clkops clkops_omap3_noncore_dpll_ops;
161extern const struct clkops clkops_omap3_core_dpll_ops;
162extern const struct clkops clkops_omap4_dpllmx_ops;
163
164#endif