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1/*
2 * linux/arch/arm/mach-omap1/board-fsample.c
3 *
4 * Modified from board-perseus2.c
5 *
6 * Original OMAP730 support by Jean Pihet <j-pihet@ti.com>
7 * Updated for 2.6 by Kevin Hilman <kjh@hilman.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/platform_device.h>
17#include <linux/delay.h>
18#include <linux/mtd/mtd.h>
19#include <linux/mtd/nand.h>
20#include <linux/mtd/partitions.h>
21#include <linux/mtd/physmap.h>
22#include <linux/input.h>
23#include <linux/smc91x.h>
24
25#include <mach/hardware.h>
26#include <asm/mach-types.h>
27#include <asm/mach/arch.h>
28#include <asm/mach/map.h>
29
30#include <plat/tc.h>
31#include <mach/gpio.h>
32#include <plat/mux.h>
33#include <plat/flash.h>
34#include <plat/fpga.h>
35#include <plat/keypad.h>
36#include <plat/common.h>
37#include <plat/board.h>
38
39/* fsample is pretty close to p2-sample */
40
41#define fsample_cpld_read(reg) __raw_readb(reg)
42#define fsample_cpld_write(val, reg) __raw_writeb(val, reg)
43
44#define FSAMPLE_CPLD_BASE 0xE8100000
45#define FSAMPLE_CPLD_SIZE SZ_4K
46#define FSAMPLE_CPLD_START 0x05080000
47
48#define FSAMPLE_CPLD_REG_A (FSAMPLE_CPLD_BASE + 0x00)
49#define FSAMPLE_CPLD_SWITCH (FSAMPLE_CPLD_BASE + 0x02)
50#define FSAMPLE_CPLD_UART (FSAMPLE_CPLD_BASE + 0x02)
51#define FSAMPLE_CPLD_REG_B (FSAMPLE_CPLD_BASE + 0x04)
52#define FSAMPLE_CPLD_VERSION (FSAMPLE_CPLD_BASE + 0x06)
53#define FSAMPLE_CPLD_SET_CLR (FSAMPLE_CPLD_BASE + 0x06)
54
55#define FSAMPLE_CPLD_BIT_BT_RESET 0
56#define FSAMPLE_CPLD_BIT_LCD_RESET 1
57#define FSAMPLE_CPLD_BIT_CAM_PWDN 2
58#define FSAMPLE_CPLD_BIT_CHARGER_ENABLE 3
59#define FSAMPLE_CPLD_BIT_SD_MMC_EN 4
60#define FSAMPLE_CPLD_BIT_aGPS_PWREN 5
61#define FSAMPLE_CPLD_BIT_BACKLIGHT 6
62#define FSAMPLE_CPLD_BIT_aGPS_EN_RESET 7
63#define FSAMPLE_CPLD_BIT_aGPS_SLEEPx_N 8
64#define FSAMPLE_CPLD_BIT_OTG_RESET 9
65
66#define fsample_cpld_set(bit) \
67 fsample_cpld_write((((bit) & 15) << 4) | 0x0f, FSAMPLE_CPLD_SET_CLR)
68
69#define fsample_cpld_clear(bit) \
70 fsample_cpld_write(0xf0 | ((bit) & 15), FSAMPLE_CPLD_SET_CLR)
71
72static const unsigned int fsample_keymap[] = {
73 KEY(0, 0, KEY_UP),
74 KEY(1, 0, KEY_RIGHT),
75 KEY(2, 0, KEY_LEFT),
76 KEY(3, 0, KEY_DOWN),
77 KEY(4, 0, KEY_ENTER),
78 KEY(0, 1, KEY_F10),
79 KEY(1, 1, KEY_SEND),
80 KEY(2, 1, KEY_END),
81 KEY(3, 1, KEY_VOLUMEDOWN),
82 KEY(4, 1, KEY_VOLUMEUP),
83 KEY(5, 1, KEY_RECORD),
84 KEY(0, 2, KEY_F9),
85 KEY(1, 2, KEY_3),
86 KEY(2, 2, KEY_6),
87 KEY(3, 2, KEY_9),
88 KEY(4, 2, KEY_KPDOT),
89 KEY(0, 3, KEY_BACK),
90 KEY(1, 3, KEY_2),
91 KEY(2, 3, KEY_5),
92 KEY(3, 3, KEY_8),
93 KEY(4, 3, KEY_0),
94 KEY(5, 3, KEY_KPSLASH),
95 KEY(0, 4, KEY_HOME),
96 KEY(1, 4, KEY_1),
97 KEY(2, 4, KEY_4),
98 KEY(3, 4, KEY_7),
99 KEY(4, 4, KEY_KPASTERISK),
100 KEY(5, 4, KEY_POWER),
101};
102
103static struct smc91x_platdata smc91x_info = {
104 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
105 .leda = RPC_LED_100_10,
106 .ledb = RPC_LED_TX_RX,
107};
108
109static struct resource smc91x_resources[] = {
110 [0] = {
111 .start = H2P2_DBG_FPGA_ETHR_START, /* Physical */
112 .end = H2P2_DBG_FPGA_ETHR_START + 0xf,
113 .flags = IORESOURCE_MEM,
114 },
115 [1] = {
116 .start = INT_7XX_MPU_EXT_NIRQ,
117 .end = 0,
118 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
119 },
120};
121
122static void __init fsample_init_smc91x(void)
123{
124 fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
125 mdelay(50);
126 fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1,
127 H2P2_DBG_FPGA_LAN_RESET);
128 mdelay(50);
129}
130
131static struct mtd_partition nor_partitions[] = {
132 /* bootloader (U-Boot, etc) in first sector */
133 {
134 .name = "bootloader",
135 .offset = 0,
136 .size = SZ_128K,
137 .mask_flags = MTD_WRITEABLE, /* force read-only */
138 },
139 /* bootloader params in the next sector */
140 {
141 .name = "params",
142 .offset = MTDPART_OFS_APPEND,
143 .size = SZ_128K,
144 .mask_flags = 0,
145 },
146 /* kernel */
147 {
148 .name = "kernel",
149 .offset = MTDPART_OFS_APPEND,
150 .size = SZ_2M,
151 .mask_flags = 0
152 },
153 /* rest of flash is a file system */
154 {
155 .name = "rootfs",
156 .offset = MTDPART_OFS_APPEND,
157 .size = MTDPART_SIZ_FULL,
158 .mask_flags = 0
159 },
160};
161
162static struct physmap_flash_data nor_data = {
163 .width = 2,
164 .set_vpp = omap1_set_vpp,
165 .parts = nor_partitions,
166 .nr_parts = ARRAY_SIZE(nor_partitions),
167};
168
169static struct resource nor_resource = {
170 .start = OMAP_CS0_PHYS,
171 .end = OMAP_CS0_PHYS + SZ_32M - 1,
172 .flags = IORESOURCE_MEM,
173};
174
175static struct platform_device nor_device = {
176 .name = "physmap-flash",
177 .id = 0,
178 .dev = {
179 .platform_data = &nor_data,
180 },
181 .num_resources = 1,
182 .resource = &nor_resource,
183};
184
185static void nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
186{
187 struct nand_chip *this = mtd->priv;
188 unsigned long mask;
189
190 if (cmd == NAND_CMD_NONE)
191 return;
192
193 mask = (ctrl & NAND_CLE) ? 0x02 : 0;
194 if (ctrl & NAND_ALE)
195 mask |= 0x04;
196 writeb(cmd, (unsigned long)this->IO_ADDR_W | mask);
197}
198
199#define FSAMPLE_NAND_RB_GPIO_PIN 62
200
201static int nand_dev_ready(struct mtd_info *mtd)
202{
203 return gpio_get_value(FSAMPLE_NAND_RB_GPIO_PIN);
204}
205
206static const char *part_probes[] = { "cmdlinepart", NULL };
207
208static struct platform_nand_data nand_data = {
209 .chip = {
210 .nr_chips = 1,
211 .chip_offset = 0,
212 .options = NAND_SAMSUNG_LP_OPTIONS,
213 .part_probe_types = part_probes,
214 },
215 .ctrl = {
216 .cmd_ctrl = nand_cmd_ctl,
217 .dev_ready = nand_dev_ready,
218 },
219};
220
221static struct resource nand_resource = {
222 .start = OMAP_CS3_PHYS,
223 .end = OMAP_CS3_PHYS + SZ_4K - 1,
224 .flags = IORESOURCE_MEM,
225};
226
227static struct platform_device nand_device = {
228 .name = "gen_nand",
229 .id = 0,
230 .dev = {
231 .platform_data = &nand_data,
232 },
233 .num_resources = 1,
234 .resource = &nand_resource,
235};
236
237static struct platform_device smc91x_device = {
238 .name = "smc91x",
239 .id = 0,
240 .dev = {
241 .platform_data = &smc91x_info,
242 },
243 .num_resources = ARRAY_SIZE(smc91x_resources),
244 .resource = smc91x_resources,
245};
246
247static struct resource kp_resources[] = {
248 [0] = {
249 .start = INT_7XX_MPUIO_KEYPAD,
250 .end = INT_7XX_MPUIO_KEYPAD,
251 .flags = IORESOURCE_IRQ,
252 },
253};
254
255static const struct matrix_keymap_data fsample_keymap_data = {
256 .keymap = fsample_keymap,
257 .keymap_size = ARRAY_SIZE(fsample_keymap),
258};
259
260static struct omap_kp_platform_data kp_data = {
261 .rows = 8,
262 .cols = 8,
263 .keymap_data = &fsample_keymap_data,
264 .delay = 4,
265};
266
267static struct platform_device kp_device = {
268 .name = "omap-keypad",
269 .id = -1,
270 .dev = {
271 .platform_data = &kp_data,
272 },
273 .num_resources = ARRAY_SIZE(kp_resources),
274 .resource = kp_resources,
275};
276
277static struct platform_device lcd_device = {
278 .name = "lcd_p2",
279 .id = -1,
280};
281
282static struct platform_device *devices[] __initdata = {
283 &nor_device,
284 &nand_device,
285 &smc91x_device,
286 &kp_device,
287 &lcd_device,
288};
289
290static struct omap_lcd_config fsample_lcd_config = {
291 .ctrl_name = "internal",
292};
293
294static struct omap_board_config_kernel fsample_config[] __initdata = {
295 { OMAP_TAG_LCD, &fsample_lcd_config },
296};
297
298static void __init omap_fsample_init(void)
299{
300 fsample_init_smc91x();
301
302 if (gpio_request(FSAMPLE_NAND_RB_GPIO_PIN, "NAND ready") < 0)
303 BUG();
304 gpio_direction_input(FSAMPLE_NAND_RB_GPIO_PIN);
305
306 omap_cfg_reg(L3_1610_FLASH_CS2B_OE);
307 omap_cfg_reg(M8_1610_FLASH_CS2B_WE);
308
309 /* Mux pins for keypad */
310 omap_cfg_reg(E2_7XX_KBR0);
311 omap_cfg_reg(J7_7XX_KBR1);
312 omap_cfg_reg(E1_7XX_KBR2);
313 omap_cfg_reg(F3_7XX_KBR3);
314 omap_cfg_reg(D2_7XX_KBR4);
315 omap_cfg_reg(C2_7XX_KBC0);
316 omap_cfg_reg(D3_7XX_KBC1);
317 omap_cfg_reg(E4_7XX_KBC2);
318 omap_cfg_reg(F4_7XX_KBC3);
319 omap_cfg_reg(E3_7XX_KBC4);
320
321 platform_add_devices(devices, ARRAY_SIZE(devices));
322
323 omap_board_config = fsample_config;
324 omap_board_config_size = ARRAY_SIZE(fsample_config);
325 omap_serial_init();
326 omap_register_i2c_bus(1, 100, NULL, 0);
327}
328
329static void __init omap_fsample_init_irq(void)
330{
331 omap1_init_common_hw();
332 omap1_init_irq();
333}
334
335/* Only FPGA needs to be mapped here. All others are done with ioremap */
336static struct map_desc omap_fsample_io_desc[] __initdata = {
337 {
338 .virtual = H2P2_DBG_FPGA_BASE,
339 .pfn = __phys_to_pfn(H2P2_DBG_FPGA_START),
340 .length = H2P2_DBG_FPGA_SIZE,
341 .type = MT_DEVICE
342 },
343 {
344 .virtual = FSAMPLE_CPLD_BASE,
345 .pfn = __phys_to_pfn(FSAMPLE_CPLD_START),
346 .length = FSAMPLE_CPLD_SIZE,
347 .type = MT_DEVICE
348 }
349};
350
351static void __init omap_fsample_map_io(void)
352{
353 omap1_map_common_io();
354 iotable_init(omap_fsample_io_desc,
355 ARRAY_SIZE(omap_fsample_io_desc));
356
357 /* Early, board-dependent init */
358
359 /*
360 * Hold GSM Reset until needed
361 */
362 omap_writew(omap_readw(OMAP7XX_DSP_M_CTL) & ~1, OMAP7XX_DSP_M_CTL);
363
364 /*
365 * UARTs -> done automagically by 8250 driver
366 */
367
368 /*
369 * CSx timings, GPIO Mux ... setup
370 */
371
372 /* Flash: CS0 timings setup */
373 omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_0);
374 omap_writel(0x00000088, OMAP7XX_FLASH_ACFG_0);
375
376 /*
377 * Ethernet support through the debug board
378 * CS1 timings setup
379 */
380 omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_1);
381 omap_writel(0x00000000, OMAP7XX_FLASH_ACFG_1);
382
383 /*
384 * Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
385 * It is used as the Ethernet controller interrupt
386 */
387 omap_writel(omap_readl(OMAP7XX_IO_CONF_9) & 0x1FFFFFFF, OMAP7XX_IO_CONF_9);
388}
389
390MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample")
391/* Maintainer: Brian Swetland <swetland@google.com> */
392 .boot_params = 0x10000100,
393 .map_io = omap_fsample_map_io,
394 .reserve = omap_reserve,
395 .init_irq = omap_fsample_init_irq,
396 .init_machine = omap_fsample_init,
397 .timer = &omap1_timer,
398MACHINE_END