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1/*
2 * linux/arch/arm/mach-mmp/mmp2.c
3 *
4 * code name MMP2
5 *
6 * Copyright (C) 2009 Marvell International Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/io.h>
17
18#include <asm/hardware/cache-tauros2.h>
19
20#include <asm/mach/time.h>
21#include <mach/addr-map.h>
22#include <mach/regs-apbc.h>
23#include <mach/regs-apmu.h>
24#include <mach/cputype.h>
25#include <mach/irqs.h>
26#include <mach/dma.h>
27#include <mach/mfp.h>
28#include <mach/gpio.h>
29#include <mach/devices.h>
30#include <mach/mmp2.h>
31
32#include "common.h"
33#include "clock.h"
34
35#define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000)
36
37#define APMASK(i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x9c)
38
39static struct mfp_addr_map mmp2_addr_map[] __initdata = {
40
41 MFP_ADDR_X(GPIO0, GPIO58, 0x54),
42 MFP_ADDR_X(GPIO59, GPIO73, 0x280),
43 MFP_ADDR_X(GPIO74, GPIO101, 0x170),
44
45 MFP_ADDR(GPIO102, 0x0),
46 MFP_ADDR(GPIO103, 0x4),
47 MFP_ADDR(GPIO104, 0x1fc),
48 MFP_ADDR(GPIO105, 0x1f8),
49 MFP_ADDR(GPIO106, 0x1f4),
50 MFP_ADDR(GPIO107, 0x1f0),
51 MFP_ADDR(GPIO108, 0x21c),
52 MFP_ADDR(GPIO109, 0x218),
53 MFP_ADDR(GPIO110, 0x214),
54 MFP_ADDR(GPIO111, 0x200),
55 MFP_ADDR(GPIO112, 0x244),
56 MFP_ADDR(GPIO113, 0x25c),
57 MFP_ADDR(GPIO114, 0x164),
58 MFP_ADDR_X(GPIO115, GPIO122, 0x260),
59
60 MFP_ADDR(GPIO123, 0x148),
61 MFP_ADDR_X(GPIO124, GPIO141, 0xc),
62
63 MFP_ADDR(GPIO142, 0x8),
64 MFP_ADDR_X(GPIO143, GPIO151, 0x220),
65 MFP_ADDR_X(GPIO152, GPIO153, 0x248),
66 MFP_ADDR_X(GPIO154, GPIO155, 0x254),
67 MFP_ADDR_X(GPIO156, GPIO159, 0x14c),
68
69 MFP_ADDR(GPIO160, 0x250),
70 MFP_ADDR(GPIO161, 0x210),
71 MFP_ADDR(GPIO162, 0x20c),
72 MFP_ADDR(GPIO163, 0x208),
73 MFP_ADDR(GPIO164, 0x204),
74 MFP_ADDR(GPIO165, 0x1ec),
75 MFP_ADDR(GPIO166, 0x1e8),
76 MFP_ADDR(GPIO167, 0x1e4),
77 MFP_ADDR(GPIO168, 0x1e0),
78
79 MFP_ADDR_X(TWSI1_SCL, TWSI1_SDA, 0x140),
80 MFP_ADDR_X(TWSI4_SCL, TWSI4_SDA, 0x2bc),
81
82 MFP_ADDR(PMIC_INT, 0x2c4),
83 MFP_ADDR(CLK_REQ, 0x160),
84
85 MFP_ADDR_END,
86};
87
88void mmp2_clear_pmic_int(void)
89{
90 unsigned long mfpr_pmic, data;
91
92 mfpr_pmic = APB_VIRT_BASE + 0x1e000 + 0x2c4;
93 data = __raw_readl(mfpr_pmic);
94 __raw_writel(data | (1 << 6), mfpr_pmic);
95 __raw_writel(data, mfpr_pmic);
96}
97
98static void __init mmp2_init_gpio(void)
99{
100 int i;
101
102 /* enable GPIO clock */
103 __raw_writel(APBC_APBCLK | APBC_FNCLK, APBC_MMP2_GPIO);
104
105 /* unmask GPIO edge detection for all 6 banks -- APMASKx */
106 for (i = 0; i < 6; i++)
107 __raw_writel(0xffffffff, APMASK(i));
108
109 pxa_init_gpio(IRQ_MMP2_GPIO, 0, 167, NULL);
110}
111
112void __init mmp2_init_irq(void)
113{
114 mmp2_init_icu();
115 mmp2_init_gpio();
116}
117
118static void sdhc_clk_enable(struct clk *clk)
119{
120 uint32_t clk_rst;
121
122 clk_rst = __raw_readl(clk->clk_rst);
123 clk_rst |= clk->enable_val;
124 __raw_writel(clk_rst, clk->clk_rst);
125}
126
127static void sdhc_clk_disable(struct clk *clk)
128{
129 uint32_t clk_rst;
130
131 clk_rst = __raw_readl(clk->clk_rst);
132 clk_rst &= ~clk->enable_val;
133 __raw_writel(clk_rst, clk->clk_rst);
134}
135
136struct clkops sdhc_clk_ops = {
137 .enable = sdhc_clk_enable,
138 .disable = sdhc_clk_disable,
139};
140
141/* APB peripheral clocks */
142static APBC_CLK(uart1, MMP2_UART1, 1, 26000000);
143static APBC_CLK(uart2, MMP2_UART2, 1, 26000000);
144static APBC_CLK(uart3, MMP2_UART3, 1, 26000000);
145static APBC_CLK(uart4, MMP2_UART4, 1, 26000000);
146static APBC_CLK(twsi1, MMP2_TWSI1, 0, 26000000);
147static APBC_CLK(twsi2, MMP2_TWSI2, 0, 26000000);
148static APBC_CLK(twsi3, MMP2_TWSI3, 0, 26000000);
149static APBC_CLK(twsi4, MMP2_TWSI4, 0, 26000000);
150static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000);
151static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000);
152
153static APMU_CLK(nand, NAND, 0xbf, 100000000);
154static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops);
155static APMU_CLK_OPS(sdh1, SDH1, 0x1b, 200000000, &sdhc_clk_ops);
156static APMU_CLK_OPS(sdh2, SDH2, 0x1b, 200000000, &sdhc_clk_ops);
157static APMU_CLK_OPS(sdh3, SDH3, 0x1b, 200000000, &sdhc_clk_ops);
158
159static struct clk_lookup mmp2_clkregs[] = {
160 INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
161 INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
162 INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
163 INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL),
164 INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL),
165 INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL),
166 INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL),
167 INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL),
168 INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL),
169 INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL),
170 INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
171 INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"),
172 INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"),
173 INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"),
174 INIT_CLKREG(&clk_sdh3, "sdhci-pxav3.3", "PXA-SDHCLK"),
175};
176
177static int __init mmp2_init(void)
178{
179 if (cpu_is_mmp2()) {
180#ifdef CONFIG_CACHE_TAUROS2
181 tauros2_init();
182#endif
183 mfp_init_base(MFPR_VIRT_BASE);
184 mfp_init_addr(mmp2_addr_map);
185 pxa_init_dma(IRQ_MMP2_DMA_RIQ, 16);
186 clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs));
187 }
188
189 return 0;
190}
191postcore_initcall(mmp2_init);
192
193static void __init mmp2_timer_init(void)
194{
195 unsigned long clk_rst;
196
197 __raw_writel(APBC_APBCLK | APBC_RST, APBC_MMP2_TIMERS);
198
199 /*
200 * enable bus/functional clock, enable 6.5MHz (divider 4),
201 * release reset
202 */
203 clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1);
204 __raw_writel(clk_rst, APBC_MMP2_TIMERS);
205
206 timer_init(IRQ_MMP2_TIMER1);
207}
208
209struct sys_timer mmp2_timer = {
210 .init = mmp2_timer_init,
211};
212
213/* on-chip devices */
214MMP2_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4030000, 0x30, 4, 5);
215MMP2_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4017000, 0x30, 20, 21);
216MMP2_DEVICE(uart3, "pxa2xx-uart", 2, UART3, 0xd4018000, 0x30, 22, 23);
217MMP2_DEVICE(uart4, "pxa2xx-uart", 3, UART4, 0xd4016000, 0x30, 18, 19);
218MMP2_DEVICE(twsi1, "pxa2xx-i2c", 0, TWSI1, 0xd4011000, 0x70);
219MMP2_DEVICE(twsi2, "pxa2xx-i2c", 1, TWSI2, 0xd4031000, 0x70);
220MMP2_DEVICE(twsi3, "pxa2xx-i2c", 2, TWSI3, 0xd4032000, 0x70);
221MMP2_DEVICE(twsi4, "pxa2xx-i2c", 3, TWSI4, 0xd4033000, 0x70);
222MMP2_DEVICE(twsi5, "pxa2xx-i2c", 4, TWSI5, 0xd4033800, 0x70);
223MMP2_DEVICE(twsi6, "pxa2xx-i2c", 5, TWSI6, 0xd4034000, 0x70);
224MMP2_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x100, 28, 29);
225MMP2_DEVICE(sdh0, "sdhci-pxav3", 0, MMC, 0xd4280000, 0x120);
226MMP2_DEVICE(sdh1, "sdhci-pxav3", 1, MMC2, 0xd4280800, 0x120);
227MMP2_DEVICE(sdh2, "sdhci-pxav3", 2, MMC3, 0xd4281000, 0x120);
228MMP2_DEVICE(sdh3, "sdhci-pxav3", 3, MMC4, 0xd4281800, 0x120);
229