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1/*
2 * arch/arm/mach-at91/at91sam9263_devices.c
3 *
4 * Copyright (C) 2007 Atmel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12#include <asm/mach/arch.h>
13#include <asm/mach/map.h>
14
15#include <linux/dma-mapping.h>
16#include <linux/platform_device.h>
17#include <linux/i2c-gpio.h>
18
19#include <linux/fb.h>
20#include <video/atmel_lcdc.h>
21
22#include <mach/board.h>
23#include <mach/gpio.h>
24#include <mach/at91sam9263.h>
25#include <mach/at91sam9263_matrix.h>
26#include <mach/at91sam9_smc.h>
27
28#include "generic.h"
29
30
31/* --------------------------------------------------------------------
32 * USB Host
33 * -------------------------------------------------------------------- */
34
35#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
36static u64 ohci_dmamask = DMA_BIT_MASK(32);
37static struct at91_usbh_data usbh_data;
38
39static struct resource usbh_resources[] = {
40 [0] = {
41 .start = AT91SAM9263_UHP_BASE,
42 .end = AT91SAM9263_UHP_BASE + SZ_1M - 1,
43 .flags = IORESOURCE_MEM,
44 },
45 [1] = {
46 .start = AT91SAM9263_ID_UHP,
47 .end = AT91SAM9263_ID_UHP,
48 .flags = IORESOURCE_IRQ,
49 },
50};
51
52static struct platform_device at91_usbh_device = {
53 .name = "at91_ohci",
54 .id = -1,
55 .dev = {
56 .dma_mask = &ohci_dmamask,
57 .coherent_dma_mask = DMA_BIT_MASK(32),
58 .platform_data = &usbh_data,
59 },
60 .resource = usbh_resources,
61 .num_resources = ARRAY_SIZE(usbh_resources),
62};
63
64void __init at91_add_device_usbh(struct at91_usbh_data *data)
65{
66 int i;
67
68 if (!data)
69 return;
70
71 /* Enable VBus control for UHP ports */
72 for (i = 0; i < data->ports; i++) {
73 if (data->vbus_pin[i])
74 at91_set_gpio_output(data->vbus_pin[i], 0);
75 }
76
77 usbh_data = *data;
78 platform_device_register(&at91_usbh_device);
79}
80#else
81void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
82#endif
83
84
85/* --------------------------------------------------------------------
86 * USB Device (Gadget)
87 * -------------------------------------------------------------------- */
88
89#ifdef CONFIG_USB_GADGET_AT91
90static struct at91_udc_data udc_data;
91
92static struct resource udc_resources[] = {
93 [0] = {
94 .start = AT91SAM9263_BASE_UDP,
95 .end = AT91SAM9263_BASE_UDP + SZ_16K - 1,
96 .flags = IORESOURCE_MEM,
97 },
98 [1] = {
99 .start = AT91SAM9263_ID_UDP,
100 .end = AT91SAM9263_ID_UDP,
101 .flags = IORESOURCE_IRQ,
102 },
103};
104
105static struct platform_device at91_udc_device = {
106 .name = "at91_udc",
107 .id = -1,
108 .dev = {
109 .platform_data = &udc_data,
110 },
111 .resource = udc_resources,
112 .num_resources = ARRAY_SIZE(udc_resources),
113};
114
115void __init at91_add_device_udc(struct at91_udc_data *data)
116{
117 if (!data)
118 return;
119
120 if (data->vbus_pin) {
121 at91_set_gpio_input(data->vbus_pin, 0);
122 at91_set_deglitch(data->vbus_pin, 1);
123 }
124
125 /* Pullup pin is handled internally by USB device peripheral */
126
127 udc_data = *data;
128 platform_device_register(&at91_udc_device);
129}
130#else
131void __init at91_add_device_udc(struct at91_udc_data *data) {}
132#endif
133
134
135/* --------------------------------------------------------------------
136 * Ethernet
137 * -------------------------------------------------------------------- */
138
139#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
140static u64 eth_dmamask = DMA_BIT_MASK(32);
141static struct at91_eth_data eth_data;
142
143static struct resource eth_resources[] = {
144 [0] = {
145 .start = AT91SAM9263_BASE_EMAC,
146 .end = AT91SAM9263_BASE_EMAC + SZ_16K - 1,
147 .flags = IORESOURCE_MEM,
148 },
149 [1] = {
150 .start = AT91SAM9263_ID_EMAC,
151 .end = AT91SAM9263_ID_EMAC,
152 .flags = IORESOURCE_IRQ,
153 },
154};
155
156static struct platform_device at91sam9263_eth_device = {
157 .name = "macb",
158 .id = -1,
159 .dev = {
160 .dma_mask = ð_dmamask,
161 .coherent_dma_mask = DMA_BIT_MASK(32),
162 .platform_data = ð_data,
163 },
164 .resource = eth_resources,
165 .num_resources = ARRAY_SIZE(eth_resources),
166};
167
168void __init at91_add_device_eth(struct at91_eth_data *data)
169{
170 if (!data)
171 return;
172
173 if (data->phy_irq_pin) {
174 at91_set_gpio_input(data->phy_irq_pin, 0);
175 at91_set_deglitch(data->phy_irq_pin, 1);
176 }
177
178 /* Pins used for MII and RMII */
179 at91_set_A_periph(AT91_PIN_PE21, 0); /* ETXCK_EREFCK */
180 at91_set_B_periph(AT91_PIN_PC25, 0); /* ERXDV */
181 at91_set_A_periph(AT91_PIN_PE25, 0); /* ERX0 */
182 at91_set_A_periph(AT91_PIN_PE26, 0); /* ERX1 */
183 at91_set_A_periph(AT91_PIN_PE27, 0); /* ERXER */
184 at91_set_A_periph(AT91_PIN_PE28, 0); /* ETXEN */
185 at91_set_A_periph(AT91_PIN_PE23, 0); /* ETX0 */
186 at91_set_A_periph(AT91_PIN_PE24, 0); /* ETX1 */
187 at91_set_A_periph(AT91_PIN_PE30, 0); /* EMDIO */
188 at91_set_A_periph(AT91_PIN_PE29, 0); /* EMDC */
189
190 if (!data->is_rmii) {
191 at91_set_A_periph(AT91_PIN_PE22, 0); /* ECRS */
192 at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */
193 at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */
194 at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */
195 at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */
196 at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */
197 at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */
198 at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */
199 }
200
201 eth_data = *data;
202 platform_device_register(&at91sam9263_eth_device);
203}
204#else
205void __init at91_add_device_eth(struct at91_eth_data *data) {}
206#endif
207
208
209/* --------------------------------------------------------------------
210 * MMC / SD
211 * -------------------------------------------------------------------- */
212
213#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
214static u64 mmc_dmamask = DMA_BIT_MASK(32);
215static struct at91_mmc_data mmc0_data, mmc1_data;
216
217static struct resource mmc0_resources[] = {
218 [0] = {
219 .start = AT91SAM9263_BASE_MCI0,
220 .end = AT91SAM9263_BASE_MCI0 + SZ_16K - 1,
221 .flags = IORESOURCE_MEM,
222 },
223 [1] = {
224 .start = AT91SAM9263_ID_MCI0,
225 .end = AT91SAM9263_ID_MCI0,
226 .flags = IORESOURCE_IRQ,
227 },
228};
229
230static struct platform_device at91sam9263_mmc0_device = {
231 .name = "at91_mci",
232 .id = 0,
233 .dev = {
234 .dma_mask = &mmc_dmamask,
235 .coherent_dma_mask = DMA_BIT_MASK(32),
236 .platform_data = &mmc0_data,
237 },
238 .resource = mmc0_resources,
239 .num_resources = ARRAY_SIZE(mmc0_resources),
240};
241
242static struct resource mmc1_resources[] = {
243 [0] = {
244 .start = AT91SAM9263_BASE_MCI1,
245 .end = AT91SAM9263_BASE_MCI1 + SZ_16K - 1,
246 .flags = IORESOURCE_MEM,
247 },
248 [1] = {
249 .start = AT91SAM9263_ID_MCI1,
250 .end = AT91SAM9263_ID_MCI1,
251 .flags = IORESOURCE_IRQ,
252 },
253};
254
255static struct platform_device at91sam9263_mmc1_device = {
256 .name = "at91_mci",
257 .id = 1,
258 .dev = {
259 .dma_mask = &mmc_dmamask,
260 .coherent_dma_mask = DMA_BIT_MASK(32),
261 .platform_data = &mmc1_data,
262 },
263 .resource = mmc1_resources,
264 .num_resources = ARRAY_SIZE(mmc1_resources),
265};
266
267void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
268{
269 if (!data)
270 return;
271
272 /* input/irq */
273 if (data->det_pin) {
274 at91_set_gpio_input(data->det_pin, 1);
275 at91_set_deglitch(data->det_pin, 1);
276 }
277 if (data->wp_pin)
278 at91_set_gpio_input(data->wp_pin, 1);
279 if (data->vcc_pin)
280 at91_set_gpio_output(data->vcc_pin, 0);
281
282 if (mmc_id == 0) { /* MCI0 */
283 /* CLK */
284 at91_set_A_periph(AT91_PIN_PA12, 0);
285
286 if (data->slot_b) {
287 /* CMD */
288 at91_set_A_periph(AT91_PIN_PA16, 1);
289
290 /* DAT0, maybe DAT1..DAT3 */
291 at91_set_A_periph(AT91_PIN_PA17, 1);
292 if (data->wire4) {
293 at91_set_A_periph(AT91_PIN_PA18, 1);
294 at91_set_A_periph(AT91_PIN_PA19, 1);
295 at91_set_A_periph(AT91_PIN_PA20, 1);
296 }
297 } else {
298 /* CMD */
299 at91_set_A_periph(AT91_PIN_PA1, 1);
300
301 /* DAT0, maybe DAT1..DAT3 */
302 at91_set_A_periph(AT91_PIN_PA0, 1);
303 if (data->wire4) {
304 at91_set_A_periph(AT91_PIN_PA3, 1);
305 at91_set_A_periph(AT91_PIN_PA4, 1);
306 at91_set_A_periph(AT91_PIN_PA5, 1);
307 }
308 }
309
310 mmc0_data = *data;
311 platform_device_register(&at91sam9263_mmc0_device);
312 } else { /* MCI1 */
313 /* CLK */
314 at91_set_A_periph(AT91_PIN_PA6, 0);
315
316 if (data->slot_b) {
317 /* CMD */
318 at91_set_A_periph(AT91_PIN_PA21, 1);
319
320 /* DAT0, maybe DAT1..DAT3 */
321 at91_set_A_periph(AT91_PIN_PA22, 1);
322 if (data->wire4) {
323 at91_set_A_periph(AT91_PIN_PA23, 1);
324 at91_set_A_periph(AT91_PIN_PA24, 1);
325 at91_set_A_periph(AT91_PIN_PA25, 1);
326 }
327 } else {
328 /* CMD */
329 at91_set_A_periph(AT91_PIN_PA7, 1);
330
331 /* DAT0, maybe DAT1..DAT3 */
332 at91_set_A_periph(AT91_PIN_PA8, 1);
333 if (data->wire4) {
334 at91_set_A_periph(AT91_PIN_PA9, 1);
335 at91_set_A_periph(AT91_PIN_PA10, 1);
336 at91_set_A_periph(AT91_PIN_PA11, 1);
337 }
338 }
339
340 mmc1_data = *data;
341 platform_device_register(&at91sam9263_mmc1_device);
342 }
343}
344#else
345void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
346#endif
347
348/* --------------------------------------------------------------------
349 * Compact Flash (PCMCIA or IDE)
350 * -------------------------------------------------------------------- */
351
352#if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE) || \
353 defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE)
354
355static struct at91_cf_data cf0_data;
356
357static struct resource cf0_resources[] = {
358 [0] = {
359 .start = AT91_CHIPSELECT_4,
360 .end = AT91_CHIPSELECT_4 + SZ_256M - 1,
361 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
362 }
363};
364
365static struct platform_device cf0_device = {
366 .id = 0,
367 .dev = {
368 .platform_data = &cf0_data,
369 },
370 .resource = cf0_resources,
371 .num_resources = ARRAY_SIZE(cf0_resources),
372};
373
374static struct at91_cf_data cf1_data;
375
376static struct resource cf1_resources[] = {
377 [0] = {
378 .start = AT91_CHIPSELECT_5,
379 .end = AT91_CHIPSELECT_5 + SZ_256M - 1,
380 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
381 }
382};
383
384static struct platform_device cf1_device = {
385 .id = 1,
386 .dev = {
387 .platform_data = &cf1_data,
388 },
389 .resource = cf1_resources,
390 .num_resources = ARRAY_SIZE(cf1_resources),
391};
392
393void __init at91_add_device_cf(struct at91_cf_data *data)
394{
395 unsigned long ebi0_csa;
396 struct platform_device *pdev;
397
398 if (!data)
399 return;
400
401 /*
402 * assign CS4 or CS5 to SMC with Compact Flash logic support,
403 * we assume SMC timings are configured by board code,
404 * except True IDE where timings are controlled by driver
405 */
406 ebi0_csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
407 switch (data->chipselect) {
408 case 4:
409 at91_set_A_periph(AT91_PIN_PD6, 0); /* EBI0_NCS4/CFCS0 */
410 ebi0_csa |= AT91_MATRIX_EBI0_CS4A_SMC_CF1;
411 cf0_data = *data;
412 pdev = &cf0_device;
413 break;
414 case 5:
415 at91_set_A_periph(AT91_PIN_PD7, 0); /* EBI0_NCS5/CFCS1 */
416 ebi0_csa |= AT91_MATRIX_EBI0_CS5A_SMC_CF2;
417 cf1_data = *data;
418 pdev = &cf1_device;
419 break;
420 default:
421 printk(KERN_ERR "AT91 CF: bad chip-select requested (%u)\n",
422 data->chipselect);
423 return;
424 }
425 at91_sys_write(AT91_MATRIX_EBI0CSA, ebi0_csa);
426
427 if (data->det_pin) {
428 at91_set_gpio_input(data->det_pin, 1);
429 at91_set_deglitch(data->det_pin, 1);
430 }
431
432 if (data->irq_pin) {
433 at91_set_gpio_input(data->irq_pin, 1);
434 at91_set_deglitch(data->irq_pin, 1);
435 }
436
437 if (data->vcc_pin)
438 /* initially off */
439 at91_set_gpio_output(data->vcc_pin, 0);
440
441 /* enable EBI controlled pins */
442 at91_set_A_periph(AT91_PIN_PD5, 1); /* NWAIT */
443 at91_set_A_periph(AT91_PIN_PD8, 0); /* CFCE1 */
444 at91_set_A_periph(AT91_PIN_PD9, 0); /* CFCE2 */
445 at91_set_A_periph(AT91_PIN_PD14, 0); /* CFNRW */
446
447 pdev->name = (data->flags & AT91_CF_TRUE_IDE) ? "at91_ide" : "at91_cf";
448 platform_device_register(pdev);
449}
450#else
451void __init at91_add_device_cf(struct at91_cf_data *data) {}
452#endif
453
454/* --------------------------------------------------------------------
455 * NAND / SmartMedia
456 * -------------------------------------------------------------------- */
457
458#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
459static struct atmel_nand_data nand_data;
460
461#define NAND_BASE AT91_CHIPSELECT_3
462
463static struct resource nand_resources[] = {
464 [0] = {
465 .start = NAND_BASE,
466 .end = NAND_BASE + SZ_256M - 1,
467 .flags = IORESOURCE_MEM,
468 },
469 [1] = {
470 .start = AT91_BASE_SYS + AT91_ECC0,
471 .end = AT91_BASE_SYS + AT91_ECC0 + SZ_512 - 1,
472 .flags = IORESOURCE_MEM,
473 }
474};
475
476static struct platform_device at91sam9263_nand_device = {
477 .name = "atmel_nand",
478 .id = -1,
479 .dev = {
480 .platform_data = &nand_data,
481 },
482 .resource = nand_resources,
483 .num_resources = ARRAY_SIZE(nand_resources),
484};
485
486void __init at91_add_device_nand(struct atmel_nand_data *data)
487{
488 unsigned long csa;
489
490 if (!data)
491 return;
492
493 csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
494 at91_sys_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
495
496 /* enable pin */
497 if (data->enable_pin)
498 at91_set_gpio_output(data->enable_pin, 1);
499
500 /* ready/busy pin */
501 if (data->rdy_pin)
502 at91_set_gpio_input(data->rdy_pin, 1);
503
504 /* card detect pin */
505 if (data->det_pin)
506 at91_set_gpio_input(data->det_pin, 1);
507
508 nand_data = *data;
509 platform_device_register(&at91sam9263_nand_device);
510}
511#else
512void __init at91_add_device_nand(struct atmel_nand_data *data) {}
513#endif
514
515
516/* --------------------------------------------------------------------
517 * TWI (i2c)
518 * -------------------------------------------------------------------- */
519
520/*
521 * Prefer the GPIO code since the TWI controller isn't robust
522 * (gets overruns and underruns under load) and can only issue
523 * repeated STARTs in one scenario (the driver doesn't yet handle them).
524 */
525#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
526
527static struct i2c_gpio_platform_data pdata = {
528 .sda_pin = AT91_PIN_PB4,
529 .sda_is_open_drain = 1,
530 .scl_pin = AT91_PIN_PB5,
531 .scl_is_open_drain = 1,
532 .udelay = 2, /* ~100 kHz */
533};
534
535static struct platform_device at91sam9263_twi_device = {
536 .name = "i2c-gpio",
537 .id = -1,
538 .dev.platform_data = &pdata,
539};
540
541void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
542{
543 at91_set_GPIO_periph(AT91_PIN_PB4, 1); /* TWD (SDA) */
544 at91_set_multi_drive(AT91_PIN_PB4, 1);
545
546 at91_set_GPIO_periph(AT91_PIN_PB5, 1); /* TWCK (SCL) */
547 at91_set_multi_drive(AT91_PIN_PB5, 1);
548
549 i2c_register_board_info(0, devices, nr_devices);
550 platform_device_register(&at91sam9263_twi_device);
551}
552
553#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
554
555static struct resource twi_resources[] = {
556 [0] = {
557 .start = AT91SAM9263_BASE_TWI,
558 .end = AT91SAM9263_BASE_TWI + SZ_16K - 1,
559 .flags = IORESOURCE_MEM,
560 },
561 [1] = {
562 .start = AT91SAM9263_ID_TWI,
563 .end = AT91SAM9263_ID_TWI,
564 .flags = IORESOURCE_IRQ,
565 },
566};
567
568static struct platform_device at91sam9263_twi_device = {
569 .name = "at91_i2c",
570 .id = -1,
571 .resource = twi_resources,
572 .num_resources = ARRAY_SIZE(twi_resources),
573};
574
575void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
576{
577 /* pins used for TWI interface */
578 at91_set_A_periph(AT91_PIN_PB4, 0); /* TWD */
579 at91_set_multi_drive(AT91_PIN_PB4, 1);
580
581 at91_set_A_periph(AT91_PIN_PB5, 0); /* TWCK */
582 at91_set_multi_drive(AT91_PIN_PB5, 1);
583
584 i2c_register_board_info(0, devices, nr_devices);
585 platform_device_register(&at91sam9263_twi_device);
586}
587#else
588void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
589#endif
590
591
592/* --------------------------------------------------------------------
593 * SPI
594 * -------------------------------------------------------------------- */
595
596#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
597static u64 spi_dmamask = DMA_BIT_MASK(32);
598
599static struct resource spi0_resources[] = {
600 [0] = {
601 .start = AT91SAM9263_BASE_SPI0,
602 .end = AT91SAM9263_BASE_SPI0 + SZ_16K - 1,
603 .flags = IORESOURCE_MEM,
604 },
605 [1] = {
606 .start = AT91SAM9263_ID_SPI0,
607 .end = AT91SAM9263_ID_SPI0,
608 .flags = IORESOURCE_IRQ,
609 },
610};
611
612static struct platform_device at91sam9263_spi0_device = {
613 .name = "atmel_spi",
614 .id = 0,
615 .dev = {
616 .dma_mask = &spi_dmamask,
617 .coherent_dma_mask = DMA_BIT_MASK(32),
618 },
619 .resource = spi0_resources,
620 .num_resources = ARRAY_SIZE(spi0_resources),
621};
622
623static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA5, AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PB11 };
624
625static struct resource spi1_resources[] = {
626 [0] = {
627 .start = AT91SAM9263_BASE_SPI1,
628 .end = AT91SAM9263_BASE_SPI1 + SZ_16K - 1,
629 .flags = IORESOURCE_MEM,
630 },
631 [1] = {
632 .start = AT91SAM9263_ID_SPI1,
633 .end = AT91SAM9263_ID_SPI1,
634 .flags = IORESOURCE_IRQ,
635 },
636};
637
638static struct platform_device at91sam9263_spi1_device = {
639 .name = "atmel_spi",
640 .id = 1,
641 .dev = {
642 .dma_mask = &spi_dmamask,
643 .coherent_dma_mask = DMA_BIT_MASK(32),
644 },
645 .resource = spi1_resources,
646 .num_resources = ARRAY_SIZE(spi1_resources),
647};
648
649static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB15, AT91_PIN_PB16, AT91_PIN_PB17, AT91_PIN_PB18 };
650
651void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
652{
653 int i;
654 unsigned long cs_pin;
655 short enable_spi0 = 0;
656 short enable_spi1 = 0;
657
658 /* Choose SPI chip-selects */
659 for (i = 0; i < nr_devices; i++) {
660 if (devices[i].controller_data)
661 cs_pin = (unsigned long) devices[i].controller_data;
662 else if (devices[i].bus_num == 0)
663 cs_pin = spi0_standard_cs[devices[i].chip_select];
664 else
665 cs_pin = spi1_standard_cs[devices[i].chip_select];
666
667 if (devices[i].bus_num == 0)
668 enable_spi0 = 1;
669 else
670 enable_spi1 = 1;
671
672 /* enable chip-select pin */
673 at91_set_gpio_output(cs_pin, 1);
674
675 /* pass chip-select pin to driver */
676 devices[i].controller_data = (void *) cs_pin;
677 }
678
679 spi_register_board_info(devices, nr_devices);
680
681 /* Configure SPI bus(es) */
682 if (enable_spi0) {
683 at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
684 at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
685 at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
686
687 platform_device_register(&at91sam9263_spi0_device);
688 }
689 if (enable_spi1) {
690 at91_set_A_periph(AT91_PIN_PB12, 0); /* SPI1_MISO */
691 at91_set_A_periph(AT91_PIN_PB13, 0); /* SPI1_MOSI */
692 at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_SPCK */
693
694 platform_device_register(&at91sam9263_spi1_device);
695 }
696}
697#else
698void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
699#endif
700
701
702/* --------------------------------------------------------------------
703 * AC97
704 * -------------------------------------------------------------------- */
705
706#if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
707static u64 ac97_dmamask = DMA_BIT_MASK(32);
708static struct ac97c_platform_data ac97_data;
709
710static struct resource ac97_resources[] = {
711 [0] = {
712 .start = AT91SAM9263_BASE_AC97C,
713 .end = AT91SAM9263_BASE_AC97C + SZ_16K - 1,
714 .flags = IORESOURCE_MEM,
715 },
716 [1] = {
717 .start = AT91SAM9263_ID_AC97C,
718 .end = AT91SAM9263_ID_AC97C,
719 .flags = IORESOURCE_IRQ,
720 },
721};
722
723static struct platform_device at91sam9263_ac97_device = {
724 .name = "atmel_ac97c",
725 .id = 0,
726 .dev = {
727 .dma_mask = &ac97_dmamask,
728 .coherent_dma_mask = DMA_BIT_MASK(32),
729 .platform_data = &ac97_data,
730 },
731 .resource = ac97_resources,
732 .num_resources = ARRAY_SIZE(ac97_resources),
733};
734
735void __init at91_add_device_ac97(struct ac97c_platform_data *data)
736{
737 if (!data)
738 return;
739
740 at91_set_A_periph(AT91_PIN_PB0, 0); /* AC97FS */
741 at91_set_A_periph(AT91_PIN_PB1, 0); /* AC97CK */
742 at91_set_A_periph(AT91_PIN_PB2, 0); /* AC97TX */
743 at91_set_A_periph(AT91_PIN_PB3, 0); /* AC97RX */
744
745 /* reset */
746 if (data->reset_pin)
747 at91_set_gpio_output(data->reset_pin, 0);
748
749 ac97_data = *data;
750 platform_device_register(&at91sam9263_ac97_device);
751}
752#else
753void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
754#endif
755
756/* --------------------------------------------------------------------
757 * CAN Controller
758 * -------------------------------------------------------------------- */
759
760#if defined(CONFIG_CAN_AT91) || defined(CONFIG_CAN_AT91_MODULE)
761static struct resource can_resources[] = {
762 [0] = {
763 .start = AT91SAM9263_BASE_CAN,
764 .end = AT91SAM9263_BASE_CAN + SZ_16K - 1,
765 .flags = IORESOURCE_MEM,
766 },
767 [1] = {
768 .start = AT91SAM9263_ID_CAN,
769 .end = AT91SAM9263_ID_CAN,
770 .flags = IORESOURCE_IRQ,
771 },
772};
773
774static struct platform_device at91sam9263_can_device = {
775 .name = "at91_can",
776 .id = -1,
777 .resource = can_resources,
778 .num_resources = ARRAY_SIZE(can_resources),
779};
780
781void __init at91_add_device_can(struct at91_can_data *data)
782{
783 at91_set_A_periph(AT91_PIN_PA13, 0); /* CANTX */
784 at91_set_A_periph(AT91_PIN_PA14, 0); /* CANRX */
785 at91sam9263_can_device.dev.platform_data = data;
786
787 platform_device_register(&at91sam9263_can_device);
788}
789#else
790void __init at91_add_device_can(struct at91_can_data *data) {}
791#endif
792
793/* --------------------------------------------------------------------
794 * LCD Controller
795 * -------------------------------------------------------------------- */
796
797#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
798static u64 lcdc_dmamask = DMA_BIT_MASK(32);
799static struct atmel_lcdfb_info lcdc_data;
800
801static struct resource lcdc_resources[] = {
802 [0] = {
803 .start = AT91SAM9263_LCDC_BASE,
804 .end = AT91SAM9263_LCDC_BASE + SZ_4K - 1,
805 .flags = IORESOURCE_MEM,
806 },
807 [1] = {
808 .start = AT91SAM9263_ID_LCDC,
809 .end = AT91SAM9263_ID_LCDC,
810 .flags = IORESOURCE_IRQ,
811 },
812};
813
814static struct platform_device at91_lcdc_device = {
815 .name = "atmel_lcdfb",
816 .id = 0,
817 .dev = {
818 .dma_mask = &lcdc_dmamask,
819 .coherent_dma_mask = DMA_BIT_MASK(32),
820 .platform_data = &lcdc_data,
821 },
822 .resource = lcdc_resources,
823 .num_resources = ARRAY_SIZE(lcdc_resources),
824};
825
826void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
827{
828 if (!data)
829 return;
830
831 at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
832 at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
833 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
834 at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
835 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
836 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
837 at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
838 at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
839 at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
840 at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
841 at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
842 at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
843 at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
844 at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */
845 at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
846 at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
847 at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
848 at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
849 at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
850 at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */
851 at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
852 at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
853
854 lcdc_data = *data;
855 platform_device_register(&at91_lcdc_device);
856}
857#else
858void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
859#endif
860
861
862/* --------------------------------------------------------------------
863 * Image Sensor Interface
864 * -------------------------------------------------------------------- */
865
866#if defined(CONFIG_VIDEO_AT91_ISI) || defined(CONFIG_VIDEO_AT91_ISI_MODULE)
867
868struct resource isi_resources[] = {
869 [0] = {
870 .start = AT91SAM9263_BASE_ISI,
871 .end = AT91SAM9263_BASE_ISI + SZ_16K - 1,
872 .flags = IORESOURCE_MEM,
873 },
874 [1] = {
875 .start = AT91SAM9263_ID_ISI,
876 .end = AT91SAM9263_ID_ISI,
877 .flags = IORESOURCE_IRQ,
878 },
879};
880
881static struct platform_device at91sam9263_isi_device = {
882 .name = "at91_isi",
883 .id = -1,
884 .resource = isi_resources,
885 .num_resources = ARRAY_SIZE(isi_resources),
886};
887
888void __init at91_add_device_isi(void)
889{
890 at91_set_A_periph(AT91_PIN_PE0, 0); /* ISI_D0 */
891 at91_set_A_periph(AT91_PIN_PE1, 0); /* ISI_D1 */
892 at91_set_A_periph(AT91_PIN_PE2, 0); /* ISI_D2 */
893 at91_set_A_periph(AT91_PIN_PE3, 0); /* ISI_D3 */
894 at91_set_A_periph(AT91_PIN_PE4, 0); /* ISI_D4 */
895 at91_set_A_periph(AT91_PIN_PE5, 0); /* ISI_D5 */
896 at91_set_A_periph(AT91_PIN_PE6, 0); /* ISI_D6 */
897 at91_set_A_periph(AT91_PIN_PE7, 0); /* ISI_D7 */
898 at91_set_A_periph(AT91_PIN_PE8, 0); /* ISI_PCK */
899 at91_set_A_periph(AT91_PIN_PE9, 0); /* ISI_HSYNC */
900 at91_set_A_periph(AT91_PIN_PE10, 0); /* ISI_VSYNC */
901 at91_set_B_periph(AT91_PIN_PE11, 0); /* ISI_MCK (PCK3) */
902 at91_set_B_periph(AT91_PIN_PE12, 0); /* ISI_PD8 */
903 at91_set_B_periph(AT91_PIN_PE13, 0); /* ISI_PD9 */
904 at91_set_B_periph(AT91_PIN_PE14, 0); /* ISI_PD10 */
905 at91_set_B_periph(AT91_PIN_PE15, 0); /* ISI_PD11 */
906}
907#else
908void __init at91_add_device_isi(void) {}
909#endif
910
911
912/* --------------------------------------------------------------------
913 * Timer/Counter block
914 * -------------------------------------------------------------------- */
915
916#ifdef CONFIG_ATMEL_TCLIB
917
918static struct resource tcb_resources[] = {
919 [0] = {
920 .start = AT91SAM9263_BASE_TCB0,
921 .end = AT91SAM9263_BASE_TCB0 + SZ_16K - 1,
922 .flags = IORESOURCE_MEM,
923 },
924 [1] = {
925 .start = AT91SAM9263_ID_TCB,
926 .end = AT91SAM9263_ID_TCB,
927 .flags = IORESOURCE_IRQ,
928 },
929};
930
931static struct platform_device at91sam9263_tcb_device = {
932 .name = "atmel_tcb",
933 .id = 0,
934 .resource = tcb_resources,
935 .num_resources = ARRAY_SIZE(tcb_resources),
936};
937
938static void __init at91_add_device_tc(void)
939{
940 platform_device_register(&at91sam9263_tcb_device);
941}
942#else
943static void __init at91_add_device_tc(void) { }
944#endif
945
946
947/* --------------------------------------------------------------------
948 * RTT
949 * -------------------------------------------------------------------- */
950
951static struct resource rtt0_resources[] = {
952 {
953 .start = AT91_BASE_SYS + AT91_RTT0,
954 .end = AT91_BASE_SYS + AT91_RTT0 + SZ_16 - 1,
955 .flags = IORESOURCE_MEM,
956 }
957};
958
959static struct platform_device at91sam9263_rtt0_device = {
960 .name = "at91_rtt",
961 .id = 0,
962 .resource = rtt0_resources,
963 .num_resources = ARRAY_SIZE(rtt0_resources),
964};
965
966static struct resource rtt1_resources[] = {
967 {
968 .start = AT91_BASE_SYS + AT91_RTT1,
969 .end = AT91_BASE_SYS + AT91_RTT1 + SZ_16 - 1,
970 .flags = IORESOURCE_MEM,
971 }
972};
973
974static struct platform_device at91sam9263_rtt1_device = {
975 .name = "at91_rtt",
976 .id = 1,
977 .resource = rtt1_resources,
978 .num_resources = ARRAY_SIZE(rtt1_resources),
979};
980
981static void __init at91_add_device_rtt(void)
982{
983 platform_device_register(&at91sam9263_rtt0_device);
984 platform_device_register(&at91sam9263_rtt1_device);
985}
986
987
988/* --------------------------------------------------------------------
989 * Watchdog
990 * -------------------------------------------------------------------- */
991
992#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
993static struct platform_device at91sam9263_wdt_device = {
994 .name = "at91_wdt",
995 .id = -1,
996 .num_resources = 0,
997};
998
999static void __init at91_add_device_watchdog(void)
1000{
1001 platform_device_register(&at91sam9263_wdt_device);
1002}
1003#else
1004static void __init at91_add_device_watchdog(void) {}
1005#endif
1006
1007
1008/* --------------------------------------------------------------------
1009 * PWM
1010 * --------------------------------------------------------------------*/
1011
1012#if defined(CONFIG_ATMEL_PWM)
1013static u32 pwm_mask;
1014
1015static struct resource pwm_resources[] = {
1016 [0] = {
1017 .start = AT91SAM9263_BASE_PWMC,
1018 .end = AT91SAM9263_BASE_PWMC + SZ_16K - 1,
1019 .flags = IORESOURCE_MEM,
1020 },
1021 [1] = {
1022 .start = AT91SAM9263_ID_PWMC,
1023 .end = AT91SAM9263_ID_PWMC,
1024 .flags = IORESOURCE_IRQ,
1025 },
1026};
1027
1028static struct platform_device at91sam9263_pwm0_device = {
1029 .name = "atmel_pwm",
1030 .id = -1,
1031 .dev = {
1032 .platform_data = &pwm_mask,
1033 },
1034 .resource = pwm_resources,
1035 .num_resources = ARRAY_SIZE(pwm_resources),
1036};
1037
1038void __init at91_add_device_pwm(u32 mask)
1039{
1040 if (mask & (1 << AT91_PWM0))
1041 at91_set_B_periph(AT91_PIN_PB7, 1); /* enable PWM0 */
1042
1043 if (mask & (1 << AT91_PWM1))
1044 at91_set_B_periph(AT91_PIN_PB8, 1); /* enable PWM1 */
1045
1046 if (mask & (1 << AT91_PWM2))
1047 at91_set_B_periph(AT91_PIN_PC29, 1); /* enable PWM2 */
1048
1049 if (mask & (1 << AT91_PWM3))
1050 at91_set_B_periph(AT91_PIN_PB29, 1); /* enable PWM3 */
1051
1052 pwm_mask = mask;
1053
1054 platform_device_register(&at91sam9263_pwm0_device);
1055}
1056#else
1057void __init at91_add_device_pwm(u32 mask) {}
1058#endif
1059
1060
1061/* --------------------------------------------------------------------
1062 * SSC -- Synchronous Serial Controller
1063 * -------------------------------------------------------------------- */
1064
1065#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
1066static u64 ssc0_dmamask = DMA_BIT_MASK(32);
1067
1068static struct resource ssc0_resources[] = {
1069 [0] = {
1070 .start = AT91SAM9263_BASE_SSC0,
1071 .end = AT91SAM9263_BASE_SSC0 + SZ_16K - 1,
1072 .flags = IORESOURCE_MEM,
1073 },
1074 [1] = {
1075 .start = AT91SAM9263_ID_SSC0,
1076 .end = AT91SAM9263_ID_SSC0,
1077 .flags = IORESOURCE_IRQ,
1078 },
1079};
1080
1081static struct platform_device at91sam9263_ssc0_device = {
1082 .name = "ssc",
1083 .id = 0,
1084 .dev = {
1085 .dma_mask = &ssc0_dmamask,
1086 .coherent_dma_mask = DMA_BIT_MASK(32),
1087 },
1088 .resource = ssc0_resources,
1089 .num_resources = ARRAY_SIZE(ssc0_resources),
1090};
1091
1092static inline void configure_ssc0_pins(unsigned pins)
1093{
1094 if (pins & ATMEL_SSC_TF)
1095 at91_set_B_periph(AT91_PIN_PB0, 1);
1096 if (pins & ATMEL_SSC_TK)
1097 at91_set_B_periph(AT91_PIN_PB1, 1);
1098 if (pins & ATMEL_SSC_TD)
1099 at91_set_B_periph(AT91_PIN_PB2, 1);
1100 if (pins & ATMEL_SSC_RD)
1101 at91_set_B_periph(AT91_PIN_PB3, 1);
1102 if (pins & ATMEL_SSC_RK)
1103 at91_set_B_periph(AT91_PIN_PB4, 1);
1104 if (pins & ATMEL_SSC_RF)
1105 at91_set_B_periph(AT91_PIN_PB5, 1);
1106}
1107
1108static u64 ssc1_dmamask = DMA_BIT_MASK(32);
1109
1110static struct resource ssc1_resources[] = {
1111 [0] = {
1112 .start = AT91SAM9263_BASE_SSC1,
1113 .end = AT91SAM9263_BASE_SSC1 + SZ_16K - 1,
1114 .flags = IORESOURCE_MEM,
1115 },
1116 [1] = {
1117 .start = AT91SAM9263_ID_SSC1,
1118 .end = AT91SAM9263_ID_SSC1,
1119 .flags = IORESOURCE_IRQ,
1120 },
1121};
1122
1123static struct platform_device at91sam9263_ssc1_device = {
1124 .name = "ssc",
1125 .id = 1,
1126 .dev = {
1127 .dma_mask = &ssc1_dmamask,
1128 .coherent_dma_mask = DMA_BIT_MASK(32),
1129 },
1130 .resource = ssc1_resources,
1131 .num_resources = ARRAY_SIZE(ssc1_resources),
1132};
1133
1134static inline void configure_ssc1_pins(unsigned pins)
1135{
1136 if (pins & ATMEL_SSC_TF)
1137 at91_set_A_periph(AT91_PIN_PB6, 1);
1138 if (pins & ATMEL_SSC_TK)
1139 at91_set_A_periph(AT91_PIN_PB7, 1);
1140 if (pins & ATMEL_SSC_TD)
1141 at91_set_A_periph(AT91_PIN_PB8, 1);
1142 if (pins & ATMEL_SSC_RD)
1143 at91_set_A_periph(AT91_PIN_PB9, 1);
1144 if (pins & ATMEL_SSC_RK)
1145 at91_set_A_periph(AT91_PIN_PB10, 1);
1146 if (pins & ATMEL_SSC_RF)
1147 at91_set_A_periph(AT91_PIN_PB11, 1);
1148}
1149
1150/*
1151 * SSC controllers are accessed through library code, instead of any
1152 * kind of all-singing/all-dancing driver. For example one could be
1153 * used by a particular I2S audio codec's driver, while another one
1154 * on the same system might be used by a custom data capture driver.
1155 */
1156void __init at91_add_device_ssc(unsigned id, unsigned pins)
1157{
1158 struct platform_device *pdev;
1159
1160 /*
1161 * NOTE: caller is responsible for passing information matching
1162 * "pins" to whatever will be using each particular controller.
1163 */
1164 switch (id) {
1165 case AT91SAM9263_ID_SSC0:
1166 pdev = &at91sam9263_ssc0_device;
1167 configure_ssc0_pins(pins);
1168 break;
1169 case AT91SAM9263_ID_SSC1:
1170 pdev = &at91sam9263_ssc1_device;
1171 configure_ssc1_pins(pins);
1172 break;
1173 default:
1174 return;
1175 }
1176
1177 platform_device_register(pdev);
1178}
1179
1180#else
1181void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
1182#endif
1183
1184
1185/* --------------------------------------------------------------------
1186 * UART
1187 * -------------------------------------------------------------------- */
1188
1189#if defined(CONFIG_SERIAL_ATMEL)
1190
1191static struct resource dbgu_resources[] = {
1192 [0] = {
1193 .start = AT91_VA_BASE_SYS + AT91_DBGU,
1194 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
1195 .flags = IORESOURCE_MEM,
1196 },
1197 [1] = {
1198 .start = AT91_ID_SYS,
1199 .end = AT91_ID_SYS,
1200 .flags = IORESOURCE_IRQ,
1201 },
1202};
1203
1204static struct atmel_uart_data dbgu_data = {
1205 .use_dma_tx = 0,
1206 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
1207 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
1208};
1209
1210static u64 dbgu_dmamask = DMA_BIT_MASK(32);
1211
1212static struct platform_device at91sam9263_dbgu_device = {
1213 .name = "atmel_usart",
1214 .id = 0,
1215 .dev = {
1216 .dma_mask = &dbgu_dmamask,
1217 .coherent_dma_mask = DMA_BIT_MASK(32),
1218 .platform_data = &dbgu_data,
1219 },
1220 .resource = dbgu_resources,
1221 .num_resources = ARRAY_SIZE(dbgu_resources),
1222};
1223
1224static inline void configure_dbgu_pins(void)
1225{
1226 at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
1227 at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
1228}
1229
1230static struct resource uart0_resources[] = {
1231 [0] = {
1232 .start = AT91SAM9263_BASE_US0,
1233 .end = AT91SAM9263_BASE_US0 + SZ_16K - 1,
1234 .flags = IORESOURCE_MEM,
1235 },
1236 [1] = {
1237 .start = AT91SAM9263_ID_US0,
1238 .end = AT91SAM9263_ID_US0,
1239 .flags = IORESOURCE_IRQ,
1240 },
1241};
1242
1243static struct atmel_uart_data uart0_data = {
1244 .use_dma_tx = 1,
1245 .use_dma_rx = 1,
1246};
1247
1248static u64 uart0_dmamask = DMA_BIT_MASK(32);
1249
1250static struct platform_device at91sam9263_uart0_device = {
1251 .name = "atmel_usart",
1252 .id = 1,
1253 .dev = {
1254 .dma_mask = &uart0_dmamask,
1255 .coherent_dma_mask = DMA_BIT_MASK(32),
1256 .platform_data = &uart0_data,
1257 },
1258 .resource = uart0_resources,
1259 .num_resources = ARRAY_SIZE(uart0_resources),
1260};
1261
1262static inline void configure_usart0_pins(unsigned pins)
1263{
1264 at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */
1265 at91_set_A_periph(AT91_PIN_PA27, 0); /* RXD0 */
1266
1267 if (pins & ATMEL_UART_RTS)
1268 at91_set_A_periph(AT91_PIN_PA28, 0); /* RTS0 */
1269 if (pins & ATMEL_UART_CTS)
1270 at91_set_A_periph(AT91_PIN_PA29, 0); /* CTS0 */
1271}
1272
1273static struct resource uart1_resources[] = {
1274 [0] = {
1275 .start = AT91SAM9263_BASE_US1,
1276 .end = AT91SAM9263_BASE_US1 + SZ_16K - 1,
1277 .flags = IORESOURCE_MEM,
1278 },
1279 [1] = {
1280 .start = AT91SAM9263_ID_US1,
1281 .end = AT91SAM9263_ID_US1,
1282 .flags = IORESOURCE_IRQ,
1283 },
1284};
1285
1286static struct atmel_uart_data uart1_data = {
1287 .use_dma_tx = 1,
1288 .use_dma_rx = 1,
1289};
1290
1291static u64 uart1_dmamask = DMA_BIT_MASK(32);
1292
1293static struct platform_device at91sam9263_uart1_device = {
1294 .name = "atmel_usart",
1295 .id = 2,
1296 .dev = {
1297 .dma_mask = &uart1_dmamask,
1298 .coherent_dma_mask = DMA_BIT_MASK(32),
1299 .platform_data = &uart1_data,
1300 },
1301 .resource = uart1_resources,
1302 .num_resources = ARRAY_SIZE(uart1_resources),
1303};
1304
1305static inline void configure_usart1_pins(unsigned pins)
1306{
1307 at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
1308 at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */
1309
1310 if (pins & ATMEL_UART_RTS)
1311 at91_set_B_periph(AT91_PIN_PD7, 0); /* RTS1 */
1312 if (pins & ATMEL_UART_CTS)
1313 at91_set_B_periph(AT91_PIN_PD8, 0); /* CTS1 */
1314}
1315
1316static struct resource uart2_resources[] = {
1317 [0] = {
1318 .start = AT91SAM9263_BASE_US2,
1319 .end = AT91SAM9263_BASE_US2 + SZ_16K - 1,
1320 .flags = IORESOURCE_MEM,
1321 },
1322 [1] = {
1323 .start = AT91SAM9263_ID_US2,
1324 .end = AT91SAM9263_ID_US2,
1325 .flags = IORESOURCE_IRQ,
1326 },
1327};
1328
1329static struct atmel_uart_data uart2_data = {
1330 .use_dma_tx = 1,
1331 .use_dma_rx = 1,
1332};
1333
1334static u64 uart2_dmamask = DMA_BIT_MASK(32);
1335
1336static struct platform_device at91sam9263_uart2_device = {
1337 .name = "atmel_usart",
1338 .id = 3,
1339 .dev = {
1340 .dma_mask = &uart2_dmamask,
1341 .coherent_dma_mask = DMA_BIT_MASK(32),
1342 .platform_data = &uart2_data,
1343 },
1344 .resource = uart2_resources,
1345 .num_resources = ARRAY_SIZE(uart2_resources),
1346};
1347
1348static inline void configure_usart2_pins(unsigned pins)
1349{
1350 at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
1351 at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */
1352
1353 if (pins & ATMEL_UART_RTS)
1354 at91_set_B_periph(AT91_PIN_PD5, 0); /* RTS2 */
1355 if (pins & ATMEL_UART_CTS)
1356 at91_set_B_periph(AT91_PIN_PD6, 0); /* CTS2 */
1357}
1358
1359static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1360struct platform_device *atmel_default_console_device; /* the serial console device */
1361
1362void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1363{
1364 struct platform_device *pdev;
1365 struct atmel_uart_data *pdata;
1366
1367 switch (id) {
1368 case 0: /* DBGU */
1369 pdev = &at91sam9263_dbgu_device;
1370 configure_dbgu_pins();
1371 break;
1372 case AT91SAM9263_ID_US0:
1373 pdev = &at91sam9263_uart0_device;
1374 configure_usart0_pins(pins);
1375 break;
1376 case AT91SAM9263_ID_US1:
1377 pdev = &at91sam9263_uart1_device;
1378 configure_usart1_pins(pins);
1379 break;
1380 case AT91SAM9263_ID_US2:
1381 pdev = &at91sam9263_uart2_device;
1382 configure_usart2_pins(pins);
1383 break;
1384 default:
1385 return;
1386 }
1387 pdata = pdev->dev.platform_data;
1388 pdata->num = portnr; /* update to mapped ID */
1389
1390 if (portnr < ATMEL_MAX_UART)
1391 at91_uarts[portnr] = pdev;
1392}
1393
1394void __init at91_set_serial_console(unsigned portnr)
1395{
1396 if (portnr < ATMEL_MAX_UART) {
1397 atmel_default_console_device = at91_uarts[portnr];
1398 at91sam9263_set_console_clock(at91_uarts[portnr]->id);
1399 }
1400}
1401
1402void __init at91_add_device_serial(void)
1403{
1404 int i;
1405
1406 for (i = 0; i < ATMEL_MAX_UART; i++) {
1407 if (at91_uarts[i])
1408 platform_device_register(at91_uarts[i]);
1409 }
1410
1411 if (!atmel_default_console_device)
1412 printk(KERN_INFO "AT91: No default serial console defined.\n");
1413}
1414#else
1415void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1416void __init at91_set_serial_console(unsigned portnr) {}
1417void __init at91_add_device_serial(void) {}
1418#endif
1419
1420
1421/* -------------------------------------------------------------------- */
1422/*
1423 * These devices are always present and don't need any board-specific
1424 * setup.
1425 */
1426static int __init at91_add_standard_devices(void)
1427{
1428 at91_add_device_rtt();
1429 at91_add_device_watchdog();
1430 at91_add_device_tc();
1431 return 0;
1432}
1433
1434arch_initcall(at91_add_standard_devices);