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1/*
2 * arch/arm/mach-at91/at91sam9260.c
3 *
4 * Copyright (C) 2006 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12
13#include <linux/module.h>
14#include <linux/pm.h>
15
16#include <asm/irq.h>
17#include <asm/mach/arch.h>
18#include <asm/mach/map.h>
19#include <mach/cpu.h>
20#include <mach/at91_dbgu.h>
21#include <mach/at91sam9260.h>
22#include <mach/at91_pmc.h>
23#include <mach/at91_rstc.h>
24#include <mach/at91_shdwc.h>
25
26#include "soc.h"
27#include "generic.h"
28#include "clock.h"
29
30/* --------------------------------------------------------------------
31 * Clocks
32 * -------------------------------------------------------------------- */
33
34/*
35 * The peripheral clocks.
36 */
37static struct clk pioA_clk = {
38 .name = "pioA_clk",
39 .pmc_mask = 1 << AT91SAM9260_ID_PIOA,
40 .type = CLK_TYPE_PERIPHERAL,
41};
42static struct clk pioB_clk = {
43 .name = "pioB_clk",
44 .pmc_mask = 1 << AT91SAM9260_ID_PIOB,
45 .type = CLK_TYPE_PERIPHERAL,
46};
47static struct clk pioC_clk = {
48 .name = "pioC_clk",
49 .pmc_mask = 1 << AT91SAM9260_ID_PIOC,
50 .type = CLK_TYPE_PERIPHERAL,
51};
52static struct clk adc_clk = {
53 .name = "adc_clk",
54 .pmc_mask = 1 << AT91SAM9260_ID_ADC,
55 .type = CLK_TYPE_PERIPHERAL,
56};
57static struct clk usart0_clk = {
58 .name = "usart0_clk",
59 .pmc_mask = 1 << AT91SAM9260_ID_US0,
60 .type = CLK_TYPE_PERIPHERAL,
61};
62static struct clk usart1_clk = {
63 .name = "usart1_clk",
64 .pmc_mask = 1 << AT91SAM9260_ID_US1,
65 .type = CLK_TYPE_PERIPHERAL,
66};
67static struct clk usart2_clk = {
68 .name = "usart2_clk",
69 .pmc_mask = 1 << AT91SAM9260_ID_US2,
70 .type = CLK_TYPE_PERIPHERAL,
71};
72static struct clk mmc_clk = {
73 .name = "mci_clk",
74 .pmc_mask = 1 << AT91SAM9260_ID_MCI,
75 .type = CLK_TYPE_PERIPHERAL,
76};
77static struct clk udc_clk = {
78 .name = "udc_clk",
79 .pmc_mask = 1 << AT91SAM9260_ID_UDP,
80 .type = CLK_TYPE_PERIPHERAL,
81};
82static struct clk twi_clk = {
83 .name = "twi_clk",
84 .pmc_mask = 1 << AT91SAM9260_ID_TWI,
85 .type = CLK_TYPE_PERIPHERAL,
86};
87static struct clk spi0_clk = {
88 .name = "spi0_clk",
89 .pmc_mask = 1 << AT91SAM9260_ID_SPI0,
90 .type = CLK_TYPE_PERIPHERAL,
91};
92static struct clk spi1_clk = {
93 .name = "spi1_clk",
94 .pmc_mask = 1 << AT91SAM9260_ID_SPI1,
95 .type = CLK_TYPE_PERIPHERAL,
96};
97static struct clk ssc_clk = {
98 .name = "ssc_clk",
99 .pmc_mask = 1 << AT91SAM9260_ID_SSC,
100 .type = CLK_TYPE_PERIPHERAL,
101};
102static struct clk tc0_clk = {
103 .name = "tc0_clk",
104 .pmc_mask = 1 << AT91SAM9260_ID_TC0,
105 .type = CLK_TYPE_PERIPHERAL,
106};
107static struct clk tc1_clk = {
108 .name = "tc1_clk",
109 .pmc_mask = 1 << AT91SAM9260_ID_TC1,
110 .type = CLK_TYPE_PERIPHERAL,
111};
112static struct clk tc2_clk = {
113 .name = "tc2_clk",
114 .pmc_mask = 1 << AT91SAM9260_ID_TC2,
115 .type = CLK_TYPE_PERIPHERAL,
116};
117static struct clk ohci_clk = {
118 .name = "ohci_clk",
119 .pmc_mask = 1 << AT91SAM9260_ID_UHP,
120 .type = CLK_TYPE_PERIPHERAL,
121};
122static struct clk macb_clk = {
123 .name = "macb_clk",
124 .pmc_mask = 1 << AT91SAM9260_ID_EMAC,
125 .type = CLK_TYPE_PERIPHERAL,
126};
127static struct clk isi_clk = {
128 .name = "isi_clk",
129 .pmc_mask = 1 << AT91SAM9260_ID_ISI,
130 .type = CLK_TYPE_PERIPHERAL,
131};
132static struct clk usart3_clk = {
133 .name = "usart3_clk",
134 .pmc_mask = 1 << AT91SAM9260_ID_US3,
135 .type = CLK_TYPE_PERIPHERAL,
136};
137static struct clk usart4_clk = {
138 .name = "usart4_clk",
139 .pmc_mask = 1 << AT91SAM9260_ID_US4,
140 .type = CLK_TYPE_PERIPHERAL,
141};
142static struct clk usart5_clk = {
143 .name = "usart5_clk",
144 .pmc_mask = 1 << AT91SAM9260_ID_US5,
145 .type = CLK_TYPE_PERIPHERAL,
146};
147static struct clk tc3_clk = {
148 .name = "tc3_clk",
149 .pmc_mask = 1 << AT91SAM9260_ID_TC3,
150 .type = CLK_TYPE_PERIPHERAL,
151};
152static struct clk tc4_clk = {
153 .name = "tc4_clk",
154 .pmc_mask = 1 << AT91SAM9260_ID_TC4,
155 .type = CLK_TYPE_PERIPHERAL,
156};
157static struct clk tc5_clk = {
158 .name = "tc5_clk",
159 .pmc_mask = 1 << AT91SAM9260_ID_TC5,
160 .type = CLK_TYPE_PERIPHERAL,
161};
162
163static struct clk *periph_clocks[] __initdata = {
164 &pioA_clk,
165 &pioB_clk,
166 &pioC_clk,
167 &adc_clk,
168 &usart0_clk,
169 &usart1_clk,
170 &usart2_clk,
171 &mmc_clk,
172 &udc_clk,
173 &twi_clk,
174 &spi0_clk,
175 &spi1_clk,
176 &ssc_clk,
177 &tc0_clk,
178 &tc1_clk,
179 &tc2_clk,
180 &ohci_clk,
181 &macb_clk,
182 &isi_clk,
183 &usart3_clk,
184 &usart4_clk,
185 &usart5_clk,
186 &tc3_clk,
187 &tc4_clk,
188 &tc5_clk,
189 // irq0 .. irq2
190};
191
192static struct clk_lookup periph_clocks_lookups[] = {
193 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
194 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
195 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
196 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
197 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
198 CLKDEV_CON_DEV_ID("t3_clk", "atmel_tcb.1", &tc3_clk),
199 CLKDEV_CON_DEV_ID("t4_clk", "atmel_tcb.1", &tc4_clk),
200 CLKDEV_CON_DEV_ID("t5_clk", "atmel_tcb.1", &tc5_clk),
201 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk),
202};
203
204static struct clk_lookup usart_clocks_lookups[] = {
205 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
206 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
207 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
208 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
209 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
210 CLKDEV_CON_DEV_ID("usart", "atmel_usart.5", &usart4_clk),
211 CLKDEV_CON_DEV_ID("usart", "atmel_usart.6", &usart5_clk),
212};
213
214/*
215 * The two programmable clocks.
216 * You must configure pin multiplexing to bring these signals out.
217 */
218static struct clk pck0 = {
219 .name = "pck0",
220 .pmc_mask = AT91_PMC_PCK0,
221 .type = CLK_TYPE_PROGRAMMABLE,
222 .id = 0,
223};
224static struct clk pck1 = {
225 .name = "pck1",
226 .pmc_mask = AT91_PMC_PCK1,
227 .type = CLK_TYPE_PROGRAMMABLE,
228 .id = 1,
229};
230
231static void __init at91sam9260_register_clocks(void)
232{
233 int i;
234
235 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
236 clk_register(periph_clocks[i]);
237
238 clkdev_add_table(periph_clocks_lookups,
239 ARRAY_SIZE(periph_clocks_lookups));
240 clkdev_add_table(usart_clocks_lookups,
241 ARRAY_SIZE(usart_clocks_lookups));
242
243 clk_register(&pck0);
244 clk_register(&pck1);
245}
246
247static struct clk_lookup console_clock_lookup;
248
249void __init at91sam9260_set_console_clock(int id)
250{
251 if (id >= ARRAY_SIZE(usart_clocks_lookups))
252 return;
253
254 console_clock_lookup.con_id = "usart";
255 console_clock_lookup.clk = usart_clocks_lookups[id].clk;
256 clkdev_add(&console_clock_lookup);
257}
258
259/* --------------------------------------------------------------------
260 * GPIO
261 * -------------------------------------------------------------------- */
262
263static struct at91_gpio_bank at91sam9260_gpio[] = {
264 {
265 .id = AT91SAM9260_ID_PIOA,
266 .offset = AT91_PIOA,
267 .clock = &pioA_clk,
268 }, {
269 .id = AT91SAM9260_ID_PIOB,
270 .offset = AT91_PIOB,
271 .clock = &pioB_clk,
272 }, {
273 .id = AT91SAM9260_ID_PIOC,
274 .offset = AT91_PIOC,
275 .clock = &pioC_clk,
276 }
277};
278
279static void at91sam9260_poweroff(void)
280{
281 at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
282}
283
284
285/* --------------------------------------------------------------------
286 * AT91SAM9260 processor initialization
287 * -------------------------------------------------------------------- */
288
289static void __init at91sam9xe_map_io(void)
290{
291 unsigned long sram_size;
292
293 switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
294 case AT91_CIDR_SRAMSIZ_32K:
295 sram_size = 2 * SZ_16K;
296 break;
297 case AT91_CIDR_SRAMSIZ_16K:
298 default:
299 sram_size = SZ_16K;
300 }
301
302 at91_init_sram(0, AT91SAM9XE_SRAM_BASE, sram_size);
303}
304
305static void __init at91sam9260_map_io(void)
306{
307 if (cpu_is_at91sam9xe()) {
308 at91sam9xe_map_io();
309 } else if (cpu_is_at91sam9g20()) {
310 at91_init_sram(0, AT91SAM9G20_SRAM0_BASE, AT91SAM9G20_SRAM0_SIZE);
311 at91_init_sram(1, AT91SAM9G20_SRAM1_BASE, AT91SAM9G20_SRAM1_SIZE);
312 } else {
313 at91_init_sram(0, AT91SAM9260_SRAM0_BASE, AT91SAM9260_SRAM0_SIZE);
314 at91_init_sram(1, AT91SAM9260_SRAM1_BASE, AT91SAM9260_SRAM1_SIZE);
315 }
316}
317
318static void __init at91sam9260_initialize(void)
319{
320 at91_arch_reset = at91sam9_alt_reset;
321 pm_power_off = at91sam9260_poweroff;
322 at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
323 | (1 << AT91SAM9260_ID_IRQ2);
324
325 /* Register GPIO subsystem */
326 at91_gpio_init(at91sam9260_gpio, 3);
327}
328
329/* --------------------------------------------------------------------
330 * Interrupt initialization
331 * -------------------------------------------------------------------- */
332
333/*
334 * The default interrupt priority levels (0 = lowest, 7 = highest).
335 */
336static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
337 7, /* Advanced Interrupt Controller */
338 7, /* System Peripherals */
339 1, /* Parallel IO Controller A */
340 1, /* Parallel IO Controller B */
341 1, /* Parallel IO Controller C */
342 0, /* Analog-to-Digital Converter */
343 5, /* USART 0 */
344 5, /* USART 1 */
345 5, /* USART 2 */
346 0, /* Multimedia Card Interface */
347 2, /* USB Device Port */
348 6, /* Two-Wire Interface */
349 5, /* Serial Peripheral Interface 0 */
350 5, /* Serial Peripheral Interface 1 */
351 5, /* Serial Synchronous Controller */
352 0,
353 0,
354 0, /* Timer Counter 0 */
355 0, /* Timer Counter 1 */
356 0, /* Timer Counter 2 */
357 2, /* USB Host port */
358 3, /* Ethernet */
359 0, /* Image Sensor Interface */
360 5, /* USART 3 */
361 5, /* USART 4 */
362 5, /* USART 5 */
363 0, /* Timer Counter 3 */
364 0, /* Timer Counter 4 */
365 0, /* Timer Counter 5 */
366 0, /* Advanced Interrupt Controller */
367 0, /* Advanced Interrupt Controller */
368 0, /* Advanced Interrupt Controller */
369};
370
371struct at91_init_soc __initdata at91sam9260_soc = {
372 .map_io = at91sam9260_map_io,
373 .default_irq_priority = at91sam9260_default_irq_priority,
374 .register_clocks = at91sam9260_register_clocks,
375 .init = at91sam9260_initialize,
376};