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1/*
2 * arch/arm/mach-at91/at91cap9.c
3 *
4 * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
5 * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
6 * Copyright (C) 2007 Atmel Corporation.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 */
14
15#include <linux/module.h>
16#include <linux/pm.h>
17
18#include <asm/irq.h>
19#include <asm/mach/arch.h>
20#include <asm/mach/map.h>
21
22#include <mach/cpu.h>
23#include <mach/at91cap9.h>
24#include <mach/at91_pmc.h>
25#include <mach/at91_rstc.h>
26#include <mach/at91_shdwc.h>
27
28#include "soc.h"
29#include "generic.h"
30#include "clock.h"
31
32/* --------------------------------------------------------------------
33 * Clocks
34 * -------------------------------------------------------------------- */
35
36/*
37 * The peripheral clocks.
38 */
39static struct clk pioABCD_clk = {
40 .name = "pioABCD_clk",
41 .pmc_mask = 1 << AT91CAP9_ID_PIOABCD,
42 .type = CLK_TYPE_PERIPHERAL,
43};
44static struct clk mpb0_clk = {
45 .name = "mpb0_clk",
46 .pmc_mask = 1 << AT91CAP9_ID_MPB0,
47 .type = CLK_TYPE_PERIPHERAL,
48};
49static struct clk mpb1_clk = {
50 .name = "mpb1_clk",
51 .pmc_mask = 1 << AT91CAP9_ID_MPB1,
52 .type = CLK_TYPE_PERIPHERAL,
53};
54static struct clk mpb2_clk = {
55 .name = "mpb2_clk",
56 .pmc_mask = 1 << AT91CAP9_ID_MPB2,
57 .type = CLK_TYPE_PERIPHERAL,
58};
59static struct clk mpb3_clk = {
60 .name = "mpb3_clk",
61 .pmc_mask = 1 << AT91CAP9_ID_MPB3,
62 .type = CLK_TYPE_PERIPHERAL,
63};
64static struct clk mpb4_clk = {
65 .name = "mpb4_clk",
66 .pmc_mask = 1 << AT91CAP9_ID_MPB4,
67 .type = CLK_TYPE_PERIPHERAL,
68};
69static struct clk usart0_clk = {
70 .name = "usart0_clk",
71 .pmc_mask = 1 << AT91CAP9_ID_US0,
72 .type = CLK_TYPE_PERIPHERAL,
73};
74static struct clk usart1_clk = {
75 .name = "usart1_clk",
76 .pmc_mask = 1 << AT91CAP9_ID_US1,
77 .type = CLK_TYPE_PERIPHERAL,
78};
79static struct clk usart2_clk = {
80 .name = "usart2_clk",
81 .pmc_mask = 1 << AT91CAP9_ID_US2,
82 .type = CLK_TYPE_PERIPHERAL,
83};
84static struct clk mmc0_clk = {
85 .name = "mci0_clk",
86 .pmc_mask = 1 << AT91CAP9_ID_MCI0,
87 .type = CLK_TYPE_PERIPHERAL,
88};
89static struct clk mmc1_clk = {
90 .name = "mci1_clk",
91 .pmc_mask = 1 << AT91CAP9_ID_MCI1,
92 .type = CLK_TYPE_PERIPHERAL,
93};
94static struct clk can_clk = {
95 .name = "can_clk",
96 .pmc_mask = 1 << AT91CAP9_ID_CAN,
97 .type = CLK_TYPE_PERIPHERAL,
98};
99static struct clk twi_clk = {
100 .name = "twi_clk",
101 .pmc_mask = 1 << AT91CAP9_ID_TWI,
102 .type = CLK_TYPE_PERIPHERAL,
103};
104static struct clk spi0_clk = {
105 .name = "spi0_clk",
106 .pmc_mask = 1 << AT91CAP9_ID_SPI0,
107 .type = CLK_TYPE_PERIPHERAL,
108};
109static struct clk spi1_clk = {
110 .name = "spi1_clk",
111 .pmc_mask = 1 << AT91CAP9_ID_SPI1,
112 .type = CLK_TYPE_PERIPHERAL,
113};
114static struct clk ssc0_clk = {
115 .name = "ssc0_clk",
116 .pmc_mask = 1 << AT91CAP9_ID_SSC0,
117 .type = CLK_TYPE_PERIPHERAL,
118};
119static struct clk ssc1_clk = {
120 .name = "ssc1_clk",
121 .pmc_mask = 1 << AT91CAP9_ID_SSC1,
122 .type = CLK_TYPE_PERIPHERAL,
123};
124static struct clk ac97_clk = {
125 .name = "ac97_clk",
126 .pmc_mask = 1 << AT91CAP9_ID_AC97C,
127 .type = CLK_TYPE_PERIPHERAL,
128};
129static struct clk tcb_clk = {
130 .name = "tcb_clk",
131 .pmc_mask = 1 << AT91CAP9_ID_TCB,
132 .type = CLK_TYPE_PERIPHERAL,
133};
134static struct clk pwm_clk = {
135 .name = "pwm_clk",
136 .pmc_mask = 1 << AT91CAP9_ID_PWMC,
137 .type = CLK_TYPE_PERIPHERAL,
138};
139static struct clk macb_clk = {
140 .name = "macb_clk",
141 .pmc_mask = 1 << AT91CAP9_ID_EMAC,
142 .type = CLK_TYPE_PERIPHERAL,
143};
144static struct clk aestdes_clk = {
145 .name = "aestdes_clk",
146 .pmc_mask = 1 << AT91CAP9_ID_AESTDES,
147 .type = CLK_TYPE_PERIPHERAL,
148};
149static struct clk adc_clk = {
150 .name = "adc_clk",
151 .pmc_mask = 1 << AT91CAP9_ID_ADC,
152 .type = CLK_TYPE_PERIPHERAL,
153};
154static struct clk isi_clk = {
155 .name = "isi_clk",
156 .pmc_mask = 1 << AT91CAP9_ID_ISI,
157 .type = CLK_TYPE_PERIPHERAL,
158};
159static struct clk lcdc_clk = {
160 .name = "lcdc_clk",
161 .pmc_mask = 1 << AT91CAP9_ID_LCDC,
162 .type = CLK_TYPE_PERIPHERAL,
163};
164static struct clk dma_clk = {
165 .name = "dma_clk",
166 .pmc_mask = 1 << AT91CAP9_ID_DMA,
167 .type = CLK_TYPE_PERIPHERAL,
168};
169static struct clk udphs_clk = {
170 .name = "udphs_clk",
171 .pmc_mask = 1 << AT91CAP9_ID_UDPHS,
172 .type = CLK_TYPE_PERIPHERAL,
173};
174static struct clk ohci_clk = {
175 .name = "ohci_clk",
176 .pmc_mask = 1 << AT91CAP9_ID_UHP,
177 .type = CLK_TYPE_PERIPHERAL,
178};
179
180static struct clk *periph_clocks[] __initdata = {
181 &pioABCD_clk,
182 &mpb0_clk,
183 &mpb1_clk,
184 &mpb2_clk,
185 &mpb3_clk,
186 &mpb4_clk,
187 &usart0_clk,
188 &usart1_clk,
189 &usart2_clk,
190 &mmc0_clk,
191 &mmc1_clk,
192 &can_clk,
193 &twi_clk,
194 &spi0_clk,
195 &spi1_clk,
196 &ssc0_clk,
197 &ssc1_clk,
198 &ac97_clk,
199 &tcb_clk,
200 &pwm_clk,
201 &macb_clk,
202 &aestdes_clk,
203 &adc_clk,
204 &isi_clk,
205 &lcdc_clk,
206 &dma_clk,
207 &udphs_clk,
208 &ohci_clk,
209 // irq0 .. irq1
210};
211
212static struct clk_lookup periph_clocks_lookups[] = {
213 CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
214 CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
215 CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
216 CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk),
217 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
218 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
219 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
220 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
221 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
222};
223
224static struct clk_lookup usart_clocks_lookups[] = {
225 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
226 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
227 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
228 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
229};
230
231/*
232 * The four programmable clocks.
233 * You must configure pin multiplexing to bring these signals out.
234 */
235static struct clk pck0 = {
236 .name = "pck0",
237 .pmc_mask = AT91_PMC_PCK0,
238 .type = CLK_TYPE_PROGRAMMABLE,
239 .id = 0,
240};
241static struct clk pck1 = {
242 .name = "pck1",
243 .pmc_mask = AT91_PMC_PCK1,
244 .type = CLK_TYPE_PROGRAMMABLE,
245 .id = 1,
246};
247static struct clk pck2 = {
248 .name = "pck2",
249 .pmc_mask = AT91_PMC_PCK2,
250 .type = CLK_TYPE_PROGRAMMABLE,
251 .id = 2,
252};
253static struct clk pck3 = {
254 .name = "pck3",
255 .pmc_mask = AT91_PMC_PCK3,
256 .type = CLK_TYPE_PROGRAMMABLE,
257 .id = 3,
258};
259
260static void __init at91cap9_register_clocks(void)
261{
262 int i;
263
264 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
265 clk_register(periph_clocks[i]);
266
267 clkdev_add_table(periph_clocks_lookups,
268 ARRAY_SIZE(periph_clocks_lookups));
269 clkdev_add_table(usart_clocks_lookups,
270 ARRAY_SIZE(usart_clocks_lookups));
271
272 clk_register(&pck0);
273 clk_register(&pck1);
274 clk_register(&pck2);
275 clk_register(&pck3);
276}
277
278static struct clk_lookup console_clock_lookup;
279
280void __init at91cap9_set_console_clock(int id)
281{
282 if (id >= ARRAY_SIZE(usart_clocks_lookups))
283 return;
284
285 console_clock_lookup.con_id = "usart";
286 console_clock_lookup.clk = usart_clocks_lookups[id].clk;
287 clkdev_add(&console_clock_lookup);
288}
289
290/* --------------------------------------------------------------------
291 * GPIO
292 * -------------------------------------------------------------------- */
293
294static struct at91_gpio_bank at91cap9_gpio[] = {
295 {
296 .id = AT91CAP9_ID_PIOABCD,
297 .offset = AT91_PIOA,
298 .clock = &pioABCD_clk,
299 }, {
300 .id = AT91CAP9_ID_PIOABCD,
301 .offset = AT91_PIOB,
302 .clock = &pioABCD_clk,
303 }, {
304 .id = AT91CAP9_ID_PIOABCD,
305 .offset = AT91_PIOC,
306 .clock = &pioABCD_clk,
307 }, {
308 .id = AT91CAP9_ID_PIOABCD,
309 .offset = AT91_PIOD,
310 .clock = &pioABCD_clk,
311 }
312};
313
314static void at91cap9_reset(void)
315{
316 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
317}
318
319static void at91cap9_poweroff(void)
320{
321 at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
322}
323
324
325/* --------------------------------------------------------------------
326 * AT91CAP9 processor initialization
327 * -------------------------------------------------------------------- */
328
329static void __init at91cap9_map_io(void)
330{
331 at91_init_sram(0, AT91CAP9_SRAM_BASE, AT91CAP9_SRAM_SIZE);
332}
333
334static void __init at91cap9_initialize(void)
335{
336 at91_arch_reset = at91cap9_reset;
337 pm_power_off = at91cap9_poweroff;
338 at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
339
340 /* Register GPIO subsystem */
341 at91_gpio_init(at91cap9_gpio, 4);
342
343 /* Remember the silicon revision */
344 if (cpu_is_at91cap9_revB())
345 system_rev = 0xB;
346 else if (cpu_is_at91cap9_revC())
347 system_rev = 0xC;
348}
349
350/* --------------------------------------------------------------------
351 * Interrupt initialization
352 * -------------------------------------------------------------------- */
353
354/*
355 * The default interrupt priority levels (0 = lowest, 7 = highest).
356 */
357static unsigned int at91cap9_default_irq_priority[NR_AIC_IRQS] __initdata = {
358 7, /* Advanced Interrupt Controller (FIQ) */
359 7, /* System Peripherals */
360 1, /* Parallel IO Controller A, B, C and D */
361 0, /* MP Block Peripheral 0 */
362 0, /* MP Block Peripheral 1 */
363 0, /* MP Block Peripheral 2 */
364 0, /* MP Block Peripheral 3 */
365 0, /* MP Block Peripheral 4 */
366 5, /* USART 0 */
367 5, /* USART 1 */
368 5, /* USART 2 */
369 0, /* Multimedia Card Interface 0 */
370 0, /* Multimedia Card Interface 1 */
371 3, /* CAN */
372 6, /* Two-Wire Interface */
373 5, /* Serial Peripheral Interface 0 */
374 5, /* Serial Peripheral Interface 1 */
375 4, /* Serial Synchronous Controller 0 */
376 4, /* Serial Synchronous Controller 1 */
377 5, /* AC97 Controller */
378 0, /* Timer Counter 0, 1 and 2 */
379 0, /* Pulse Width Modulation Controller */
380 3, /* Ethernet */
381 0, /* Advanced Encryption Standard, Triple DES*/
382 0, /* Analog-to-Digital Converter */
383 0, /* Image Sensor Interface */
384 3, /* LCD Controller */
385 0, /* DMA Controller */
386 2, /* USB Device Port */
387 2, /* USB Host port */
388 0, /* Advanced Interrupt Controller (IRQ0) */
389 0, /* Advanced Interrupt Controller (IRQ1) */
390};
391
392struct at91_init_soc __initdata at91cap9_soc = {
393 .map_io = at91cap9_map_io,
394 .default_irq_priority = at91cap9_default_irq_priority,
395 .register_clocks = at91cap9_register_clocks,
396 .init = at91cap9_initialize,
397};