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1// SPDX-License-Identifier: GPL-2.0
2//
3// Copyright 2015 Freescale Semiconductor, Inc.
4
5#include <dt-bindings/clock/imx6ul-clock.h>
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/input.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include "imx6ul-pinfunc.h"
10
11/ {
12 #address-cells = <1>;
13 #size-cells = <1>;
14 /*
15 * The decompressor and also some bootloaders rely on a
16 * pre-existing /chosen node to be available to insert the
17 * command line and merge other ATAGS info.
18 */
19 chosen {};
20
21 aliases {
22 ethernet0 = &fec1;
23 ethernet1 = &fec2;
24 gpio0 = &gpio1;
25 gpio1 = &gpio2;
26 gpio2 = &gpio3;
27 gpio3 = &gpio4;
28 gpio4 = &gpio5;
29 i2c0 = &i2c1;
30 i2c1 = &i2c2;
31 i2c2 = &i2c3;
32 i2c3 = &i2c4;
33 mmc0 = &usdhc1;
34 mmc1 = &usdhc2;
35 serial0 = &uart1;
36 serial1 = &uart2;
37 serial2 = &uart3;
38 serial3 = &uart4;
39 serial4 = &uart5;
40 serial5 = &uart6;
41 serial6 = &uart7;
42 serial7 = &uart8;
43 sai1 = &sai1;
44 sai2 = &sai2;
45 sai3 = &sai3;
46 spi0 = &ecspi1;
47 spi1 = &ecspi2;
48 spi2 = &ecspi3;
49 spi3 = &ecspi4;
50 usb0 = &usbotg1;
51 usb1 = &usbotg2;
52 usbphy0 = &usbphy1;
53 usbphy1 = &usbphy2;
54 };
55
56 cpus {
57 #address-cells = <1>;
58 #size-cells = <0>;
59
60 cpu0: cpu@0 {
61 compatible = "arm,cortex-a7";
62 device_type = "cpu";
63 reg = <0>;
64 clock-frequency = <696000000>;
65 clock-latency = <61036>; /* two CLK32 periods */
66 #cooling-cells = <2>;
67 operating-points =
68 /* kHz uV */
69 <696000 1275000>,
70 <528000 1175000>,
71 <396000 1025000>,
72 <198000 950000>;
73 fsl,soc-operating-points =
74 /* KHz uV */
75 <696000 1275000>,
76 <528000 1175000>,
77 <396000 1175000>,
78 <198000 1175000>;
79 clocks = <&clks IMX6UL_CLK_ARM>,
80 <&clks IMX6UL_CLK_PLL2_BUS>,
81 <&clks IMX6UL_CLK_PLL2_PFD2>,
82 <&clks IMX6UL_CA7_SECONDARY_SEL>,
83 <&clks IMX6UL_CLK_STEP>,
84 <&clks IMX6UL_CLK_PLL1_SW>,
85 <&clks IMX6UL_CLK_PLL1_SYS>;
86 clock-names = "arm", "pll2_bus", "pll2_pfd2_396m",
87 "secondary_sel", "step", "pll1_sw",
88 "pll1_sys";
89 arm-supply = <®_arm>;
90 soc-supply = <®_soc>;
91 nvmem-cells = <&cpu_speed_grade>;
92 nvmem-cell-names = "speed_grade";
93 };
94 };
95
96 timer {
97 compatible = "arm,armv7-timer";
98 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
99 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
100 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
101 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
102 interrupt-parent = <&intc>;
103 status = "disabled";
104 };
105
106 ckil: clock-cli {
107 compatible = "fixed-clock";
108 #clock-cells = <0>;
109 clock-frequency = <32768>;
110 clock-output-names = "ckil";
111 };
112
113 osc: clock-osc {
114 compatible = "fixed-clock";
115 #clock-cells = <0>;
116 clock-frequency = <24000000>;
117 clock-output-names = "osc";
118 };
119
120 ipp_di0: clock-di0 {
121 compatible = "fixed-clock";
122 #clock-cells = <0>;
123 clock-frequency = <0>;
124 clock-output-names = "ipp_di0";
125 };
126
127 ipp_di1: clock-di1 {
128 compatible = "fixed-clock";
129 #clock-cells = <0>;
130 clock-frequency = <0>;
131 clock-output-names = "ipp_di1";
132 };
133
134 pmu {
135 compatible = "arm,cortex-a7-pmu";
136 interrupt-parent = <&gpc>;
137 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
138 };
139
140 soc: soc {
141 #address-cells = <1>;
142 #size-cells = <1>;
143 compatible = "simple-bus";
144 interrupt-parent = <&gpc>;
145 ranges;
146
147 ocram: sram@900000 {
148 compatible = "mmio-sram";
149 reg = <0x00900000 0x20000>;
150 ranges = <0 0x00900000 0x20000>;
151 #address-cells = <1>;
152 #size-cells = <1>;
153 };
154
155 intc: interrupt-controller@a01000 {
156 compatible = "arm,gic-400", "arm,cortex-a7-gic";
157 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
158 #interrupt-cells = <3>;
159 interrupt-controller;
160 interrupt-parent = <&intc>;
161 reg = <0x00a01000 0x1000>,
162 <0x00a02000 0x2000>,
163 <0x00a04000 0x2000>,
164 <0x00a06000 0x2000>;
165 };
166
167 dma_apbh: dma-controller@1804000 {
168 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
169 reg = <0x01804000 0x2000>;
170 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
171 <0 13 IRQ_TYPE_LEVEL_HIGH>,
172 <0 13 IRQ_TYPE_LEVEL_HIGH>,
173 <0 13 IRQ_TYPE_LEVEL_HIGH>;
174 #dma-cells = <1>;
175 dma-channels = <4>;
176 clocks = <&clks IMX6UL_CLK_APBHDMA>;
177 };
178
179 gpmi: nand-controller@1806000 {
180 compatible = "fsl,imx6q-gpmi-nand";
181 #address-cells = <1>;
182 #size-cells = <0>;
183 reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
184 reg-names = "gpmi-nand", "bch";
185 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
186 interrupt-names = "bch";
187 clocks = <&clks IMX6UL_CLK_GPMI_IO>,
188 <&clks IMX6UL_CLK_GPMI_APB>,
189 <&clks IMX6UL_CLK_GPMI_BCH>,
190 <&clks IMX6UL_CLK_GPMI_BCH_APB>,
191 <&clks IMX6UL_CLK_PER_BCH>;
192 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
193 "gpmi_bch_apb", "per1_bch";
194 dmas = <&dma_apbh 0>;
195 dma-names = "rx-tx";
196 status = "disabled";
197 };
198
199 aips1: bus@2000000 {
200 compatible = "fsl,aips-bus", "simple-bus";
201 #address-cells = <1>;
202 #size-cells = <1>;
203 reg = <0x02000000 0x100000>;
204 ranges;
205
206 spba-bus@2000000 {
207 compatible = "fsl,spba-bus", "simple-bus";
208 #address-cells = <1>;
209 #size-cells = <1>;
210 reg = <0x02000000 0x40000>;
211 ranges;
212
213 ecspi1: spi@2008000 {
214 #address-cells = <1>;
215 #size-cells = <0>;
216 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
217 reg = <0x02008000 0x4000>;
218 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&clks IMX6UL_CLK_ECSPI1>,
220 <&clks IMX6UL_CLK_ECSPI1>;
221 clock-names = "ipg", "per";
222 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
223 dma-names = "rx", "tx";
224 status = "disabled";
225 };
226
227 ecspi2: spi@200c000 {
228 #address-cells = <1>;
229 #size-cells = <0>;
230 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
231 reg = <0x0200c000 0x4000>;
232 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&clks IMX6UL_CLK_ECSPI2>,
234 <&clks IMX6UL_CLK_ECSPI2>;
235 clock-names = "ipg", "per";
236 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
237 dma-names = "rx", "tx";
238 status = "disabled";
239 };
240
241 ecspi3: spi@2010000 {
242 #address-cells = <1>;
243 #size-cells = <0>;
244 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
245 reg = <0x02010000 0x4000>;
246 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
247 clocks = <&clks IMX6UL_CLK_ECSPI3>,
248 <&clks IMX6UL_CLK_ECSPI3>;
249 clock-names = "ipg", "per";
250 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
251 dma-names = "rx", "tx";
252 status = "disabled";
253 };
254
255 ecspi4: spi@2014000 {
256 #address-cells = <1>;
257 #size-cells = <0>;
258 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
259 reg = <0x02014000 0x4000>;
260 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
261 clocks = <&clks IMX6UL_CLK_ECSPI4>,
262 <&clks IMX6UL_CLK_ECSPI4>;
263 clock-names = "ipg", "per";
264 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
265 dma-names = "rx", "tx";
266 status = "disabled";
267 };
268
269 uart7: serial@2018000 {
270 compatible = "fsl,imx6ul-uart",
271 "fsl,imx6q-uart";
272 reg = <0x02018000 0x4000>;
273 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
274 clocks = <&clks IMX6UL_CLK_UART7_IPG>,
275 <&clks IMX6UL_CLK_UART7_SERIAL>;
276 clock-names = "ipg", "per";
277 dmas = <&sdma 43 4 0>, <&sdma 44 4 0>;
278 dma-names = "rx", "tx";
279 status = "disabled";
280 };
281
282 uart1: serial@2020000 {
283 compatible = "fsl,imx6ul-uart",
284 "fsl,imx6q-uart";
285 reg = <0x02020000 0x4000>;
286 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
287 clocks = <&clks IMX6UL_CLK_UART1_IPG>,
288 <&clks IMX6UL_CLK_UART1_SERIAL>;
289 clock-names = "ipg", "per";
290 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
291 dma-names = "rx", "tx";
292 status = "disabled";
293 };
294
295 uart8: serial@2024000 {
296 compatible = "fsl,imx6ul-uart",
297 "fsl,imx6q-uart";
298 reg = <0x02024000 0x4000>;
299 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
300 clocks = <&clks IMX6UL_CLK_UART8_IPG>,
301 <&clks IMX6UL_CLK_UART8_SERIAL>;
302 clock-names = "ipg", "per";
303 dmas = <&sdma 45 4 0>, <&sdma 46 4 0>;
304 dma-names = "rx", "tx";
305 status = "disabled";
306 };
307
308 sai1: sai@2028000 {
309 #sound-dai-cells = <0>;
310 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
311 reg = <0x02028000 0x4000>;
312 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
314 <&clks IMX6UL_CLK_SAI1>,
315 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
316 clock-names = "bus", "mclk1", "mclk2", "mclk3";
317 dmas = <&sdma 35 24 0>,
318 <&sdma 36 24 0>;
319 dma-names = "rx", "tx";
320 status = "disabled";
321 };
322
323 sai2: sai@202c000 {
324 #sound-dai-cells = <0>;
325 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
326 reg = <0x0202c000 0x4000>;
327 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
329 <&clks IMX6UL_CLK_SAI2>,
330 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
331 clock-names = "bus", "mclk1", "mclk2", "mclk3";
332 dmas = <&sdma 37 24 0>,
333 <&sdma 38 24 0>;
334 dma-names = "rx", "tx";
335 status = "disabled";
336 };
337
338 sai3: sai@2030000 {
339 #sound-dai-cells = <0>;
340 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
341 reg = <0x02030000 0x4000>;
342 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
343 clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
344 <&clks IMX6UL_CLK_SAI3>,
345 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
346 clock-names = "bus", "mclk1", "mclk2", "mclk3";
347 dmas = <&sdma 39 24 0>,
348 <&sdma 40 24 0>;
349 dma-names = "rx", "tx";
350 status = "disabled";
351 };
352
353 asrc: asrc@2034000 {
354 compatible = "fsl,imx6ul-asrc", "fsl,imx53-asrc";
355 reg = <0x2034000 0x4000>;
356 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&clks IMX6UL_CLK_ASRC_IPG>,
358 <&clks IMX6UL_CLK_ASRC_MEM>, <&clks 0>,
359 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
360 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
361 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
362 <&clks IMX6UL_CLK_SPDIF>, <&clks 0>, <&clks 0>,
363 <&clks IMX6UL_CLK_SPBA>;
364 clock-names = "mem", "ipg", "asrck_0",
365 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
366 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
367 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
368 "asrck_d", "asrck_e", "asrck_f", "spba";
369 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
370 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
371 dma-names = "rxa", "rxb", "rxc",
372 "txa", "txb", "txc";
373 fsl,asrc-rate = <48000>;
374 fsl,asrc-width = <16>;
375 status = "okay";
376 };
377 };
378
379 tsc: touchscreen@2040000 {
380 compatible = "fsl,imx6ul-tsc";
381 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
382 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
383 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
384 clocks = <&clks IMX6UL_CLK_IPG>,
385 <&clks IMX6UL_CLK_ADC2>;
386 clock-names = "tsc", "adc";
387 status = "disabled";
388 };
389
390 pwm1: pwm@2080000 {
391 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
392 reg = <0x02080000 0x4000>;
393 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
394 clocks = <&clks IMX6UL_CLK_PWM1>,
395 <&clks IMX6UL_CLK_PWM1>;
396 clock-names = "ipg", "per";
397 #pwm-cells = <3>;
398 status = "disabled";
399 };
400
401 pwm2: pwm@2084000 {
402 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
403 reg = <0x02084000 0x4000>;
404 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&clks IMX6UL_CLK_PWM2>,
406 <&clks IMX6UL_CLK_PWM2>;
407 clock-names = "ipg", "per";
408 #pwm-cells = <3>;
409 status = "disabled";
410 };
411
412 pwm3: pwm@2088000 {
413 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
414 reg = <0x02088000 0x4000>;
415 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
416 clocks = <&clks IMX6UL_CLK_PWM3>,
417 <&clks IMX6UL_CLK_PWM3>;
418 clock-names = "ipg", "per";
419 #pwm-cells = <3>;
420 status = "disabled";
421 };
422
423 pwm4: pwm@208c000 {
424 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
425 reg = <0x0208c000 0x4000>;
426 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
427 clocks = <&clks IMX6UL_CLK_PWM4>,
428 <&clks IMX6UL_CLK_PWM4>;
429 clock-names = "ipg", "per";
430 #pwm-cells = <3>;
431 status = "disabled";
432 };
433
434 can1: can@2090000 {
435 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
436 reg = <0x02090000 0x4000>;
437 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
439 <&clks IMX6UL_CLK_CAN1_SERIAL>;
440 clock-names = "ipg", "per";
441 fsl,stop-mode = <&gpr 0x10 1>;
442 status = "disabled";
443 };
444
445 can2: can@2094000 {
446 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
447 reg = <0x02094000 0x4000>;
448 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
449 clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
450 <&clks IMX6UL_CLK_CAN2_SERIAL>;
451 clock-names = "ipg", "per";
452 fsl,stop-mode = <&gpr 0x10 2>;
453 status = "disabled";
454 };
455
456 gpt1: timer@2098000 {
457 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
458 reg = <0x02098000 0x4000>;
459 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
461 <&clks IMX6UL_CLK_GPT1_SERIAL>;
462 clock-names = "ipg", "per";
463 };
464
465 gpio1: gpio@209c000 {
466 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
467 reg = <0x0209c000 0x4000>;
468 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
469 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
470 clocks = <&clks IMX6UL_CLK_GPIO1>;
471 gpio-controller;
472 #gpio-cells = <2>;
473 interrupt-controller;
474 #interrupt-cells = <2>;
475 gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>,
476 <&iomuxc 16 33 16>;
477 };
478
479 gpio2: gpio@20a0000 {
480 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
481 reg = <0x020a0000 0x4000>;
482 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
483 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
484 clocks = <&clks IMX6UL_CLK_GPIO2>;
485 gpio-controller;
486 #gpio-cells = <2>;
487 interrupt-controller;
488 #interrupt-cells = <2>;
489 gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>;
490 };
491
492 gpio3: gpio@20a4000 {
493 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
494 reg = <0x020a4000 0x4000>;
495 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
496 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
497 clocks = <&clks IMX6UL_CLK_GPIO3>;
498 gpio-controller;
499 #gpio-cells = <2>;
500 interrupt-controller;
501 #interrupt-cells = <2>;
502 gpio-ranges = <&iomuxc 0 65 29>;
503 };
504
505 gpio4: gpio@20a8000 {
506 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
507 reg = <0x020a8000 0x4000>;
508 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
510 clocks = <&clks IMX6UL_CLK_GPIO4>;
511 gpio-controller;
512 #gpio-cells = <2>;
513 interrupt-controller;
514 #interrupt-cells = <2>;
515 gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
516 };
517
518 gpio5: gpio@20ac000 {
519 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
520 reg = <0x020ac000 0x4000>;
521 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
522 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
523 clocks = <&clks IMX6UL_CLK_GPIO5>;
524 gpio-controller;
525 #gpio-cells = <2>;
526 interrupt-controller;
527 #interrupt-cells = <2>;
528 gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
529 };
530
531 fec2: ethernet@20b4000 {
532 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
533 reg = <0x020b4000 0x4000>;
534 interrupt-names = "int0", "pps";
535 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
536 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
537 clocks = <&clks IMX6UL_CLK_ENET>,
538 <&clks IMX6UL_CLK_ENET_AHB>,
539 <&clks IMX6UL_CLK_ENET_PTP>,
540 <&clks IMX6UL_CLK_ENET2_REF_SEL>;
541 clock-names = "ipg", "ahb", "ptp",
542 "enet_clk_ref";
543 fsl,num-tx-queues = <1>;
544 fsl,num-rx-queues = <1>;
545 fsl,stop-mode = <&gpr 0x10 4>;
546 fsl,magic-packet;
547 nvmem-cells = <&fec2_mac_addr>;
548 nvmem-cell-names = "mac-address";
549 status = "disabled";
550 };
551
552 kpp: keypad@20b8000 {
553 compatible = "fsl,imx6ul-kpp", "fsl,imx21-kpp";
554 reg = <0x020b8000 0x4000>;
555 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
556 clocks = <&clks IMX6UL_CLK_KPP>;
557 status = "disabled";
558 };
559
560 wdog1: watchdog@20bc000 {
561 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
562 reg = <0x020bc000 0x4000>;
563 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
564 clocks = <&clks IMX6UL_CLK_WDOG1>;
565 };
566
567 wdog2: watchdog@20c0000 {
568 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
569 reg = <0x020c0000 0x4000>;
570 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
571 clocks = <&clks IMX6UL_CLK_WDOG2>;
572 status = "disabled";
573 };
574
575 clks: clock-controller@20c4000 {
576 compatible = "fsl,imx6ul-ccm";
577 reg = <0x020c4000 0x4000>;
578 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
579 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
580 #clock-cells = <1>;
581 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
582 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
583 };
584
585 anatop: anatop@20c8000 {
586 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
587 "syscon", "simple-mfd";
588 reg = <0x020c8000 0x1000>;
589 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
590 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
591 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
592
593 reg_3p0: regulator-3p0 {
594 compatible = "fsl,anatop-regulator";
595 regulator-name = "vdd3p0";
596 regulator-min-microvolt = <2625000>;
597 regulator-max-microvolt = <3400000>;
598 anatop-reg-offset = <0x120>;
599 anatop-vol-bit-shift = <8>;
600 anatop-vol-bit-width = <5>;
601 anatop-min-bit-val = <0>;
602 anatop-min-voltage = <2625000>;
603 anatop-max-voltage = <3400000>;
604 anatop-enable-bit = <0>;
605 };
606
607 reg_arm: regulator-vddcore {
608 compatible = "fsl,anatop-regulator";
609 regulator-name = "cpu";
610 regulator-min-microvolt = <725000>;
611 regulator-max-microvolt = <1450000>;
612 regulator-always-on;
613 anatop-reg-offset = <0x140>;
614 anatop-vol-bit-shift = <0>;
615 anatop-vol-bit-width = <5>;
616 anatop-delay-reg-offset = <0x170>;
617 anatop-delay-bit-shift = <24>;
618 anatop-delay-bit-width = <2>;
619 anatop-min-bit-val = <1>;
620 anatop-min-voltage = <725000>;
621 anatop-max-voltage = <1450000>;
622 };
623
624 reg_soc: regulator-vddsoc {
625 compatible = "fsl,anatop-regulator";
626 regulator-name = "vddsoc";
627 regulator-min-microvolt = <725000>;
628 regulator-max-microvolt = <1450000>;
629 regulator-always-on;
630 anatop-reg-offset = <0x140>;
631 anatop-vol-bit-shift = <18>;
632 anatop-vol-bit-width = <5>;
633 anatop-delay-reg-offset = <0x170>;
634 anatop-delay-bit-shift = <28>;
635 anatop-delay-bit-width = <2>;
636 anatop-min-bit-val = <1>;
637 anatop-min-voltage = <725000>;
638 anatop-max-voltage = <1450000>;
639 };
640
641 tempmon: tempmon {
642 compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
643 interrupt-parent = <&gpc>;
644 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
645 fsl,tempmon = <&anatop>;
646 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
647 nvmem-cell-names = "calib", "temp_grade";
648 clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
649 #thermal-sensor-cells = <0>;
650 };
651 };
652
653 usbphy1: usbphy@20c9000 {
654 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
655 reg = <0x020c9000 0x1000>;
656 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
657 clocks = <&clks IMX6UL_CLK_USBPHY1>;
658 phy-3p0-supply = <®_3p0>;
659 fsl,anatop = <&anatop>;
660 };
661
662 usbphy2: usbphy@20ca000 {
663 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
664 reg = <0x020ca000 0x1000>;
665 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
666 clocks = <&clks IMX6UL_CLK_USBPHY2>;
667 phy-3p0-supply = <®_3p0>;
668 fsl,anatop = <&anatop>;
669 };
670
671 snvs: snvs@20cc000 {
672 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
673 reg = <0x020cc000 0x4000>;
674
675 snvs_rtc: snvs-rtc-lp {
676 compatible = "fsl,sec-v4.0-mon-rtc-lp";
677 regmap = <&snvs>;
678 offset = <0x34>;
679 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
680 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
681 };
682
683 snvs_poweroff: snvs-poweroff {
684 compatible = "syscon-poweroff";
685 regmap = <&snvs>;
686 offset = <0x38>;
687 value = <0x60>;
688 mask = <0x60>;
689 status = "disabled";
690 };
691
692 snvs_pwrkey: snvs-powerkey {
693 compatible = "fsl,sec-v4.0-pwrkey";
694 regmap = <&snvs>;
695 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
696 linux,keycode = <KEY_POWER>;
697 wakeup-source;
698 status = "disabled";
699 };
700
701 snvs_lpgpr: snvs-lpgpr {
702 compatible = "fsl,imx6ul-snvs-lpgpr";
703 };
704 };
705
706 epit1: epit@20d0000 {
707 reg = <0x020d0000 0x4000>;
708 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
709 };
710
711 epit2: epit@20d4000 {
712 reg = <0x020d4000 0x4000>;
713 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
714 };
715
716 src: reset-controller@20d8000 {
717 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
718 reg = <0x020d8000 0x4000>;
719 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
720 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
721 #reset-cells = <1>;
722 };
723
724 gpc: gpc@20dc000 {
725 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
726 reg = <0x020dc000 0x4000>;
727 interrupt-controller;
728 #interrupt-cells = <3>;
729 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
730 interrupt-parent = <&intc>;
731 clocks = <&clks IMX6UL_CLK_IPG>;
732 clock-names = "ipg";
733
734 pgc {
735 #address-cells = <1>;
736 #size-cells = <0>;
737
738 power-domain@0 {
739 reg = <0>;
740 #power-domain-cells = <0>;
741 };
742 };
743 };
744
745 iomuxc: pinctrl@20e0000 {
746 compatible = "fsl,imx6ul-iomuxc";
747 reg = <0x020e0000 0x4000>;
748 };
749
750 gpr: iomuxc-gpr@20e4000 {
751 compatible = "fsl,imx6ul-iomuxc-gpr",
752 "fsl,imx6q-iomuxc-gpr", "syscon";
753 reg = <0x020e4000 0x4000>;
754 };
755
756 gpt2: timer@20e8000 {
757 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
758 reg = <0x020e8000 0x4000>;
759 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
760 clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
761 <&clks IMX6UL_CLK_GPT2_SERIAL>;
762 clock-names = "ipg", "per";
763 status = "disabled";
764 };
765
766 sdma: dma-controller@20ec000 {
767 compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
768 "fsl,imx35-sdma";
769 reg = <0x020ec000 0x4000>;
770 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
771 clocks = <&clks IMX6UL_CLK_IPG>,
772 <&clks IMX6UL_CLK_SDMA>;
773 clock-names = "ipg", "ahb";
774 #dma-cells = <3>;
775 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
776 };
777
778 pwm5: pwm@20f0000 {
779 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
780 reg = <0x020f0000 0x4000>;
781 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
782 clocks = <&clks IMX6UL_CLK_PWM5>,
783 <&clks IMX6UL_CLK_PWM5>;
784 clock-names = "ipg", "per";
785 #pwm-cells = <3>;
786 status = "disabled";
787 };
788
789 pwm6: pwm@20f4000 {
790 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
791 reg = <0x020f4000 0x4000>;
792 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
793 clocks = <&clks IMX6UL_CLK_PWM6>,
794 <&clks IMX6UL_CLK_PWM6>;
795 clock-names = "ipg", "per";
796 #pwm-cells = <3>;
797 status = "disabled";
798 };
799
800 pwm7: pwm@20f8000 {
801 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
802 reg = <0x020f8000 0x4000>;
803 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
804 clocks = <&clks IMX6UL_CLK_PWM7>,
805 <&clks IMX6UL_CLK_PWM7>;
806 clock-names = "ipg", "per";
807 #pwm-cells = <3>;
808 status = "disabled";
809 };
810
811 pwm8: pwm@20fc000 {
812 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
813 reg = <0x020fc000 0x4000>;
814 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
815 clocks = <&clks IMX6UL_CLK_PWM8>,
816 <&clks IMX6UL_CLK_PWM8>;
817 clock-names = "ipg", "per";
818 #pwm-cells = <3>;
819 status = "disabled";
820 };
821 };
822
823 aips2: bus@2100000 {
824 compatible = "fsl,aips-bus", "simple-bus";
825 #address-cells = <1>;
826 #size-cells = <1>;
827 reg = <0x02100000 0x100000>;
828 ranges;
829
830 crypto: crypto@2140000 {
831 compatible = "fsl,imx6ul-caam", "fsl,sec-v4.0";
832 #address-cells = <1>;
833 #size-cells = <1>;
834 reg = <0x2140000 0x3c000>;
835 ranges = <0 0x2140000 0x3c000>;
836 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
837 clocks = <&clks IMX6UL_CLK_CAAM_IPG>, <&clks IMX6UL_CLK_CAAM_ACLK>,
838 <&clks IMX6UL_CLK_CAAM_MEM>;
839 clock-names = "ipg", "aclk", "mem";
840
841 sec_jr0: jr@1000 {
842 compatible = "fsl,sec-v4.0-job-ring";
843 reg = <0x1000 0x1000>;
844 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
845 };
846
847 sec_jr1: jr@2000 {
848 compatible = "fsl,sec-v4.0-job-ring";
849 reg = <0x2000 0x1000>;
850 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
851 };
852
853 sec_jr2: jr@3000 {
854 compatible = "fsl,sec-v4.0-job-ring";
855 reg = <0x3000 0x1000>;
856 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
857 };
858 };
859
860 usbotg1: usb@2184000 {
861 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
862 reg = <0x02184000 0x200>;
863 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
864 clocks = <&clks IMX6UL_CLK_USBOH3>;
865 fsl,usbphy = <&usbphy1>;
866 fsl,usbmisc = <&usbmisc 0>;
867 ahb-burst-config = <0x0>;
868 tx-burst-size-dword = <0x10>;
869 rx-burst-size-dword = <0x10>;
870 status = "disabled";
871 };
872
873 usbotg2: usb@2184200 {
874 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
875 reg = <0x02184200 0x200>;
876 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
877 clocks = <&clks IMX6UL_CLK_USBOH3>;
878 fsl,usbphy = <&usbphy2>;
879 fsl,usbmisc = <&usbmisc 1>;
880 ahb-burst-config = <0x0>;
881 tx-burst-size-dword = <0x10>;
882 rx-burst-size-dword = <0x10>;
883 status = "disabled";
884 };
885
886 usbmisc: usbmisc@2184800 {
887 #index-cells = <1>;
888 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
889 reg = <0x02184800 0x200>;
890 };
891
892 fec1: ethernet@2188000 {
893 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
894 reg = <0x02188000 0x4000>;
895 interrupt-names = "int0", "pps";
896 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
897 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
898 clocks = <&clks IMX6UL_CLK_ENET>,
899 <&clks IMX6UL_CLK_ENET_AHB>,
900 <&clks IMX6UL_CLK_ENET_PTP>,
901 <&clks IMX6UL_CLK_ENET1_REF_SEL>;
902 clock-names = "ipg", "ahb", "ptp",
903 "enet_clk_ref";
904 fsl,num-tx-queues = <1>;
905 fsl,num-rx-queues = <1>;
906 fsl,stop-mode = <&gpr 0x10 3>;
907 fsl,magic-packet;
908 nvmem-cells = <&fec1_mac_addr>;
909 nvmem-cell-names = "mac-address";
910 status = "disabled";
911 };
912
913 usdhc1: mmc@2190000 {
914 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
915 reg = <0x02190000 0x4000>;
916 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
917 clocks = <&clks IMX6UL_CLK_USDHC1>,
918 <&clks IMX6UL_CLK_USDHC1>,
919 <&clks IMX6UL_CLK_USDHC1>;
920 clock-names = "ipg", "ahb", "per";
921 fsl,tuning-step = <2>;
922 fsl,tuning-start-tap = <20>;
923 bus-width = <4>;
924 status = "disabled";
925 };
926
927 usdhc2: mmc@2194000 {
928 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
929 reg = <0x02194000 0x4000>;
930 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
931 clocks = <&clks IMX6UL_CLK_USDHC2>,
932 <&clks IMX6UL_CLK_USDHC2>,
933 <&clks IMX6UL_CLK_USDHC2>;
934 clock-names = "ipg", "ahb", "per";
935 bus-width = <4>;
936 fsl,tuning-step = <2>;
937 fsl,tuning-start-tap = <20>;
938 status = "disabled";
939 };
940
941 adc1: adc@2198000 {
942 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
943 reg = <0x02198000 0x4000>;
944 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
945 clocks = <&clks IMX6UL_CLK_ADC1>;
946 clock-names = "adc";
947 fsl,adck-max-frequency = <30000000>, <40000000>,
948 <20000000>;
949 status = "disabled";
950 };
951
952 i2c1: i2c@21a0000 {
953 #address-cells = <1>;
954 #size-cells = <0>;
955 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
956 reg = <0x021a0000 0x4000>;
957 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
958 clocks = <&clks IMX6UL_CLK_I2C1>;
959 status = "disabled";
960 };
961
962 i2c2: i2c@21a4000 {
963 #address-cells = <1>;
964 #size-cells = <0>;
965 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
966 reg = <0x021a4000 0x4000>;
967 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
968 clocks = <&clks IMX6UL_CLK_I2C2>;
969 status = "disabled";
970 };
971
972 i2c3: i2c@21a8000 {
973 #address-cells = <1>;
974 #size-cells = <0>;
975 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
976 reg = <0x021a8000 0x4000>;
977 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
978 clocks = <&clks IMX6UL_CLK_I2C3>;
979 status = "disabled";
980 };
981
982 memory-controller@21b0000 {
983 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
984 reg = <0x021b0000 0x4000>;
985 clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>;
986 };
987
988 weim: memory-controller@21b8000 {
989 #address-cells = <2>;
990 #size-cells = <1>;
991 compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim";
992 reg = <0x021b8000 0x4000>;
993 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
994 clocks = <&clks IMX6UL_CLK_EIM>;
995 fsl,weim-cs-gpr = <&gpr>;
996 status = "disabled";
997 };
998
999 ocotp: efuse@21bc000 {
1000 #address-cells = <1>;
1001 #size-cells = <1>;
1002 compatible = "fsl,imx6ul-ocotp", "syscon";
1003 reg = <0x021bc000 0x4000>;
1004 clocks = <&clks IMX6UL_CLK_OCOTP>;
1005
1006 tempmon_calib: calib@38 {
1007 reg = <0x38 4>;
1008 };
1009
1010 tempmon_temp_grade: temp-grade@20 {
1011 reg = <0x20 4>;
1012 };
1013
1014 cpu_speed_grade: speed-grade@10 {
1015 reg = <0x10 4>;
1016 };
1017
1018 fec1_mac_addr: mac-addr@88 {
1019 reg = <0x88 6>;
1020 };
1021
1022 fec2_mac_addr: mac-addr@8e {
1023 reg = <0x8e 6>;
1024 };
1025 };
1026
1027 csi: csi@21c4000 {
1028 compatible = "fsl,imx6ul-csi";
1029 reg = <0x021c4000 0x4000>;
1030 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1031 clocks = <&clks IMX6UL_CLK_CSI>;
1032 clock-names = "mclk";
1033 status = "disabled";
1034 };
1035
1036 lcdif: lcdif@21c8000 {
1037 compatible = "fsl,imx6ul-lcdif", "fsl,imx6sx-lcdif";
1038 reg = <0x021c8000 0x4000>;
1039 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1040 clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
1041 <&clks IMX6UL_CLK_LCDIF_APB>,
1042 <&clks IMX6UL_CLK_DUMMY>;
1043 clock-names = "pix", "axi", "disp_axi";
1044 status = "disabled";
1045 };
1046
1047 pxp: pxp@21cc000 {
1048 compatible = "fsl,imx6ul-pxp";
1049 reg = <0x021cc000 0x4000>;
1050 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1051 clocks = <&clks IMX6UL_CLK_PXP>;
1052 clock-names = "axi";
1053 };
1054
1055 qspi: spi@21e0000 {
1056 #address-cells = <1>;
1057 #size-cells = <0>;
1058 compatible = "fsl,imx6ul-qspi";
1059 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1060 reg-names = "QuadSPI", "QuadSPI-memory";
1061 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1062 clocks = <&clks IMX6UL_CLK_QSPI>,
1063 <&clks IMX6UL_CLK_QSPI>;
1064 clock-names = "qspi_en", "qspi";
1065 status = "disabled";
1066 };
1067
1068 wdog3: watchdog@21e4000 {
1069 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
1070 reg = <0x021e4000 0x4000>;
1071 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1072 clocks = <&clks IMX6UL_CLK_WDOG3>;
1073 status = "disabled";
1074 };
1075
1076 uart2: serial@21e8000 {
1077 compatible = "fsl,imx6ul-uart",
1078 "fsl,imx6q-uart";
1079 reg = <0x021e8000 0x4000>;
1080 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1081 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
1082 <&clks IMX6UL_CLK_UART2_SERIAL>;
1083 clock-names = "ipg", "per";
1084 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1085 dma-names = "rx", "tx";
1086 status = "disabled";
1087 };
1088
1089 uart3: serial@21ec000 {
1090 compatible = "fsl,imx6ul-uart",
1091 "fsl,imx6q-uart";
1092 reg = <0x021ec000 0x4000>;
1093 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1094 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
1095 <&clks IMX6UL_CLK_UART3_SERIAL>;
1096 clock-names = "ipg", "per";
1097 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1098 dma-names = "rx", "tx";
1099 status = "disabled";
1100 };
1101
1102 uart4: serial@21f0000 {
1103 compatible = "fsl,imx6ul-uart",
1104 "fsl,imx6q-uart";
1105 reg = <0x021f0000 0x4000>;
1106 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1107 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
1108 <&clks IMX6UL_CLK_UART4_SERIAL>;
1109 clock-names = "ipg", "per";
1110 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1111 dma-names = "rx", "tx";
1112 status = "disabled";
1113 };
1114
1115 uart5: serial@21f4000 {
1116 compatible = "fsl,imx6ul-uart",
1117 "fsl,imx6q-uart";
1118 reg = <0x021f4000 0x4000>;
1119 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1120 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
1121 <&clks IMX6UL_CLK_UART5_SERIAL>;
1122 clock-names = "ipg", "per";
1123 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1124 dma-names = "rx", "tx";
1125 status = "disabled";
1126 };
1127
1128 i2c4: i2c@21f8000 {
1129 #address-cells = <1>;
1130 #size-cells = <0>;
1131 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
1132 reg = <0x021f8000 0x4000>;
1133 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1134 clocks = <&clks IMX6UL_CLK_I2C4>;
1135 status = "disabled";
1136 };
1137
1138 uart6: serial@21fc000 {
1139 compatible = "fsl,imx6ul-uart",
1140 "fsl,imx6q-uart";
1141 reg = <0x021fc000 0x4000>;
1142 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1143 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
1144 <&clks IMX6UL_CLK_UART6_SERIAL>;
1145 clock-names = "ipg", "per";
1146 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1147 dma-names = "rx", "tx";
1148 status = "disabled";
1149 };
1150 };
1151 };
1152};