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1# SPDX-License-Identifier: GPL-2.0
2config ARM
3 bool
4 default y
5 select ARCH_32BIT_OFF_T
6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND
7 select ARCH_HAS_BINFMT_FLAT
8 select ARCH_HAS_CPU_CACHE_ALIASING
9 select ARCH_HAS_CPU_FINALIZE_INIT if MMU
10 select ARCH_HAS_CURRENT_STACK_POINTER
11 select ARCH_HAS_DEBUG_VIRTUAL if MMU
12 select ARCH_HAS_DMA_ALLOC if MMU
13 select ARCH_HAS_DMA_OPS
14 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE
15 select ARCH_HAS_ELF_RANDOMIZE
16 select ARCH_HAS_FORTIFY_SOURCE
17 select ARCH_HAS_KEEPINITRD
18 select ARCH_HAS_KCOV
19 select ARCH_HAS_MEMBARRIER_SYNC_CORE
20 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
21 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
22 select ARCH_HAS_SETUP_DMA_OPS
23 select ARCH_HAS_SET_MEMORY
24 select ARCH_STACKWALK
25 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
26 select ARCH_HAS_STRICT_MODULE_RWX if MMU
27 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
28 select ARCH_HAS_SYNC_DMA_FOR_CPU
29 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
30 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
31 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K
32 select ARCH_HAS_GCOV_PROFILE_ALL
33 select ARCH_KEEP_MEMBLOCK
34 select ARCH_HAS_UBSAN
35 select ARCH_MIGHT_HAVE_PC_PARPORT
36 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
37 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
38 select ARCH_NEED_CMPXCHG_1_EMU if CPU_V6
39 select ARCH_SUPPORTS_ATOMIC_RMW
40 select ARCH_SUPPORTS_CFI_CLANG
41 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE
42 select ARCH_SUPPORTS_PER_VMA_LOCK
43 select ARCH_USE_BUILTIN_BSWAP
44 select ARCH_USE_CMPXCHG_LOCKREF
45 select ARCH_USE_MEMTEST
46 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
47 select ARCH_WANT_GENERAL_HUGETLB
48 select ARCH_WANT_IPC_PARSE_VERSION
49 select ARCH_WANT_LD_ORPHAN_WARN
50 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
51 select BUILDTIME_TABLE_SORT if MMU
52 select COMMON_CLK if !(ARCH_RPC || ARCH_FOOTBRIDGE)
53 select CLONE_BACKWARDS
54 select CPU_PM if SUSPEND || CPU_IDLE
55 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
56 select DMA_DECLARE_COHERENT
57 select DMA_GLOBAL_POOL if !MMU
58 select DMA_NONCOHERENT_MMAP if MMU
59 select EDAC_SUPPORT
60 select EDAC_ATOMIC_SCRUB
61 select GENERIC_ALLOCATOR
62 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
63 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
64 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
65 select GENERIC_IRQ_IPI if SMP
66 select GENERIC_CPU_AUTOPROBE
67 select GENERIC_CPU_DEVICES
68 select GENERIC_EARLY_IOREMAP
69 select GENERIC_IDLE_POLL_SETUP
70 select GENERIC_IRQ_MULTI_HANDLER
71 select GENERIC_IRQ_PROBE
72 select GENERIC_IRQ_SHOW
73 select GENERIC_IRQ_SHOW_LEVEL
74 select GENERIC_LIB_DEVMEM_IS_ALLOWED
75 select GENERIC_PCI_IOMAP
76 select GENERIC_SCHED_CLOCK
77 select GENERIC_SMP_IDLE_THREAD
78 select HARDIRQS_SW_RESEND
79 select HAS_IOPORT
80 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
81 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
82 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
83 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL
84 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
85 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL
86 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
87 select HAVE_ARCH_MMAP_RND_BITS if MMU
88 select HAVE_ARCH_PFN_VALID
89 select HAVE_ARCH_SECCOMP
90 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
91 select HAVE_ARCH_STACKLEAK
92 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
93 select HAVE_ARCH_TRACEHOOK
94 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE
95 select HAVE_ARM_SMCCC if CPU_V7
96 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
97 select HAVE_CONTEXT_TRACKING_USER
98 select HAVE_C_RECORDMCOUNT
99 select HAVE_BUILDTIME_MCOUNT_SORT
100 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL
101 select HAVE_DMA_CONTIGUOUS if MMU
102 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
103 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
104 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
105 select HAVE_EXIT_THREAD
106 select HAVE_GUP_FAST if ARM_LPAE
107 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
108 select HAVE_FUNCTION_ERROR_INJECTION
109 select HAVE_FUNCTION_GRAPH_TRACER
110 select HAVE_FUNCTION_TRACER if !XIP_KERNEL
111 select HAVE_GCC_PLUGINS
112 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
113 select HAVE_IRQ_TIME_ACCOUNTING
114 select HAVE_KERNEL_GZIP
115 select HAVE_KERNEL_LZ4
116 select HAVE_KERNEL_LZMA
117 select HAVE_KERNEL_LZO
118 select HAVE_KERNEL_XZ
119 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
120 select HAVE_KRETPROBES if HAVE_KPROBES
121 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION if (LD_VERSION >= 23600 || LD_IS_LLD)
122 select HAVE_MOD_ARCH_SPECIFIC
123 select HAVE_NMI
124 select HAVE_OPTPROBES if !THUMB2_KERNEL
125 select HAVE_PAGE_SIZE_4KB
126 select HAVE_PCI if MMU
127 select HAVE_PERF_EVENTS
128 select HAVE_PERF_REGS
129 select HAVE_PERF_USER_STACK_DUMP
130 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE
131 select HAVE_REGS_AND_STACK_ACCESS_API
132 select HAVE_RSEQ
133 select HAVE_STACKPROTECTOR
134 select HAVE_SYSCALL_TRACEPOINTS
135 select HAVE_UID16
136 select HAVE_VIRT_CPU_ACCOUNTING_GEN
137 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU
138 select IRQ_FORCED_THREADING
139 select LOCK_MM_AND_FIND_VMA
140 select MODULES_USE_ELF_REL
141 select NEED_DMA_MAP_STATE
142 select OF_EARLY_FLATTREE if OF
143 select OLD_SIGACTION
144 select OLD_SIGSUSPEND3
145 select PCI_DOMAINS_GENERIC if PCI
146 select PCI_SYSCALL if PCI
147 select PERF_USE_VMALLOC
148 select RTC_LIB
149 select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC)
150 select SYS_SUPPORTS_APM_EMULATION
151 select THREAD_INFO_IN_TASK
152 select TIMER_OF if OF
153 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS
154 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M
155 select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
156 # Above selects are sorted alphabetically; please add new ones
157 # according to that. Thanks.
158 help
159 The ARM series is a line of low-power-consumption RISC chip designs
160 licensed by ARM Ltd and targeted at embedded applications and
161 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
162 manufactured, but legacy ARM-based PC hardware remains popular in
163 Europe. There is an ARM Linux project with a web page at
164 <http://www.arm.linux.org.uk/>.
165
166config ARM_HAS_GROUP_RELOCS
167 def_bool y
168 depends on !LD_IS_LLD || LLD_VERSION >= 140000
169 depends on !COMPILE_TEST
170 help
171 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group
172 relocations, which have been around for a long time, but were not
173 supported in LLD until version 14. The combined range is -/+ 256 MiB,
174 which is usually sufficient, but not for allyesconfig, so we disable
175 this feature when doing compile testing.
176
177config ARM_DMA_USE_IOMMU
178 bool
179 select NEED_SG_DMA_LENGTH
180
181if ARM_DMA_USE_IOMMU
182
183config ARM_DMA_IOMMU_ALIGNMENT
184 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
185 range 4 9
186 default 8
187 help
188 DMA mapping framework by default aligns all buffers to the smallest
189 PAGE_SIZE order which is greater than or equal to the requested buffer
190 size. This works well for buffers up to a few hundreds kilobytes, but
191 for larger buffers it just a waste of address space. Drivers which has
192 relatively small addressing window (like 64Mib) might run out of
193 virtual space with just a few allocations.
194
195 With this parameter you can specify the maximum PAGE_SIZE order for
196 DMA IOMMU buffers. Larger buffers will be aligned only to this
197 specified order. The order is expressed as a power of two multiplied
198 by the PAGE_SIZE.
199
200endif
201
202config SYS_SUPPORTS_APM_EMULATION
203 bool
204
205config HAVE_TCM
206 bool
207 select GENERIC_ALLOCATOR
208
209config HAVE_PROC_CPU
210 bool
211
212config NO_IOPORT_MAP
213 bool
214
215config SBUS
216 bool
217
218config STACKTRACE_SUPPORT
219 bool
220 default y
221
222config LOCKDEP_SUPPORT
223 bool
224 default y
225
226config ARCH_HAS_ILOG2_U32
227 bool
228
229config ARCH_HAS_ILOG2_U64
230 bool
231
232config ARCH_HAS_BANDGAP
233 bool
234
235config FIX_EARLYCON_MEM
236 def_bool y if MMU
237
238config GENERIC_HWEIGHT
239 bool
240 default y
241
242config GENERIC_CALIBRATE_DELAY
243 bool
244 default y
245
246config ARCH_MAY_HAVE_PC_FDC
247 bool
248
249config ARCH_SUPPORTS_UPROBES
250 def_bool y
251
252config GENERIC_ISA_DMA
253 bool
254
255config FIQ
256 bool
257
258config ARCH_MTD_XIP
259 bool
260
261config ARM_PATCH_PHYS_VIRT
262 bool "Patch physical to virtual translations at runtime" if !ARCH_MULTIPLATFORM
263 default y
264 depends on MMU
265 help
266 Patch phys-to-virt and virt-to-phys translation functions at
267 boot and module load time according to the position of the
268 kernel in system memory.
269
270 This can only be used with non-XIP MMU kernels where the base
271 of physical memory is at a 2 MiB boundary.
272
273 Only disable this option if you know that you do not require
274 this feature (eg, building a kernel for a single machine) and
275 you need to shrink the kernel to the minimal size.
276
277config NEED_MACH_IO_H
278 bool
279 help
280 Select this when mach/io.h is required to provide special
281 definitions for this platform. The need for mach/io.h should
282 be avoided when possible.
283
284config NEED_MACH_MEMORY_H
285 bool
286 help
287 Select this when mach/memory.h is required to provide special
288 definitions for this platform. The need for mach/memory.h should
289 be avoided when possible.
290
291config PHYS_OFFSET
292 hex "Physical address of main memory" if MMU
293 depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR
294 default DRAM_BASE if !MMU
295 default 0x00000000 if ARCH_FOOTBRIDGE
296 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
297 default 0xa0000000 if ARCH_PXA
298 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100
299 default 0
300 help
301 Please provide the physical address corresponding to the
302 location of main memory in your system.
303
304config GENERIC_BUG
305 def_bool y
306 depends on BUG
307
308config PGTABLE_LEVELS
309 int
310 default 3 if ARM_LPAE
311 default 2
312
313menu "System Type"
314
315config MMU
316 bool "MMU-based Paged Memory Management Support"
317 default y
318 help
319 Select if you want MMU-based virtualised addressing space
320 support by paged memory management. If unsure, say 'Y'.
321
322config ARM_SINGLE_ARMV7M
323 def_bool !MMU
324 select ARM_NVIC
325 select CPU_V7M
326 select NO_IOPORT_MAP
327
328config ARCH_MMAP_RND_BITS_MIN
329 default 8
330
331config ARCH_MMAP_RND_BITS_MAX
332 default 14 if PAGE_OFFSET=0x40000000
333 default 15 if PAGE_OFFSET=0x80000000
334 default 16
335
336config ARCH_MULTIPLATFORM
337 bool "Require kernel to be portable to multiple machines" if EXPERT
338 depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
339 default y
340 help
341 In general, all Arm machines can be supported in a single
342 kernel image, covering either Armv4/v5 or Armv6/v7.
343
344 However, some configuration options require hardcoding machine
345 specific physical addresses or enable errata workarounds that may
346 break other machines.
347
348 Selecting N here allows using those options, including
349 DEBUG_UNCOMPRESS, XIP_KERNEL and ZBOOT_ROM. If unsure, say Y.
350
351source "arch/arm/Kconfig.platforms"
352
353#
354# This is sorted alphabetically by mach-* pathname. However, plat-*
355# Kconfigs may be included either alphabetically (according to the
356# plat- suffix) or along side the corresponding mach-* source.
357#
358source "arch/arm/mach-actions/Kconfig"
359
360source "arch/arm/mach-alpine/Kconfig"
361
362source "arch/arm/mach-artpec/Kconfig"
363
364source "arch/arm/mach-aspeed/Kconfig"
365
366source "arch/arm/mach-at91/Kconfig"
367
368source "arch/arm/mach-axxia/Kconfig"
369
370source "arch/arm/mach-bcm/Kconfig"
371
372source "arch/arm/mach-berlin/Kconfig"
373
374source "arch/arm/mach-clps711x/Kconfig"
375
376source "arch/arm/mach-davinci/Kconfig"
377
378source "arch/arm/mach-digicolor/Kconfig"
379
380source "arch/arm/mach-dove/Kconfig"
381
382source "arch/arm/mach-ep93xx/Kconfig"
383
384source "arch/arm/mach-exynos/Kconfig"
385
386source "arch/arm/mach-footbridge/Kconfig"
387
388source "arch/arm/mach-gemini/Kconfig"
389
390source "arch/arm/mach-highbank/Kconfig"
391
392source "arch/arm/mach-hisi/Kconfig"
393
394source "arch/arm/mach-hpe/Kconfig"
395
396source "arch/arm/mach-imx/Kconfig"
397
398source "arch/arm/mach-ixp4xx/Kconfig"
399
400source "arch/arm/mach-keystone/Kconfig"
401
402source "arch/arm/mach-lpc32xx/Kconfig"
403
404source "arch/arm/mach-mediatek/Kconfig"
405
406source "arch/arm/mach-meson/Kconfig"
407
408source "arch/arm/mach-milbeaut/Kconfig"
409
410source "arch/arm/mach-mmp/Kconfig"
411
412source "arch/arm/mach-mstar/Kconfig"
413
414source "arch/arm/mach-mv78xx0/Kconfig"
415
416source "arch/arm/mach-mvebu/Kconfig"
417
418source "arch/arm/mach-mxs/Kconfig"
419
420source "arch/arm/mach-nomadik/Kconfig"
421
422source "arch/arm/mach-npcm/Kconfig"
423
424source "arch/arm/mach-omap1/Kconfig"
425
426source "arch/arm/mach-omap2/Kconfig"
427
428source "arch/arm/mach-orion5x/Kconfig"
429
430source "arch/arm/mach-pxa/Kconfig"
431
432source "arch/arm/mach-qcom/Kconfig"
433
434source "arch/arm/mach-realtek/Kconfig"
435
436source "arch/arm/mach-rpc/Kconfig"
437
438source "arch/arm/mach-rockchip/Kconfig"
439
440source "arch/arm/mach-s3c/Kconfig"
441
442source "arch/arm/mach-s5pv210/Kconfig"
443
444source "arch/arm/mach-sa1100/Kconfig"
445
446source "arch/arm/mach-shmobile/Kconfig"
447
448source "arch/arm/mach-socfpga/Kconfig"
449
450source "arch/arm/mach-spear/Kconfig"
451
452source "arch/arm/mach-sti/Kconfig"
453
454source "arch/arm/mach-stm32/Kconfig"
455
456source "arch/arm/mach-sunxi/Kconfig"
457
458source "arch/arm/mach-tegra/Kconfig"
459
460source "arch/arm/mach-ux500/Kconfig"
461
462source "arch/arm/mach-versatile/Kconfig"
463
464source "arch/arm/mach-vt8500/Kconfig"
465
466source "arch/arm/mach-zynq/Kconfig"
467
468# ARMv7-M architecture
469config ARCH_LPC18XX
470 bool "NXP LPC18xx/LPC43xx"
471 depends on ARM_SINGLE_ARMV7M
472 select ARCH_HAS_RESET_CONTROLLER
473 select ARM_AMBA
474 select CLKSRC_LPC32XX
475 select PINCTRL
476 help
477 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
478 high performance microcontrollers.
479
480config ARCH_MPS2
481 bool "ARM MPS2 platform"
482 depends on ARM_SINGLE_ARMV7M
483 select ARM_AMBA
484 select CLKSRC_MPS2
485 help
486 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
487 with a range of available cores like Cortex-M3/M4/M7.
488
489 Please, note that depends which Application Note is used memory map
490 for the platform may vary, so adjustment of RAM base might be needed.
491
492# Definitions to make life easier
493config ARCH_ACORN
494 bool
495
496config PLAT_ORION
497 bool
498 select CLKSRC_MMIO
499 select GENERIC_IRQ_CHIP
500 select IRQ_DOMAIN
501
502config PLAT_ORION_LEGACY
503 bool
504 select PLAT_ORION
505
506config PLAT_VERSATILE
507 bool
508
509source "arch/arm/mm/Kconfig"
510
511config IWMMXT
512 bool "Enable iWMMXt support"
513 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK
514 default y if PXA27x || PXA3xx || ARCH_MMP
515 help
516 Enable support for iWMMXt context switching at run time if
517 running on a CPU that supports it.
518
519if !MMU
520source "arch/arm/Kconfig-nommu"
521endif
522
523config PJ4B_ERRATA_4742
524 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
525 depends on CPU_PJ4B && MACH_ARMADA_370
526 default y
527 help
528 When coming out of either a Wait for Interrupt (WFI) or a Wait for
529 Event (WFE) IDLE states, a specific timing sensitivity exists between
530 the retiring WFI/WFE instructions and the newly issued subsequent
531 instructions. This sensitivity can result in a CPU hang scenario.
532 Workaround:
533 The software must insert either a Data Synchronization Barrier (DSB)
534 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
535 instruction
536
537config ARM_ERRATA_326103
538 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
539 depends on CPU_V6
540 help
541 Executing a SWP instruction to read-only memory does not set bit 11
542 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
543 treat the access as a read, preventing a COW from occurring and
544 causing the faulting task to livelock.
545
546config ARM_ERRATA_411920
547 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
548 depends on CPU_V6 || CPU_V6K
549 help
550 Invalidation of the Instruction Cache operation can
551 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
552 It does not affect the MPCore. This option enables the ARM Ltd.
553 recommended workaround.
554
555config ARM_ERRATA_430973
556 bool "ARM errata: Stale prediction on replaced interworking branch"
557 depends on CPU_V7
558 help
559 This option enables the workaround for the 430973 Cortex-A8
560 r1p* erratum. If a code sequence containing an ARM/Thumb
561 interworking branch is replaced with another code sequence at the
562 same virtual address, whether due to self-modifying code or virtual
563 to physical address re-mapping, Cortex-A8 does not recover from the
564 stale interworking branch prediction. This results in Cortex-A8
565 executing the new code sequence in the incorrect ARM or Thumb state.
566 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
567 and also flushes the branch target cache at every context switch.
568 Note that setting specific bits in the ACTLR register may not be
569 available in non-secure mode.
570
571config ARM_ERRATA_458693
572 bool "ARM errata: Processor deadlock when a false hazard is created"
573 depends on CPU_V7
574 depends on !ARCH_MULTIPLATFORM
575 help
576 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
577 erratum. For very specific sequences of memory operations, it is
578 possible for a hazard condition intended for a cache line to instead
579 be incorrectly associated with a different cache line. This false
580 hazard might then cause a processor deadlock. The workaround enables
581 the L1 caching of the NEON accesses and disables the PLD instruction
582 in the ACTLR register. Note that setting specific bits in the ACTLR
583 register may not be available in non-secure mode and thus is not
584 available on a multiplatform kernel. This should be applied by the
585 bootloader instead.
586
587config ARM_ERRATA_460075
588 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
589 depends on CPU_V7
590 depends on !ARCH_MULTIPLATFORM
591 help
592 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
593 erratum. Any asynchronous access to the L2 cache may encounter a
594 situation in which recent store transactions to the L2 cache are lost
595 and overwritten with stale memory contents from external memory. The
596 workaround disables the write-allocate mode for the L2 cache via the
597 ACTLR register. Note that setting specific bits in the ACTLR register
598 may not be available in non-secure mode and thus is not available on
599 a multiplatform kernel. This should be applied by the bootloader
600 instead.
601
602config ARM_ERRATA_742230
603 bool "ARM errata: DMB operation may be faulty"
604 depends on CPU_V7 && SMP
605 depends on !ARCH_MULTIPLATFORM
606 help
607 This option enables the workaround for the 742230 Cortex-A9
608 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
609 between two write operations may not ensure the correct visibility
610 ordering of the two writes. This workaround sets a specific bit in
611 the diagnostic register of the Cortex-A9 which causes the DMB
612 instruction to behave as a DSB, ensuring the correct behaviour of
613 the two writes. Note that setting specific bits in the diagnostics
614 register may not be available in non-secure mode and thus is not
615 available on a multiplatform kernel. This should be applied by the
616 bootloader instead.
617
618config ARM_ERRATA_742231
619 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
620 depends on CPU_V7 && SMP
621 depends on !ARCH_MULTIPLATFORM
622 help
623 This option enables the workaround for the 742231 Cortex-A9
624 (r2p0..r2p2) erratum. Under certain conditions, specific to the
625 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
626 accessing some data located in the same cache line, may get corrupted
627 data due to bad handling of the address hazard when the line gets
628 replaced from one of the CPUs at the same time as another CPU is
629 accessing it. This workaround sets specific bits in the diagnostic
630 register of the Cortex-A9 which reduces the linefill issuing
631 capabilities of the processor. Note that setting specific bits in the
632 diagnostics register may not be available in non-secure mode and thus
633 is not available on a multiplatform kernel. This should be applied by
634 the bootloader instead.
635
636config ARM_ERRATA_643719
637 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
638 depends on CPU_V7 && SMP
639 default y
640 help
641 This option enables the workaround for the 643719 Cortex-A9 (prior to
642 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
643 register returns zero when it should return one. The workaround
644 corrects this value, ensuring cache maintenance operations which use
645 it behave as intended and avoiding data corruption.
646
647config ARM_ERRATA_720789
648 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
649 depends on CPU_V7
650 help
651 This option enables the workaround for the 720789 Cortex-A9 (prior to
652 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
653 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
654 As a consequence of this erratum, some TLB entries which should be
655 invalidated are not, resulting in an incoherency in the system page
656 tables. The workaround changes the TLB flushing routines to invalidate
657 entries regardless of the ASID.
658
659config ARM_ERRATA_743622
660 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
661 depends on CPU_V7
662 depends on !ARCH_MULTIPLATFORM
663 help
664 This option enables the workaround for the 743622 Cortex-A9
665 (r2p*) erratum. Under very rare conditions, a faulty
666 optimisation in the Cortex-A9 Store Buffer may lead to data
667 corruption. This workaround sets a specific bit in the diagnostic
668 register of the Cortex-A9 which disables the Store Buffer
669 optimisation, preventing the defect from occurring. This has no
670 visible impact on the overall performance or power consumption of the
671 processor. Note that setting specific bits in the diagnostics register
672 may not be available in non-secure mode and thus is not available on a
673 multiplatform kernel. This should be applied by the bootloader instead.
674
675config ARM_ERRATA_751472
676 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
677 depends on CPU_V7
678 depends on !ARCH_MULTIPLATFORM
679 help
680 This option enables the workaround for the 751472 Cortex-A9 (prior
681 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
682 completion of a following broadcasted operation if the second
683 operation is received by a CPU before the ICIALLUIS has completed,
684 potentially leading to corrupted entries in the cache or TLB.
685 Note that setting specific bits in the diagnostics register may
686 not be available in non-secure mode and thus is not available on
687 a multiplatform kernel. This should be applied by the bootloader
688 instead.
689
690config ARM_ERRATA_754322
691 bool "ARM errata: possible faulty MMU translations following an ASID switch"
692 depends on CPU_V7
693 help
694 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
695 r3p*) erratum. A speculative memory access may cause a page table walk
696 which starts prior to an ASID switch but completes afterwards. This
697 can populate the micro-TLB with a stale entry which may be hit with
698 the new ASID. This workaround places two dsb instructions in the mm
699 switching code so that no page table walks can cross the ASID switch.
700
701config ARM_ERRATA_754327
702 bool "ARM errata: no automatic Store Buffer drain"
703 depends on CPU_V7 && SMP
704 help
705 This option enables the workaround for the 754327 Cortex-A9 (prior to
706 r2p0) erratum. The Store Buffer does not have any automatic draining
707 mechanism and therefore a livelock may occur if an external agent
708 continuously polls a memory location waiting to observe an update.
709 This workaround defines cpu_relax() as smp_mb(), preventing correctly
710 written polling loops from denying visibility of updates to memory.
711
712config ARM_ERRATA_364296
713 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
714 depends on CPU_V6
715 help
716 This options enables the workaround for the 364296 ARM1136
717 r0p2 erratum (possible cache data corruption with
718 hit-under-miss enabled). It sets the undocumented bit 31 in
719 the auxiliary control register and the FI bit in the control
720 register, thus disabling hit-under-miss without putting the
721 processor into full low interrupt latency mode. ARM11MPCore
722 is not affected.
723
724config ARM_ERRATA_764369
725 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
726 depends on CPU_V7 && SMP
727 help
728 This option enables the workaround for erratum 764369
729 affecting Cortex-A9 MPCore with two or more processors (all
730 current revisions). Under certain timing circumstances, a data
731 cache line maintenance operation by MVA targeting an Inner
732 Shareable memory region may fail to proceed up to either the
733 Point of Coherency or to the Point of Unification of the
734 system. This workaround adds a DSB instruction before the
735 relevant cache maintenance functions and sets a specific bit
736 in the diagnostic control register of the SCU.
737
738config ARM_ERRATA_764319
739 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction"
740 depends on CPU_V7
741 help
742 This option enables the workaround for the 764319 Cortex-A9 erratum.
743 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an
744 unexpected Undefined Instruction exception when the DBGSWENABLE
745 external pin is set to 0, even when the CP14 accesses are performed
746 from a privileged mode. This work around catches the exception in a
747 way the kernel does not stop execution.
748
749config ARM_ERRATA_775420
750 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
751 depends on CPU_V7
752 help
753 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
754 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
755 operation aborts with MMU exception, it might cause the processor
756 to deadlock. This workaround puts DSB before executing ISB if
757 an abort may occur on cache maintenance.
758
759config ARM_ERRATA_798181
760 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
761 depends on CPU_V7 && SMP
762 help
763 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
764 adequately shooting down all use of the old entries. This
765 option enables the Linux kernel workaround for this erratum
766 which sends an IPI to the CPUs that are running the same ASID
767 as the one being invalidated.
768
769config ARM_ERRATA_773022
770 bool "ARM errata: incorrect instructions may be executed from loop buffer"
771 depends on CPU_V7
772 help
773 This option enables the workaround for the 773022 Cortex-A15
774 (up to r0p4) erratum. In certain rare sequences of code, the
775 loop buffer may deliver incorrect instructions. This
776 workaround disables the loop buffer to avoid the erratum.
777
778config ARM_ERRATA_818325_852422
779 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
780 depends on CPU_V7
781 help
782 This option enables the workaround for:
783 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
784 instruction might deadlock. Fixed in r0p1.
785 - Cortex-A12 852422: Execution of a sequence of instructions might
786 lead to either a data corruption or a CPU deadlock. Not fixed in
787 any Cortex-A12 cores yet.
788 This workaround for all both errata involves setting bit[12] of the
789 Feature Register. This bit disables an optimisation applied to a
790 sequence of 2 instructions that use opposing condition codes.
791
792config ARM_ERRATA_821420
793 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
794 depends on CPU_V7
795 help
796 This option enables the workaround for the 821420 Cortex-A12
797 (all revs) erratum. In very rare timing conditions, a sequence
798 of VMOV to Core registers instructions, for which the second
799 one is in the shadow of a branch or abort, can lead to a
800 deadlock when the VMOV instructions are issued out-of-order.
801
802config ARM_ERRATA_825619
803 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
804 depends on CPU_V7
805 help
806 This option enables the workaround for the 825619 Cortex-A12
807 (all revs) erratum. Within rare timing constraints, executing a
808 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
809 and Device/Strongly-Ordered loads and stores might cause deadlock
810
811config ARM_ERRATA_857271
812 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
813 depends on CPU_V7
814 help
815 This option enables the workaround for the 857271 Cortex-A12
816 (all revs) erratum. Under very rare timing conditions, the CPU might
817 hang. The workaround is expected to have a < 1% performance impact.
818
819config ARM_ERRATA_852421
820 bool "ARM errata: A17: DMB ST might fail to create order between stores"
821 depends on CPU_V7
822 help
823 This option enables the workaround for the 852421 Cortex-A17
824 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
825 execution of a DMB ST instruction might fail to properly order
826 stores from GroupA and stores from GroupB.
827
828config ARM_ERRATA_852423
829 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
830 depends on CPU_V7
831 help
832 This option enables the workaround for:
833 - Cortex-A17 852423: Execution of a sequence of instructions might
834 lead to either a data corruption or a CPU deadlock. Not fixed in
835 any Cortex-A17 cores yet.
836 This is identical to Cortex-A12 erratum 852422. It is a separate
837 config option from the A12 erratum due to the way errata are checked
838 for and handled.
839
840config ARM_ERRATA_857272
841 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
842 depends on CPU_V7
843 help
844 This option enables the workaround for the 857272 Cortex-A17 erratum.
845 This erratum is not known to be fixed in any A17 revision.
846 This is identical to Cortex-A12 erratum 857271. It is a separate
847 config option from the A12 erratum due to the way errata are checked
848 for and handled.
849
850endmenu
851
852source "arch/arm/common/Kconfig"
853
854menu "Bus support"
855
856config ISA
857 bool
858 help
859 Find out whether you have ISA slots on your motherboard. ISA is the
860 name of a bus system, i.e. the way the CPU talks to the other stuff
861 inside your box. Other bus systems are PCI, EISA, MicroChannel
862 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
863 newer boards don't support it. If you have ISA, say Y, otherwise N.
864
865# Select ISA DMA interface
866config ISA_DMA_API
867 bool
868
869config ARM_ERRATA_814220
870 bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
871 depends on CPU_V7
872 help
873 The v7 ARM states that all cache and branch predictor maintenance
874 operations that do not specify an address execute, relative to
875 each other, in program order.
876 However, because of this erratum, an L2 set/way cache maintenance
877 operation can overtake an L1 set/way cache maintenance operation.
878 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
879 r0p4, r0p5.
880
881endmenu
882
883menu "Kernel Features"
884
885config HAVE_SMP
886 bool
887 help
888 This option should be selected by machines which have an SMP-
889 capable CPU.
890
891 The only effect of this option is to make the SMP-related
892 options available to the user for configuration.
893
894config SMP
895 bool "Symmetric Multi-Processing"
896 depends on CPU_V6K || CPU_V7
897 depends on HAVE_SMP
898 depends on MMU || ARM_MPU
899 select IRQ_WORK
900 help
901 This enables support for systems with more than one CPU. If you have
902 a system with only one CPU, say N. If you have a system with more
903 than one CPU, say Y.
904
905 If you say N here, the kernel will run on uni- and multiprocessor
906 machines, but will use only one CPU of a multiprocessor machine. If
907 you say Y here, the kernel will run on many, but not all,
908 uniprocessor machines. On a uniprocessor machine, the kernel
909 will run faster if you say N here.
910
911 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>,
912 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
913 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
914
915 If you don't know what to do here, say N.
916
917config SMP_ON_UP
918 bool "Allow booting SMP kernel on uniprocessor systems"
919 depends on SMP && MMU
920 default y
921 help
922 SMP kernels contain instructions which fail on non-SMP processors.
923 Enabling this option allows the kernel to modify itself to make
924 these instructions safe. Disabling it allows about 1K of space
925 savings.
926
927 If you don't know what to do here, say Y.
928
929
930config CURRENT_POINTER_IN_TPIDRURO
931 def_bool y
932 depends on CPU_32v6K && !CPU_V6
933
934config IRQSTACKS
935 def_bool y
936 select HAVE_IRQ_EXIT_ON_IRQ_STACK
937 select HAVE_SOFTIRQ_ON_OWN_STACK
938
939config ARM_CPU_TOPOLOGY
940 bool "Support cpu topology definition"
941 depends on SMP && CPU_V7
942 default y
943 help
944 Support ARM cpu topology definition. The MPIDR register defines
945 affinity between processors which is then used to describe the cpu
946 topology of an ARM System.
947
948config SCHED_MC
949 bool "Multi-core scheduler support"
950 depends on ARM_CPU_TOPOLOGY
951 help
952 Multi-core scheduler support improves the CPU scheduler's decision
953 making when dealing with multi-core CPU chips at a cost of slightly
954 increased overhead in some places. If unsure say N here.
955
956config SCHED_SMT
957 bool "SMT scheduler support"
958 depends on ARM_CPU_TOPOLOGY
959 help
960 Improves the CPU scheduler's decision making when dealing with
961 MultiThreading at a cost of slightly increased overhead in some
962 places. If unsure say N here.
963
964config HAVE_ARM_SCU
965 bool
966 help
967 This option enables support for the ARM snoop control unit
968
969config HAVE_ARM_ARCH_TIMER
970 bool "Architected timer support"
971 depends on CPU_V7
972 select ARM_ARCH_TIMER
973 help
974 This option enables support for the ARM architected timer
975
976config HAVE_ARM_TWD
977 bool
978 help
979 This options enables support for the ARM timer and watchdog unit
980
981config MCPM
982 bool "Multi-Cluster Power Management"
983 depends on CPU_V7 && SMP
984 help
985 This option provides the common power management infrastructure
986 for (multi-)cluster based systems, such as big.LITTLE based
987 systems.
988
989config MCPM_QUAD_CLUSTER
990 bool
991 depends on MCPM
992 help
993 To avoid wasting resources unnecessarily, MCPM only supports up
994 to 2 clusters by default.
995 Platforms with 3 or 4 clusters that use MCPM must select this
996 option to allow the additional clusters to be managed.
997
998config BIG_LITTLE
999 bool "big.LITTLE support (Experimental)"
1000 depends on CPU_V7 && SMP
1001 select MCPM
1002 help
1003 This option enables support selections for the big.LITTLE
1004 system architecture.
1005
1006config BL_SWITCHER
1007 bool "big.LITTLE switcher support"
1008 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1009 select CPU_PM
1010 help
1011 The big.LITTLE "switcher" provides the core functionality to
1012 transparently handle transition between a cluster of A15's
1013 and a cluster of A7's in a big.LITTLE system.
1014
1015config BL_SWITCHER_DUMMY_IF
1016 tristate "Simple big.LITTLE switcher user interface"
1017 depends on BL_SWITCHER && DEBUG_KERNEL
1018 help
1019 This is a simple and dummy char dev interface to control
1020 the big.LITTLE switcher core code. It is meant for
1021 debugging purposes only.
1022
1023choice
1024 prompt "Memory split"
1025 depends on MMU
1026 default VMSPLIT_3G
1027 help
1028 Select the desired split between kernel and user memory.
1029
1030 If you are not absolutely sure what you are doing, leave this
1031 option alone!
1032
1033 config VMSPLIT_3G
1034 bool "3G/1G user/kernel split"
1035 config VMSPLIT_3G_OPT
1036 depends on !ARM_LPAE
1037 bool "3G/1G user/kernel split (for full 1G low memory)"
1038 config VMSPLIT_2G
1039 bool "2G/2G user/kernel split"
1040 config VMSPLIT_1G
1041 bool "1G/3G user/kernel split"
1042endchoice
1043
1044config PAGE_OFFSET
1045 hex
1046 default PHYS_OFFSET if !MMU
1047 default 0x40000000 if VMSPLIT_1G
1048 default 0x80000000 if VMSPLIT_2G
1049 default 0xB0000000 if VMSPLIT_3G_OPT
1050 default 0xC0000000
1051
1052config KASAN_SHADOW_OFFSET
1053 hex
1054 depends on KASAN
1055 default 0x1f000000 if PAGE_OFFSET=0x40000000
1056 default 0x5f000000 if PAGE_OFFSET=0x80000000
1057 default 0x9f000000 if PAGE_OFFSET=0xC0000000
1058 default 0x8f000000 if PAGE_OFFSET=0xB0000000
1059 default 0xffffffff
1060
1061config NR_CPUS
1062 int "Maximum number of CPUs (2-32)"
1063 range 2 16 if DEBUG_KMAP_LOCAL
1064 range 2 32 if !DEBUG_KMAP_LOCAL
1065 depends on SMP
1066 default "4"
1067 help
1068 The maximum number of CPUs that the kernel can support.
1069 Up to 32 CPUs can be supported, or up to 16 if kmap_local()
1070 debugging is enabled, which uses half of the per-CPU fixmap
1071 slots as guard regions.
1072
1073config HOTPLUG_CPU
1074 bool "Support for hot-pluggable CPUs"
1075 depends on SMP
1076 select GENERIC_IRQ_MIGRATION
1077 help
1078 Say Y here to experiment with turning CPUs off and on. CPUs
1079 can be controlled through /sys/devices/system/cpu.
1080
1081config ARM_PSCI
1082 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1083 depends on HAVE_ARM_SMCCC
1084 select ARM_PSCI_FW
1085 help
1086 Say Y here if you want Linux to communicate with system firmware
1087 implementing the PSCI specification for CPU-centric power
1088 management operations described in ARM document number ARM DEN
1089 0022A ("Power State Coordination Interface System Software on
1090 ARM processors").
1091
1092config HZ_FIXED
1093 int
1094 default 128 if SOC_AT91RM9200
1095 default 0
1096
1097choice
1098 depends on HZ_FIXED = 0
1099 prompt "Timer frequency"
1100
1101config HZ_100
1102 bool "100 Hz"
1103
1104config HZ_200
1105 bool "200 Hz"
1106
1107config HZ_250
1108 bool "250 Hz"
1109
1110config HZ_300
1111 bool "300 Hz"
1112
1113config HZ_500
1114 bool "500 Hz"
1115
1116config HZ_1000
1117 bool "1000 Hz"
1118
1119endchoice
1120
1121config HZ
1122 int
1123 default HZ_FIXED if HZ_FIXED != 0
1124 default 100 if HZ_100
1125 default 200 if HZ_200
1126 default 250 if HZ_250
1127 default 300 if HZ_300
1128 default 500 if HZ_500
1129 default 1000
1130
1131config SCHED_HRTICK
1132 def_bool HIGH_RES_TIMERS
1133
1134config THUMB2_KERNEL
1135 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1136 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1137 default y if CPU_THUMBONLY
1138 select ARM_UNWIND
1139 help
1140 By enabling this option, the kernel will be compiled in
1141 Thumb-2 mode.
1142
1143 If unsure, say N.
1144
1145config ARM_PATCH_IDIV
1146 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1147 depends on CPU_32v7
1148 default y
1149 help
1150 The ARM compiler inserts calls to __aeabi_idiv() and
1151 __aeabi_uidiv() when it needs to perform division on signed
1152 and unsigned integers. Some v7 CPUs have support for the sdiv
1153 and udiv instructions that can be used to implement those
1154 functions.
1155
1156 Enabling this option allows the kernel to modify itself to
1157 replace the first two instructions of these library functions
1158 with the sdiv or udiv plus "bx lr" instructions when the CPU
1159 it is running on supports them. Typically this will be faster
1160 and less power intensive than running the original library
1161 code to do integer division.
1162
1163config AEABI
1164 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \
1165 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG
1166 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG
1167 help
1168 This option allows for the kernel to be compiled using the latest
1169 ARM ABI (aka EABI). This is only useful if you are using a user
1170 space environment that is also compiled with EABI.
1171
1172 Since there are major incompatibilities between the legacy ABI and
1173 EABI, especially with regard to structure member alignment, this
1174 option also changes the kernel syscall calling convention to
1175 disambiguate both ABIs and allow for backward compatibility support
1176 (selected with CONFIG_OABI_COMPAT).
1177
1178 To use this you need GCC version 4.0.0 or later.
1179
1180config OABI_COMPAT
1181 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1182 depends on AEABI && !THUMB2_KERNEL
1183 help
1184 This option preserves the old syscall interface along with the
1185 new (ARM EABI) one. It also provides a compatibility layer to
1186 intercept syscalls that have structure arguments which layout
1187 in memory differs between the legacy ABI and the new ARM EABI
1188 (only for non "thumb" binaries). This option adds a tiny
1189 overhead to all syscalls and produces a slightly larger kernel.
1190
1191 The seccomp filter system will not be available when this is
1192 selected, since there is no way yet to sensibly distinguish
1193 between calling conventions during filtering.
1194
1195 If you know you'll be using only pure EABI user space then you
1196 can say N here. If this option is not selected and you attempt
1197 to execute a legacy ABI binary then the result will be
1198 UNPREDICTABLE (in fact it can be predicted that it won't work
1199 at all). If in doubt say N.
1200
1201config ARCH_SELECT_MEMORY_MODEL
1202 def_bool y
1203
1204config ARCH_FLATMEM_ENABLE
1205 def_bool !(ARCH_RPC || ARCH_SA1100)
1206
1207config ARCH_SPARSEMEM_ENABLE
1208 def_bool !ARCH_FOOTBRIDGE
1209 select SPARSEMEM_STATIC if SPARSEMEM
1210
1211config HIGHMEM
1212 bool "High Memory Support"
1213 depends on MMU
1214 select KMAP_LOCAL
1215 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY
1216 help
1217 The address space of ARM processors is only 4 Gigabytes large
1218 and it has to accommodate user address space, kernel address
1219 space as well as some memory mapped IO. That means that, if you
1220 have a large amount of physical memory and/or IO, not all of the
1221 memory can be "permanently mapped" by the kernel. The physical
1222 memory that is not permanently mapped is called "high memory".
1223
1224 Depending on the selected kernel/user memory split, minimum
1225 vmalloc space and actual amount of RAM, you may not need this
1226 option which should result in a slightly faster kernel.
1227
1228 If unsure, say n.
1229
1230config HIGHPTE
1231 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1232 depends on HIGHMEM
1233 default y
1234 help
1235 The VM uses one page of physical memory for each page table.
1236 For systems with a lot of processes, this can use a lot of
1237 precious low memory, eventually leading to low memory being
1238 consumed by page tables. Setting this option will allow
1239 user-space 2nd level page tables to reside in high memory.
1240
1241config ARM_PAN
1242 bool "Enable privileged no-access"
1243 depends on MMU
1244 default y
1245 help
1246 Increase kernel security by ensuring that normal kernel accesses
1247 are unable to access userspace addresses. This can help prevent
1248 use-after-free bugs becoming an exploitable privilege escalation
1249 by ensuring that magic values (such as LIST_POISON) will always
1250 fault when dereferenced.
1251
1252 The implementation uses CPU domains when !CONFIG_ARM_LPAE and
1253 disabling of TTBR0 page table walks with CONFIG_ARM_LPAE.
1254
1255config CPU_SW_DOMAIN_PAN
1256 def_bool y
1257 depends on ARM_PAN && !ARM_LPAE
1258 help
1259 Enable use of CPU domains to implement privileged no-access.
1260
1261 CPUs with low-vector mappings use a best-efforts implementation.
1262 Their lower 1MB needs to remain accessible for the vectors, but
1263 the remainder of userspace will become appropriately inaccessible.
1264
1265config CPU_TTBR0_PAN
1266 def_bool y
1267 depends on ARM_PAN && ARM_LPAE
1268 help
1269 Enable privileged no-access by disabling TTBR0 page table walks when
1270 running in kernel mode.
1271
1272config HW_PERF_EVENTS
1273 def_bool y
1274 depends on ARM_PMU
1275
1276config ARM_MODULE_PLTS
1277 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1278 depends on MODULES
1279 select KASAN_VMALLOC if KASAN
1280 default y
1281 help
1282 Allocate PLTs when loading modules so that jumps and calls whose
1283 targets are too far away for their relative offsets to be encoded
1284 in the instructions themselves can be bounced via veneers in the
1285 module's PLT. This allows modules to be allocated in the generic
1286 vmalloc area after the dedicated module memory area has been
1287 exhausted. The modules will use slightly more memory, but after
1288 rounding up to page size, the actual memory footprint is usually
1289 the same.
1290
1291 Disabling this is usually safe for small single-platform
1292 configurations. If unsure, say y.
1293
1294config ARCH_FORCE_MAX_ORDER
1295 int "Order of maximal physically contiguous allocations"
1296 default "11" if SOC_AM33XX
1297 default "8" if SA1111
1298 default "10"
1299 help
1300 The kernel page allocator limits the size of maximal physically
1301 contiguous allocations. The limit is called MAX_PAGE_ORDER and it
1302 defines the maximal power of two of number of pages that can be
1303 allocated as a single contiguous block. This option allows
1304 overriding the default setting when ability to allocate very
1305 large blocks of physically contiguous memory is required.
1306
1307 Don't change if unsure.
1308
1309config ALIGNMENT_TRAP
1310 def_bool CPU_CP15_MMU
1311 select HAVE_PROC_CPU if PROC_FS
1312 help
1313 ARM processors cannot fetch/store information which is not
1314 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1315 address divisible by 4. On 32-bit ARM processors, these non-aligned
1316 fetch/store instructions will be emulated in software if you say
1317 here, which has a severe performance impact. This is necessary for
1318 correct operation of some network protocols. With an IP-only
1319 configuration it is safe to say N, otherwise say Y.
1320
1321config UACCESS_WITH_MEMCPY
1322 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1323 depends on MMU
1324 default y if CPU_FEROCEON
1325 help
1326 Implement faster copy_to_user and clear_user methods for CPU
1327 cores where a 8-word STM instruction give significantly higher
1328 memory write throughput than a sequence of individual 32bit stores.
1329
1330 A possible side effect is a slight increase in scheduling latency
1331 between threads sharing the same address space if they invoke
1332 such copy operations with large buffers.
1333
1334 However, if the CPU data cache is using a write-allocate mode,
1335 this option is unlikely to provide any performance gain.
1336
1337config PARAVIRT
1338 bool "Enable paravirtualization code"
1339 help
1340 This changes the kernel so it can modify itself when it is run
1341 under a hypervisor, potentially improving performance significantly
1342 over full virtualization.
1343
1344config PARAVIRT_TIME_ACCOUNTING
1345 bool "Paravirtual steal time accounting"
1346 select PARAVIRT
1347 help
1348 Select this option to enable fine granularity task steal time
1349 accounting. Time spent executing other tasks in parallel with
1350 the current vCPU is discounted from the vCPU power. To account for
1351 that, there can be a small performance impact.
1352
1353 If in doubt, say N here.
1354
1355config XEN_DOM0
1356 def_bool y
1357 depends on XEN
1358
1359config XEN
1360 bool "Xen guest support on ARM"
1361 depends on ARM && AEABI && OF
1362 depends on CPU_V7 && !CPU_V6
1363 depends on !GENERIC_ATOMIC64
1364 depends on MMU
1365 select ARCH_DMA_ADDR_T_64BIT
1366 select ARM_PSCI
1367 select SWIOTLB
1368 select SWIOTLB_XEN
1369 select PARAVIRT
1370 help
1371 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1372
1373config CC_HAVE_STACKPROTECTOR_TLS
1374 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0)
1375
1376config STACKPROTECTOR_PER_TASK
1377 bool "Use a unique stack canary value for each task"
1378 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA
1379 depends on GCC_PLUGINS || CC_HAVE_STACKPROTECTOR_TLS
1380 select GCC_PLUGIN_ARM_SSP_PER_TASK if !CC_HAVE_STACKPROTECTOR_TLS
1381 default y
1382 help
1383 Due to the fact that GCC uses an ordinary symbol reference from
1384 which to load the value of the stack canary, this value can only
1385 change at reboot time on SMP systems, and all tasks running in the
1386 kernel's address space are forced to use the same canary value for
1387 the entire duration that the system is up.
1388
1389 Enable this option to switch to a different method that uses a
1390 different canary value for each task.
1391
1392endmenu
1393
1394menu "Boot options"
1395
1396config USE_OF
1397 bool "Flattened Device Tree support"
1398 select IRQ_DOMAIN
1399 select OF
1400 help
1401 Include support for flattened device tree machine descriptions.
1402
1403config ARCH_WANT_FLAT_DTB_INSTALL
1404 def_bool y
1405
1406config ATAGS
1407 bool "Support for the traditional ATAGS boot data passing"
1408 default y
1409 help
1410 This is the traditional way of passing data to the kernel at boot
1411 time. If you are solely relying on the flattened device tree (or
1412 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1413 to remove ATAGS support from your kernel binary.
1414
1415config DEPRECATED_PARAM_STRUCT
1416 bool "Provide old way to pass kernel parameters"
1417 depends on ATAGS
1418 help
1419 This was deprecated in 2001 and announced to live on for 5 years.
1420 Some old boot loaders still use this way.
1421
1422# Compressed boot loader in ROM. Yes, we really want to ask about
1423# TEXT and BSS so we preserve their values in the config files.
1424config ZBOOT_ROM_TEXT
1425 hex "Compressed ROM boot loader base address"
1426 default 0x0
1427 help
1428 The physical address at which the ROM-able zImage is to be
1429 placed in the target. Platforms which normally make use of
1430 ROM-able zImage formats normally set this to a suitable
1431 value in their defconfig file.
1432
1433 If ZBOOT_ROM is not enabled, this has no effect.
1434
1435config ZBOOT_ROM_BSS
1436 hex "Compressed ROM boot loader BSS address"
1437 default 0x0
1438 help
1439 The base address of an area of read/write memory in the target
1440 for the ROM-able zImage which must be available while the
1441 decompressor is running. It must be large enough to hold the
1442 entire decompressed kernel plus an additional 128 KiB.
1443 Platforms which normally make use of ROM-able zImage formats
1444 normally set this to a suitable value in their defconfig file.
1445
1446 If ZBOOT_ROM is not enabled, this has no effect.
1447
1448config ZBOOT_ROM
1449 bool "Compressed boot loader in ROM/flash"
1450 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1451 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1452 help
1453 Say Y here if you intend to execute your compressed kernel image
1454 (zImage) directly from ROM or flash. If unsure, say N.
1455
1456config ARM_APPENDED_DTB
1457 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1458 depends on OF
1459 help
1460 With this option, the boot code will look for a device tree binary
1461 (DTB) appended to zImage
1462 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1463
1464 This is meant as a backward compatibility convenience for those
1465 systems with a bootloader that can't be upgraded to accommodate
1466 the documented boot protocol using a device tree.
1467
1468 Beware that there is very little in terms of protection against
1469 this option being confused by leftover garbage in memory that might
1470 look like a DTB header after a reboot if no actual DTB is appended
1471 to zImage. Do not leave this option active in a production kernel
1472 if you don't intend to always append a DTB. Proper passing of the
1473 location into r2 of a bootloader provided DTB is always preferable
1474 to this option.
1475
1476config ARM_ATAG_DTB_COMPAT
1477 bool "Supplement the appended DTB with traditional ATAG information"
1478 depends on ARM_APPENDED_DTB
1479 help
1480 Some old bootloaders can't be updated to a DTB capable one, yet
1481 they provide ATAGs with memory configuration, the ramdisk address,
1482 the kernel cmdline string, etc. Such information is dynamically
1483 provided by the bootloader and can't always be stored in a static
1484 DTB. To allow a device tree enabled kernel to be used with such
1485 bootloaders, this option allows zImage to extract the information
1486 from the ATAG list and store it at run time into the appended DTB.
1487
1488choice
1489 prompt "Kernel command line type"
1490 depends on ARM_ATAG_DTB_COMPAT
1491 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1492
1493config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1494 bool "Use bootloader kernel arguments if available"
1495 help
1496 Uses the command-line options passed by the boot loader instead of
1497 the device tree bootargs property. If the boot loader doesn't provide
1498 any, the device tree bootargs property will be used.
1499
1500config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1501 bool "Extend with bootloader kernel arguments"
1502 help
1503 The command-line arguments provided by the boot loader will be
1504 appended to the the device tree bootargs property.
1505
1506endchoice
1507
1508config CMDLINE
1509 string "Default kernel command string"
1510 default ""
1511 help
1512 On some architectures (e.g. CATS), there is currently no way
1513 for the boot loader to pass arguments to the kernel. For these
1514 architectures, you should supply some command-line options at build
1515 time by entering them here. As a minimum, you should specify the
1516 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1517
1518choice
1519 prompt "Kernel command line type"
1520 depends on CMDLINE != ""
1521 default CMDLINE_FROM_BOOTLOADER
1522
1523config CMDLINE_FROM_BOOTLOADER
1524 bool "Use bootloader kernel arguments if available"
1525 help
1526 Uses the command-line options passed by the boot loader. If
1527 the boot loader doesn't provide any, the default kernel command
1528 string provided in CMDLINE will be used.
1529
1530config CMDLINE_EXTEND
1531 bool "Extend bootloader kernel arguments"
1532 help
1533 The command-line arguments provided by the boot loader will be
1534 appended to the default kernel command string.
1535
1536config CMDLINE_FORCE
1537 bool "Always use the default kernel command string"
1538 help
1539 Always use the default kernel command string, even if the boot
1540 loader passes other arguments to the kernel.
1541 This is useful if you cannot or don't want to change the
1542 command-line options your boot loader passes to the kernel.
1543endchoice
1544
1545config XIP_KERNEL
1546 bool "Kernel Execute-In-Place from ROM"
1547 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1548 depends on !ARM_PATCH_IDIV && !ARM_PATCH_PHYS_VIRT && !SMP_ON_UP
1549 help
1550 Execute-In-Place allows the kernel to run from non-volatile storage
1551 directly addressable by the CPU, such as NOR flash. This saves RAM
1552 space since the text section of the kernel is not loaded from flash
1553 to RAM. Read-write sections, such as the data section and stack,
1554 are still copied to RAM. The XIP kernel is not compressed since
1555 it has to run directly from flash, so it will take more space to
1556 store it. The flash address used to link the kernel object files,
1557 and for storing it, is configuration dependent. Therefore, if you
1558 say Y here, you must know the proper physical address where to
1559 store the kernel image depending on your own flash memory usage.
1560
1561 Also note that the make target becomes "make xipImage" rather than
1562 "make zImage" or "make Image". The final kernel binary to put in
1563 ROM memory will be arch/arm/boot/xipImage.
1564
1565 If unsure, say N.
1566
1567config XIP_PHYS_ADDR
1568 hex "XIP Kernel Physical Location"
1569 depends on XIP_KERNEL
1570 default "0x00080000"
1571 help
1572 This is the physical address in your flash memory the kernel will
1573 be linked for and stored to. This address is dependent on your
1574 own flash usage.
1575
1576config XIP_DEFLATED_DATA
1577 bool "Store kernel .data section compressed in ROM"
1578 depends on XIP_KERNEL
1579 select ZLIB_INFLATE
1580 help
1581 Before the kernel is actually executed, its .data section has to be
1582 copied to RAM from ROM. This option allows for storing that data
1583 in compressed form and decompressed to RAM rather than merely being
1584 copied, saving some precious ROM space. A possible drawback is a
1585 slightly longer boot delay.
1586
1587config ARCH_SUPPORTS_KEXEC
1588 def_bool (!SMP || PM_SLEEP_SMP) && MMU
1589
1590config ATAGS_PROC
1591 bool "Export atags in procfs"
1592 depends on ATAGS && KEXEC
1593 default y
1594 help
1595 Should the atags used to boot the kernel be exported in an "atags"
1596 file in procfs. Useful with kexec.
1597
1598config ARCH_SUPPORTS_CRASH_DUMP
1599 def_bool y
1600
1601config ARCH_DEFAULT_CRASH_DUMP
1602 def_bool y
1603
1604config AUTO_ZRELADDR
1605 bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM
1606 default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
1607 help
1608 ZRELADDR is the physical address where the decompressed kernel
1609 image will be placed. If AUTO_ZRELADDR is selected, the address
1610 will be determined at run-time, either by masking the current IP
1611 with 0xf8000000, or, if invalid, from the DTB passed in r2.
1612 This assumes the zImage being placed in the first 128MB from
1613 start of memory.
1614
1615config EFI_STUB
1616 bool
1617
1618config EFI
1619 bool "UEFI runtime support"
1620 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
1621 select UCS2_STRING
1622 select EFI_PARAMS_FROM_FDT
1623 select EFI_STUB
1624 select EFI_GENERIC_STUB
1625 select EFI_RUNTIME_WRAPPERS
1626 help
1627 This option provides support for runtime services provided
1628 by UEFI firmware (such as non-volatile variables, realtime
1629 clock, and platform reset). A UEFI stub is also provided to
1630 allow the kernel to be booted as an EFI application. This
1631 is only useful for kernels that may run on systems that have
1632 UEFI firmware.
1633
1634config DMI
1635 bool "Enable support for SMBIOS (DMI) tables"
1636 depends on EFI
1637 default y
1638 help
1639 This enables SMBIOS/DMI feature for systems.
1640
1641 This option is only useful on systems that have UEFI firmware.
1642 However, even with this option, the resultant kernel should
1643 continue to boot on existing non-UEFI platforms.
1644
1645 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
1646 i.e., the the practice of identifying the platform via DMI to
1647 decide whether certain workarounds for buggy hardware and/or
1648 firmware need to be enabled. This would require the DMI subsystem
1649 to be enabled much earlier than we do on ARM, which is non-trivial.
1650
1651endmenu
1652
1653menu "CPU Power Management"
1654
1655source "drivers/cpufreq/Kconfig"
1656
1657source "drivers/cpuidle/Kconfig"
1658
1659endmenu
1660
1661menu "Floating point emulation"
1662
1663comment "At least one emulation must be selected"
1664
1665config FPE_NWFPE
1666 bool "NWFPE math emulation"
1667 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1668 help
1669 Say Y to include the NWFPE floating point emulator in the kernel.
1670 This is necessary to run most binaries. Linux does not currently
1671 support floating point hardware so you need to say Y here even if
1672 your machine has an FPA or floating point co-processor podule.
1673
1674 You may say N here if you are going to load the Acorn FPEmulator
1675 early in the bootup.
1676
1677config FPE_NWFPE_XP
1678 bool "Support extended precision"
1679 depends on FPE_NWFPE
1680 help
1681 Say Y to include 80-bit support in the kernel floating-point
1682 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1683 Note that gcc does not generate 80-bit operations by default,
1684 so in most cases this option only enlarges the size of the
1685 floating point emulator without any good reason.
1686
1687 You almost surely want to say N here.
1688
1689config FPE_FASTFPE
1690 bool "FastFPE math emulation (EXPERIMENTAL)"
1691 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
1692 help
1693 Say Y here to include the FAST floating point emulator in the kernel.
1694 This is an experimental much faster emulator which now also has full
1695 precision for the mantissa. It does not support any exceptions.
1696 It is very simple, and approximately 3-6 times faster than NWFPE.
1697
1698 It should be sufficient for most programs. It may be not suitable
1699 for scientific calculations, but you have to check this for yourself.
1700 If you do not feel you need a faster FP emulation you should better
1701 choose NWFPE.
1702
1703config VFP
1704 bool "VFP-format floating point maths"
1705 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1706 help
1707 Say Y to include VFP support code in the kernel. This is needed
1708 if your hardware includes a VFP unit.
1709
1710 Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for
1711 release notes and additional status information.
1712
1713 Say N if your target does not have VFP hardware.
1714
1715config VFPv3
1716 bool
1717 depends on VFP
1718 default y if CPU_V7
1719
1720config NEON
1721 bool "Advanced SIMD (NEON) Extension support"
1722 depends on VFPv3 && CPU_V7
1723 help
1724 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1725 Extension.
1726
1727config KERNEL_MODE_NEON
1728 bool "Support for NEON in kernel mode"
1729 depends on NEON && AEABI
1730 help
1731 Say Y to include support for NEON in kernel mode.
1732
1733endmenu
1734
1735menu "Power management options"
1736
1737source "kernel/power/Kconfig"
1738
1739config ARCH_SUSPEND_POSSIBLE
1740 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
1741 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
1742 def_bool y
1743
1744config ARM_CPU_SUSPEND
1745 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
1746 depends on ARCH_SUSPEND_POSSIBLE
1747
1748config ARCH_HIBERNATION_POSSIBLE
1749 bool
1750 depends on MMU
1751 default y if ARCH_SUSPEND_POSSIBLE
1752
1753endmenu
1754
1755source "arch/arm/Kconfig.assembler"
1config ARM
2 bool
3 default y
4 select HAVE_AOUT
5 select HAVE_DMA_API_DEBUG
6 select HAVE_IDE
7 select HAVE_MEMBLOCK
8 select RTC_LIB
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
12 select HAVE_ARCH_KGDB
13 select HAVE_KPROBES if !XIP_KERNEL
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
23 select HAVE_IRQ_WORK
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
32 help
33 The ARM series is a line of low-power-consumption RISC chip designs
34 licensed by ARM Ltd and targeted at embedded applications and
35 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
36 manufactured, but legacy ARM-based PC hardware remains popular in
37 Europe. There is an ARM Linux project with a web page at
38 <http://www.arm.linux.org.uk/>.
39
40config ARM_HAS_SG_CHAIN
41 bool
42
43config HAVE_PWM
44 bool
45
46config MIGHT_HAVE_PCI
47 bool
48
49config SYS_SUPPORTS_APM_EMULATION
50 bool
51
52config HAVE_SCHED_CLOCK
53 bool
54
55config GENERIC_GPIO
56 bool
57
58config ARCH_USES_GETTIMEOFFSET
59 bool
60 default n
61
62config GENERIC_CLOCKEVENTS
63 bool
64
65config GENERIC_CLOCKEVENTS_BROADCAST
66 bool
67 depends on GENERIC_CLOCKEVENTS
68 default y if SMP
69
70config KTIME_SCALAR
71 bool
72 default y
73
74config HAVE_TCM
75 bool
76 select GENERIC_ALLOCATOR
77
78config HAVE_PROC_CPU
79 bool
80
81config NO_IOPORT
82 bool
83
84config EISA
85 bool
86 ---help---
87 The Extended Industry Standard Architecture (EISA) bus was
88 developed as an open alternative to the IBM MicroChannel bus.
89
90 The EISA bus provided some of the features of the IBM MicroChannel
91 bus while maintaining backward compatibility with cards made for
92 the older ISA bus. The EISA bus saw limited use between 1988 and
93 1995 when it was made obsolete by the PCI bus.
94
95 Say Y here if you are building a kernel for an EISA-based machine.
96
97 Otherwise, say N.
98
99config SBUS
100 bool
101
102config MCA
103 bool
104 help
105 MicroChannel Architecture is found in some IBM PS/2 machines and
106 laptops. It is a bus system similar to PCI or ISA. See
107 <file:Documentation/mca.txt> (and especially the web page given
108 there) before attempting to build an MCA bus kernel.
109
110config STACKTRACE_SUPPORT
111 bool
112 default y
113
114config HAVE_LATENCYTOP_SUPPORT
115 bool
116 depends on !SMP
117 default y
118
119config LOCKDEP_SUPPORT
120 bool
121 default y
122
123config TRACE_IRQFLAGS_SUPPORT
124 bool
125 default y
126
127config HARDIRQS_SW_RESEND
128 bool
129 default y
130
131config GENERIC_IRQ_PROBE
132 bool
133 default y
134
135config GENERIC_LOCKBREAK
136 bool
137 default y
138 depends on SMP && PREEMPT
139
140config RWSEM_GENERIC_SPINLOCK
141 bool
142 default y
143
144config RWSEM_XCHGADD_ALGORITHM
145 bool
146
147config ARCH_HAS_ILOG2_U32
148 bool
149
150config ARCH_HAS_ILOG2_U64
151 bool
152
153config ARCH_HAS_CPUFREQ
154 bool
155 help
156 Internal node to signify that the ARCH has CPUFREQ support
157 and that the relevant menu configurations are displayed for
158 it.
159
160config ARCH_HAS_CPU_IDLE_WAIT
161 def_bool y
162
163config GENERIC_HWEIGHT
164 bool
165 default y
166
167config GENERIC_CALIBRATE_DELAY
168 bool
169 default y
170
171config ARCH_MAY_HAVE_PC_FDC
172 bool
173
174config ZONE_DMA
175 bool
176
177config NEED_DMA_MAP_STATE
178 def_bool y
179
180config GENERIC_ISA_DMA
181 bool
182
183config FIQ
184 bool
185
186config ARCH_MTD_XIP
187 bool
188
189config VECTORS_BASE
190 hex
191 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
192 default DRAM_BASE if REMAP_VECTORS_TO_RAM
193 default 0x00000000
194 help
195 The base address of exception vectors.
196
197config ARM_PATCH_PHYS_VIRT
198 bool "Patch physical to virtual translations at runtime"
199 depends on !XIP_KERNEL && MMU
200 depends on !ARCH_REALVIEW || !SPARSEMEM
201 help
202 Patch phys-to-virt and virt-to-phys translation functions at
203 boot and module load time according to the position of the
204 kernel in system memory.
205
206 This can only be used with non-XIP MMU kernels where the base
207 of physical memory is at a 16MB boundary, or theoretically 64K
208 for the MSM machine class.
209
210config ARM_PATCH_PHYS_VIRT_16BIT
211 def_bool y
212 depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM
213 help
214 This option extends the physical to virtual translation patching
215 to allow physical memory down to a theoretical minimum of 64K
216 boundaries.
217
218source "init/Kconfig"
219
220source "kernel/Kconfig.freezer"
221
222menu "System Type"
223
224config MMU
225 bool "MMU-based Paged Memory Management Support"
226 default y
227 help
228 Select if you want MMU-based virtualised addressing space
229 support by paged memory management. If unsure, say 'Y'.
230
231#
232# The "ARM system type" choice list is ordered alphabetically by option
233# text. Please add new entries in the option alphabetic order.
234#
235choice
236 prompt "ARM system type"
237 default ARCH_VERSATILE
238
239config ARCH_INTEGRATOR
240 bool "ARM Ltd. Integrator family"
241 select ARM_AMBA
242 select ARCH_HAS_CPUFREQ
243 select CLKDEV_LOOKUP
244 select HAVE_MACH_CLKDEV
245 select ICST
246 select GENERIC_CLOCKEVENTS
247 select PLAT_VERSATILE
248 select PLAT_VERSATILE_FPGA_IRQ
249 help
250 Support for ARM's Integrator platform.
251
252config ARCH_REALVIEW
253 bool "ARM Ltd. RealView family"
254 select ARM_AMBA
255 select CLKDEV_LOOKUP
256 select HAVE_MACH_CLKDEV
257 select ICST
258 select GENERIC_CLOCKEVENTS
259 select ARCH_WANT_OPTIONAL_GPIOLIB
260 select PLAT_VERSATILE
261 select PLAT_VERSATILE_CLCD
262 select ARM_TIMER_SP804
263 select GPIO_PL061 if GPIOLIB
264 help
265 This enables support for ARM Ltd RealView boards.
266
267config ARCH_VERSATILE
268 bool "ARM Ltd. Versatile family"
269 select ARM_AMBA
270 select ARM_VIC
271 select CLKDEV_LOOKUP
272 select HAVE_MACH_CLKDEV
273 select ICST
274 select GENERIC_CLOCKEVENTS
275 select ARCH_WANT_OPTIONAL_GPIOLIB
276 select PLAT_VERSATILE
277 select PLAT_VERSATILE_CLCD
278 select PLAT_VERSATILE_FPGA_IRQ
279 select ARM_TIMER_SP804
280 help
281 This enables support for ARM Ltd Versatile board.
282
283config ARCH_VEXPRESS
284 bool "ARM Ltd. Versatile Express family"
285 select ARCH_WANT_OPTIONAL_GPIOLIB
286 select ARM_AMBA
287 select ARM_TIMER_SP804
288 select CLKDEV_LOOKUP
289 select HAVE_MACH_CLKDEV
290 select GENERIC_CLOCKEVENTS
291 select HAVE_CLK
292 select HAVE_PATA_PLATFORM
293 select ICST
294 select PLAT_VERSATILE
295 select PLAT_VERSATILE_CLCD
296 help
297 This enables support for the ARM Ltd Versatile Express boards.
298
299config ARCH_AT91
300 bool "Atmel AT91"
301 select ARCH_REQUIRE_GPIOLIB
302 select HAVE_CLK
303 select CLKDEV_LOOKUP
304 select ARM_PATCH_PHYS_VIRT if MMU
305 help
306 This enables support for systems based on the Atmel AT91RM9200,
307 AT91SAM9 and AT91CAP9 processors.
308
309config ARCH_BCMRING
310 bool "Broadcom BCMRING"
311 depends on MMU
312 select CPU_V6
313 select ARM_AMBA
314 select ARM_TIMER_SP804
315 select CLKDEV_LOOKUP
316 select GENERIC_CLOCKEVENTS
317 select ARCH_WANT_OPTIONAL_GPIOLIB
318 help
319 Support for Broadcom's BCMRing platform.
320
321config ARCH_CLPS711X
322 bool "Cirrus Logic CLPS711x/EP721x-based"
323 select CPU_ARM720T
324 select ARCH_USES_GETTIMEOFFSET
325 help
326 Support for Cirrus Logic 711x/721x based boards.
327
328config ARCH_CNS3XXX
329 bool "Cavium Networks CNS3XXX family"
330 select CPU_V6K
331 select GENERIC_CLOCKEVENTS
332 select ARM_GIC
333 select MIGHT_HAVE_PCI
334 select PCI_DOMAINS if PCI
335 help
336 Support for Cavium Networks CNS3XXX platform.
337
338config ARCH_GEMINI
339 bool "Cortina Systems Gemini"
340 select CPU_FA526
341 select ARCH_REQUIRE_GPIOLIB
342 select ARCH_USES_GETTIMEOFFSET
343 help
344 Support for the Cortina Systems Gemini family SoCs
345
346config ARCH_PRIMA2
347 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
348 select CPU_V7
349 select GENERIC_TIME
350 select NO_IOPORT
351 select GENERIC_CLOCKEVENTS
352 select CLKDEV_LOOKUP
353 select GENERIC_IRQ_CHIP
354 select USE_OF
355 select ZONE_DMA
356 help
357 Support for CSR SiRFSoC ARM Cortex A9 Platform
358
359config ARCH_EBSA110
360 bool "EBSA-110"
361 select CPU_SA110
362 select ISA
363 select NO_IOPORT
364 select ARCH_USES_GETTIMEOFFSET
365 help
366 This is an evaluation board for the StrongARM processor available
367 from Digital. It has limited hardware on-board, including an
368 Ethernet interface, two PCMCIA sockets, two serial ports and a
369 parallel port.
370
371config ARCH_EP93XX
372 bool "EP93xx-based"
373 select CPU_ARM920T
374 select ARM_AMBA
375 select ARM_VIC
376 select CLKDEV_LOOKUP
377 select ARCH_REQUIRE_GPIOLIB
378 select ARCH_HAS_HOLES_MEMORYMODEL
379 select ARCH_USES_GETTIMEOFFSET
380 help
381 This enables support for the Cirrus EP93xx series of CPUs.
382
383config ARCH_FOOTBRIDGE
384 bool "FootBridge"
385 select CPU_SA110
386 select FOOTBRIDGE
387 select GENERIC_CLOCKEVENTS
388 help
389 Support for systems based on the DC21285 companion chip
390 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
391
392config ARCH_MXC
393 bool "Freescale MXC/iMX-based"
394 select GENERIC_CLOCKEVENTS
395 select ARCH_REQUIRE_GPIOLIB
396 select CLKDEV_LOOKUP
397 select CLKSRC_MMIO
398 select GENERIC_IRQ_CHIP
399 select HAVE_SCHED_CLOCK
400 help
401 Support for Freescale MXC/iMX-based family of processors
402
403config ARCH_MXS
404 bool "Freescale MXS-based"
405 select GENERIC_CLOCKEVENTS
406 select ARCH_REQUIRE_GPIOLIB
407 select CLKDEV_LOOKUP
408 select CLKSRC_MMIO
409 help
410 Support for Freescale MXS-based family of processors
411
412config ARCH_NETX
413 bool "Hilscher NetX based"
414 select CLKSRC_MMIO
415 select CPU_ARM926T
416 select ARM_VIC
417 select GENERIC_CLOCKEVENTS
418 help
419 This enables support for systems based on the Hilscher NetX Soc
420
421config ARCH_H720X
422 bool "Hynix HMS720x-based"
423 select CPU_ARM720T
424 select ISA_DMA_API
425 select ARCH_USES_GETTIMEOFFSET
426 help
427 This enables support for systems based on the Hynix HMS720x
428
429config ARCH_IOP13XX
430 bool "IOP13xx-based"
431 depends on MMU
432 select CPU_XSC3
433 select PLAT_IOP
434 select PCI
435 select ARCH_SUPPORTS_MSI
436 select VMSPLIT_1G
437 help
438 Support for Intel's IOP13XX (XScale) family of processors.
439
440config ARCH_IOP32X
441 bool "IOP32x-based"
442 depends on MMU
443 select CPU_XSCALE
444 select PLAT_IOP
445 select PCI
446 select ARCH_REQUIRE_GPIOLIB
447 help
448 Support for Intel's 80219 and IOP32X (XScale) family of
449 processors.
450
451config ARCH_IOP33X
452 bool "IOP33x-based"
453 depends on MMU
454 select CPU_XSCALE
455 select PLAT_IOP
456 select PCI
457 select ARCH_REQUIRE_GPIOLIB
458 help
459 Support for Intel's IOP33X (XScale) family of processors.
460
461config ARCH_IXP23XX
462 bool "IXP23XX-based"
463 depends on MMU
464 select CPU_XSC3
465 select PCI
466 select ARCH_USES_GETTIMEOFFSET
467 help
468 Support for Intel's IXP23xx (XScale) family of processors.
469
470config ARCH_IXP2000
471 bool "IXP2400/2800-based"
472 depends on MMU
473 select CPU_XSCALE
474 select PCI
475 select ARCH_USES_GETTIMEOFFSET
476 help
477 Support for Intel's IXP2400/2800 (XScale) family of processors.
478
479config ARCH_IXP4XX
480 bool "IXP4xx-based"
481 depends on MMU
482 select CLKSRC_MMIO
483 select CPU_XSCALE
484 select GENERIC_GPIO
485 select GENERIC_CLOCKEVENTS
486 select HAVE_SCHED_CLOCK
487 select MIGHT_HAVE_PCI
488 select DMABOUNCE if PCI
489 help
490 Support for Intel's IXP4XX (XScale) family of processors.
491
492config ARCH_DOVE
493 bool "Marvell Dove"
494 select CPU_V7
495 select PCI
496 select ARCH_REQUIRE_GPIOLIB
497 select GENERIC_CLOCKEVENTS
498 select PLAT_ORION
499 help
500 Support for the Marvell Dove SoC 88AP510
501
502config ARCH_KIRKWOOD
503 bool "Marvell Kirkwood"
504 select CPU_FEROCEON
505 select PCI
506 select ARCH_REQUIRE_GPIOLIB
507 select GENERIC_CLOCKEVENTS
508 select PLAT_ORION
509 help
510 Support for the following Marvell Kirkwood series SoCs:
511 88F6180, 88F6192 and 88F6281.
512
513config ARCH_LPC32XX
514 bool "NXP LPC32XX"
515 select CLKSRC_MMIO
516 select CPU_ARM926T
517 select ARCH_REQUIRE_GPIOLIB
518 select HAVE_IDE
519 select ARM_AMBA
520 select USB_ARCH_HAS_OHCI
521 select CLKDEV_LOOKUP
522 select GENERIC_TIME
523 select GENERIC_CLOCKEVENTS
524 help
525 Support for the NXP LPC32XX family of processors
526
527config ARCH_MV78XX0
528 bool "Marvell MV78xx0"
529 select CPU_FEROCEON
530 select PCI
531 select ARCH_REQUIRE_GPIOLIB
532 select GENERIC_CLOCKEVENTS
533 select PLAT_ORION
534 help
535 Support for the following Marvell MV78xx0 series SoCs:
536 MV781x0, MV782x0.
537
538config ARCH_ORION5X
539 bool "Marvell Orion"
540 depends on MMU
541 select CPU_FEROCEON
542 select PCI
543 select ARCH_REQUIRE_GPIOLIB
544 select GENERIC_CLOCKEVENTS
545 select PLAT_ORION
546 help
547 Support for the following Marvell Orion 5x series SoCs:
548 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
549 Orion-2 (5281), Orion-1-90 (6183).
550
551config ARCH_MMP
552 bool "Marvell PXA168/910/MMP2"
553 depends on MMU
554 select ARCH_REQUIRE_GPIOLIB
555 select CLKDEV_LOOKUP
556 select GENERIC_CLOCKEVENTS
557 select HAVE_SCHED_CLOCK
558 select TICK_ONESHOT
559 select PLAT_PXA
560 select SPARSE_IRQ
561 help
562 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
563
564config ARCH_KS8695
565 bool "Micrel/Kendin KS8695"
566 select CPU_ARM922T
567 select ARCH_REQUIRE_GPIOLIB
568 select ARCH_USES_GETTIMEOFFSET
569 help
570 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
571 System-on-Chip devices.
572
573config ARCH_W90X900
574 bool "Nuvoton W90X900 CPU"
575 select CPU_ARM926T
576 select ARCH_REQUIRE_GPIOLIB
577 select CLKDEV_LOOKUP
578 select CLKSRC_MMIO
579 select GENERIC_CLOCKEVENTS
580 help
581 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
582 At present, the w90x900 has been renamed nuc900, regarding
583 the ARM series product line, you can login the following
584 link address to know more.
585
586 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
587 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
588
589config ARCH_NUC93X
590 bool "Nuvoton NUC93X CPU"
591 select CPU_ARM926T
592 select CLKDEV_LOOKUP
593 help
594 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
595 low-power and high performance MPEG-4/JPEG multimedia controller chip.
596
597config ARCH_TEGRA
598 bool "NVIDIA Tegra"
599 select CLKDEV_LOOKUP
600 select CLKSRC_MMIO
601 select GENERIC_TIME
602 select GENERIC_CLOCKEVENTS
603 select GENERIC_GPIO
604 select HAVE_CLK
605 select HAVE_SCHED_CLOCK
606 select ARCH_HAS_CPUFREQ
607 help
608 This enables support for NVIDIA Tegra based systems (Tegra APX,
609 Tegra 6xx and Tegra 2 series).
610
611config ARCH_PNX4008
612 bool "Philips Nexperia PNX4008 Mobile"
613 select CPU_ARM926T
614 select CLKDEV_LOOKUP
615 select ARCH_USES_GETTIMEOFFSET
616 help
617 This enables support for Philips PNX4008 mobile platform.
618
619config ARCH_PXA
620 bool "PXA2xx/PXA3xx-based"
621 depends on MMU
622 select ARCH_MTD_XIP
623 select ARCH_HAS_CPUFREQ
624 select CLKDEV_LOOKUP
625 select CLKSRC_MMIO
626 select ARCH_REQUIRE_GPIOLIB
627 select GENERIC_CLOCKEVENTS
628 select HAVE_SCHED_CLOCK
629 select TICK_ONESHOT
630 select PLAT_PXA
631 select SPARSE_IRQ
632 select AUTO_ZRELADDR
633 select MULTI_IRQ_HANDLER
634 help
635 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
636
637config ARCH_MSM
638 bool "Qualcomm MSM"
639 select HAVE_CLK
640 select GENERIC_CLOCKEVENTS
641 select ARCH_REQUIRE_GPIOLIB
642 select CLKDEV_LOOKUP
643 help
644 Support for Qualcomm MSM/QSD based systems. This runs on the
645 apps processor of the MSM/QSD and depends on a shared memory
646 interface to the modem processor which runs the baseband
647 stack and controls some vital subsystems
648 (clock and power control, etc).
649
650config ARCH_SHMOBILE
651 bool "Renesas SH-Mobile / R-Mobile"
652 select HAVE_CLK
653 select CLKDEV_LOOKUP
654 select HAVE_MACH_CLKDEV
655 select GENERIC_CLOCKEVENTS
656 select NO_IOPORT
657 select SPARSE_IRQ
658 select MULTI_IRQ_HANDLER
659 select PM_GENERIC_DOMAINS if PM
660 help
661 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
662
663config ARCH_RPC
664 bool "RiscPC"
665 select ARCH_ACORN
666 select FIQ
667 select TIMER_ACORN
668 select ARCH_MAY_HAVE_PC_FDC
669 select HAVE_PATA_PLATFORM
670 select ISA_DMA_API
671 select NO_IOPORT
672 select ARCH_SPARSEMEM_ENABLE
673 select ARCH_USES_GETTIMEOFFSET
674 help
675 On the Acorn Risc-PC, Linux can support the internal IDE disk and
676 CD-ROM interface, serial and parallel port, and the floppy drive.
677
678config ARCH_SA1100
679 bool "SA1100-based"
680 select CLKSRC_MMIO
681 select CPU_SA1100
682 select ISA
683 select ARCH_SPARSEMEM_ENABLE
684 select ARCH_MTD_XIP
685 select ARCH_HAS_CPUFREQ
686 select CPU_FREQ
687 select GENERIC_CLOCKEVENTS
688 select HAVE_CLK
689 select HAVE_SCHED_CLOCK
690 select TICK_ONESHOT
691 select ARCH_REQUIRE_GPIOLIB
692 help
693 Support for StrongARM 11x0 based boards.
694
695config ARCH_S3C2410
696 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
697 select GENERIC_GPIO
698 select ARCH_HAS_CPUFREQ
699 select HAVE_CLK
700 select CLKDEV_LOOKUP
701 select ARCH_USES_GETTIMEOFFSET
702 select HAVE_S3C2410_I2C if I2C
703 help
704 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
705 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
706 the Samsung SMDK2410 development board (and derivatives).
707
708 Note, the S3C2416 and the S3C2450 are so close that they even share
709 the same SoC ID code. This means that there is no separate machine
710 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
711
712config ARCH_S3C64XX
713 bool "Samsung S3C64XX"
714 select PLAT_SAMSUNG
715 select CPU_V6
716 select ARM_VIC
717 select HAVE_CLK
718 select CLKDEV_LOOKUP
719 select NO_IOPORT
720 select ARCH_USES_GETTIMEOFFSET
721 select ARCH_HAS_CPUFREQ
722 select ARCH_REQUIRE_GPIOLIB
723 select SAMSUNG_CLKSRC
724 select SAMSUNG_IRQ_VIC_TIMER
725 select SAMSUNG_IRQ_UART
726 select S3C_GPIO_TRACK
727 select S3C_GPIO_PULL_UPDOWN
728 select S3C_GPIO_CFG_S3C24XX
729 select S3C_GPIO_CFG_S3C64XX
730 select S3C_DEV_NAND
731 select USB_ARCH_HAS_OHCI
732 select SAMSUNG_GPIOLIB_4BIT
733 select HAVE_S3C2410_I2C if I2C
734 select HAVE_S3C2410_WATCHDOG if WATCHDOG
735 help
736 Samsung S3C64XX series based systems
737
738config ARCH_S5P64X0
739 bool "Samsung S5P6440 S5P6450"
740 select CPU_V6
741 select GENERIC_GPIO
742 select HAVE_CLK
743 select CLKDEV_LOOKUP
744 select CLKSRC_MMIO
745 select HAVE_S3C2410_WATCHDOG if WATCHDOG
746 select GENERIC_CLOCKEVENTS
747 select HAVE_SCHED_CLOCK
748 select HAVE_S3C2410_I2C if I2C
749 select HAVE_S3C_RTC if RTC_CLASS
750 help
751 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
752 SMDK6450.
753
754config ARCH_S5PC100
755 bool "Samsung S5PC100"
756 select GENERIC_GPIO
757 select HAVE_CLK
758 select CLKDEV_LOOKUP
759 select CPU_V7
760 select ARM_L1_CACHE_SHIFT_6
761 select ARCH_USES_GETTIMEOFFSET
762 select HAVE_S3C2410_I2C if I2C
763 select HAVE_S3C_RTC if RTC_CLASS
764 select HAVE_S3C2410_WATCHDOG if WATCHDOG
765 help
766 Samsung S5PC100 series based systems
767
768config ARCH_S5PV210
769 bool "Samsung S5PV210/S5PC110"
770 select CPU_V7
771 select ARCH_SPARSEMEM_ENABLE
772 select ARCH_HAS_HOLES_MEMORYMODEL
773 select GENERIC_GPIO
774 select HAVE_CLK
775 select CLKDEV_LOOKUP
776 select CLKSRC_MMIO
777 select ARM_L1_CACHE_SHIFT_6
778 select ARCH_HAS_CPUFREQ
779 select GENERIC_CLOCKEVENTS
780 select HAVE_SCHED_CLOCK
781 select HAVE_S3C2410_I2C if I2C
782 select HAVE_S3C_RTC if RTC_CLASS
783 select HAVE_S3C2410_WATCHDOG if WATCHDOG
784 help
785 Samsung S5PV210/S5PC110 series based systems
786
787config ARCH_EXYNOS4
788 bool "Samsung EXYNOS4"
789 select CPU_V7
790 select ARCH_SPARSEMEM_ENABLE
791 select ARCH_HAS_HOLES_MEMORYMODEL
792 select GENERIC_GPIO
793 select HAVE_CLK
794 select CLKDEV_LOOKUP
795 select ARCH_HAS_CPUFREQ
796 select GENERIC_CLOCKEVENTS
797 select HAVE_S3C_RTC if RTC_CLASS
798 select HAVE_S3C2410_I2C if I2C
799 select HAVE_S3C2410_WATCHDOG if WATCHDOG
800 help
801 Samsung EXYNOS4 series based systems
802
803config ARCH_SHARK
804 bool "Shark"
805 select CPU_SA110
806 select ISA
807 select ISA_DMA
808 select ZONE_DMA
809 select PCI
810 select ARCH_USES_GETTIMEOFFSET
811 help
812 Support for the StrongARM based Digital DNARD machine, also known
813 as "Shark" (<http://www.shark-linux.de/shark.html>).
814
815config ARCH_TCC_926
816 bool "Telechips TCC ARM926-based systems"
817 select CLKSRC_MMIO
818 select CPU_ARM926T
819 select HAVE_CLK
820 select CLKDEV_LOOKUP
821 select GENERIC_CLOCKEVENTS
822 help
823 Support for Telechips TCC ARM926-based systems.
824
825config ARCH_U300
826 bool "ST-Ericsson U300 Series"
827 depends on MMU
828 select CLKSRC_MMIO
829 select CPU_ARM926T
830 select HAVE_SCHED_CLOCK
831 select HAVE_TCM
832 select ARM_AMBA
833 select ARM_VIC
834 select GENERIC_CLOCKEVENTS
835 select CLKDEV_LOOKUP
836 select HAVE_MACH_CLKDEV
837 select GENERIC_GPIO
838 help
839 Support for ST-Ericsson U300 series mobile platforms.
840
841config ARCH_U8500
842 bool "ST-Ericsson U8500 Series"
843 select CPU_V7
844 select ARM_AMBA
845 select GENERIC_CLOCKEVENTS
846 select CLKDEV_LOOKUP
847 select ARCH_REQUIRE_GPIOLIB
848 select ARCH_HAS_CPUFREQ
849 help
850 Support for ST-Ericsson's Ux500 architecture
851
852config ARCH_NOMADIK
853 bool "STMicroelectronics Nomadik"
854 select ARM_AMBA
855 select ARM_VIC
856 select CPU_ARM926T
857 select CLKDEV_LOOKUP
858 select GENERIC_CLOCKEVENTS
859 select ARCH_REQUIRE_GPIOLIB
860 help
861 Support for the Nomadik platform by ST-Ericsson
862
863config ARCH_DAVINCI
864 bool "TI DaVinci"
865 select GENERIC_CLOCKEVENTS
866 select ARCH_REQUIRE_GPIOLIB
867 select ZONE_DMA
868 select HAVE_IDE
869 select CLKDEV_LOOKUP
870 select GENERIC_ALLOCATOR
871 select GENERIC_IRQ_CHIP
872 select ARCH_HAS_HOLES_MEMORYMODEL
873 help
874 Support for TI's DaVinci platform.
875
876config ARCH_OMAP
877 bool "TI OMAP"
878 select HAVE_CLK
879 select ARCH_REQUIRE_GPIOLIB
880 select ARCH_HAS_CPUFREQ
881 select CLKSRC_MMIO
882 select GENERIC_CLOCKEVENTS
883 select HAVE_SCHED_CLOCK
884 select ARCH_HAS_HOLES_MEMORYMODEL
885 help
886 Support for TI's OMAP platform (OMAP1/2/3/4).
887
888config PLAT_SPEAR
889 bool "ST SPEAr"
890 select ARM_AMBA
891 select ARCH_REQUIRE_GPIOLIB
892 select CLKDEV_LOOKUP
893 select CLKSRC_MMIO
894 select GENERIC_CLOCKEVENTS
895 select HAVE_CLK
896 help
897 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
898
899config ARCH_VT8500
900 bool "VIA/WonderMedia 85xx"
901 select CPU_ARM926T
902 select GENERIC_GPIO
903 select ARCH_HAS_CPUFREQ
904 select GENERIC_CLOCKEVENTS
905 select ARCH_REQUIRE_GPIOLIB
906 select HAVE_PWM
907 help
908 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
909
910config ARCH_ZYNQ
911 bool "Xilinx Zynq ARM Cortex A9 Platform"
912 select CPU_V7
913 select GENERIC_TIME
914 select GENERIC_CLOCKEVENTS
915 select CLKDEV_LOOKUP
916 select ARM_GIC
917 select ARM_AMBA
918 select ICST
919 select USE_OF
920 help
921 Support for Xilinx Zynq ARM Cortex A9 Platform
922endchoice
923
924#
925# This is sorted alphabetically by mach-* pathname. However, plat-*
926# Kconfigs may be included either alphabetically (according to the
927# plat- suffix) or along side the corresponding mach-* source.
928#
929source "arch/arm/mach-at91/Kconfig"
930
931source "arch/arm/mach-bcmring/Kconfig"
932
933source "arch/arm/mach-clps711x/Kconfig"
934
935source "arch/arm/mach-cns3xxx/Kconfig"
936
937source "arch/arm/mach-davinci/Kconfig"
938
939source "arch/arm/mach-dove/Kconfig"
940
941source "arch/arm/mach-ep93xx/Kconfig"
942
943source "arch/arm/mach-footbridge/Kconfig"
944
945source "arch/arm/mach-gemini/Kconfig"
946
947source "arch/arm/mach-h720x/Kconfig"
948
949source "arch/arm/mach-integrator/Kconfig"
950
951source "arch/arm/mach-iop32x/Kconfig"
952
953source "arch/arm/mach-iop33x/Kconfig"
954
955source "arch/arm/mach-iop13xx/Kconfig"
956
957source "arch/arm/mach-ixp4xx/Kconfig"
958
959source "arch/arm/mach-ixp2000/Kconfig"
960
961source "arch/arm/mach-ixp23xx/Kconfig"
962
963source "arch/arm/mach-kirkwood/Kconfig"
964
965source "arch/arm/mach-ks8695/Kconfig"
966
967source "arch/arm/mach-lpc32xx/Kconfig"
968
969source "arch/arm/mach-msm/Kconfig"
970
971source "arch/arm/mach-mv78xx0/Kconfig"
972
973source "arch/arm/plat-mxc/Kconfig"
974
975source "arch/arm/mach-mxs/Kconfig"
976
977source "arch/arm/mach-netx/Kconfig"
978
979source "arch/arm/mach-nomadik/Kconfig"
980source "arch/arm/plat-nomadik/Kconfig"
981
982source "arch/arm/mach-nuc93x/Kconfig"
983
984source "arch/arm/plat-omap/Kconfig"
985
986source "arch/arm/mach-omap1/Kconfig"
987
988source "arch/arm/mach-omap2/Kconfig"
989
990source "arch/arm/mach-orion5x/Kconfig"
991
992source "arch/arm/mach-pxa/Kconfig"
993source "arch/arm/plat-pxa/Kconfig"
994
995source "arch/arm/mach-mmp/Kconfig"
996
997source "arch/arm/mach-realview/Kconfig"
998
999source "arch/arm/mach-sa1100/Kconfig"
1000
1001source "arch/arm/plat-samsung/Kconfig"
1002source "arch/arm/plat-s3c24xx/Kconfig"
1003source "arch/arm/plat-s5p/Kconfig"
1004
1005source "arch/arm/plat-spear/Kconfig"
1006
1007source "arch/arm/plat-tcc/Kconfig"
1008
1009if ARCH_S3C2410
1010source "arch/arm/mach-s3c2410/Kconfig"
1011source "arch/arm/mach-s3c2412/Kconfig"
1012source "arch/arm/mach-s3c2416/Kconfig"
1013source "arch/arm/mach-s3c2440/Kconfig"
1014source "arch/arm/mach-s3c2443/Kconfig"
1015endif
1016
1017if ARCH_S3C64XX
1018source "arch/arm/mach-s3c64xx/Kconfig"
1019endif
1020
1021source "arch/arm/mach-s5p64x0/Kconfig"
1022
1023source "arch/arm/mach-s5pc100/Kconfig"
1024
1025source "arch/arm/mach-s5pv210/Kconfig"
1026
1027source "arch/arm/mach-exynos4/Kconfig"
1028
1029source "arch/arm/mach-shmobile/Kconfig"
1030
1031source "arch/arm/mach-tegra/Kconfig"
1032
1033source "arch/arm/mach-u300/Kconfig"
1034
1035source "arch/arm/mach-ux500/Kconfig"
1036
1037source "arch/arm/mach-versatile/Kconfig"
1038
1039source "arch/arm/mach-vexpress/Kconfig"
1040source "arch/arm/plat-versatile/Kconfig"
1041
1042source "arch/arm/mach-vt8500/Kconfig"
1043
1044source "arch/arm/mach-w90x900/Kconfig"
1045
1046# Definitions to make life easier
1047config ARCH_ACORN
1048 bool
1049
1050config PLAT_IOP
1051 bool
1052 select GENERIC_CLOCKEVENTS
1053 select HAVE_SCHED_CLOCK
1054
1055config PLAT_ORION
1056 bool
1057 select CLKSRC_MMIO
1058 select GENERIC_IRQ_CHIP
1059 select HAVE_SCHED_CLOCK
1060
1061config PLAT_PXA
1062 bool
1063
1064config PLAT_VERSATILE
1065 bool
1066
1067config ARM_TIMER_SP804
1068 bool
1069 select CLKSRC_MMIO
1070
1071source arch/arm/mm/Kconfig
1072
1073config IWMMXT
1074 bool "Enable iWMMXt support"
1075 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1076 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1077 help
1078 Enable support for iWMMXt context switching at run time if
1079 running on a CPU that supports it.
1080
1081# bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1082config XSCALE_PMU
1083 bool
1084 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1085 default y
1086
1087config CPU_HAS_PMU
1088 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1089 (!ARCH_OMAP3 || OMAP3_EMU)
1090 default y
1091 bool
1092
1093config MULTI_IRQ_HANDLER
1094 bool
1095 help
1096 Allow each machine to specify it's own IRQ handler at run time.
1097
1098if !MMU
1099source "arch/arm/Kconfig-nommu"
1100endif
1101
1102config ARM_ERRATA_411920
1103 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1104 depends on CPU_V6 || CPU_V6K
1105 help
1106 Invalidation of the Instruction Cache operation can
1107 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1108 It does not affect the MPCore. This option enables the ARM Ltd.
1109 recommended workaround.
1110
1111config ARM_ERRATA_430973
1112 bool "ARM errata: Stale prediction on replaced interworking branch"
1113 depends on CPU_V7
1114 help
1115 This option enables the workaround for the 430973 Cortex-A8
1116 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1117 interworking branch is replaced with another code sequence at the
1118 same virtual address, whether due to self-modifying code or virtual
1119 to physical address re-mapping, Cortex-A8 does not recover from the
1120 stale interworking branch prediction. This results in Cortex-A8
1121 executing the new code sequence in the incorrect ARM or Thumb state.
1122 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1123 and also flushes the branch target cache at every context switch.
1124 Note that setting specific bits in the ACTLR register may not be
1125 available in non-secure mode.
1126
1127config ARM_ERRATA_458693
1128 bool "ARM errata: Processor deadlock when a false hazard is created"
1129 depends on CPU_V7
1130 help
1131 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1132 erratum. For very specific sequences of memory operations, it is
1133 possible for a hazard condition intended for a cache line to instead
1134 be incorrectly associated with a different cache line. This false
1135 hazard might then cause a processor deadlock. The workaround enables
1136 the L1 caching of the NEON accesses and disables the PLD instruction
1137 in the ACTLR register. Note that setting specific bits in the ACTLR
1138 register may not be available in non-secure mode.
1139
1140config ARM_ERRATA_460075
1141 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1142 depends on CPU_V7
1143 help
1144 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1145 erratum. Any asynchronous access to the L2 cache may encounter a
1146 situation in which recent store transactions to the L2 cache are lost
1147 and overwritten with stale memory contents from external memory. The
1148 workaround disables the write-allocate mode for the L2 cache via the
1149 ACTLR register. Note that setting specific bits in the ACTLR register
1150 may not be available in non-secure mode.
1151
1152config ARM_ERRATA_742230
1153 bool "ARM errata: DMB operation may be faulty"
1154 depends on CPU_V7 && SMP
1155 help
1156 This option enables the workaround for the 742230 Cortex-A9
1157 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1158 between two write operations may not ensure the correct visibility
1159 ordering of the two writes. This workaround sets a specific bit in
1160 the diagnostic register of the Cortex-A9 which causes the DMB
1161 instruction to behave as a DSB, ensuring the correct behaviour of
1162 the two writes.
1163
1164config ARM_ERRATA_742231
1165 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1166 depends on CPU_V7 && SMP
1167 help
1168 This option enables the workaround for the 742231 Cortex-A9
1169 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1170 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1171 accessing some data located in the same cache line, may get corrupted
1172 data due to bad handling of the address hazard when the line gets
1173 replaced from one of the CPUs at the same time as another CPU is
1174 accessing it. This workaround sets specific bits in the diagnostic
1175 register of the Cortex-A9 which reduces the linefill issuing
1176 capabilities of the processor.
1177
1178config PL310_ERRATA_588369
1179 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1180 depends on CACHE_L2X0
1181 help
1182 The PL310 L2 cache controller implements three types of Clean &
1183 Invalidate maintenance operations: by Physical Address
1184 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1185 They are architecturally defined to behave as the execution of a
1186 clean operation followed immediately by an invalidate operation,
1187 both performing to the same memory location. This functionality
1188 is not correctly implemented in PL310 as clean lines are not
1189 invalidated as a result of these operations.
1190
1191config ARM_ERRATA_720789
1192 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1193 depends on CPU_V7 && SMP
1194 help
1195 This option enables the workaround for the 720789 Cortex-A9 (prior to
1196 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1197 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1198 As a consequence of this erratum, some TLB entries which should be
1199 invalidated are not, resulting in an incoherency in the system page
1200 tables. The workaround changes the TLB flushing routines to invalidate
1201 entries regardless of the ASID.
1202
1203config PL310_ERRATA_727915
1204 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1205 depends on CACHE_L2X0
1206 help
1207 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1208 operation (offset 0x7FC). This operation runs in background so that
1209 PL310 can handle normal accesses while it is in progress. Under very
1210 rare circumstances, due to this erratum, write data can be lost when
1211 PL310 treats a cacheable write transaction during a Clean &
1212 Invalidate by Way operation.
1213
1214config ARM_ERRATA_743622
1215 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1216 depends on CPU_V7
1217 help
1218 This option enables the workaround for the 743622 Cortex-A9
1219 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1220 optimisation in the Cortex-A9 Store Buffer may lead to data
1221 corruption. This workaround sets a specific bit in the diagnostic
1222 register of the Cortex-A9 which disables the Store Buffer
1223 optimisation, preventing the defect from occurring. This has no
1224 visible impact on the overall performance or power consumption of the
1225 processor.
1226
1227config ARM_ERRATA_751472
1228 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1229 depends on CPU_V7 && SMP
1230 help
1231 This option enables the workaround for the 751472 Cortex-A9 (prior
1232 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1233 completion of a following broadcasted operation if the second
1234 operation is received by a CPU before the ICIALLUIS has completed,
1235 potentially leading to corrupted entries in the cache or TLB.
1236
1237config ARM_ERRATA_753970
1238 bool "ARM errata: cache sync operation may be faulty"
1239 depends on CACHE_PL310
1240 help
1241 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1242
1243 Under some condition the effect of cache sync operation on
1244 the store buffer still remains when the operation completes.
1245 This means that the store buffer is always asked to drain and
1246 this prevents it from merging any further writes. The workaround
1247 is to replace the normal offset of cache sync operation (0x730)
1248 by another offset targeting an unmapped PL310 register 0x740.
1249 This has the same effect as the cache sync operation: store buffer
1250 drain and waiting for all buffers empty.
1251
1252config ARM_ERRATA_754322
1253 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1254 depends on CPU_V7
1255 help
1256 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1257 r3p*) erratum. A speculative memory access may cause a page table walk
1258 which starts prior to an ASID switch but completes afterwards. This
1259 can populate the micro-TLB with a stale entry which may be hit with
1260 the new ASID. This workaround places two dsb instructions in the mm
1261 switching code so that no page table walks can cross the ASID switch.
1262
1263config ARM_ERRATA_754327
1264 bool "ARM errata: no automatic Store Buffer drain"
1265 depends on CPU_V7 && SMP
1266 help
1267 This option enables the workaround for the 754327 Cortex-A9 (prior to
1268 r2p0) erratum. The Store Buffer does not have any automatic draining
1269 mechanism and therefore a livelock may occur if an external agent
1270 continuously polls a memory location waiting to observe an update.
1271 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1272 written polling loops from denying visibility of updates to memory.
1273
1274config ARM_ERRATA_364296
1275 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1276 depends on CPU_V6 && !SMP
1277 help
1278 This options enables the workaround for the 364296 ARM1136
1279 r0p2 erratum (possible cache data corruption with
1280 hit-under-miss enabled). It sets the undocumented bit 31 in
1281 the auxiliary control register and the FI bit in the control
1282 register, thus disabling hit-under-miss without putting the
1283 processor into full low interrupt latency mode. ARM11MPCore
1284 is not affected.
1285
1286config ARM_ERRATA_764369
1287 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1288 depends on CPU_V7 && SMP
1289 help
1290 This option enables the workaround for erratum 764369
1291 affecting Cortex-A9 MPCore with two or more processors (all
1292 current revisions). Under certain timing circumstances, a data
1293 cache line maintenance operation by MVA targeting an Inner
1294 Shareable memory region may fail to proceed up to either the
1295 Point of Coherency or to the Point of Unification of the
1296 system. This workaround adds a DSB instruction before the
1297 relevant cache maintenance functions and sets a specific bit
1298 in the diagnostic control register of the SCU.
1299
1300endmenu
1301
1302source "arch/arm/common/Kconfig"
1303
1304menu "Bus support"
1305
1306config ARM_AMBA
1307 bool
1308
1309config ISA
1310 bool
1311 help
1312 Find out whether you have ISA slots on your motherboard. ISA is the
1313 name of a bus system, i.e. the way the CPU talks to the other stuff
1314 inside your box. Other bus systems are PCI, EISA, MicroChannel
1315 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1316 newer boards don't support it. If you have ISA, say Y, otherwise N.
1317
1318# Select ISA DMA controller support
1319config ISA_DMA
1320 bool
1321 select ISA_DMA_API
1322
1323# Select ISA DMA interface
1324config ISA_DMA_API
1325 bool
1326
1327config PCI
1328 bool "PCI support" if MIGHT_HAVE_PCI
1329 help
1330 Find out whether you have a PCI motherboard. PCI is the name of a
1331 bus system, i.e. the way the CPU talks to the other stuff inside
1332 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1333 VESA. If you have PCI, say Y, otherwise N.
1334
1335config PCI_DOMAINS
1336 bool
1337 depends on PCI
1338
1339config PCI_NANOENGINE
1340 bool "BSE nanoEngine PCI support"
1341 depends on SA1100_NANOENGINE
1342 help
1343 Enable PCI on the BSE nanoEngine board.
1344
1345config PCI_SYSCALL
1346 def_bool PCI
1347
1348# Select the host bridge type
1349config PCI_HOST_VIA82C505
1350 bool
1351 depends on PCI && ARCH_SHARK
1352 default y
1353
1354config PCI_HOST_ITE8152
1355 bool
1356 depends on PCI && MACH_ARMCORE
1357 default y
1358 select DMABOUNCE
1359
1360source "drivers/pci/Kconfig"
1361
1362source "drivers/pcmcia/Kconfig"
1363
1364endmenu
1365
1366menu "Kernel Features"
1367
1368source "kernel/time/Kconfig"
1369
1370config SMP
1371 bool "Symmetric Multi-Processing"
1372 depends on CPU_V6K || CPU_V7
1373 depends on GENERIC_CLOCKEVENTS
1374 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1375 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1376 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1377 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1378 select USE_GENERIC_SMP_HELPERS
1379 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1380 help
1381 This enables support for systems with more than one CPU. If you have
1382 a system with only one CPU, like most personal computers, say N. If
1383 you have a system with more than one CPU, say Y.
1384
1385 If you say N here, the kernel will run on single and multiprocessor
1386 machines, but will use only one CPU of a multiprocessor machine. If
1387 you say Y here, the kernel will run on many, but not all, single
1388 processor machines. On a single processor machine, the kernel will
1389 run faster if you say N here.
1390
1391 See also <file:Documentation/i386/IO-APIC.txt>,
1392 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1393 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1394
1395 If you don't know what to do here, say N.
1396
1397config SMP_ON_UP
1398 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1399 depends on EXPERIMENTAL
1400 depends on SMP && !XIP_KERNEL
1401 default y
1402 help
1403 SMP kernels contain instructions which fail on non-SMP processors.
1404 Enabling this option allows the kernel to modify itself to make
1405 these instructions safe. Disabling it allows about 1K of space
1406 savings.
1407
1408 If you don't know what to do here, say Y.
1409
1410config HAVE_ARM_SCU
1411 bool
1412 help
1413 This option enables support for the ARM system coherency unit
1414
1415config HAVE_ARM_TWD
1416 bool
1417 depends on SMP
1418 select TICK_ONESHOT
1419 help
1420 This options enables support for the ARM timer and watchdog unit
1421
1422choice
1423 prompt "Memory split"
1424 default VMSPLIT_3G
1425 help
1426 Select the desired split between kernel and user memory.
1427
1428 If you are not absolutely sure what you are doing, leave this
1429 option alone!
1430
1431 config VMSPLIT_3G
1432 bool "3G/1G user/kernel split"
1433 config VMSPLIT_2G
1434 bool "2G/2G user/kernel split"
1435 config VMSPLIT_1G
1436 bool "1G/3G user/kernel split"
1437endchoice
1438
1439config PAGE_OFFSET
1440 hex
1441 default 0x40000000 if VMSPLIT_1G
1442 default 0x80000000 if VMSPLIT_2G
1443 default 0xC0000000
1444
1445config NR_CPUS
1446 int "Maximum number of CPUs (2-32)"
1447 range 2 32
1448 depends on SMP
1449 default "4"
1450
1451config HOTPLUG_CPU
1452 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1453 depends on SMP && HOTPLUG && EXPERIMENTAL
1454 help
1455 Say Y here to experiment with turning CPUs off and on. CPUs
1456 can be controlled through /sys/devices/system/cpu.
1457
1458config LOCAL_TIMERS
1459 bool "Use local timer interrupts"
1460 depends on SMP
1461 default y
1462 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1463 help
1464 Enable support for local timers on SMP platforms, rather then the
1465 legacy IPI broadcast method. Local timers allows the system
1466 accounting to be spread across the timer interval, preventing a
1467 "thundering herd" at every timer tick.
1468
1469source kernel/Kconfig.preempt
1470
1471config HZ
1472 int
1473 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1474 ARCH_S5PV210 || ARCH_EXYNOS4
1475 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1476 default AT91_TIMER_HZ if ARCH_AT91
1477 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1478 default 100
1479
1480config THUMB2_KERNEL
1481 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1482 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1483 select AEABI
1484 select ARM_ASM_UNIFIED
1485 help
1486 By enabling this option, the kernel will be compiled in
1487 Thumb-2 mode. A compiler/assembler that understand the unified
1488 ARM-Thumb syntax is needed.
1489
1490 If unsure, say N.
1491
1492config THUMB2_AVOID_R_ARM_THM_JUMP11
1493 bool "Work around buggy Thumb-2 short branch relocations in gas"
1494 depends on THUMB2_KERNEL && MODULES
1495 default y
1496 help
1497 Various binutils versions can resolve Thumb-2 branches to
1498 locally-defined, preemptible global symbols as short-range "b.n"
1499 branch instructions.
1500
1501 This is a problem, because there's no guarantee the final
1502 destination of the symbol, or any candidate locations for a
1503 trampoline, are within range of the branch. For this reason, the
1504 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1505 relocation in modules at all, and it makes little sense to add
1506 support.
1507
1508 The symptom is that the kernel fails with an "unsupported
1509 relocation" error when loading some modules.
1510
1511 Until fixed tools are available, passing
1512 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1513 code which hits this problem, at the cost of a bit of extra runtime
1514 stack usage in some cases.
1515
1516 The problem is described in more detail at:
1517 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1518
1519 Only Thumb-2 kernels are affected.
1520
1521 Unless you are sure your tools don't have this problem, say Y.
1522
1523config ARM_ASM_UNIFIED
1524 bool
1525
1526config AEABI
1527 bool "Use the ARM EABI to compile the kernel"
1528 help
1529 This option allows for the kernel to be compiled using the latest
1530 ARM ABI (aka EABI). This is only useful if you are using a user
1531 space environment that is also compiled with EABI.
1532
1533 Since there are major incompatibilities between the legacy ABI and
1534 EABI, especially with regard to structure member alignment, this
1535 option also changes the kernel syscall calling convention to
1536 disambiguate both ABIs and allow for backward compatibility support
1537 (selected with CONFIG_OABI_COMPAT).
1538
1539 To use this you need GCC version 4.0.0 or later.
1540
1541config OABI_COMPAT
1542 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1543 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1544 default y
1545 help
1546 This option preserves the old syscall interface along with the
1547 new (ARM EABI) one. It also provides a compatibility layer to
1548 intercept syscalls that have structure arguments which layout
1549 in memory differs between the legacy ABI and the new ARM EABI
1550 (only for non "thumb" binaries). This option adds a tiny
1551 overhead to all syscalls and produces a slightly larger kernel.
1552 If you know you'll be using only pure EABI user space then you
1553 can say N here. If this option is not selected and you attempt
1554 to execute a legacy ABI binary then the result will be
1555 UNPREDICTABLE (in fact it can be predicted that it won't work
1556 at all). If in doubt say Y.
1557
1558config ARCH_HAS_HOLES_MEMORYMODEL
1559 bool
1560
1561config ARCH_SPARSEMEM_ENABLE
1562 bool
1563
1564config ARCH_SPARSEMEM_DEFAULT
1565 def_bool ARCH_SPARSEMEM_ENABLE
1566
1567config ARCH_SELECT_MEMORY_MODEL
1568 def_bool ARCH_SPARSEMEM_ENABLE
1569
1570config HAVE_ARCH_PFN_VALID
1571 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1572
1573config HIGHMEM
1574 bool "High Memory Support"
1575 depends on MMU
1576 help
1577 The address space of ARM processors is only 4 Gigabytes large
1578 and it has to accommodate user address space, kernel address
1579 space as well as some memory mapped IO. That means that, if you
1580 have a large amount of physical memory and/or IO, not all of the
1581 memory can be "permanently mapped" by the kernel. The physical
1582 memory that is not permanently mapped is called "high memory".
1583
1584 Depending on the selected kernel/user memory split, minimum
1585 vmalloc space and actual amount of RAM, you may not need this
1586 option which should result in a slightly faster kernel.
1587
1588 If unsure, say n.
1589
1590config HIGHPTE
1591 bool "Allocate 2nd-level pagetables from highmem"
1592 depends on HIGHMEM
1593
1594config HW_PERF_EVENTS
1595 bool "Enable hardware performance counter support for perf events"
1596 depends on PERF_EVENTS && CPU_HAS_PMU
1597 default y
1598 help
1599 Enable hardware performance counter support for perf events. If
1600 disabled, perf events will use software events only.
1601
1602source "mm/Kconfig"
1603
1604config FORCE_MAX_ZONEORDER
1605 int "Maximum zone order" if ARCH_SHMOBILE
1606 range 11 64 if ARCH_SHMOBILE
1607 default "9" if SA1111
1608 default "11"
1609 help
1610 The kernel memory allocator divides physically contiguous memory
1611 blocks into "zones", where each zone is a power of two number of
1612 pages. This option selects the largest power of two that the kernel
1613 keeps in the memory allocator. If you need to allocate very large
1614 blocks of physically contiguous memory, then you may need to
1615 increase this value.
1616
1617 This config option is actually maximum order plus one. For example,
1618 a value of 11 means that the largest free memory block is 2^10 pages.
1619
1620config LEDS
1621 bool "Timer and CPU usage LEDs"
1622 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1623 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1624 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1625 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1626 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1627 ARCH_AT91 || ARCH_DAVINCI || \
1628 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1629 help
1630 If you say Y here, the LEDs on your machine will be used
1631 to provide useful information about your current system status.
1632
1633 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1634 be able to select which LEDs are active using the options below. If
1635 you are compiling a kernel for the EBSA-110 or the LART however, the
1636 red LED will simply flash regularly to indicate that the system is
1637 still functional. It is safe to say Y here if you have a CATS
1638 system, but the driver will do nothing.
1639
1640config LEDS_TIMER
1641 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1642 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1643 || MACH_OMAP_PERSEUS2
1644 depends on LEDS
1645 depends on !GENERIC_CLOCKEVENTS
1646 default y if ARCH_EBSA110
1647 help
1648 If you say Y here, one of the system LEDs (the green one on the
1649 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1650 will flash regularly to indicate that the system is still
1651 operational. This is mainly useful to kernel hackers who are
1652 debugging unstable kernels.
1653
1654 The LART uses the same LED for both Timer LED and CPU usage LED
1655 functions. You may choose to use both, but the Timer LED function
1656 will overrule the CPU usage LED.
1657
1658config LEDS_CPU
1659 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1660 !ARCH_OMAP) \
1661 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1662 || MACH_OMAP_PERSEUS2
1663 depends on LEDS
1664 help
1665 If you say Y here, the red LED will be used to give a good real
1666 time indication of CPU usage, by lighting whenever the idle task
1667 is not currently executing.
1668
1669 The LART uses the same LED for both Timer LED and CPU usage LED
1670 functions. You may choose to use both, but the Timer LED function
1671 will overrule the CPU usage LED.
1672
1673config ALIGNMENT_TRAP
1674 bool
1675 depends on CPU_CP15_MMU
1676 default y if !ARCH_EBSA110
1677 select HAVE_PROC_CPU if PROC_FS
1678 help
1679 ARM processors cannot fetch/store information which is not
1680 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1681 address divisible by 4. On 32-bit ARM processors, these non-aligned
1682 fetch/store instructions will be emulated in software if you say
1683 here, which has a severe performance impact. This is necessary for
1684 correct operation of some network protocols. With an IP-only
1685 configuration it is safe to say N, otherwise say Y.
1686
1687config UACCESS_WITH_MEMCPY
1688 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1689 depends on MMU && EXPERIMENTAL
1690 default y if CPU_FEROCEON
1691 help
1692 Implement faster copy_to_user and clear_user methods for CPU
1693 cores where a 8-word STM instruction give significantly higher
1694 memory write throughput than a sequence of individual 32bit stores.
1695
1696 A possible side effect is a slight increase in scheduling latency
1697 between threads sharing the same address space if they invoke
1698 such copy operations with large buffers.
1699
1700 However, if the CPU data cache is using a write-allocate mode,
1701 this option is unlikely to provide any performance gain.
1702
1703config SECCOMP
1704 bool
1705 prompt "Enable seccomp to safely compute untrusted bytecode"
1706 ---help---
1707 This kernel feature is useful for number crunching applications
1708 that may need to compute untrusted bytecode during their
1709 execution. By using pipes or other transports made available to
1710 the process as file descriptors supporting the read/write
1711 syscalls, it's possible to isolate those applications in
1712 their own address space using seccomp. Once seccomp is
1713 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1714 and the task is only allowed to execute a few safe syscalls
1715 defined by each seccomp mode.
1716
1717config CC_STACKPROTECTOR
1718 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1719 depends on EXPERIMENTAL
1720 help
1721 This option turns on the -fstack-protector GCC feature. This
1722 feature puts, at the beginning of functions, a canary value on
1723 the stack just before the return address, and validates
1724 the value just before actually returning. Stack based buffer
1725 overflows (that need to overwrite this return address) now also
1726 overwrite the canary, which gets detected and the attack is then
1727 neutralized via a kernel panic.
1728 This feature requires gcc version 4.2 or above.
1729
1730config DEPRECATED_PARAM_STRUCT
1731 bool "Provide old way to pass kernel parameters"
1732 help
1733 This was deprecated in 2001 and announced to live on for 5 years.
1734 Some old boot loaders still use this way.
1735
1736endmenu
1737
1738menu "Boot options"
1739
1740config USE_OF
1741 bool "Flattened Device Tree support"
1742 select OF
1743 select OF_EARLY_FLATTREE
1744 select IRQ_DOMAIN
1745 help
1746 Include support for flattened device tree machine descriptions.
1747
1748# Compressed boot loader in ROM. Yes, we really want to ask about
1749# TEXT and BSS so we preserve their values in the config files.
1750config ZBOOT_ROM_TEXT
1751 hex "Compressed ROM boot loader base address"
1752 default "0"
1753 help
1754 The physical address at which the ROM-able zImage is to be
1755 placed in the target. Platforms which normally make use of
1756 ROM-able zImage formats normally set this to a suitable
1757 value in their defconfig file.
1758
1759 If ZBOOT_ROM is not enabled, this has no effect.
1760
1761config ZBOOT_ROM_BSS
1762 hex "Compressed ROM boot loader BSS address"
1763 default "0"
1764 help
1765 The base address of an area of read/write memory in the target
1766 for the ROM-able zImage which must be available while the
1767 decompressor is running. It must be large enough to hold the
1768 entire decompressed kernel plus an additional 128 KiB.
1769 Platforms which normally make use of ROM-able zImage formats
1770 normally set this to a suitable value in their defconfig file.
1771
1772 If ZBOOT_ROM is not enabled, this has no effect.
1773
1774config ZBOOT_ROM
1775 bool "Compressed boot loader in ROM/flash"
1776 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1777 help
1778 Say Y here if you intend to execute your compressed kernel image
1779 (zImage) directly from ROM or flash. If unsure, say N.
1780
1781choice
1782 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1783 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1784 default ZBOOT_ROM_NONE
1785 help
1786 Include experimental SD/MMC loading code in the ROM-able zImage.
1787 With this enabled it is possible to write the the ROM-able zImage
1788 kernel image to an MMC or SD card and boot the kernel straight
1789 from the reset vector. At reset the processor Mask ROM will load
1790 the first part of the the ROM-able zImage which in turn loads the
1791 rest the kernel image to RAM.
1792
1793config ZBOOT_ROM_NONE
1794 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1795 help
1796 Do not load image from SD or MMC
1797
1798config ZBOOT_ROM_MMCIF
1799 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1800 help
1801 Load image from MMCIF hardware block.
1802
1803config ZBOOT_ROM_SH_MOBILE_SDHI
1804 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1805 help
1806 Load image from SDHI hardware block
1807
1808endchoice
1809
1810config CMDLINE
1811 string "Default kernel command string"
1812 default ""
1813 help
1814 On some architectures (EBSA110 and CATS), there is currently no way
1815 for the boot loader to pass arguments to the kernel. For these
1816 architectures, you should supply some command-line options at build
1817 time by entering them here. As a minimum, you should specify the
1818 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1819
1820choice
1821 prompt "Kernel command line type" if CMDLINE != ""
1822 default CMDLINE_FROM_BOOTLOADER
1823
1824config CMDLINE_FROM_BOOTLOADER
1825 bool "Use bootloader kernel arguments if available"
1826 help
1827 Uses the command-line options passed by the boot loader. If
1828 the boot loader doesn't provide any, the default kernel command
1829 string provided in CMDLINE will be used.
1830
1831config CMDLINE_EXTEND
1832 bool "Extend bootloader kernel arguments"
1833 help
1834 The command-line arguments provided by the boot loader will be
1835 appended to the default kernel command string.
1836
1837config CMDLINE_FORCE
1838 bool "Always use the default kernel command string"
1839 help
1840 Always use the default kernel command string, even if the boot
1841 loader passes other arguments to the kernel.
1842 This is useful if you cannot or don't want to change the
1843 command-line options your boot loader passes to the kernel.
1844endchoice
1845
1846config XIP_KERNEL
1847 bool "Kernel Execute-In-Place from ROM"
1848 depends on !ZBOOT_ROM
1849 help
1850 Execute-In-Place allows the kernel to run from non-volatile storage
1851 directly addressable by the CPU, such as NOR flash. This saves RAM
1852 space since the text section of the kernel is not loaded from flash
1853 to RAM. Read-write sections, such as the data section and stack,
1854 are still copied to RAM. The XIP kernel is not compressed since
1855 it has to run directly from flash, so it will take more space to
1856 store it. The flash address used to link the kernel object files,
1857 and for storing it, is configuration dependent. Therefore, if you
1858 say Y here, you must know the proper physical address where to
1859 store the kernel image depending on your own flash memory usage.
1860
1861 Also note that the make target becomes "make xipImage" rather than
1862 "make zImage" or "make Image". The final kernel binary to put in
1863 ROM memory will be arch/arm/boot/xipImage.
1864
1865 If unsure, say N.
1866
1867config XIP_PHYS_ADDR
1868 hex "XIP Kernel Physical Location"
1869 depends on XIP_KERNEL
1870 default "0x00080000"
1871 help
1872 This is the physical address in your flash memory the kernel will
1873 be linked for and stored to. This address is dependent on your
1874 own flash usage.
1875
1876config KEXEC
1877 bool "Kexec system call (EXPERIMENTAL)"
1878 depends on EXPERIMENTAL
1879 help
1880 kexec is a system call that implements the ability to shutdown your
1881 current kernel, and to start another kernel. It is like a reboot
1882 but it is independent of the system firmware. And like a reboot
1883 you can start any kernel with it, not just Linux.
1884
1885 It is an ongoing process to be certain the hardware in a machine
1886 is properly shutdown, so do not be surprised if this code does not
1887 initially work for you. It may help to enable device hotplugging
1888 support.
1889
1890config ATAGS_PROC
1891 bool "Export atags in procfs"
1892 depends on KEXEC
1893 default y
1894 help
1895 Should the atags used to boot the kernel be exported in an "atags"
1896 file in procfs. Useful with kexec.
1897
1898config CRASH_DUMP
1899 bool "Build kdump crash kernel (EXPERIMENTAL)"
1900 depends on EXPERIMENTAL
1901 help
1902 Generate crash dump after being started by kexec. This should
1903 be normally only set in special crash dump kernels which are
1904 loaded in the main kernel with kexec-tools into a specially
1905 reserved region and then later executed after a crash by
1906 kdump/kexec. The crash dump kernel must be compiled to a
1907 memory address not used by the main kernel
1908
1909 For more details see Documentation/kdump/kdump.txt
1910
1911config AUTO_ZRELADDR
1912 bool "Auto calculation of the decompressed kernel image address"
1913 depends on !ZBOOT_ROM && !ARCH_U300
1914 help
1915 ZRELADDR is the physical address where the decompressed kernel
1916 image will be placed. If AUTO_ZRELADDR is selected, the address
1917 will be determined at run-time by masking the current IP with
1918 0xf8000000. This assumes the zImage being placed in the first 128MB
1919 from start of memory.
1920
1921endmenu
1922
1923menu "CPU Power Management"
1924
1925if ARCH_HAS_CPUFREQ
1926
1927source "drivers/cpufreq/Kconfig"
1928
1929config CPU_FREQ_IMX
1930 tristate "CPUfreq driver for i.MX CPUs"
1931 depends on ARCH_MXC && CPU_FREQ
1932 help
1933 This enables the CPUfreq driver for i.MX CPUs.
1934
1935config CPU_FREQ_SA1100
1936 bool
1937
1938config CPU_FREQ_SA1110
1939 bool
1940
1941config CPU_FREQ_INTEGRATOR
1942 tristate "CPUfreq driver for ARM Integrator CPUs"
1943 depends on ARCH_INTEGRATOR && CPU_FREQ
1944 default y
1945 help
1946 This enables the CPUfreq driver for ARM Integrator CPUs.
1947
1948 For details, take a look at <file:Documentation/cpu-freq>.
1949
1950 If in doubt, say Y.
1951
1952config CPU_FREQ_PXA
1953 bool
1954 depends on CPU_FREQ && ARCH_PXA && PXA25x
1955 default y
1956 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1957
1958config CPU_FREQ_S3C
1959 bool
1960 help
1961 Internal configuration node for common cpufreq on Samsung SoC
1962
1963config CPU_FREQ_S3C24XX
1964 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1965 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1966 select CPU_FREQ_S3C
1967 help
1968 This enables the CPUfreq driver for the Samsung S3C24XX family
1969 of CPUs.
1970
1971 For details, take a look at <file:Documentation/cpu-freq>.
1972
1973 If in doubt, say N.
1974
1975config CPU_FREQ_S3C24XX_PLL
1976 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
1977 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1978 help
1979 Compile in support for changing the PLL frequency from the
1980 S3C24XX series CPUfreq driver. The PLL takes time to settle
1981 after a frequency change, so by default it is not enabled.
1982
1983 This also means that the PLL tables for the selected CPU(s) will
1984 be built which may increase the size of the kernel image.
1985
1986config CPU_FREQ_S3C24XX_DEBUG
1987 bool "Debug CPUfreq Samsung driver core"
1988 depends on CPU_FREQ_S3C24XX
1989 help
1990 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
1991
1992config CPU_FREQ_S3C24XX_IODEBUG
1993 bool "Debug CPUfreq Samsung driver IO timing"
1994 depends on CPU_FREQ_S3C24XX
1995 help
1996 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
1997
1998config CPU_FREQ_S3C24XX_DEBUGFS
1999 bool "Export debugfs for CPUFreq"
2000 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2001 help
2002 Export status information via debugfs.
2003
2004endif
2005
2006source "drivers/cpuidle/Kconfig"
2007
2008endmenu
2009
2010menu "Floating point emulation"
2011
2012comment "At least one emulation must be selected"
2013
2014config FPE_NWFPE
2015 bool "NWFPE math emulation"
2016 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2017 ---help---
2018 Say Y to include the NWFPE floating point emulator in the kernel.
2019 This is necessary to run most binaries. Linux does not currently
2020 support floating point hardware so you need to say Y here even if
2021 your machine has an FPA or floating point co-processor podule.
2022
2023 You may say N here if you are going to load the Acorn FPEmulator
2024 early in the bootup.
2025
2026config FPE_NWFPE_XP
2027 bool "Support extended precision"
2028 depends on FPE_NWFPE
2029 help
2030 Say Y to include 80-bit support in the kernel floating-point
2031 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2032 Note that gcc does not generate 80-bit operations by default,
2033 so in most cases this option only enlarges the size of the
2034 floating point emulator without any good reason.
2035
2036 You almost surely want to say N here.
2037
2038config FPE_FASTFPE
2039 bool "FastFPE math emulation (EXPERIMENTAL)"
2040 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2041 ---help---
2042 Say Y here to include the FAST floating point emulator in the kernel.
2043 This is an experimental much faster emulator which now also has full
2044 precision for the mantissa. It does not support any exceptions.
2045 It is very simple, and approximately 3-6 times faster than NWFPE.
2046
2047 It should be sufficient for most programs. It may be not suitable
2048 for scientific calculations, but you have to check this for yourself.
2049 If you do not feel you need a faster FP emulation you should better
2050 choose NWFPE.
2051
2052config VFP
2053 bool "VFP-format floating point maths"
2054 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2055 help
2056 Say Y to include VFP support code in the kernel. This is needed
2057 if your hardware includes a VFP unit.
2058
2059 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2060 release notes and additional status information.
2061
2062 Say N if your target does not have VFP hardware.
2063
2064config VFPv3
2065 bool
2066 depends on VFP
2067 default y if CPU_V7
2068
2069config NEON
2070 bool "Advanced SIMD (NEON) Extension support"
2071 depends on VFPv3 && CPU_V7
2072 help
2073 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2074 Extension.
2075
2076endmenu
2077
2078menu "Userspace binary formats"
2079
2080source "fs/Kconfig.binfmt"
2081
2082config ARTHUR
2083 tristate "RISC OS personality"
2084 depends on !AEABI
2085 help
2086 Say Y here to include the kernel code necessary if you want to run
2087 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2088 experimental; if this sounds frightening, say N and sleep in peace.
2089 You can also say M here to compile this support as a module (which
2090 will be called arthur).
2091
2092endmenu
2093
2094menu "Power management options"
2095
2096source "kernel/power/Kconfig"
2097
2098config ARCH_SUSPEND_POSSIBLE
2099 depends on !ARCH_S5P64X0 && !ARCH_S5PC100
2100 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2101 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2102 def_bool y
2103
2104endmenu
2105
2106source "net/Kconfig"
2107
2108source "drivers/Kconfig"
2109
2110source "fs/Kconfig"
2111
2112source "arch/arm/Kconfig.debug"
2113
2114source "security/Kconfig"
2115
2116source "crypto/Kconfig"
2117
2118source "lib/Kconfig"