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1 ============================
2 LINUX KERNEL MEMORY BARRIERS
3 ============================
4
5By: David Howells <dhowells@redhat.com>
6 Paul E. McKenney <paulmck@linux.ibm.com>
7 Will Deacon <will.deacon@arm.com>
8 Peter Zijlstra <peterz@infradead.org>
9
10==========
11DISCLAIMER
12==========
13
14This document is not a specification; it is intentionally (for the sake of
15brevity) and unintentionally (due to being human) incomplete. This document is
16meant as a guide to using the various memory barriers provided by Linux, but
17in case of any doubt (and there are many) please ask. Some doubts may be
18resolved by referring to the formal memory consistency model and related
19documentation at tools/memory-model/. Nevertheless, even this memory
20model should be viewed as the collective opinion of its maintainers rather
21than as an infallible oracle.
22
23To repeat, this document is not a specification of what Linux expects from
24hardware.
25
26The purpose of this document is twofold:
27
28 (1) to specify the minimum functionality that one can rely on for any
29 particular barrier, and
30
31 (2) to provide a guide as to how to use the barriers that are available.
32
33Note that an architecture can provide more than the minimum requirement
34for any particular barrier, but if the architecture provides less than
35that, that architecture is incorrect.
36
37Note also that it is possible that a barrier may be a no-op for an
38architecture because the way that arch works renders an explicit barrier
39unnecessary in that case.
40
41
42========
43CONTENTS
44========
45
46 (*) Abstract memory access model.
47
48 - Device operations.
49 - Guarantees.
50
51 (*) What are memory barriers?
52
53 - Varieties of memory barrier.
54 - What may not be assumed about memory barriers?
55 - Address-dependency barriers (historical).
56 - Control dependencies.
57 - SMP barrier pairing.
58 - Examples of memory barrier sequences.
59 - Read memory barriers vs load speculation.
60 - Multicopy atomicity.
61
62 (*) Explicit kernel barriers.
63
64 - Compiler barrier.
65 - CPU memory barriers.
66
67 (*) Implicit kernel memory barriers.
68
69 - Lock acquisition functions.
70 - Interrupt disabling functions.
71 - Sleep and wake-up functions.
72 - Miscellaneous functions.
73
74 (*) Inter-CPU acquiring barrier effects.
75
76 - Acquires vs memory accesses.
77
78 (*) Where are memory barriers needed?
79
80 - Interprocessor interaction.
81 - Atomic operations.
82 - Accessing devices.
83 - Interrupts.
84
85 (*) Kernel I/O barrier effects.
86
87 (*) Assumed minimum execution ordering model.
88
89 (*) The effects of the cpu cache.
90
91 - Cache coherency vs DMA.
92 - Cache coherency vs MMIO.
93
94 (*) The things CPUs get up to.
95
96 - And then there's the Alpha.
97 - Virtual Machine Guests.
98
99 (*) Example uses.
100
101 - Circular buffers.
102
103 (*) References.
104
105
106============================
107ABSTRACT MEMORY ACCESS MODEL
108============================
109
110Consider the following abstract model of the system:
111
112 : :
113 : :
114 : :
115 +-------+ : +--------+ : +-------+
116 | | : | | : | |
117 | | : | | : | |
118 | CPU 1 |<----->| Memory |<----->| CPU 2 |
119 | | : | | : | |
120 | | : | | : | |
121 +-------+ : +--------+ : +-------+
122 ^ : ^ : ^
123 | : | : |
124 | : | : |
125 | : v : |
126 | : +--------+ : |
127 | : | | : |
128 | : | | : |
129 +---------->| Device |<----------+
130 : | | :
131 : | | :
132 : +--------+ :
133 : :
134
135Each CPU executes a program that generates memory access operations. In the
136abstract CPU, memory operation ordering is very relaxed, and a CPU may actually
137perform the memory operations in any order it likes, provided program causality
138appears to be maintained. Similarly, the compiler may also arrange the
139instructions it emits in any order it likes, provided it doesn't affect the
140apparent operation of the program.
141
142So in the above diagram, the effects of the memory operations performed by a
143CPU are perceived by the rest of the system as the operations cross the
144interface between the CPU and rest of the system (the dotted lines).
145
146
147For example, consider the following sequence of events:
148
149 CPU 1 CPU 2
150 =============== ===============
151 { A == 1; B == 2 }
152 A = 3; x = B;
153 B = 4; y = A;
154
155The set of accesses as seen by the memory system in the middle can be arranged
156in 24 different combinations:
157
158 STORE A=3, STORE B=4, y=LOAD A->3, x=LOAD B->4
159 STORE A=3, STORE B=4, x=LOAD B->4, y=LOAD A->3
160 STORE A=3, y=LOAD A->3, STORE B=4, x=LOAD B->4
161 STORE A=3, y=LOAD A->3, x=LOAD B->2, STORE B=4
162 STORE A=3, x=LOAD B->2, STORE B=4, y=LOAD A->3
163 STORE A=3, x=LOAD B->2, y=LOAD A->3, STORE B=4
164 STORE B=4, STORE A=3, y=LOAD A->3, x=LOAD B->4
165 STORE B=4, ...
166 ...
167
168and can thus result in four different combinations of values:
169
170 x == 2, y == 1
171 x == 2, y == 3
172 x == 4, y == 1
173 x == 4, y == 3
174
175
176Furthermore, the stores committed by a CPU to the memory system may not be
177perceived by the loads made by another CPU in the same order as the stores were
178committed.
179
180
181As a further example, consider this sequence of events:
182
183 CPU 1 CPU 2
184 =============== ===============
185 { A == 1, B == 2, C == 3, P == &A, Q == &C }
186 B = 4; Q = P;
187 P = &B; D = *Q;
188
189There is an obvious address dependency here, as the value loaded into D depends
190on the address retrieved from P by CPU 2. At the end of the sequence, any of
191the following results are possible:
192
193 (Q == &A) and (D == 1)
194 (Q == &B) and (D == 2)
195 (Q == &B) and (D == 4)
196
197Note that CPU 2 will never try and load C into D because the CPU will load P
198into Q before issuing the load of *Q.
199
200
201DEVICE OPERATIONS
202-----------------
203
204Some devices present their control interfaces as collections of memory
205locations, but the order in which the control registers are accessed is very
206important. For instance, imagine an ethernet card with a set of internal
207registers that are accessed through an address port register (A) and a data
208port register (D). To read internal register 5, the following code might then
209be used:
210
211 *A = 5;
212 x = *D;
213
214but this might show up as either of the following two sequences:
215
216 STORE *A = 5, x = LOAD *D
217 x = LOAD *D, STORE *A = 5
218
219the second of which will almost certainly result in a malfunction, since it set
220the address _after_ attempting to read the register.
221
222
223GUARANTEES
224----------
225
226There are some minimal guarantees that may be expected of a CPU:
227
228 (*) On any given CPU, dependent memory accesses will be issued in order, with
229 respect to itself. This means that for:
230
231 Q = READ_ONCE(P); D = READ_ONCE(*Q);
232
233 the CPU will issue the following memory operations:
234
235 Q = LOAD P, D = LOAD *Q
236
237 and always in that order. However, on DEC Alpha, READ_ONCE() also
238 emits a memory-barrier instruction, so that a DEC Alpha CPU will
239 instead issue the following memory operations:
240
241 Q = LOAD P, MEMORY_BARRIER, D = LOAD *Q, MEMORY_BARRIER
242
243 Whether on DEC Alpha or not, the READ_ONCE() also prevents compiler
244 mischief.
245
246 (*) Overlapping loads and stores within a particular CPU will appear to be
247 ordered within that CPU. This means that for:
248
249 a = READ_ONCE(*X); WRITE_ONCE(*X, b);
250
251 the CPU will only issue the following sequence of memory operations:
252
253 a = LOAD *X, STORE *X = b
254
255 And for:
256
257 WRITE_ONCE(*X, c); d = READ_ONCE(*X);
258
259 the CPU will only issue:
260
261 STORE *X = c, d = LOAD *X
262
263 (Loads and stores overlap if they are targeted at overlapping pieces of
264 memory).
265
266And there are a number of things that _must_ or _must_not_ be assumed:
267
268 (*) It _must_not_ be assumed that the compiler will do what you want
269 with memory references that are not protected by READ_ONCE() and
270 WRITE_ONCE(). Without them, the compiler is within its rights to
271 do all sorts of "creative" transformations, which are covered in
272 the COMPILER BARRIER section.
273
274 (*) It _must_not_ be assumed that independent loads and stores will be issued
275 in the order given. This means that for:
276
277 X = *A; Y = *B; *D = Z;
278
279 we may get any of the following sequences:
280
281 X = LOAD *A, Y = LOAD *B, STORE *D = Z
282 X = LOAD *A, STORE *D = Z, Y = LOAD *B
283 Y = LOAD *B, X = LOAD *A, STORE *D = Z
284 Y = LOAD *B, STORE *D = Z, X = LOAD *A
285 STORE *D = Z, X = LOAD *A, Y = LOAD *B
286 STORE *D = Z, Y = LOAD *B, X = LOAD *A
287
288 (*) It _must_ be assumed that overlapping memory accesses may be merged or
289 discarded. This means that for:
290
291 X = *A; Y = *(A + 4);
292
293 we may get any one of the following sequences:
294
295 X = LOAD *A; Y = LOAD *(A + 4);
296 Y = LOAD *(A + 4); X = LOAD *A;
297 {X, Y} = LOAD {*A, *(A + 4) };
298
299 And for:
300
301 *A = X; *(A + 4) = Y;
302
303 we may get any of:
304
305 STORE *A = X; STORE *(A + 4) = Y;
306 STORE *(A + 4) = Y; STORE *A = X;
307 STORE {*A, *(A + 4) } = {X, Y};
308
309And there are anti-guarantees:
310
311 (*) These guarantees do not apply to bitfields, because compilers often
312 generate code to modify these using non-atomic read-modify-write
313 sequences. Do not attempt to use bitfields to synchronize parallel
314 algorithms.
315
316 (*) Even in cases where bitfields are protected by locks, all fields
317 in a given bitfield must be protected by one lock. If two fields
318 in a given bitfield are protected by different locks, the compiler's
319 non-atomic read-modify-write sequences can cause an update to one
320 field to corrupt the value of an adjacent field.
321
322 (*) These guarantees apply only to properly aligned and sized scalar
323 variables. "Properly sized" currently means variables that are
324 the same size as "char", "short", "int" and "long". "Properly
325 aligned" means the natural alignment, thus no constraints for
326 "char", two-byte alignment for "short", four-byte alignment for
327 "int", and either four-byte or eight-byte alignment for "long",
328 on 32-bit and 64-bit systems, respectively. Note that these
329 guarantees were introduced into the C11 standard, so beware when
330 using older pre-C11 compilers (for example, gcc 4.6). The portion
331 of the standard containing this guarantee is Section 3.14, which
332 defines "memory location" as follows:
333
334 memory location
335 either an object of scalar type, or a maximal sequence
336 of adjacent bit-fields all having nonzero width
337
338 NOTE 1: Two threads of execution can update and access
339 separate memory locations without interfering with
340 each other.
341
342 NOTE 2: A bit-field and an adjacent non-bit-field member
343 are in separate memory locations. The same applies
344 to two bit-fields, if one is declared inside a nested
345 structure declaration and the other is not, or if the two
346 are separated by a zero-length bit-field declaration,
347 or if they are separated by a non-bit-field member
348 declaration. It is not safe to concurrently update two
349 bit-fields in the same structure if all members declared
350 between them are also bit-fields, no matter what the
351 sizes of those intervening bit-fields happen to be.
352
353
354=========================
355WHAT ARE MEMORY BARRIERS?
356=========================
357
358As can be seen above, independent memory operations are effectively performed
359in random order, but this can be a problem for CPU-CPU interaction and for I/O.
360What is required is some way of intervening to instruct the compiler and the
361CPU to restrict the order.
362
363Memory barriers are such interventions. They impose a perceived partial
364ordering over the memory operations on either side of the barrier.
365
366Such enforcement is important because the CPUs and other devices in a system
367can use a variety of tricks to improve performance, including reordering,
368deferral and combination of memory operations; speculative loads; speculative
369branch prediction and various types of caching. Memory barriers are used to
370override or suppress these tricks, allowing the code to sanely control the
371interaction of multiple CPUs and/or devices.
372
373
374VARIETIES OF MEMORY BARRIER
375---------------------------
376
377Memory barriers come in four basic varieties:
378
379 (1) Write (or store) memory barriers.
380
381 A write memory barrier gives a guarantee that all the STORE operations
382 specified before the barrier will appear to happen before all the STORE
383 operations specified after the barrier with respect to the other
384 components of the system.
385
386 A write barrier is a partial ordering on stores only; it is not required
387 to have any effect on loads.
388
389 A CPU can be viewed as committing a sequence of store operations to the
390 memory system as time progresses. All stores _before_ a write barrier
391 will occur _before_ all the stores after the write barrier.
392
393 [!] Note that write barriers should normally be paired with read or
394 address-dependency barriers; see the "SMP barrier pairing" subsection.
395
396
397 (2) Address-dependency barriers (historical).
398 [!] This section is marked as HISTORICAL: it covers the long-obsolete
399 smp_read_barrier_depends() macro, the semantics of which are now
400 implicit in all marked accesses. For more up-to-date information,
401 including how compiler transformations can sometimes break address
402 dependencies, see Documentation/RCU/rcu_dereference.rst.
403
404 An address-dependency barrier is a weaker form of read barrier. In the
405 case where two loads are performed such that the second depends on the
406 result of the first (eg: the first load retrieves the address to which
407 the second load will be directed), an address-dependency barrier would
408 be required to make sure that the target of the second load is updated
409 after the address obtained by the first load is accessed.
410
411 An address-dependency barrier is a partial ordering on interdependent
412 loads only; it is not required to have any effect on stores, independent
413 loads or overlapping loads.
414
415 As mentioned in (1), the other CPUs in the system can be viewed as
416 committing sequences of stores to the memory system that the CPU being
417 considered can then perceive. An address-dependency barrier issued by
418 the CPU under consideration guarantees that for any load preceding it,
419 if that load touches one of a sequence of stores from another CPU, then
420 by the time the barrier completes, the effects of all the stores prior to
421 that touched by the load will be perceptible to any loads issued after
422 the address-dependency barrier.
423
424 See the "Examples of memory barrier sequences" subsection for diagrams
425 showing the ordering constraints.
426
427 [!] Note that the first load really has to have an _address_ dependency and
428 not a control dependency. If the address for the second load is dependent
429 on the first load, but the dependency is through a conditional rather than
430 actually loading the address itself, then it's a _control_ dependency and
431 a full read barrier or better is required. See the "Control dependencies"
432 subsection for more information.
433
434 [!] Note that address-dependency barriers should normally be paired with
435 write barriers; see the "SMP barrier pairing" subsection.
436
437 [!] Kernel release v5.9 removed kernel APIs for explicit address-
438 dependency barriers. Nowadays, APIs for marking loads from shared
439 variables such as READ_ONCE() and rcu_dereference() provide implicit
440 address-dependency barriers.
441
442 (3) Read (or load) memory barriers.
443
444 A read barrier is an address-dependency barrier plus a guarantee that all
445 the LOAD operations specified before the barrier will appear to happen
446 before all the LOAD operations specified after the barrier with respect to
447 the other components of the system.
448
449 A read barrier is a partial ordering on loads only; it is not required to
450 have any effect on stores.
451
452 Read memory barriers imply address-dependency barriers, and so can
453 substitute for them.
454
455 [!] Note that read barriers should normally be paired with write barriers;
456 see the "SMP barrier pairing" subsection.
457
458
459 (4) General memory barriers.
460
461 A general memory barrier gives a guarantee that all the LOAD and STORE
462 operations specified before the barrier will appear to happen before all
463 the LOAD and STORE operations specified after the barrier with respect to
464 the other components of the system.
465
466 A general memory barrier is a partial ordering over both loads and stores.
467
468 General memory barriers imply both read and write memory barriers, and so
469 can substitute for either.
470
471
472And a couple of implicit varieties:
473
474 (5) ACQUIRE operations.
475
476 This acts as a one-way permeable barrier. It guarantees that all memory
477 operations after the ACQUIRE operation will appear to happen after the
478 ACQUIRE operation with respect to the other components of the system.
479 ACQUIRE operations include LOCK operations and both smp_load_acquire()
480 and smp_cond_load_acquire() operations.
481
482 Memory operations that occur before an ACQUIRE operation may appear to
483 happen after it completes.
484
485 An ACQUIRE operation should almost always be paired with a RELEASE
486 operation.
487
488
489 (6) RELEASE operations.
490
491 This also acts as a one-way permeable barrier. It guarantees that all
492 memory operations before the RELEASE operation will appear to happen
493 before the RELEASE operation with respect to the other components of the
494 system. RELEASE operations include UNLOCK operations and
495 smp_store_release() operations.
496
497 Memory operations that occur after a RELEASE operation may appear to
498 happen before it completes.
499
500 The use of ACQUIRE and RELEASE operations generally precludes the need
501 for other sorts of memory barrier. In addition, a RELEASE+ACQUIRE pair is
502 -not- guaranteed to act as a full memory barrier. However, after an
503 ACQUIRE on a given variable, all memory accesses preceding any prior
504 RELEASE on that same variable are guaranteed to be visible. In other
505 words, within a given variable's critical section, all accesses of all
506 previous critical sections for that variable are guaranteed to have
507 completed.
508
509 This means that ACQUIRE acts as a minimal "acquire" operation and
510 RELEASE acts as a minimal "release" operation.
511
512A subset of the atomic operations described in atomic_t.txt have ACQUIRE and
513RELEASE variants in addition to fully-ordered and relaxed (no barrier
514semantics) definitions. For compound atomics performing both a load and a
515store, ACQUIRE semantics apply only to the load and RELEASE semantics apply
516only to the store portion of the operation.
517
518Memory barriers are only required where there's a possibility of interaction
519between two CPUs or between a CPU and a device. If it can be guaranteed that
520there won't be any such interaction in any particular piece of code, then
521memory barriers are unnecessary in that piece of code.
522
523
524Note that these are the _minimum_ guarantees. Different architectures may give
525more substantial guarantees, but they may _not_ be relied upon outside of arch
526specific code.
527
528
529WHAT MAY NOT BE ASSUMED ABOUT MEMORY BARRIERS?
530----------------------------------------------
531
532There are certain things that the Linux kernel memory barriers do not guarantee:
533
534 (*) There is no guarantee that any of the memory accesses specified before a
535 memory barrier will be _complete_ by the completion of a memory barrier
536 instruction; the barrier can be considered to draw a line in that CPU's
537 access queue that accesses of the appropriate type may not cross.
538
539 (*) There is no guarantee that issuing a memory barrier on one CPU will have
540 any direct effect on another CPU or any other hardware in the system. The
541 indirect effect will be the order in which the second CPU sees the effects
542 of the first CPU's accesses occur, but see the next point:
543
544 (*) There is no guarantee that a CPU will see the correct order of effects
545 from a second CPU's accesses, even _if_ the second CPU uses a memory
546 barrier, unless the first CPU _also_ uses a matching memory barrier (see
547 the subsection on "SMP Barrier Pairing").
548
549 (*) There is no guarantee that some intervening piece of off-the-CPU
550 hardware[*] will not reorder the memory accesses. CPU cache coherency
551 mechanisms should propagate the indirect effects of a memory barrier
552 between CPUs, but might not do so in order.
553
554 [*] For information on bus mastering DMA and coherency please read:
555
556 Documentation/driver-api/pci/pci.rst
557 Documentation/core-api/dma-api-howto.rst
558 Documentation/core-api/dma-api.rst
559
560
561ADDRESS-DEPENDENCY BARRIERS (HISTORICAL)
562----------------------------------------
563[!] This section is marked as HISTORICAL: it covers the long-obsolete
564smp_read_barrier_depends() macro, the semantics of which are now implicit
565in all marked accesses. For more up-to-date information, including
566how compiler transformations can sometimes break address dependencies,
567see Documentation/RCU/rcu_dereference.rst.
568
569As of v4.15 of the Linux kernel, an smp_mb() was added to READ_ONCE() for
570DEC Alpha, which means that about the only people who need to pay attention
571to this section are those working on DEC Alpha architecture-specific code
572and those working on READ_ONCE() itself. For those who need it, and for
573those who are interested in the history, here is the story of
574address-dependency barriers.
575
576[!] While address dependencies are observed in both load-to-load and
577load-to-store relations, address-dependency barriers are not necessary
578for load-to-store situations.
579
580The requirement of address-dependency barriers is a little subtle, and
581it's not always obvious that they're needed. To illustrate, consider the
582following sequence of events:
583
584 CPU 1 CPU 2
585 =============== ===============
586 { A == 1, B == 2, C == 3, P == &A, Q == &C }
587 B = 4;
588 <write barrier>
589 WRITE_ONCE(P, &B);
590 Q = READ_ONCE_OLD(P);
591 D = *Q;
592
593[!] READ_ONCE_OLD() corresponds to READ_ONCE() of pre-4.15 kernel, which
594doesn't imply an address-dependency barrier.
595
596There's a clear address dependency here, and it would seem that by the end of
597the sequence, Q must be either &A or &B, and that:
598
599 (Q == &A) implies (D == 1)
600 (Q == &B) implies (D == 4)
601
602But! CPU 2's perception of P may be updated _before_ its perception of B, thus
603leading to the following situation:
604
605 (Q == &B) and (D == 2) ????
606
607While this may seem like a failure of coherency or causality maintenance, it
608isn't, and this behaviour can be observed on certain real CPUs (such as the DEC
609Alpha).
610
611To deal with this, READ_ONCE() provides an implicit address-dependency barrier
612since kernel release v4.15:
613
614 CPU 1 CPU 2
615 =============== ===============
616 { A == 1, B == 2, C == 3, P == &A, Q == &C }
617 B = 4;
618 <write barrier>
619 WRITE_ONCE(P, &B);
620 Q = READ_ONCE(P);
621 <implicit address-dependency barrier>
622 D = *Q;
623
624This enforces the occurrence of one of the two implications, and prevents the
625third possibility from arising.
626
627
628[!] Note that this extremely counterintuitive situation arises most easily on
629machines with split caches, so that, for example, one cache bank processes
630even-numbered cache lines and the other bank processes odd-numbered cache
631lines. The pointer P might be stored in an odd-numbered cache line, and the
632variable B might be stored in an even-numbered cache line. Then, if the
633even-numbered bank of the reading CPU's cache is extremely busy while the
634odd-numbered bank is idle, one can see the new value of the pointer P (&B),
635but the old value of the variable B (2).
636
637
638An address-dependency barrier is not required to order dependent writes
639because the CPUs that the Linux kernel supports don't do writes until they
640are certain (1) that the write will actually happen, (2) of the location of
641the write, and (3) of the value to be written.
642But please carefully read the "CONTROL DEPENDENCIES" section and the
643Documentation/RCU/rcu_dereference.rst file: The compiler can and does break
644dependencies in a great many highly creative ways.
645
646 CPU 1 CPU 2
647 =============== ===============
648 { A == 1, B == 2, C = 3, P == &A, Q == &C }
649 B = 4;
650 <write barrier>
651 WRITE_ONCE(P, &B);
652 Q = READ_ONCE_OLD(P);
653 WRITE_ONCE(*Q, 5);
654
655Therefore, no address-dependency barrier is required to order the read into
656Q with the store into *Q. In other words, this outcome is prohibited,
657even without an implicit address-dependency barrier of modern READ_ONCE():
658
659 (Q == &B) && (B == 4)
660
661Please note that this pattern should be rare. After all, the whole point
662of dependency ordering is to -prevent- writes to the data structure, along
663with the expensive cache misses associated with those writes. This pattern
664can be used to record rare error conditions and the like, and the CPUs'
665naturally occurring ordering prevents such records from being lost.
666
667
668Note well that the ordering provided by an address dependency is local to
669the CPU containing it. See the section on "Multicopy atomicity" for
670more information.
671
672
673The address-dependency barrier is very important to the RCU system,
674for example. See rcu_assign_pointer() and rcu_dereference() in
675include/linux/rcupdate.h. This permits the current target of an RCU'd
676pointer to be replaced with a new modified target, without the replacement
677target appearing to be incompletely initialised.
678
679
680CONTROL DEPENDENCIES
681--------------------
682
683Control dependencies can be a bit tricky because current compilers do
684not understand them. The purpose of this section is to help you prevent
685the compiler's ignorance from breaking your code.
686
687A load-load control dependency requires a full read memory barrier, not
688simply an (implicit) address-dependency barrier to make it work correctly.
689Consider the following bit of code:
690
691 q = READ_ONCE(a);
692 <implicit address-dependency barrier>
693 if (q) {
694 /* BUG: No address dependency!!! */
695 p = READ_ONCE(b);
696 }
697
698This will not have the desired effect because there is no actual address
699dependency, but rather a control dependency that the CPU may short-circuit
700by attempting to predict the outcome in advance, so that other CPUs see
701the load from b as having happened before the load from a. In such a case
702what's actually required is:
703
704 q = READ_ONCE(a);
705 if (q) {
706 <read barrier>
707 p = READ_ONCE(b);
708 }
709
710However, stores are not speculated. This means that ordering -is- provided
711for load-store control dependencies, as in the following example:
712
713 q = READ_ONCE(a);
714 if (q) {
715 WRITE_ONCE(b, 1);
716 }
717
718Control dependencies pair normally with other types of barriers.
719That said, please note that neither READ_ONCE() nor WRITE_ONCE()
720are optional! Without the READ_ONCE(), the compiler might combine the
721load from 'a' with other loads from 'a'. Without the WRITE_ONCE(),
722the compiler might combine the store to 'b' with other stores to 'b'.
723Either can result in highly counterintuitive effects on ordering.
724
725Worse yet, if the compiler is able to prove (say) that the value of
726variable 'a' is always non-zero, it would be well within its rights
727to optimize the original example by eliminating the "if" statement
728as follows:
729
730 q = a;
731 b = 1; /* BUG: Compiler and CPU can both reorder!!! */
732
733So don't leave out the READ_ONCE().
734
735It is tempting to try to enforce ordering on identical stores on both
736branches of the "if" statement as follows:
737
738 q = READ_ONCE(a);
739 if (q) {
740 barrier();
741 WRITE_ONCE(b, 1);
742 do_something();
743 } else {
744 barrier();
745 WRITE_ONCE(b, 1);
746 do_something_else();
747 }
748
749Unfortunately, current compilers will transform this as follows at high
750optimization levels:
751
752 q = READ_ONCE(a);
753 barrier();
754 WRITE_ONCE(b, 1); /* BUG: No ordering vs. load from a!!! */
755 if (q) {
756 /* WRITE_ONCE(b, 1); -- moved up, BUG!!! */
757 do_something();
758 } else {
759 /* WRITE_ONCE(b, 1); -- moved up, BUG!!! */
760 do_something_else();
761 }
762
763Now there is no conditional between the load from 'a' and the store to
764'b', which means that the CPU is within its rights to reorder them:
765The conditional is absolutely required, and must be present in the
766assembly code even after all compiler optimizations have been applied.
767Therefore, if you need ordering in this example, you need explicit
768memory barriers, for example, smp_store_release():
769
770 q = READ_ONCE(a);
771 if (q) {
772 smp_store_release(&b, 1);
773 do_something();
774 } else {
775 smp_store_release(&b, 1);
776 do_something_else();
777 }
778
779In contrast, without explicit memory barriers, two-legged-if control
780ordering is guaranteed only when the stores differ, for example:
781
782 q = READ_ONCE(a);
783 if (q) {
784 WRITE_ONCE(b, 1);
785 do_something();
786 } else {
787 WRITE_ONCE(b, 2);
788 do_something_else();
789 }
790
791The initial READ_ONCE() is still required to prevent the compiler from
792proving the value of 'a'.
793
794In addition, you need to be careful what you do with the local variable 'q',
795otherwise the compiler might be able to guess the value and again remove
796the needed conditional. For example:
797
798 q = READ_ONCE(a);
799 if (q % MAX) {
800 WRITE_ONCE(b, 1);
801 do_something();
802 } else {
803 WRITE_ONCE(b, 2);
804 do_something_else();
805 }
806
807If MAX is defined to be 1, then the compiler knows that (q % MAX) is
808equal to zero, in which case the compiler is within its rights to
809transform the above code into the following:
810
811 q = READ_ONCE(a);
812 WRITE_ONCE(b, 2);
813 do_something_else();
814
815Given this transformation, the CPU is not required to respect the ordering
816between the load from variable 'a' and the store to variable 'b'. It is
817tempting to add a barrier(), but this does not help. The conditional
818is gone, and the barrier won't bring it back. Therefore, if you are
819relying on this ordering, you should make sure that MAX is greater than
820one, perhaps as follows:
821
822 q = READ_ONCE(a);
823 BUILD_BUG_ON(MAX <= 1); /* Order load from a with store to b. */
824 if (q % MAX) {
825 WRITE_ONCE(b, 1);
826 do_something();
827 } else {
828 WRITE_ONCE(b, 2);
829 do_something_else();
830 }
831
832Please note once again that the stores to 'b' differ. If they were
833identical, as noted earlier, the compiler could pull this store outside
834of the 'if' statement.
835
836You must also be careful not to rely too much on boolean short-circuit
837evaluation. Consider this example:
838
839 q = READ_ONCE(a);
840 if (q || 1 > 0)
841 WRITE_ONCE(b, 1);
842
843Because the first condition cannot fault and the second condition is
844always true, the compiler can transform this example as following,
845defeating control dependency:
846
847 q = READ_ONCE(a);
848 WRITE_ONCE(b, 1);
849
850This example underscores the need to ensure that the compiler cannot
851out-guess your code. More generally, although READ_ONCE() does force
852the compiler to actually emit code for a given load, it does not force
853the compiler to use the results.
854
855In addition, control dependencies apply only to the then-clause and
856else-clause of the if-statement in question. In particular, it does
857not necessarily apply to code following the if-statement:
858
859 q = READ_ONCE(a);
860 if (q) {
861 WRITE_ONCE(b, 1);
862 } else {
863 WRITE_ONCE(b, 2);
864 }
865 WRITE_ONCE(c, 1); /* BUG: No ordering against the read from 'a'. */
866
867It is tempting to argue that there in fact is ordering because the
868compiler cannot reorder volatile accesses and also cannot reorder
869the writes to 'b' with the condition. Unfortunately for this line
870of reasoning, the compiler might compile the two writes to 'b' as
871conditional-move instructions, as in this fanciful pseudo-assembly
872language:
873
874 ld r1,a
875 cmp r1,$0
876 cmov,ne r4,$1
877 cmov,eq r4,$2
878 st r4,b
879 st $1,c
880
881A weakly ordered CPU would have no dependency of any sort between the load
882from 'a' and the store to 'c'. The control dependencies would extend
883only to the pair of cmov instructions and the store depending on them.
884In short, control dependencies apply only to the stores in the then-clause
885and else-clause of the if-statement in question (including functions
886invoked by those two clauses), not to code following that if-statement.
887
888
889Note well that the ordering provided by a control dependency is local
890to the CPU containing it. See the section on "Multicopy atomicity"
891for more information.
892
893
894In summary:
895
896 (*) Control dependencies can order prior loads against later stores.
897 However, they do -not- guarantee any other sort of ordering:
898 Not prior loads against later loads, nor prior stores against
899 later anything. If you need these other forms of ordering,
900 use smp_rmb(), smp_wmb(), or, in the case of prior stores and
901 later loads, smp_mb().
902
903 (*) If both legs of the "if" statement begin with identical stores to
904 the same variable, then those stores must be ordered, either by
905 preceding both of them with smp_mb() or by using smp_store_release()
906 to carry out the stores. Please note that it is -not- sufficient
907 to use barrier() at beginning of each leg of the "if" statement
908 because, as shown by the example above, optimizing compilers can
909 destroy the control dependency while respecting the letter of the
910 barrier() law.
911
912 (*) Control dependencies require at least one run-time conditional
913 between the prior load and the subsequent store, and this
914 conditional must involve the prior load. If the compiler is able
915 to optimize the conditional away, it will have also optimized
916 away the ordering. Careful use of READ_ONCE() and WRITE_ONCE()
917 can help to preserve the needed conditional.
918
919 (*) Control dependencies require that the compiler avoid reordering the
920 dependency into nonexistence. Careful use of READ_ONCE() or
921 atomic{,64}_read() can help to preserve your control dependency.
922 Please see the COMPILER BARRIER section for more information.
923
924 (*) Control dependencies apply only to the then-clause and else-clause
925 of the if-statement containing the control dependency, including
926 any functions that these two clauses call. Control dependencies
927 do -not- apply to code following the if-statement containing the
928 control dependency.
929
930 (*) Control dependencies pair normally with other types of barriers.
931
932 (*) Control dependencies do -not- provide multicopy atomicity. If you
933 need all the CPUs to see a given store at the same time, use smp_mb().
934
935 (*) Compilers do not understand control dependencies. It is therefore
936 your job to ensure that they do not break your code.
937
938
939SMP BARRIER PAIRING
940-------------------
941
942When dealing with CPU-CPU interactions, certain types of memory barrier should
943always be paired. A lack of appropriate pairing is almost certainly an error.
944
945General barriers pair with each other, though they also pair with most
946other types of barriers, albeit without multicopy atomicity. An acquire
947barrier pairs with a release barrier, but both may also pair with other
948barriers, including of course general barriers. A write barrier pairs
949with an address-dependency barrier, a control dependency, an acquire barrier,
950a release barrier, a read barrier, or a general barrier. Similarly a
951read barrier, control dependency, or an address-dependency barrier pairs
952with a write barrier, an acquire barrier, a release barrier, or a
953general barrier:
954
955 CPU 1 CPU 2
956 =============== ===============
957 WRITE_ONCE(a, 1);
958 <write barrier>
959 WRITE_ONCE(b, 2); x = READ_ONCE(b);
960 <read barrier>
961 y = READ_ONCE(a);
962
963Or:
964
965 CPU 1 CPU 2
966 =============== ===============================
967 a = 1;
968 <write barrier>
969 WRITE_ONCE(b, &a); x = READ_ONCE(b);
970 <implicit address-dependency barrier>
971 y = *x;
972
973Or even:
974
975 CPU 1 CPU 2
976 =============== ===============================
977 r1 = READ_ONCE(y);
978 <general barrier>
979 WRITE_ONCE(x, 1); if (r2 = READ_ONCE(x)) {
980 <implicit control dependency>
981 WRITE_ONCE(y, 1);
982 }
983
984 assert(r1 == 0 || r2 == 0);
985
986Basically, the read barrier always has to be there, even though it can be of
987the "weaker" type.
988
989[!] Note that the stores before the write barrier would normally be expected to
990match the loads after the read barrier or the address-dependency barrier, and
991vice versa:
992
993 CPU 1 CPU 2
994 =================== ===================
995 WRITE_ONCE(a, 1); }---- --->{ v = READ_ONCE(c);
996 WRITE_ONCE(b, 2); } \ / { w = READ_ONCE(d);
997 <write barrier> \ <read barrier>
998 WRITE_ONCE(c, 3); } / \ { x = READ_ONCE(a);
999 WRITE_ONCE(d, 4); }---- --->{ y = READ_ONCE(b);
1000
1001
1002EXAMPLES OF MEMORY BARRIER SEQUENCES
1003------------------------------------
1004
1005Firstly, write barriers act as partial orderings on store operations.
1006Consider the following sequence of events:
1007
1008 CPU 1
1009 =======================
1010 STORE A = 1
1011 STORE B = 2
1012 STORE C = 3
1013 <write barrier>
1014 STORE D = 4
1015 STORE E = 5
1016
1017This sequence of events is committed to the memory coherence system in an order
1018that the rest of the system might perceive as the unordered set of { STORE A,
1019STORE B, STORE C } all occurring before the unordered set of { STORE D, STORE E
1020}:
1021
1022 +-------+ : :
1023 | | +------+
1024 | |------>| C=3 | } /\
1025 | | : +------+ }----- \ -----> Events perceptible to
1026 | | : | A=1 | } \/ the rest of the system
1027 | | : +------+ }
1028 | CPU 1 | : | B=2 | }
1029 | | +------+ }
1030 | | wwwwwwwwwwwwwwww } <--- At this point the write barrier
1031 | | +------+ } requires all stores prior to the
1032 | | : | E=5 | } barrier to be committed before
1033 | | : +------+ } further stores may take place
1034 | |------>| D=4 | }
1035 | | +------+
1036 +-------+ : :
1037 |
1038 | Sequence in which stores are committed to the
1039 | memory system by CPU 1
1040 V
1041
1042
1043Secondly, address-dependency barriers act as partial orderings on address-
1044dependent loads. Consider the following sequence of events:
1045
1046 CPU 1 CPU 2
1047 ======================= =======================
1048 { B = 7; X = 9; Y = 8; C = &Y }
1049 STORE A = 1
1050 STORE B = 2
1051 <write barrier>
1052 STORE C = &B LOAD X
1053 STORE D = 4 LOAD C (gets &B)
1054 LOAD *C (reads B)
1055
1056Without intervention, CPU 2 may perceive the events on CPU 1 in some
1057effectively random order, despite the write barrier issued by CPU 1:
1058
1059 +-------+ : : : :
1060 | | +------+ +-------+ | Sequence of update
1061 | |------>| B=2 |----- --->| Y->8 | | of perception on
1062 | | : +------+ \ +-------+ | CPU 2
1063 | CPU 1 | : | A=1 | \ --->| C->&Y | V
1064 | | +------+ | +-------+
1065 | | wwwwwwwwwwwwwwww | : :
1066 | | +------+ | : :
1067 | | : | C=&B |--- | : : +-------+
1068 | | : +------+ \ | +-------+ | |
1069 | |------>| D=4 | ----------->| C->&B |------>| |
1070 | | +------+ | +-------+ | |
1071 +-------+ : : | : : | |
1072 | : : | |
1073 | : : | CPU 2 |
1074 | +-------+ | |
1075 Apparently incorrect ---> | | B->7 |------>| |
1076 perception of B (!) | +-------+ | |
1077 | : : | |
1078 | +-------+ | |
1079 The load of X holds ---> \ | X->9 |------>| |
1080 up the maintenance \ +-------+ | |
1081 of coherence of B ----->| B->2 | +-------+
1082 +-------+
1083 : :
1084
1085
1086In the above example, CPU 2 perceives that B is 7, despite the load of *C
1087(which would be B) coming after the LOAD of C.
1088
1089If, however, an address-dependency barrier were to be placed between the load
1090of C and the load of *C (ie: B) on CPU 2:
1091
1092 CPU 1 CPU 2
1093 ======================= =======================
1094 { B = 7; X = 9; Y = 8; C = &Y }
1095 STORE A = 1
1096 STORE B = 2
1097 <write barrier>
1098 STORE C = &B LOAD X
1099 STORE D = 4 LOAD C (gets &B)
1100 <address-dependency barrier>
1101 LOAD *C (reads B)
1102
1103then the following will occur:
1104
1105 +-------+ : : : :
1106 | | +------+ +-------+
1107 | |------>| B=2 |----- --->| Y->8 |
1108 | | : +------+ \ +-------+
1109 | CPU 1 | : | A=1 | \ --->| C->&Y |
1110 | | +------+ | +-------+
1111 | | wwwwwwwwwwwwwwww | : :
1112 | | +------+ | : :
1113 | | : | C=&B |--- | : : +-------+
1114 | | : +------+ \ | +-------+ | |
1115 | |------>| D=4 | ----------->| C->&B |------>| |
1116 | | +------+ | +-------+ | |
1117 +-------+ : : | : : | |
1118 | : : | |
1119 | : : | CPU 2 |
1120 | +-------+ | |
1121 | | X->9 |------>| |
1122 | +-------+ | |
1123 Makes sure all effects ---> \ aaaaaaaaaaaaaaaaa | |
1124 prior to the store of C \ +-------+ | |
1125 are perceptible to ----->| B->2 |------>| |
1126 subsequent loads +-------+ | |
1127 : : +-------+
1128
1129
1130And thirdly, a read barrier acts as a partial order on loads. Consider the
1131following sequence of events:
1132
1133 CPU 1 CPU 2
1134 ======================= =======================
1135 { A = 0, B = 9 }
1136 STORE A=1
1137 <write barrier>
1138 STORE B=2
1139 LOAD B
1140 LOAD A
1141
1142Without intervention, CPU 2 may then choose to perceive the events on CPU 1 in
1143some effectively random order, despite the write barrier issued by CPU 1:
1144
1145 +-------+ : : : :
1146 | | +------+ +-------+
1147 | |------>| A=1 |------ --->| A->0 |
1148 | | +------+ \ +-------+
1149 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1150 | | +------+ | +-------+
1151 | |------>| B=2 |--- | : :
1152 | | +------+ \ | : : +-------+
1153 +-------+ : : \ | +-------+ | |
1154 ---------->| B->2 |------>| |
1155 | +-------+ | CPU 2 |
1156 | | A->0 |------>| |
1157 | +-------+ | |
1158 | : : +-------+
1159 \ : :
1160 \ +-------+
1161 ---->| A->1 |
1162 +-------+
1163 : :
1164
1165
1166If, however, a read barrier were to be placed between the load of B and the
1167load of A on CPU 2:
1168
1169 CPU 1 CPU 2
1170 ======================= =======================
1171 { A = 0, B = 9 }
1172 STORE A=1
1173 <write barrier>
1174 STORE B=2
1175 LOAD B
1176 <read barrier>
1177 LOAD A
1178
1179then the partial ordering imposed by CPU 1 will be perceived correctly by CPU
11802:
1181
1182 +-------+ : : : :
1183 | | +------+ +-------+
1184 | |------>| A=1 |------ --->| A->0 |
1185 | | +------+ \ +-------+
1186 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1187 | | +------+ | +-------+
1188 | |------>| B=2 |--- | : :
1189 | | +------+ \ | : : +-------+
1190 +-------+ : : \ | +-------+ | |
1191 ---------->| B->2 |------>| |
1192 | +-------+ | CPU 2 |
1193 | : : | |
1194 | : : | |
1195 At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
1196 barrier causes all effects \ +-------+ | |
1197 prior to the storage of B ---->| A->1 |------>| |
1198 to be perceptible to CPU 2 +-------+ | |
1199 : : +-------+
1200
1201
1202To illustrate this more completely, consider what could happen if the code
1203contained a load of A either side of the read barrier:
1204
1205 CPU 1 CPU 2
1206 ======================= =======================
1207 { A = 0, B = 9 }
1208 STORE A=1
1209 <write barrier>
1210 STORE B=2
1211 LOAD B
1212 LOAD A [first load of A]
1213 <read barrier>
1214 LOAD A [second load of A]
1215
1216Even though the two loads of A both occur after the load of B, they may both
1217come up with different values:
1218
1219 +-------+ : : : :
1220 | | +------+ +-------+
1221 | |------>| A=1 |------ --->| A->0 |
1222 | | +------+ \ +-------+
1223 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1224 | | +------+ | +-------+
1225 | |------>| B=2 |--- | : :
1226 | | +------+ \ | : : +-------+
1227 +-------+ : : \ | +-------+ | |
1228 ---------->| B->2 |------>| |
1229 | +-------+ | CPU 2 |
1230 | : : | |
1231 | : : | |
1232 | +-------+ | |
1233 | | A->0 |------>| 1st |
1234 | +-------+ | |
1235 At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
1236 barrier causes all effects \ +-------+ | |
1237 prior to the storage of B ---->| A->1 |------>| 2nd |
1238 to be perceptible to CPU 2 +-------+ | |
1239 : : +-------+
1240
1241
1242But it may be that the update to A from CPU 1 becomes perceptible to CPU 2
1243before the read barrier completes anyway:
1244
1245 +-------+ : : : :
1246 | | +------+ +-------+
1247 | |------>| A=1 |------ --->| A->0 |
1248 | | +------+ \ +-------+
1249 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1250 | | +------+ | +-------+
1251 | |------>| B=2 |--- | : :
1252 | | +------+ \ | : : +-------+
1253 +-------+ : : \ | +-------+ | |
1254 ---------->| B->2 |------>| |
1255 | +-------+ | CPU 2 |
1256 | : : | |
1257 \ : : | |
1258 \ +-------+ | |
1259 ---->| A->1 |------>| 1st |
1260 +-------+ | |
1261 rrrrrrrrrrrrrrrrr | |
1262 +-------+ | |
1263 | A->1 |------>| 2nd |
1264 +-------+ | |
1265 : : +-------+
1266
1267
1268The guarantee is that the second load will always come up with A == 1 if the
1269load of B came up with B == 2. No such guarantee exists for the first load of
1270A; that may come up with either A == 0 or A == 1.
1271
1272
1273READ MEMORY BARRIERS VS LOAD SPECULATION
1274----------------------------------------
1275
1276Many CPUs speculate with loads: that is they see that they will need to load an
1277item from memory, and they find a time where they're not using the bus for any
1278other loads, and so do the load in advance - even though they haven't actually
1279got to that point in the instruction execution flow yet. This permits the
1280actual load instruction to potentially complete immediately because the CPU
1281already has the value to hand.
1282
1283It may turn out that the CPU didn't actually need the value - perhaps because a
1284branch circumvented the load - in which case it can discard the value or just
1285cache it for later use.
1286
1287Consider:
1288
1289 CPU 1 CPU 2
1290 ======================= =======================
1291 LOAD B
1292 DIVIDE } Divide instructions generally
1293 DIVIDE } take a long time to perform
1294 LOAD A
1295
1296Which might appear as this:
1297
1298 : : +-------+
1299 +-------+ | |
1300 --->| B->2 |------>| |
1301 +-------+ | CPU 2 |
1302 : :DIVIDE | |
1303 +-------+ | |
1304 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1305 division speculates on the +-------+ ~ | |
1306 LOAD of A : : ~ | |
1307 : :DIVIDE | |
1308 : : ~ | |
1309 Once the divisions are complete --> : : ~-->| |
1310 the CPU can then perform the : : | |
1311 LOAD with immediate effect : : +-------+
1312
1313
1314Placing a read barrier or an address-dependency barrier just before the second
1315load:
1316
1317 CPU 1 CPU 2
1318 ======================= =======================
1319 LOAD B
1320 DIVIDE
1321 DIVIDE
1322 <read barrier>
1323 LOAD A
1324
1325will force any value speculatively obtained to be reconsidered to an extent
1326dependent on the type of barrier used. If there was no change made to the
1327speculated memory location, then the speculated value will just be used:
1328
1329 : : +-------+
1330 +-------+ | |
1331 --->| B->2 |------>| |
1332 +-------+ | CPU 2 |
1333 : :DIVIDE | |
1334 +-------+ | |
1335 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1336 division speculates on the +-------+ ~ | |
1337 LOAD of A : : ~ | |
1338 : :DIVIDE | |
1339 : : ~ | |
1340 : : ~ | |
1341 rrrrrrrrrrrrrrrr~ | |
1342 : : ~ | |
1343 : : ~-->| |
1344 : : | |
1345 : : +-------+
1346
1347
1348but if there was an update or an invalidation from another CPU pending, then
1349the speculation will be cancelled and the value reloaded:
1350
1351 : : +-------+
1352 +-------+ | |
1353 --->| B->2 |------>| |
1354 +-------+ | CPU 2 |
1355 : :DIVIDE | |
1356 +-------+ | |
1357 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1358 division speculates on the +-------+ ~ | |
1359 LOAD of A : : ~ | |
1360 : :DIVIDE | |
1361 : : ~ | |
1362 : : ~ | |
1363 rrrrrrrrrrrrrrrrr | |
1364 +-------+ | |
1365 The speculation is discarded ---> --->| A->1 |------>| |
1366 and an updated value is +-------+ | |
1367 retrieved : : +-------+
1368
1369
1370MULTICOPY ATOMICITY
1371--------------------
1372
1373Multicopy atomicity is a deeply intuitive notion about ordering that is
1374not always provided by real computer systems, namely that a given store
1375becomes visible at the same time to all CPUs, or, alternatively, that all
1376CPUs agree on the order in which all stores become visible. However,
1377support of full multicopy atomicity would rule out valuable hardware
1378optimizations, so a weaker form called ``other multicopy atomicity''
1379instead guarantees only that a given store becomes visible at the same
1380time to all -other- CPUs. The remainder of this document discusses this
1381weaker form, but for brevity will call it simply ``multicopy atomicity''.
1382
1383The following example demonstrates multicopy atomicity:
1384
1385 CPU 1 CPU 2 CPU 3
1386 ======================= ======================= =======================
1387 { X = 0, Y = 0 }
1388 STORE X=1 r1=LOAD X (reads 1) LOAD Y (reads 1)
1389 <general barrier> <read barrier>
1390 STORE Y=r1 LOAD X
1391
1392Suppose that CPU 2's load from X returns 1, which it then stores to Y,
1393and CPU 3's load from Y returns 1. This indicates that CPU 1's store
1394to X precedes CPU 2's load from X and that CPU 2's store to Y precedes
1395CPU 3's load from Y. In addition, the memory barriers guarantee that
1396CPU 2 executes its load before its store, and CPU 3 loads from Y before
1397it loads from X. The question is then "Can CPU 3's load from X return 0?"
1398
1399Because CPU 3's load from X in some sense comes after CPU 2's load, it
1400is natural to expect that CPU 3's load from X must therefore return 1.
1401This expectation follows from multicopy atomicity: if a load executing
1402on CPU B follows a load from the same variable executing on CPU A (and
1403CPU A did not originally store the value which it read), then on
1404multicopy-atomic systems, CPU B's load must return either the same value
1405that CPU A's load did or some later value. However, the Linux kernel
1406does not require systems to be multicopy atomic.
1407
1408The use of a general memory barrier in the example above compensates
1409for any lack of multicopy atomicity. In the example, if CPU 2's load
1410from X returns 1 and CPU 3's load from Y returns 1, then CPU 3's load
1411from X must indeed also return 1.
1412
1413However, dependencies, read barriers, and write barriers are not always
1414able to compensate for non-multicopy atomicity. For example, suppose
1415that CPU 2's general barrier is removed from the above example, leaving
1416only the data dependency shown below:
1417
1418 CPU 1 CPU 2 CPU 3
1419 ======================= ======================= =======================
1420 { X = 0, Y = 0 }
1421 STORE X=1 r1=LOAD X (reads 1) LOAD Y (reads 1)
1422 <data dependency> <read barrier>
1423 STORE Y=r1 LOAD X (reads 0)
1424
1425This substitution allows non-multicopy atomicity to run rampant: in
1426this example, it is perfectly legal for CPU 2's load from X to return 1,
1427CPU 3's load from Y to return 1, and its load from X to return 0.
1428
1429The key point is that although CPU 2's data dependency orders its load
1430and store, it does not guarantee to order CPU 1's store. Thus, if this
1431example runs on a non-multicopy-atomic system where CPUs 1 and 2 share a
1432store buffer or a level of cache, CPU 2 might have early access to CPU 1's
1433writes. General barriers are therefore required to ensure that all CPUs
1434agree on the combined order of multiple accesses.
1435
1436General barriers can compensate not only for non-multicopy atomicity,
1437but can also generate additional ordering that can ensure that -all-
1438CPUs will perceive the same order of -all- operations. In contrast, a
1439chain of release-acquire pairs do not provide this additional ordering,
1440which means that only those CPUs on the chain are guaranteed to agree
1441on the combined order of the accesses. For example, switching to C code
1442in deference to the ghost of Herman Hollerith:
1443
1444 int u, v, x, y, z;
1445
1446 void cpu0(void)
1447 {
1448 r0 = smp_load_acquire(&x);
1449 WRITE_ONCE(u, 1);
1450 smp_store_release(&y, 1);
1451 }
1452
1453 void cpu1(void)
1454 {
1455 r1 = smp_load_acquire(&y);
1456 r4 = READ_ONCE(v);
1457 r5 = READ_ONCE(u);
1458 smp_store_release(&z, 1);
1459 }
1460
1461 void cpu2(void)
1462 {
1463 r2 = smp_load_acquire(&z);
1464 smp_store_release(&x, 1);
1465 }
1466
1467 void cpu3(void)
1468 {
1469 WRITE_ONCE(v, 1);
1470 smp_mb();
1471 r3 = READ_ONCE(u);
1472 }
1473
1474Because cpu0(), cpu1(), and cpu2() participate in a chain of
1475smp_store_release()/smp_load_acquire() pairs, the following outcome
1476is prohibited:
1477
1478 r0 == 1 && r1 == 1 && r2 == 1
1479
1480Furthermore, because of the release-acquire relationship between cpu0()
1481and cpu1(), cpu1() must see cpu0()'s writes, so that the following
1482outcome is prohibited:
1483
1484 r1 == 1 && r5 == 0
1485
1486However, the ordering provided by a release-acquire chain is local
1487to the CPUs participating in that chain and does not apply to cpu3(),
1488at least aside from stores. Therefore, the following outcome is possible:
1489
1490 r0 == 0 && r1 == 1 && r2 == 1 && r3 == 0 && r4 == 0
1491
1492As an aside, the following outcome is also possible:
1493
1494 r0 == 0 && r1 == 1 && r2 == 1 && r3 == 0 && r4 == 0 && r5 == 1
1495
1496Although cpu0(), cpu1(), and cpu2() will see their respective reads and
1497writes in order, CPUs not involved in the release-acquire chain might
1498well disagree on the order. This disagreement stems from the fact that
1499the weak memory-barrier instructions used to implement smp_load_acquire()
1500and smp_store_release() are not required to order prior stores against
1501subsequent loads in all cases. This means that cpu3() can see cpu0()'s
1502store to u as happening -after- cpu1()'s load from v, even though
1503both cpu0() and cpu1() agree that these two operations occurred in the
1504intended order.
1505
1506However, please keep in mind that smp_load_acquire() is not magic.
1507In particular, it simply reads from its argument with ordering. It does
1508-not- ensure that any particular value will be read. Therefore, the
1509following outcome is possible:
1510
1511 r0 == 0 && r1 == 0 && r2 == 0 && r5 == 0
1512
1513Note that this outcome can happen even on a mythical sequentially
1514consistent system where nothing is ever reordered.
1515
1516To reiterate, if your code requires full ordering of all operations,
1517use general barriers throughout.
1518
1519
1520========================
1521EXPLICIT KERNEL BARRIERS
1522========================
1523
1524The Linux kernel has a variety of different barriers that act at different
1525levels:
1526
1527 (*) Compiler barrier.
1528
1529 (*) CPU memory barriers.
1530
1531
1532COMPILER BARRIER
1533----------------
1534
1535The Linux kernel has an explicit compiler barrier function that prevents the
1536compiler from moving the memory accesses either side of it to the other side:
1537
1538 barrier();
1539
1540This is a general barrier -- there are no read-read or write-write
1541variants of barrier(). However, READ_ONCE() and WRITE_ONCE() can be
1542thought of as weak forms of barrier() that affect only the specific
1543accesses flagged by the READ_ONCE() or WRITE_ONCE().
1544
1545The barrier() function has the following effects:
1546
1547 (*) Prevents the compiler from reordering accesses following the
1548 barrier() to precede any accesses preceding the barrier().
1549 One example use for this property is to ease communication between
1550 interrupt-handler code and the code that was interrupted.
1551
1552 (*) Within a loop, forces the compiler to load the variables used
1553 in that loop's conditional on each pass through that loop.
1554
1555The READ_ONCE() and WRITE_ONCE() functions can prevent any number of
1556optimizations that, while perfectly safe in single-threaded code, can
1557be fatal in concurrent code. Here are some examples of these sorts
1558of optimizations:
1559
1560 (*) The compiler is within its rights to reorder loads and stores
1561 to the same variable, and in some cases, the CPU is within its
1562 rights to reorder loads to the same variable. This means that
1563 the following code:
1564
1565 a[0] = x;
1566 a[1] = x;
1567
1568 Might result in an older value of x stored in a[1] than in a[0].
1569 Prevent both the compiler and the CPU from doing this as follows:
1570
1571 a[0] = READ_ONCE(x);
1572 a[1] = READ_ONCE(x);
1573
1574 In short, READ_ONCE() and WRITE_ONCE() provide cache coherence for
1575 accesses from multiple CPUs to a single variable.
1576
1577 (*) The compiler is within its rights to merge successive loads from
1578 the same variable. Such merging can cause the compiler to "optimize"
1579 the following code:
1580
1581 while (tmp = a)
1582 do_something_with(tmp);
1583
1584 into the following code, which, although in some sense legitimate
1585 for single-threaded code, is almost certainly not what the developer
1586 intended:
1587
1588 if (tmp = a)
1589 for (;;)
1590 do_something_with(tmp);
1591
1592 Use READ_ONCE() to prevent the compiler from doing this to you:
1593
1594 while (tmp = READ_ONCE(a))
1595 do_something_with(tmp);
1596
1597 (*) The compiler is within its rights to reload a variable, for example,
1598 in cases where high register pressure prevents the compiler from
1599 keeping all data of interest in registers. The compiler might
1600 therefore optimize the variable 'tmp' out of our previous example:
1601
1602 while (tmp = a)
1603 do_something_with(tmp);
1604
1605 This could result in the following code, which is perfectly safe in
1606 single-threaded code, but can be fatal in concurrent code:
1607
1608 while (a)
1609 do_something_with(a);
1610
1611 For example, the optimized version of this code could result in
1612 passing a zero to do_something_with() in the case where the variable
1613 a was modified by some other CPU between the "while" statement and
1614 the call to do_something_with().
1615
1616 Again, use READ_ONCE() to prevent the compiler from doing this:
1617
1618 while (tmp = READ_ONCE(a))
1619 do_something_with(tmp);
1620
1621 Note that if the compiler runs short of registers, it might save
1622 tmp onto the stack. The overhead of this saving and later restoring
1623 is why compilers reload variables. Doing so is perfectly safe for
1624 single-threaded code, so you need to tell the compiler about cases
1625 where it is not safe.
1626
1627 (*) The compiler is within its rights to omit a load entirely if it knows
1628 what the value will be. For example, if the compiler can prove that
1629 the value of variable 'a' is always zero, it can optimize this code:
1630
1631 while (tmp = a)
1632 do_something_with(tmp);
1633
1634 Into this:
1635
1636 do { } while (0);
1637
1638 This transformation is a win for single-threaded code because it
1639 gets rid of a load and a branch. The problem is that the compiler
1640 will carry out its proof assuming that the current CPU is the only
1641 one updating variable 'a'. If variable 'a' is shared, then the
1642 compiler's proof will be erroneous. Use READ_ONCE() to tell the
1643 compiler that it doesn't know as much as it thinks it does:
1644
1645 while (tmp = READ_ONCE(a))
1646 do_something_with(tmp);
1647
1648 But please note that the compiler is also closely watching what you
1649 do with the value after the READ_ONCE(). For example, suppose you
1650 do the following and MAX is a preprocessor macro with the value 1:
1651
1652 while ((tmp = READ_ONCE(a)) % MAX)
1653 do_something_with(tmp);
1654
1655 Then the compiler knows that the result of the "%" operator applied
1656 to MAX will always be zero, again allowing the compiler to optimize
1657 the code into near-nonexistence. (It will still load from the
1658 variable 'a'.)
1659
1660 (*) Similarly, the compiler is within its rights to omit a store entirely
1661 if it knows that the variable already has the value being stored.
1662 Again, the compiler assumes that the current CPU is the only one
1663 storing into the variable, which can cause the compiler to do the
1664 wrong thing for shared variables. For example, suppose you have
1665 the following:
1666
1667 a = 0;
1668 ... Code that does not store to variable a ...
1669 a = 0;
1670
1671 The compiler sees that the value of variable 'a' is already zero, so
1672 it might well omit the second store. This would come as a fatal
1673 surprise if some other CPU might have stored to variable 'a' in the
1674 meantime.
1675
1676 Use WRITE_ONCE() to prevent the compiler from making this sort of
1677 wrong guess:
1678
1679 WRITE_ONCE(a, 0);
1680 ... Code that does not store to variable a ...
1681 WRITE_ONCE(a, 0);
1682
1683 (*) The compiler is within its rights to reorder memory accesses unless
1684 you tell it not to. For example, consider the following interaction
1685 between process-level code and an interrupt handler:
1686
1687 void process_level(void)
1688 {
1689 msg = get_message();
1690 flag = true;
1691 }
1692
1693 void interrupt_handler(void)
1694 {
1695 if (flag)
1696 process_message(msg);
1697 }
1698
1699 There is nothing to prevent the compiler from transforming
1700 process_level() to the following, in fact, this might well be a
1701 win for single-threaded code:
1702
1703 void process_level(void)
1704 {
1705 flag = true;
1706 msg = get_message();
1707 }
1708
1709 If the interrupt occurs between these two statement, then
1710 interrupt_handler() might be passed a garbled msg. Use WRITE_ONCE()
1711 to prevent this as follows:
1712
1713 void process_level(void)
1714 {
1715 WRITE_ONCE(msg, get_message());
1716 WRITE_ONCE(flag, true);
1717 }
1718
1719 void interrupt_handler(void)
1720 {
1721 if (READ_ONCE(flag))
1722 process_message(READ_ONCE(msg));
1723 }
1724
1725 Note that the READ_ONCE() and WRITE_ONCE() wrappers in
1726 interrupt_handler() are needed if this interrupt handler can itself
1727 be interrupted by something that also accesses 'flag' and 'msg',
1728 for example, a nested interrupt or an NMI. Otherwise, READ_ONCE()
1729 and WRITE_ONCE() are not needed in interrupt_handler() other than
1730 for documentation purposes. (Note also that nested interrupts
1731 do not typically occur in modern Linux kernels, in fact, if an
1732 interrupt handler returns with interrupts enabled, you will get a
1733 WARN_ONCE() splat.)
1734
1735 You should assume that the compiler can move READ_ONCE() and
1736 WRITE_ONCE() past code not containing READ_ONCE(), WRITE_ONCE(),
1737 barrier(), or similar primitives.
1738
1739 This effect could also be achieved using barrier(), but READ_ONCE()
1740 and WRITE_ONCE() are more selective: With READ_ONCE() and
1741 WRITE_ONCE(), the compiler need only forget the contents of the
1742 indicated memory locations, while with barrier() the compiler must
1743 discard the value of all memory locations that it has currently
1744 cached in any machine registers. Of course, the compiler must also
1745 respect the order in which the READ_ONCE()s and WRITE_ONCE()s occur,
1746 though the CPU of course need not do so.
1747
1748 (*) The compiler is within its rights to invent stores to a variable,
1749 as in the following example:
1750
1751 if (a)
1752 b = a;
1753 else
1754 b = 42;
1755
1756 The compiler might save a branch by optimizing this as follows:
1757
1758 b = 42;
1759 if (a)
1760 b = a;
1761
1762 In single-threaded code, this is not only safe, but also saves
1763 a branch. Unfortunately, in concurrent code, this optimization
1764 could cause some other CPU to see a spurious value of 42 -- even
1765 if variable 'a' was never zero -- when loading variable 'b'.
1766 Use WRITE_ONCE() to prevent this as follows:
1767
1768 if (a)
1769 WRITE_ONCE(b, a);
1770 else
1771 WRITE_ONCE(b, 42);
1772
1773 The compiler can also invent loads. These are usually less
1774 damaging, but they can result in cache-line bouncing and thus in
1775 poor performance and scalability. Use READ_ONCE() to prevent
1776 invented loads.
1777
1778 (*) For aligned memory locations whose size allows them to be accessed
1779 with a single memory-reference instruction, prevents "load tearing"
1780 and "store tearing," in which a single large access is replaced by
1781 multiple smaller accesses. For example, given an architecture having
1782 16-bit store instructions with 7-bit immediate fields, the compiler
1783 might be tempted to use two 16-bit store-immediate instructions to
1784 implement the following 32-bit store:
1785
1786 p = 0x00010002;
1787
1788 Please note that GCC really does use this sort of optimization,
1789 which is not surprising given that it would likely take more
1790 than two instructions to build the constant and then store it.
1791 This optimization can therefore be a win in single-threaded code.
1792 In fact, a recent bug (since fixed) caused GCC to incorrectly use
1793 this optimization in a volatile store. In the absence of such bugs,
1794 use of WRITE_ONCE() prevents store tearing in the following example:
1795
1796 WRITE_ONCE(p, 0x00010002);
1797
1798 Use of packed structures can also result in load and store tearing,
1799 as in this example:
1800
1801 struct __attribute__((__packed__)) foo {
1802 short a;
1803 int b;
1804 short c;
1805 };
1806 struct foo foo1, foo2;
1807 ...
1808
1809 foo2.a = foo1.a;
1810 foo2.b = foo1.b;
1811 foo2.c = foo1.c;
1812
1813 Because there are no READ_ONCE() or WRITE_ONCE() wrappers and no
1814 volatile markings, the compiler would be well within its rights to
1815 implement these three assignment statements as a pair of 32-bit
1816 loads followed by a pair of 32-bit stores. This would result in
1817 load tearing on 'foo1.b' and store tearing on 'foo2.b'. READ_ONCE()
1818 and WRITE_ONCE() again prevent tearing in this example:
1819
1820 foo2.a = foo1.a;
1821 WRITE_ONCE(foo2.b, READ_ONCE(foo1.b));
1822 foo2.c = foo1.c;
1823
1824All that aside, it is never necessary to use READ_ONCE() and
1825WRITE_ONCE() on a variable that has been marked volatile. For example,
1826because 'jiffies' is marked volatile, it is never necessary to
1827say READ_ONCE(jiffies). The reason for this is that READ_ONCE() and
1828WRITE_ONCE() are implemented as volatile casts, which has no effect when
1829its argument is already marked volatile.
1830
1831Please note that these compiler barriers have no direct effect on the CPU,
1832which may then reorder things however it wishes.
1833
1834
1835CPU MEMORY BARRIERS
1836-------------------
1837
1838The Linux kernel has seven basic CPU memory barriers:
1839
1840 TYPE MANDATORY SMP CONDITIONAL
1841 ======================= =============== ===============
1842 GENERAL mb() smp_mb()
1843 WRITE wmb() smp_wmb()
1844 READ rmb() smp_rmb()
1845 ADDRESS DEPENDENCY READ_ONCE()
1846
1847
1848All memory barriers except the address-dependency barriers imply a compiler
1849barrier. Address dependencies do not impose any additional compiler ordering.
1850
1851Aside: In the case of address dependencies, the compiler would be expected
1852to issue the loads in the correct order (eg. `a[b]` would have to load
1853the value of b before loading a[b]), however there is no guarantee in
1854the C specification that the compiler may not speculate the value of b
1855(eg. is equal to 1) and load a[b] before b (eg. tmp = a[1]; if (b != 1)
1856tmp = a[b]; ). There is also the problem of a compiler reloading b after
1857having loaded a[b], thus having a newer copy of b than a[b]. A consensus
1858has not yet been reached about these problems, however the READ_ONCE()
1859macro is a good place to start looking.
1860
1861SMP memory barriers are reduced to compiler barriers on uniprocessor compiled
1862systems because it is assumed that a CPU will appear to be self-consistent,
1863and will order overlapping accesses correctly with respect to itself.
1864However, see the subsection on "Virtual Machine Guests" below.
1865
1866[!] Note that SMP memory barriers _must_ be used to control the ordering of
1867references to shared memory on SMP systems, though the use of locking instead
1868is sufficient.
1869
1870Mandatory barriers should not be used to control SMP effects, since mandatory
1871barriers impose unnecessary overhead on both SMP and UP systems. They may,
1872however, be used to control MMIO effects on accesses through relaxed memory I/O
1873windows. These barriers are required even on non-SMP systems as they affect
1874the order in which memory operations appear to a device by prohibiting both the
1875compiler and the CPU from reordering them.
1876
1877
1878There are some more advanced barrier functions:
1879
1880 (*) smp_store_mb(var, value)
1881
1882 This assigns the value to the variable and then inserts a full memory
1883 barrier after it. It isn't guaranteed to insert anything more than a
1884 compiler barrier in a UP compilation.
1885
1886
1887 (*) smp_mb__before_atomic();
1888 (*) smp_mb__after_atomic();
1889
1890 These are for use with atomic RMW functions that do not imply memory
1891 barriers, but where the code needs a memory barrier. Examples for atomic
1892 RMW functions that do not imply a memory barrier are e.g. add,
1893 subtract, (failed) conditional operations, _relaxed functions,
1894 but not atomic_read or atomic_set. A common example where a memory
1895 barrier may be required is when atomic ops are used for reference
1896 counting.
1897
1898 These are also used for atomic RMW bitop functions that do not imply a
1899 memory barrier (such as set_bit and clear_bit).
1900
1901 As an example, consider a piece of code that marks an object as being dead
1902 and then decrements the object's reference count:
1903
1904 obj->dead = 1;
1905 smp_mb__before_atomic();
1906 atomic_dec(&obj->ref_count);
1907
1908 This makes sure that the death mark on the object is perceived to be set
1909 *before* the reference counter is decremented.
1910
1911 See Documentation/atomic_{t,bitops}.txt for more information.
1912
1913
1914 (*) dma_wmb();
1915 (*) dma_rmb();
1916 (*) dma_mb();
1917
1918 These are for use with consistent memory to guarantee the ordering
1919 of writes or reads of shared memory accessible to both the CPU and a
1920 DMA capable device. See Documentation/core-api/dma-api.rst file for more
1921 information about consistent memory.
1922
1923 For example, consider a device driver that shares memory with a device
1924 and uses a descriptor status value to indicate if the descriptor belongs
1925 to the device or the CPU, and a doorbell to notify it when new
1926 descriptors are available:
1927
1928 if (desc->status != DEVICE_OWN) {
1929 /* do not read data until we own descriptor */
1930 dma_rmb();
1931
1932 /* read/modify data */
1933 read_data = desc->data;
1934 desc->data = write_data;
1935
1936 /* flush modifications before status update */
1937 dma_wmb();
1938
1939 /* assign ownership */
1940 desc->status = DEVICE_OWN;
1941
1942 /* Make descriptor status visible to the device followed by
1943 * notify device of new descriptor
1944 */
1945 writel(DESC_NOTIFY, doorbell);
1946 }
1947
1948 The dma_rmb() allows us to guarantee that the device has released ownership
1949 before we read the data from the descriptor, and the dma_wmb() allows
1950 us to guarantee the data is written to the descriptor before the device
1951 can see it now has ownership. The dma_mb() implies both a dma_rmb() and
1952 a dma_wmb().
1953
1954 Note that the dma_*() barriers do not provide any ordering guarantees for
1955 accesses to MMIO regions. See the later "KERNEL I/O BARRIER EFFECTS"
1956 subsection for more information about I/O accessors and MMIO ordering.
1957
1958 (*) pmem_wmb();
1959
1960 This is for use with persistent memory to ensure that stores for which
1961 modifications are written to persistent storage reached a platform
1962 durability domain.
1963
1964 For example, after a non-temporal write to pmem region, we use pmem_wmb()
1965 to ensure that stores have reached a platform durability domain. This ensures
1966 that stores have updated persistent storage before any data access or
1967 data transfer caused by subsequent instructions is initiated. This is
1968 in addition to the ordering done by wmb().
1969
1970 For load from persistent memory, existing read memory barriers are sufficient
1971 to ensure read ordering.
1972
1973 (*) io_stop_wc();
1974
1975 For memory accesses with write-combining attributes (e.g. those returned
1976 by ioremap_wc()), the CPU may wait for prior accesses to be merged with
1977 subsequent ones. io_stop_wc() can be used to prevent the merging of
1978 write-combining memory accesses before this macro with those after it when
1979 such wait has performance implications.
1980
1981===============================
1982IMPLICIT KERNEL MEMORY BARRIERS
1983===============================
1984
1985Some of the other functions in the linux kernel imply memory barriers, amongst
1986which are locking and scheduling functions.
1987
1988This specification is a _minimum_ guarantee; any particular architecture may
1989provide more substantial guarantees, but these may not be relied upon outside
1990of arch specific code.
1991
1992
1993LOCK ACQUISITION FUNCTIONS
1994--------------------------
1995
1996The Linux kernel has a number of locking constructs:
1997
1998 (*) spin locks
1999 (*) R/W spin locks
2000 (*) mutexes
2001 (*) semaphores
2002 (*) R/W semaphores
2003
2004In all cases there are variants on "ACQUIRE" operations and "RELEASE" operations
2005for each construct. These operations all imply certain barriers:
2006
2007 (1) ACQUIRE operation implication:
2008
2009 Memory operations issued after the ACQUIRE will be completed after the
2010 ACQUIRE operation has completed.
2011
2012 Memory operations issued before the ACQUIRE may be completed after
2013 the ACQUIRE operation has completed.
2014
2015 (2) RELEASE operation implication:
2016
2017 Memory operations issued before the RELEASE will be completed before the
2018 RELEASE operation has completed.
2019
2020 Memory operations issued after the RELEASE may be completed before the
2021 RELEASE operation has completed.
2022
2023 (3) ACQUIRE vs ACQUIRE implication:
2024
2025 All ACQUIRE operations issued before another ACQUIRE operation will be
2026 completed before that ACQUIRE operation.
2027
2028 (4) ACQUIRE vs RELEASE implication:
2029
2030 All ACQUIRE operations issued before a RELEASE operation will be
2031 completed before the RELEASE operation.
2032
2033 (5) Failed conditional ACQUIRE implication:
2034
2035 Certain locking variants of the ACQUIRE operation may fail, either due to
2036 being unable to get the lock immediately, or due to receiving an unblocked
2037 signal while asleep waiting for the lock to become available. Failed
2038 locks do not imply any sort of barrier.
2039
2040[!] Note: one of the consequences of lock ACQUIREs and RELEASEs being only
2041one-way barriers is that the effects of instructions outside of a critical
2042section may seep into the inside of the critical section.
2043
2044An ACQUIRE followed by a RELEASE may not be assumed to be full memory barrier
2045because it is possible for an access preceding the ACQUIRE to happen after the
2046ACQUIRE, and an access following the RELEASE to happen before the RELEASE, and
2047the two accesses can themselves then cross:
2048
2049 *A = a;
2050 ACQUIRE M
2051 RELEASE M
2052 *B = b;
2053
2054may occur as:
2055
2056 ACQUIRE M, STORE *B, STORE *A, RELEASE M
2057
2058When the ACQUIRE and RELEASE are a lock acquisition and release,
2059respectively, this same reordering can occur if the lock's ACQUIRE and
2060RELEASE are to the same lock variable, but only from the perspective of
2061another CPU not holding that lock. In short, a ACQUIRE followed by an
2062RELEASE may -not- be assumed to be a full memory barrier.
2063
2064Similarly, the reverse case of a RELEASE followed by an ACQUIRE does
2065not imply a full memory barrier. Therefore, the CPU's execution of the
2066critical sections corresponding to the RELEASE and the ACQUIRE can cross,
2067so that:
2068
2069 *A = a;
2070 RELEASE M
2071 ACQUIRE N
2072 *B = b;
2073
2074could occur as:
2075
2076 ACQUIRE N, STORE *B, STORE *A, RELEASE M
2077
2078It might appear that this reordering could introduce a deadlock.
2079However, this cannot happen because if such a deadlock threatened,
2080the RELEASE would simply complete, thereby avoiding the deadlock.
2081
2082 Why does this work?
2083
2084 One key point is that we are only talking about the CPU doing
2085 the reordering, not the compiler. If the compiler (or, for
2086 that matter, the developer) switched the operations, deadlock
2087 -could- occur.
2088
2089 But suppose the CPU reordered the operations. In this case,
2090 the unlock precedes the lock in the assembly code. The CPU
2091 simply elected to try executing the later lock operation first.
2092 If there is a deadlock, this lock operation will simply spin (or
2093 try to sleep, but more on that later). The CPU will eventually
2094 execute the unlock operation (which preceded the lock operation
2095 in the assembly code), which will unravel the potential deadlock,
2096 allowing the lock operation to succeed.
2097
2098 But what if the lock is a sleeplock? In that case, the code will
2099 try to enter the scheduler, where it will eventually encounter
2100 a memory barrier, which will force the earlier unlock operation
2101 to complete, again unraveling the deadlock. There might be
2102 a sleep-unlock race, but the locking primitive needs to resolve
2103 such races properly in any case.
2104
2105Locks and semaphores may not provide any guarantee of ordering on UP compiled
2106systems, and so cannot be counted on in such a situation to actually achieve
2107anything at all - especially with respect to I/O accesses - unless combined
2108with interrupt disabling operations.
2109
2110See also the section on "Inter-CPU acquiring barrier effects".
2111
2112
2113As an example, consider the following:
2114
2115 *A = a;
2116 *B = b;
2117 ACQUIRE
2118 *C = c;
2119 *D = d;
2120 RELEASE
2121 *E = e;
2122 *F = f;
2123
2124The following sequence of events is acceptable:
2125
2126 ACQUIRE, {*F,*A}, *E, {*C,*D}, *B, RELEASE
2127
2128 [+] Note that {*F,*A} indicates a combined access.
2129
2130But none of the following are:
2131
2132 {*F,*A}, *B, ACQUIRE, *C, *D, RELEASE, *E
2133 *A, *B, *C, ACQUIRE, *D, RELEASE, *E, *F
2134 *A, *B, ACQUIRE, *C, RELEASE, *D, *E, *F
2135 *B, ACQUIRE, *C, *D, RELEASE, {*F,*A}, *E
2136
2137
2138
2139INTERRUPT DISABLING FUNCTIONS
2140-----------------------------
2141
2142Functions that disable interrupts (ACQUIRE equivalent) and enable interrupts
2143(RELEASE equivalent) will act as compiler barriers only. So if memory or I/O
2144barriers are required in such a situation, they must be provided from some
2145other means.
2146
2147
2148SLEEP AND WAKE-UP FUNCTIONS
2149---------------------------
2150
2151Sleeping and waking on an event flagged in global data can be viewed as an
2152interaction between two pieces of data: the task state of the task waiting for
2153the event and the global data used to indicate the event. To make sure that
2154these appear to happen in the right order, the primitives to begin the process
2155of going to sleep, and the primitives to initiate a wake up imply certain
2156barriers.
2157
2158Firstly, the sleeper normally follows something like this sequence of events:
2159
2160 for (;;) {
2161 set_current_state(TASK_UNINTERRUPTIBLE);
2162 if (event_indicated)
2163 break;
2164 schedule();
2165 }
2166
2167A general memory barrier is interpolated automatically by set_current_state()
2168after it has altered the task state:
2169
2170 CPU 1
2171 ===============================
2172 set_current_state();
2173 smp_store_mb();
2174 STORE current->state
2175 <general barrier>
2176 LOAD event_indicated
2177
2178set_current_state() may be wrapped by:
2179
2180 prepare_to_wait();
2181 prepare_to_wait_exclusive();
2182
2183which therefore also imply a general memory barrier after setting the state.
2184The whole sequence above is available in various canned forms, all of which
2185interpolate the memory barrier in the right place:
2186
2187 wait_event();
2188 wait_event_interruptible();
2189 wait_event_interruptible_exclusive();
2190 wait_event_interruptible_timeout();
2191 wait_event_killable();
2192 wait_event_timeout();
2193 wait_on_bit();
2194 wait_on_bit_lock();
2195
2196
2197Secondly, code that performs a wake up normally follows something like this:
2198
2199 event_indicated = 1;
2200 wake_up(&event_wait_queue);
2201
2202or:
2203
2204 event_indicated = 1;
2205 wake_up_process(event_daemon);
2206
2207A general memory barrier is executed by wake_up() if it wakes something up.
2208If it doesn't wake anything up then a memory barrier may or may not be
2209executed; you must not rely on it. The barrier occurs before the task state
2210is accessed, in particular, it sits between the STORE to indicate the event
2211and the STORE to set TASK_RUNNING:
2212
2213 CPU 1 (Sleeper) CPU 2 (Waker)
2214 =============================== ===============================
2215 set_current_state(); STORE event_indicated
2216 smp_store_mb(); wake_up();
2217 STORE current->state ...
2218 <general barrier> <general barrier>
2219 LOAD event_indicated if ((LOAD task->state) & TASK_NORMAL)
2220 STORE task->state
2221
2222where "task" is the thread being woken up and it equals CPU 1's "current".
2223
2224To repeat, a general memory barrier is guaranteed to be executed by wake_up()
2225if something is actually awakened, but otherwise there is no such guarantee.
2226To see this, consider the following sequence of events, where X and Y are both
2227initially zero:
2228
2229 CPU 1 CPU 2
2230 =============================== ===============================
2231 X = 1; Y = 1;
2232 smp_mb(); wake_up();
2233 LOAD Y LOAD X
2234
2235If a wakeup does occur, one (at least) of the two loads must see 1. If, on
2236the other hand, a wakeup does not occur, both loads might see 0.
2237
2238wake_up_process() always executes a general memory barrier. The barrier again
2239occurs before the task state is accessed. In particular, if the wake_up() in
2240the previous snippet were replaced by a call to wake_up_process() then one of
2241the two loads would be guaranteed to see 1.
2242
2243The available waker functions include:
2244
2245 complete();
2246 wake_up();
2247 wake_up_all();
2248 wake_up_bit();
2249 wake_up_interruptible();
2250 wake_up_interruptible_all();
2251 wake_up_interruptible_nr();
2252 wake_up_interruptible_poll();
2253 wake_up_interruptible_sync();
2254 wake_up_interruptible_sync_poll();
2255 wake_up_locked();
2256 wake_up_locked_poll();
2257 wake_up_nr();
2258 wake_up_poll();
2259 wake_up_process();
2260
2261In terms of memory ordering, these functions all provide the same guarantees of
2262a wake_up() (or stronger).
2263
2264[!] Note that the memory barriers implied by the sleeper and the waker do _not_
2265order multiple stores before the wake-up with respect to loads of those stored
2266values after the sleeper has called set_current_state(). For instance, if the
2267sleeper does:
2268
2269 set_current_state(TASK_INTERRUPTIBLE);
2270 if (event_indicated)
2271 break;
2272 __set_current_state(TASK_RUNNING);
2273 do_something(my_data);
2274
2275and the waker does:
2276
2277 my_data = value;
2278 event_indicated = 1;
2279 wake_up(&event_wait_queue);
2280
2281there's no guarantee that the change to event_indicated will be perceived by
2282the sleeper as coming after the change to my_data. In such a circumstance, the
2283code on both sides must interpolate its own memory barriers between the
2284separate data accesses. Thus the above sleeper ought to do:
2285
2286 set_current_state(TASK_INTERRUPTIBLE);
2287 if (event_indicated) {
2288 smp_rmb();
2289 do_something(my_data);
2290 }
2291
2292and the waker should do:
2293
2294 my_data = value;
2295 smp_wmb();
2296 event_indicated = 1;
2297 wake_up(&event_wait_queue);
2298
2299
2300MISCELLANEOUS FUNCTIONS
2301-----------------------
2302
2303Other functions that imply barriers:
2304
2305 (*) schedule() and similar imply full memory barriers.
2306
2307
2308===================================
2309INTER-CPU ACQUIRING BARRIER EFFECTS
2310===================================
2311
2312On SMP systems locking primitives give a more substantial form of barrier: one
2313that does affect memory access ordering on other CPUs, within the context of
2314conflict on any particular lock.
2315
2316
2317ACQUIRES VS MEMORY ACCESSES
2318---------------------------
2319
2320Consider the following: the system has a pair of spinlocks (M) and (Q), and
2321three CPUs; then should the following sequence of events occur:
2322
2323 CPU 1 CPU 2
2324 =============================== ===============================
2325 WRITE_ONCE(*A, a); WRITE_ONCE(*E, e);
2326 ACQUIRE M ACQUIRE Q
2327 WRITE_ONCE(*B, b); WRITE_ONCE(*F, f);
2328 WRITE_ONCE(*C, c); WRITE_ONCE(*G, g);
2329 RELEASE M RELEASE Q
2330 WRITE_ONCE(*D, d); WRITE_ONCE(*H, h);
2331
2332Then there is no guarantee as to what order CPU 3 will see the accesses to *A
2333through *H occur in, other than the constraints imposed by the separate locks
2334on the separate CPUs. It might, for example, see:
2335
2336 *E, ACQUIRE M, ACQUIRE Q, *G, *C, *F, *A, *B, RELEASE Q, *D, *H, RELEASE M
2337
2338But it won't see any of:
2339
2340 *B, *C or *D preceding ACQUIRE M
2341 *A, *B or *C following RELEASE M
2342 *F, *G or *H preceding ACQUIRE Q
2343 *E, *F or *G following RELEASE Q
2344
2345
2346=================================
2347WHERE ARE MEMORY BARRIERS NEEDED?
2348=================================
2349
2350Under normal operation, memory operation reordering is generally not going to
2351be a problem as a single-threaded linear piece of code will still appear to
2352work correctly, even if it's in an SMP kernel. There are, however, four
2353circumstances in which reordering definitely _could_ be a problem:
2354
2355 (*) Interprocessor interaction.
2356
2357 (*) Atomic operations.
2358
2359 (*) Accessing devices.
2360
2361 (*) Interrupts.
2362
2363
2364INTERPROCESSOR INTERACTION
2365--------------------------
2366
2367When there's a system with more than one processor, more than one CPU in the
2368system may be working on the same data set at the same time. This can cause
2369synchronisation problems, and the usual way of dealing with them is to use
2370locks. Locks, however, are quite expensive, and so it may be preferable to
2371operate without the use of a lock if at all possible. In such a case
2372operations that affect both CPUs may have to be carefully ordered to prevent
2373a malfunction.
2374
2375Consider, for example, the R/W semaphore slow path. Here a waiting process is
2376queued on the semaphore, by virtue of it having a piece of its stack linked to
2377the semaphore's list of waiting processes:
2378
2379 struct rw_semaphore {
2380 ...
2381 spinlock_t lock;
2382 struct list_head waiters;
2383 };
2384
2385 struct rwsem_waiter {
2386 struct list_head list;
2387 struct task_struct *task;
2388 };
2389
2390To wake up a particular waiter, the up_read() or up_write() functions have to:
2391
2392 (1) read the next pointer from this waiter's record to know as to where the
2393 next waiter record is;
2394
2395 (2) read the pointer to the waiter's task structure;
2396
2397 (3) clear the task pointer to tell the waiter it has been given the semaphore;
2398
2399 (4) call wake_up_process() on the task; and
2400
2401 (5) release the reference held on the waiter's task struct.
2402
2403In other words, it has to perform this sequence of events:
2404
2405 LOAD waiter->list.next;
2406 LOAD waiter->task;
2407 STORE waiter->task;
2408 CALL wakeup
2409 RELEASE task
2410
2411and if any of these steps occur out of order, then the whole thing may
2412malfunction.
2413
2414Once it has queued itself and dropped the semaphore lock, the waiter does not
2415get the lock again; it instead just waits for its task pointer to be cleared
2416before proceeding. Since the record is on the waiter's stack, this means that
2417if the task pointer is cleared _before_ the next pointer in the list is read,
2418another CPU might start processing the waiter and might clobber the waiter's
2419stack before the up*() function has a chance to read the next pointer.
2420
2421Consider then what might happen to the above sequence of events:
2422
2423 CPU 1 CPU 2
2424 =============================== ===============================
2425 down_xxx()
2426 Queue waiter
2427 Sleep
2428 up_yyy()
2429 LOAD waiter->task;
2430 STORE waiter->task;
2431 Woken up by other event
2432 <preempt>
2433 Resume processing
2434 down_xxx() returns
2435 call foo()
2436 foo() clobbers *waiter
2437 </preempt>
2438 LOAD waiter->list.next;
2439 --- OOPS ---
2440
2441This could be dealt with using the semaphore lock, but then the down_xxx()
2442function has to needlessly get the spinlock again after being woken up.
2443
2444The way to deal with this is to insert a general SMP memory barrier:
2445
2446 LOAD waiter->list.next;
2447 LOAD waiter->task;
2448 smp_mb();
2449 STORE waiter->task;
2450 CALL wakeup
2451 RELEASE task
2452
2453In this case, the barrier makes a guarantee that all memory accesses before the
2454barrier will appear to happen before all the memory accesses after the barrier
2455with respect to the other CPUs on the system. It does _not_ guarantee that all
2456the memory accesses before the barrier will be complete by the time the barrier
2457instruction itself is complete.
2458
2459On a UP system - where this wouldn't be a problem - the smp_mb() is just a
2460compiler barrier, thus making sure the compiler emits the instructions in the
2461right order without actually intervening in the CPU. Since there's only one
2462CPU, that CPU's dependency ordering logic will take care of everything else.
2463
2464
2465ATOMIC OPERATIONS
2466-----------------
2467
2468While they are technically interprocessor interaction considerations, atomic
2469operations are noted specially as some of them imply full memory barriers and
2470some don't, but they're very heavily relied on as a group throughout the
2471kernel.
2472
2473See Documentation/atomic_t.txt for more information.
2474
2475
2476ACCESSING DEVICES
2477-----------------
2478
2479Many devices can be memory mapped, and so appear to the CPU as if they're just
2480a set of memory locations. To control such a device, the driver usually has to
2481make the right memory accesses in exactly the right order.
2482
2483However, having a clever CPU or a clever compiler creates a potential problem
2484in that the carefully sequenced accesses in the driver code won't reach the
2485device in the requisite order if the CPU or the compiler thinks it is more
2486efficient to reorder, combine or merge accesses - something that would cause
2487the device to malfunction.
2488
2489Inside of the Linux kernel, I/O should be done through the appropriate accessor
2490routines - such as inb() or writel() - which know how to make such accesses
2491appropriately sequential. While this, for the most part, renders the explicit
2492use of memory barriers unnecessary, if the accessor functions are used to refer
2493to an I/O memory window with relaxed memory access properties, then _mandatory_
2494memory barriers are required to enforce ordering.
2495
2496See Documentation/driver-api/device-io.rst for more information.
2497
2498
2499INTERRUPTS
2500----------
2501
2502A driver may be interrupted by its own interrupt service routine, and thus the
2503two parts of the driver may interfere with each other's attempts to control or
2504access the device.
2505
2506This may be alleviated - at least in part - by disabling local interrupts (a
2507form of locking), such that the critical operations are all contained within
2508the interrupt-disabled section in the driver. While the driver's interrupt
2509routine is executing, the driver's core may not run on the same CPU, and its
2510interrupt is not permitted to happen again until the current interrupt has been
2511handled, thus the interrupt handler does not need to lock against that.
2512
2513However, consider a driver that was talking to an ethernet card that sports an
2514address register and a data register. If that driver's core talks to the card
2515under interrupt-disablement and then the driver's interrupt handler is invoked:
2516
2517 LOCAL IRQ DISABLE
2518 writew(ADDR, 3);
2519 writew(DATA, y);
2520 LOCAL IRQ ENABLE
2521 <interrupt>
2522 writew(ADDR, 4);
2523 q = readw(DATA);
2524 </interrupt>
2525
2526The store to the data register might happen after the second store to the
2527address register if ordering rules are sufficiently relaxed:
2528
2529 STORE *ADDR = 3, STORE *ADDR = 4, STORE *DATA = y, q = LOAD *DATA
2530
2531
2532If ordering rules are relaxed, it must be assumed that accesses done inside an
2533interrupt disabled section may leak outside of it and may interleave with
2534accesses performed in an interrupt - and vice versa - unless implicit or
2535explicit barriers are used.
2536
2537Normally this won't be a problem because the I/O accesses done inside such
2538sections will include synchronous load operations on strictly ordered I/O
2539registers that form implicit I/O barriers.
2540
2541
2542A similar situation may occur between an interrupt routine and two routines
2543running on separate CPUs that communicate with each other. If such a case is
2544likely, then interrupt-disabling locks should be used to guarantee ordering.
2545
2546
2547==========================
2548KERNEL I/O BARRIER EFFECTS
2549==========================
2550
2551Interfacing with peripherals via I/O accesses is deeply architecture and device
2552specific. Therefore, drivers which are inherently non-portable may rely on
2553specific behaviours of their target systems in order to achieve synchronization
2554in the most lightweight manner possible. For drivers intending to be portable
2555between multiple architectures and bus implementations, the kernel offers a
2556series of accessor functions that provide various degrees of ordering
2557guarantees:
2558
2559 (*) readX(), writeX():
2560
2561 The readX() and writeX() MMIO accessors take a pointer to the
2562 peripheral being accessed as an __iomem * parameter. For pointers
2563 mapped with the default I/O attributes (e.g. those returned by
2564 ioremap()), the ordering guarantees are as follows:
2565
2566 1. All readX() and writeX() accesses to the same peripheral are ordered
2567 with respect to each other. This ensures that MMIO register accesses
2568 by the same CPU thread to a particular device will arrive in program
2569 order.
2570
2571 2. A writeX() issued by a CPU thread holding a spinlock is ordered
2572 before a writeX() to the same peripheral from another CPU thread
2573 issued after a later acquisition of the same spinlock. This ensures
2574 that MMIO register writes to a particular device issued while holding
2575 a spinlock will arrive in an order consistent with acquisitions of
2576 the lock.
2577
2578 3. A writeX() by a CPU thread to the peripheral will first wait for the
2579 completion of all prior writes to memory either issued by, or
2580 propagated to, the same thread. This ensures that writes by the CPU
2581 to an outbound DMA buffer allocated by dma_alloc_coherent() will be
2582 visible to a DMA engine when the CPU writes to its MMIO control
2583 register to trigger the transfer.
2584
2585 4. A readX() by a CPU thread from the peripheral will complete before
2586 any subsequent reads from memory by the same thread can begin. This
2587 ensures that reads by the CPU from an incoming DMA buffer allocated
2588 by dma_alloc_coherent() will not see stale data after reading from
2589 the DMA engine's MMIO status register to establish that the DMA
2590 transfer has completed.
2591
2592 5. A readX() by a CPU thread from the peripheral will complete before
2593 any subsequent delay() loop can begin execution on the same thread.
2594 This ensures that two MMIO register writes by the CPU to a peripheral
2595 will arrive at least 1us apart if the first write is immediately read
2596 back with readX() and udelay(1) is called prior to the second
2597 writeX():
2598
2599 writel(42, DEVICE_REGISTER_0); // Arrives at the device...
2600 readl(DEVICE_REGISTER_0);
2601 udelay(1);
2602 writel(42, DEVICE_REGISTER_1); // ...at least 1us before this.
2603
2604 The ordering properties of __iomem pointers obtained with non-default
2605 attributes (e.g. those returned by ioremap_wc()) are specific to the
2606 underlying architecture and therefore the guarantees listed above cannot
2607 generally be relied upon for accesses to these types of mappings.
2608
2609 (*) readX_relaxed(), writeX_relaxed():
2610
2611 These are similar to readX() and writeX(), but provide weaker memory
2612 ordering guarantees. Specifically, they do not guarantee ordering with
2613 respect to locking, normal memory accesses or delay() loops (i.e.
2614 bullets 2-5 above) but they are still guaranteed to be ordered with
2615 respect to other accesses from the same CPU thread to the same
2616 peripheral when operating on __iomem pointers mapped with the default
2617 I/O attributes.
2618
2619 (*) readsX(), writesX():
2620
2621 The readsX() and writesX() MMIO accessors are designed for accessing
2622 register-based, memory-mapped FIFOs residing on peripherals that are not
2623 capable of performing DMA. Consequently, they provide only the ordering
2624 guarantees of readX_relaxed() and writeX_relaxed(), as documented above.
2625
2626 (*) inX(), outX():
2627
2628 The inX() and outX() accessors are intended to access legacy port-mapped
2629 I/O peripherals, which may require special instructions on some
2630 architectures (notably x86). The port number of the peripheral being
2631 accessed is passed as an argument.
2632
2633 Since many CPU architectures ultimately access these peripherals via an
2634 internal virtual memory mapping, the portable ordering guarantees
2635 provided by inX() and outX() are the same as those provided by readX()
2636 and writeX() respectively when accessing a mapping with the default I/O
2637 attributes.
2638
2639 Device drivers may expect outX() to emit a non-posted write transaction
2640 that waits for a completion response from the I/O peripheral before
2641 returning. This is not guaranteed by all architectures and is therefore
2642 not part of the portable ordering semantics.
2643
2644 (*) insX(), outsX():
2645
2646 As above, the insX() and outsX() accessors provide the same ordering
2647 guarantees as readsX() and writesX() respectively when accessing a
2648 mapping with the default I/O attributes.
2649
2650 (*) ioreadX(), iowriteX():
2651
2652 These will perform appropriately for the type of access they're actually
2653 doing, be it inX()/outX() or readX()/writeX().
2654
2655With the exception of the string accessors (insX(), outsX(), readsX() and
2656writesX()), all of the above assume that the underlying peripheral is
2657little-endian and will therefore perform byte-swapping operations on big-endian
2658architectures.
2659
2660
2661========================================
2662ASSUMED MINIMUM EXECUTION ORDERING MODEL
2663========================================
2664
2665It has to be assumed that the conceptual CPU is weakly-ordered but that it will
2666maintain the appearance of program causality with respect to itself. Some CPUs
2667(such as i386 or x86_64) are more constrained than others (such as powerpc or
2668frv), and so the most relaxed case (namely DEC Alpha) must be assumed outside
2669of arch-specific code.
2670
2671This means that it must be considered that the CPU will execute its instruction
2672stream in any order it feels like - or even in parallel - provided that if an
2673instruction in the stream depends on an earlier instruction, then that
2674earlier instruction must be sufficiently complete[*] before the later
2675instruction may proceed; in other words: provided that the appearance of
2676causality is maintained.
2677
2678 [*] Some instructions have more than one effect - such as changing the
2679 condition codes, changing registers or changing memory - and different
2680 instructions may depend on different effects.
2681
2682A CPU may also discard any instruction sequence that winds up having no
2683ultimate effect. For example, if two adjacent instructions both load an
2684immediate value into the same register, the first may be discarded.
2685
2686
2687Similarly, it has to be assumed that compiler might reorder the instruction
2688stream in any way it sees fit, again provided the appearance of causality is
2689maintained.
2690
2691
2692============================
2693THE EFFECTS OF THE CPU CACHE
2694============================
2695
2696The way cached memory operations are perceived across the system is affected to
2697a certain extent by the caches that lie between CPUs and memory, and by the
2698memory coherence system that maintains the consistency of state in the system.
2699
2700As far as the way a CPU interacts with another part of the system through the
2701caches goes, the memory system has to include the CPU's caches, and memory
2702barriers for the most part act at the interface between the CPU and its cache
2703(memory barriers logically act on the dotted line in the following diagram):
2704
2705 <--- CPU ---> : <----------- Memory ----------->
2706 :
2707 +--------+ +--------+ : +--------+ +-----------+
2708 | | | | : | | | | +--------+
2709 | CPU | | Memory | : | CPU | | | | |
2710 | Core |--->| Access |----->| Cache |<-->| | | |
2711 | | | Queue | : | | | |--->| Memory |
2712 | | | | : | | | | | |
2713 +--------+ +--------+ : +--------+ | | | |
2714 : | Cache | +--------+
2715 : | Coherency |
2716 : | Mechanism | +--------+
2717 +--------+ +--------+ : +--------+ | | | |
2718 | | | | : | | | | | |
2719 | CPU | | Memory | : | CPU | | |--->| Device |
2720 | Core |--->| Access |----->| Cache |<-->| | | |
2721 | | | Queue | : | | | | | |
2722 | | | | : | | | | +--------+
2723 +--------+ +--------+ : +--------+ +-----------+
2724 :
2725 :
2726
2727Although any particular load or store may not actually appear outside of the
2728CPU that issued it since it may have been satisfied within the CPU's own cache,
2729it will still appear as if the full memory access had taken place as far as the
2730other CPUs are concerned since the cache coherency mechanisms will migrate the
2731cacheline over to the accessing CPU and propagate the effects upon conflict.
2732
2733The CPU core may execute instructions in any order it deems fit, provided the
2734expected program causality appears to be maintained. Some of the instructions
2735generate load and store operations which then go into the queue of memory
2736accesses to be performed. The core may place these in the queue in any order
2737it wishes, and continue execution until it is forced to wait for an instruction
2738to complete.
2739
2740What memory barriers are concerned with is controlling the order in which
2741accesses cross from the CPU side of things to the memory side of things, and
2742the order in which the effects are perceived to happen by the other observers
2743in the system.
2744
2745[!] Memory barriers are _not_ needed within a given CPU, as CPUs always see
2746their own loads and stores as if they had happened in program order.
2747
2748[!] MMIO or other device accesses may bypass the cache system. This depends on
2749the properties of the memory window through which devices are accessed and/or
2750the use of any special device communication instructions the CPU may have.
2751
2752
2753CACHE COHERENCY VS DMA
2754----------------------
2755
2756Not all systems maintain cache coherency with respect to devices doing DMA. In
2757such cases, a device attempting DMA may obtain stale data from RAM because
2758dirty cache lines may be resident in the caches of various CPUs, and may not
2759have been written back to RAM yet. To deal with this, the appropriate part of
2760the kernel must flush the overlapping bits of cache on each CPU (and maybe
2761invalidate them as well).
2762
2763In addition, the data DMA'd to RAM by a device may be overwritten by dirty
2764cache lines being written back to RAM from a CPU's cache after the device has
2765installed its own data, or cache lines present in the CPU's cache may simply
2766obscure the fact that RAM has been updated, until at such time as the cacheline
2767is discarded from the CPU's cache and reloaded. To deal with this, the
2768appropriate part of the kernel must invalidate the overlapping bits of the
2769cache on each CPU.
2770
2771See Documentation/core-api/cachetlb.rst for more information on cache
2772management.
2773
2774
2775CACHE COHERENCY VS MMIO
2776-----------------------
2777
2778Memory mapped I/O usually takes place through memory locations that are part of
2779a window in the CPU's memory space that has different properties assigned than
2780the usual RAM directed window.
2781
2782Amongst these properties is usually the fact that such accesses bypass the
2783caching entirely and go directly to the device buses. This means MMIO accesses
2784may, in effect, overtake accesses to cached memory that were emitted earlier.
2785A memory barrier isn't sufficient in such a case, but rather the cache must be
2786flushed between the cached memory write and the MMIO access if the two are in
2787any way dependent.
2788
2789
2790=========================
2791THE THINGS CPUS GET UP TO
2792=========================
2793
2794A programmer might take it for granted that the CPU will perform memory
2795operations in exactly the order specified, so that if the CPU is, for example,
2796given the following piece of code to execute:
2797
2798 a = READ_ONCE(*A);
2799 WRITE_ONCE(*B, b);
2800 c = READ_ONCE(*C);
2801 d = READ_ONCE(*D);
2802 WRITE_ONCE(*E, e);
2803
2804they would then expect that the CPU will complete the memory operation for each
2805instruction before moving on to the next one, leading to a definite sequence of
2806operations as seen by external observers in the system:
2807
2808 LOAD *A, STORE *B, LOAD *C, LOAD *D, STORE *E.
2809
2810
2811Reality is, of course, much messier. With many CPUs and compilers, the above
2812assumption doesn't hold because:
2813
2814 (*) loads are more likely to need to be completed immediately to permit
2815 execution progress, whereas stores can often be deferred without a
2816 problem;
2817
2818 (*) loads may be done speculatively, and the result discarded should it prove
2819 to have been unnecessary;
2820
2821 (*) loads may be done speculatively, leading to the result having been fetched
2822 at the wrong time in the expected sequence of events;
2823
2824 (*) the order of the memory accesses may be rearranged to promote better use
2825 of the CPU buses and caches;
2826
2827 (*) loads and stores may be combined to improve performance when talking to
2828 memory or I/O hardware that can do batched accesses of adjacent locations,
2829 thus cutting down on transaction setup costs (memory and PCI devices may
2830 both be able to do this); and
2831
2832 (*) the CPU's data cache may affect the ordering, and while cache-coherency
2833 mechanisms may alleviate this - once the store has actually hit the cache
2834 - there's no guarantee that the coherency management will be propagated in
2835 order to other CPUs.
2836
2837So what another CPU, say, might actually observe from the above piece of code
2838is:
2839
2840 LOAD *A, ..., LOAD {*C,*D}, STORE *E, STORE *B
2841
2842 (Where "LOAD {*C,*D}" is a combined load)
2843
2844
2845However, it is guaranteed that a CPU will be self-consistent: it will see its
2846_own_ accesses appear to be correctly ordered, without the need for a memory
2847barrier. For instance with the following code:
2848
2849 U = READ_ONCE(*A);
2850 WRITE_ONCE(*A, V);
2851 WRITE_ONCE(*A, W);
2852 X = READ_ONCE(*A);
2853 WRITE_ONCE(*A, Y);
2854 Z = READ_ONCE(*A);
2855
2856and assuming no intervention by an external influence, it can be assumed that
2857the final result will appear to be:
2858
2859 U == the original value of *A
2860 X == W
2861 Z == Y
2862 *A == Y
2863
2864The code above may cause the CPU to generate the full sequence of memory
2865accesses:
2866
2867 U=LOAD *A, STORE *A=V, STORE *A=W, X=LOAD *A, STORE *A=Y, Z=LOAD *A
2868
2869in that order, but, without intervention, the sequence may have almost any
2870combination of elements combined or discarded, provided the program's view
2871of the world remains consistent. Note that READ_ONCE() and WRITE_ONCE()
2872are -not- optional in the above example, as there are architectures
2873where a given CPU might reorder successive loads to the same location.
2874On such architectures, READ_ONCE() and WRITE_ONCE() do whatever is
2875necessary to prevent this, for example, on Itanium the volatile casts
2876used by READ_ONCE() and WRITE_ONCE() cause GCC to emit the special ld.acq
2877and st.rel instructions (respectively) that prevent such reordering.
2878
2879The compiler may also combine, discard or defer elements of the sequence before
2880the CPU even sees them.
2881
2882For instance:
2883
2884 *A = V;
2885 *A = W;
2886
2887may be reduced to:
2888
2889 *A = W;
2890
2891since, without either a write barrier or an WRITE_ONCE(), it can be
2892assumed that the effect of the storage of V to *A is lost. Similarly:
2893
2894 *A = Y;
2895 Z = *A;
2896
2897may, without a memory barrier or an READ_ONCE() and WRITE_ONCE(), be
2898reduced to:
2899
2900 *A = Y;
2901 Z = Y;
2902
2903and the LOAD operation never appear outside of the CPU.
2904
2905
2906AND THEN THERE'S THE ALPHA
2907--------------------------
2908
2909The DEC Alpha CPU is one of the most relaxed CPUs there is. Not only that,
2910some versions of the Alpha CPU have a split data cache, permitting them to have
2911two semantically-related cache lines updated at separate times. This is where
2912the address-dependency barrier really becomes necessary as this synchronises
2913both caches with the memory coherence system, thus making it seem like pointer
2914changes vs new data occur in the right order.
2915
2916The Alpha defines the Linux kernel's memory model, although as of v4.15
2917the Linux kernel's addition of smp_mb() to READ_ONCE() on Alpha greatly
2918reduced its impact on the memory model.
2919
2920
2921VIRTUAL MACHINE GUESTS
2922----------------------
2923
2924Guests running within virtual machines might be affected by SMP effects even if
2925the guest itself is compiled without SMP support. This is an artifact of
2926interfacing with an SMP host while running an UP kernel. Using mandatory
2927barriers for this use-case would be possible but is often suboptimal.
2928
2929To handle this case optimally, low-level virt_mb() etc macros are available.
2930These have the same effect as smp_mb() etc when SMP is enabled, but generate
2931identical code for SMP and non-SMP systems. For example, virtual machine guests
2932should use virt_mb() rather than smp_mb() when synchronizing against a
2933(possibly SMP) host.
2934
2935These are equivalent to smp_mb() etc counterparts in all other respects,
2936in particular, they do not control MMIO effects: to control
2937MMIO effects, use mandatory barriers.
2938
2939
2940============
2941EXAMPLE USES
2942============
2943
2944CIRCULAR BUFFERS
2945----------------
2946
2947Memory barriers can be used to implement circular buffering without the need
2948of a lock to serialise the producer with the consumer. See:
2949
2950 Documentation/core-api/circular-buffers.rst
2951
2952for details.
2953
2954
2955==========
2956REFERENCES
2957==========
2958
2959Alpha AXP Architecture Reference Manual, Second Edition (Sites & Witek,
2960Digital Press)
2961 Chapter 5.2: Physical Address Space Characteristics
2962 Chapter 5.4: Caches and Write Buffers
2963 Chapter 5.5: Data Sharing
2964 Chapter 5.6: Read/Write Ordering
2965
2966AMD64 Architecture Programmer's Manual Volume 2: System Programming
2967 Chapter 7.1: Memory-Access Ordering
2968 Chapter 7.4: Buffering and Combining Memory Writes
2969
2970ARM Architecture Reference Manual (ARMv8, for ARMv8-A architecture profile)
2971 Chapter B2: The AArch64 Application Level Memory Model
2972
2973IA-32 Intel Architecture Software Developer's Manual, Volume 3:
2974System Programming Guide
2975 Chapter 7.1: Locked Atomic Operations
2976 Chapter 7.2: Memory Ordering
2977 Chapter 7.4: Serializing Instructions
2978
2979The SPARC Architecture Manual, Version 9
2980 Chapter 8: Memory Models
2981 Appendix D: Formal Specification of the Memory Models
2982 Appendix J: Programming with the Memory Models
2983
2984Storage in the PowerPC (Stone and Fitzgerald)
2985
2986UltraSPARC Programmer Reference Manual
2987 Chapter 5: Memory Accesses and Cacheability
2988 Chapter 15: Sparc-V9 Memory Models
2989
2990UltraSPARC III Cu User's Manual
2991 Chapter 9: Memory Models
2992
2993UltraSPARC IIIi Processor User's Manual
2994 Chapter 8: Memory Models
2995
2996UltraSPARC Architecture 2005
2997 Chapter 9: Memory
2998 Appendix D: Formal Specifications of the Memory Models
2999
3000UltraSPARC T1 Supplement to the UltraSPARC Architecture 2005
3001 Chapter 8: Memory Models
3002 Appendix F: Caches and Cache Coherency
3003
3004Solaris Internals, Core Kernel Architecture, p63-68:
3005 Chapter 3.3: Hardware Considerations for Locks and
3006 Synchronization
3007
3008Unix Systems for Modern Architectures, Symmetric Multiprocessing and Caching
3009for Kernel Programmers:
3010 Chapter 13: Other Memory Models
3011
3012Intel Itanium Architecture Software Developer's Manual: Volume 1:
3013 Section 2.6: Speculation
3014 Section 4.4: Memory Access
1 ============================
2 LINUX KERNEL MEMORY BARRIERS
3 ============================
4
5By: David Howells <dhowells@redhat.com>
6 Paul E. McKenney <paulmck@linux.vnet.ibm.com>
7
8Contents:
9
10 (*) Abstract memory access model.
11
12 - Device operations.
13 - Guarantees.
14
15 (*) What are memory barriers?
16
17 - Varieties of memory barrier.
18 - What may not be assumed about memory barriers?
19 - Data dependency barriers.
20 - Control dependencies.
21 - SMP barrier pairing.
22 - Examples of memory barrier sequences.
23 - Read memory barriers vs load speculation.
24 - Transitivity
25
26 (*) Explicit kernel barriers.
27
28 - Compiler barrier.
29 - CPU memory barriers.
30 - MMIO write barrier.
31
32 (*) Implicit kernel memory barriers.
33
34 - Locking functions.
35 - Interrupt disabling functions.
36 - Sleep and wake-up functions.
37 - Miscellaneous functions.
38
39 (*) Inter-CPU locking barrier effects.
40
41 - Locks vs memory accesses.
42 - Locks vs I/O accesses.
43
44 (*) Where are memory barriers needed?
45
46 - Interprocessor interaction.
47 - Atomic operations.
48 - Accessing devices.
49 - Interrupts.
50
51 (*) Kernel I/O barrier effects.
52
53 (*) Assumed minimum execution ordering model.
54
55 (*) The effects of the cpu cache.
56
57 - Cache coherency.
58 - Cache coherency vs DMA.
59 - Cache coherency vs MMIO.
60
61 (*) The things CPUs get up to.
62
63 - And then there's the Alpha.
64
65 (*) Example uses.
66
67 - Circular buffers.
68
69 (*) References.
70
71
72============================
73ABSTRACT MEMORY ACCESS MODEL
74============================
75
76Consider the following abstract model of the system:
77
78 : :
79 : :
80 : :
81 +-------+ : +--------+ : +-------+
82 | | : | | : | |
83 | | : | | : | |
84 | CPU 1 |<----->| Memory |<----->| CPU 2 |
85 | | : | | : | |
86 | | : | | : | |
87 +-------+ : +--------+ : +-------+
88 ^ : ^ : ^
89 | : | : |
90 | : | : |
91 | : v : |
92 | : +--------+ : |
93 | : | | : |
94 | : | | : |
95 +---------->| Device |<----------+
96 : | | :
97 : | | :
98 : +--------+ :
99 : :
100
101Each CPU executes a program that generates memory access operations. In the
102abstract CPU, memory operation ordering is very relaxed, and a CPU may actually
103perform the memory operations in any order it likes, provided program causality
104appears to be maintained. Similarly, the compiler may also arrange the
105instructions it emits in any order it likes, provided it doesn't affect the
106apparent operation of the program.
107
108So in the above diagram, the effects of the memory operations performed by a
109CPU are perceived by the rest of the system as the operations cross the
110interface between the CPU and rest of the system (the dotted lines).
111
112
113For example, consider the following sequence of events:
114
115 CPU 1 CPU 2
116 =============== ===============
117 { A == 1; B == 2 }
118 A = 3; x = A;
119 B = 4; y = B;
120
121The set of accesses as seen by the memory system in the middle can be arranged
122in 24 different combinations:
123
124 STORE A=3, STORE B=4, x=LOAD A->3, y=LOAD B->4
125 STORE A=3, STORE B=4, y=LOAD B->4, x=LOAD A->3
126 STORE A=3, x=LOAD A->3, STORE B=4, y=LOAD B->4
127 STORE A=3, x=LOAD A->3, y=LOAD B->2, STORE B=4
128 STORE A=3, y=LOAD B->2, STORE B=4, x=LOAD A->3
129 STORE A=3, y=LOAD B->2, x=LOAD A->3, STORE B=4
130 STORE B=4, STORE A=3, x=LOAD A->3, y=LOAD B->4
131 STORE B=4, ...
132 ...
133
134and can thus result in four different combinations of values:
135
136 x == 1, y == 2
137 x == 1, y == 4
138 x == 3, y == 2
139 x == 3, y == 4
140
141
142Furthermore, the stores committed by a CPU to the memory system may not be
143perceived by the loads made by another CPU in the same order as the stores were
144committed.
145
146
147As a further example, consider this sequence of events:
148
149 CPU 1 CPU 2
150 =============== ===============
151 { A == 1, B == 2, C = 3, P == &A, Q == &C }
152 B = 4; Q = P;
153 P = &B D = *Q;
154
155There is an obvious data dependency here, as the value loaded into D depends on
156the address retrieved from P by CPU 2. At the end of the sequence, any of the
157following results are possible:
158
159 (Q == &A) and (D == 1)
160 (Q == &B) and (D == 2)
161 (Q == &B) and (D == 4)
162
163Note that CPU 2 will never try and load C into D because the CPU will load P
164into Q before issuing the load of *Q.
165
166
167DEVICE OPERATIONS
168-----------------
169
170Some devices present their control interfaces as collections of memory
171locations, but the order in which the control registers are accessed is very
172important. For instance, imagine an ethernet card with a set of internal
173registers that are accessed through an address port register (A) and a data
174port register (D). To read internal register 5, the following code might then
175be used:
176
177 *A = 5;
178 x = *D;
179
180but this might show up as either of the following two sequences:
181
182 STORE *A = 5, x = LOAD *D
183 x = LOAD *D, STORE *A = 5
184
185the second of which will almost certainly result in a malfunction, since it set
186the address _after_ attempting to read the register.
187
188
189GUARANTEES
190----------
191
192There are some minimal guarantees that may be expected of a CPU:
193
194 (*) On any given CPU, dependent memory accesses will be issued in order, with
195 respect to itself. This means that for:
196
197 Q = P; D = *Q;
198
199 the CPU will issue the following memory operations:
200
201 Q = LOAD P, D = LOAD *Q
202
203 and always in that order.
204
205 (*) Overlapping loads and stores within a particular CPU will appear to be
206 ordered within that CPU. This means that for:
207
208 a = *X; *X = b;
209
210 the CPU will only issue the following sequence of memory operations:
211
212 a = LOAD *X, STORE *X = b
213
214 And for:
215
216 *X = c; d = *X;
217
218 the CPU will only issue:
219
220 STORE *X = c, d = LOAD *X
221
222 (Loads and stores overlap if they are targeted at overlapping pieces of
223 memory).
224
225And there are a number of things that _must_ or _must_not_ be assumed:
226
227 (*) It _must_not_ be assumed that independent loads and stores will be issued
228 in the order given. This means that for:
229
230 X = *A; Y = *B; *D = Z;
231
232 we may get any of the following sequences:
233
234 X = LOAD *A, Y = LOAD *B, STORE *D = Z
235 X = LOAD *A, STORE *D = Z, Y = LOAD *B
236 Y = LOAD *B, X = LOAD *A, STORE *D = Z
237 Y = LOAD *B, STORE *D = Z, X = LOAD *A
238 STORE *D = Z, X = LOAD *A, Y = LOAD *B
239 STORE *D = Z, Y = LOAD *B, X = LOAD *A
240
241 (*) It _must_ be assumed that overlapping memory accesses may be merged or
242 discarded. This means that for:
243
244 X = *A; Y = *(A + 4);
245
246 we may get any one of the following sequences:
247
248 X = LOAD *A; Y = LOAD *(A + 4);
249 Y = LOAD *(A + 4); X = LOAD *A;
250 {X, Y} = LOAD {*A, *(A + 4) };
251
252 And for:
253
254 *A = X; Y = *A;
255
256 we may get either of:
257
258 STORE *A = X; Y = LOAD *A;
259 STORE *A = Y = X;
260
261
262=========================
263WHAT ARE MEMORY BARRIERS?
264=========================
265
266As can be seen above, independent memory operations are effectively performed
267in random order, but this can be a problem for CPU-CPU interaction and for I/O.
268What is required is some way of intervening to instruct the compiler and the
269CPU to restrict the order.
270
271Memory barriers are such interventions. They impose a perceived partial
272ordering over the memory operations on either side of the barrier.
273
274Such enforcement is important because the CPUs and other devices in a system
275can use a variety of tricks to improve performance, including reordering,
276deferral and combination of memory operations; speculative loads; speculative
277branch prediction and various types of caching. Memory barriers are used to
278override or suppress these tricks, allowing the code to sanely control the
279interaction of multiple CPUs and/or devices.
280
281
282VARIETIES OF MEMORY BARRIER
283---------------------------
284
285Memory barriers come in four basic varieties:
286
287 (1) Write (or store) memory barriers.
288
289 A write memory barrier gives a guarantee that all the STORE operations
290 specified before the barrier will appear to happen before all the STORE
291 operations specified after the barrier with respect to the other
292 components of the system.
293
294 A write barrier is a partial ordering on stores only; it is not required
295 to have any effect on loads.
296
297 A CPU can be viewed as committing a sequence of store operations to the
298 memory system as time progresses. All stores before a write barrier will
299 occur in the sequence _before_ all the stores after the write barrier.
300
301 [!] Note that write barriers should normally be paired with read or data
302 dependency barriers; see the "SMP barrier pairing" subsection.
303
304
305 (2) Data dependency barriers.
306
307 A data dependency barrier is a weaker form of read barrier. In the case
308 where two loads are performed such that the second depends on the result
309 of the first (eg: the first load retrieves the address to which the second
310 load will be directed), a data dependency barrier would be required to
311 make sure that the target of the second load is updated before the address
312 obtained by the first load is accessed.
313
314 A data dependency barrier is a partial ordering on interdependent loads
315 only; it is not required to have any effect on stores, independent loads
316 or overlapping loads.
317
318 As mentioned in (1), the other CPUs in the system can be viewed as
319 committing sequences of stores to the memory system that the CPU being
320 considered can then perceive. A data dependency barrier issued by the CPU
321 under consideration guarantees that for any load preceding it, if that
322 load touches one of a sequence of stores from another CPU, then by the
323 time the barrier completes, the effects of all the stores prior to that
324 touched by the load will be perceptible to any loads issued after the data
325 dependency barrier.
326
327 See the "Examples of memory barrier sequences" subsection for diagrams
328 showing the ordering constraints.
329
330 [!] Note that the first load really has to have a _data_ dependency and
331 not a control dependency. If the address for the second load is dependent
332 on the first load, but the dependency is through a conditional rather than
333 actually loading the address itself, then it's a _control_ dependency and
334 a full read barrier or better is required. See the "Control dependencies"
335 subsection for more information.
336
337 [!] Note that data dependency barriers should normally be paired with
338 write barriers; see the "SMP barrier pairing" subsection.
339
340
341 (3) Read (or load) memory barriers.
342
343 A read barrier is a data dependency barrier plus a guarantee that all the
344 LOAD operations specified before the barrier will appear to happen before
345 all the LOAD operations specified after the barrier with respect to the
346 other components of the system.
347
348 A read barrier is a partial ordering on loads only; it is not required to
349 have any effect on stores.
350
351 Read memory barriers imply data dependency barriers, and so can substitute
352 for them.
353
354 [!] Note that read barriers should normally be paired with write barriers;
355 see the "SMP barrier pairing" subsection.
356
357
358 (4) General memory barriers.
359
360 A general memory barrier gives a guarantee that all the LOAD and STORE
361 operations specified before the barrier will appear to happen before all
362 the LOAD and STORE operations specified after the barrier with respect to
363 the other components of the system.
364
365 A general memory barrier is a partial ordering over both loads and stores.
366
367 General memory barriers imply both read and write memory barriers, and so
368 can substitute for either.
369
370
371And a couple of implicit varieties:
372
373 (5) LOCK operations.
374
375 This acts as a one-way permeable barrier. It guarantees that all memory
376 operations after the LOCK operation will appear to happen after the LOCK
377 operation with respect to the other components of the system.
378
379 Memory operations that occur before a LOCK operation may appear to happen
380 after it completes.
381
382 A LOCK operation should almost always be paired with an UNLOCK operation.
383
384
385 (6) UNLOCK operations.
386
387 This also acts as a one-way permeable barrier. It guarantees that all
388 memory operations before the UNLOCK operation will appear to happen before
389 the UNLOCK operation with respect to the other components of the system.
390
391 Memory operations that occur after an UNLOCK operation may appear to
392 happen before it completes.
393
394 LOCK and UNLOCK operations are guaranteed to appear with respect to each
395 other strictly in the order specified.
396
397 The use of LOCK and UNLOCK operations generally precludes the need for
398 other sorts of memory barrier (but note the exceptions mentioned in the
399 subsection "MMIO write barrier").
400
401
402Memory barriers are only required where there's a possibility of interaction
403between two CPUs or between a CPU and a device. If it can be guaranteed that
404there won't be any such interaction in any particular piece of code, then
405memory barriers are unnecessary in that piece of code.
406
407
408Note that these are the _minimum_ guarantees. Different architectures may give
409more substantial guarantees, but they may _not_ be relied upon outside of arch
410specific code.
411
412
413WHAT MAY NOT BE ASSUMED ABOUT MEMORY BARRIERS?
414----------------------------------------------
415
416There are certain things that the Linux kernel memory barriers do not guarantee:
417
418 (*) There is no guarantee that any of the memory accesses specified before a
419 memory barrier will be _complete_ by the completion of a memory barrier
420 instruction; the barrier can be considered to draw a line in that CPU's
421 access queue that accesses of the appropriate type may not cross.
422
423 (*) There is no guarantee that issuing a memory barrier on one CPU will have
424 any direct effect on another CPU or any other hardware in the system. The
425 indirect effect will be the order in which the second CPU sees the effects
426 of the first CPU's accesses occur, but see the next point:
427
428 (*) There is no guarantee that a CPU will see the correct order of effects
429 from a second CPU's accesses, even _if_ the second CPU uses a memory
430 barrier, unless the first CPU _also_ uses a matching memory barrier (see
431 the subsection on "SMP Barrier Pairing").
432
433 (*) There is no guarantee that some intervening piece of off-the-CPU
434 hardware[*] will not reorder the memory accesses. CPU cache coherency
435 mechanisms should propagate the indirect effects of a memory barrier
436 between CPUs, but might not do so in order.
437
438 [*] For information on bus mastering DMA and coherency please read:
439
440 Documentation/PCI/pci.txt
441 Documentation/PCI/PCI-DMA-mapping.txt
442 Documentation/DMA-API.txt
443
444
445DATA DEPENDENCY BARRIERS
446------------------------
447
448The usage requirements of data dependency barriers are a little subtle, and
449it's not always obvious that they're needed. To illustrate, consider the
450following sequence of events:
451
452 CPU 1 CPU 2
453 =============== ===============
454 { A == 1, B == 2, C = 3, P == &A, Q == &C }
455 B = 4;
456 <write barrier>
457 P = &B
458 Q = P;
459 D = *Q;
460
461There's a clear data dependency here, and it would seem that by the end of the
462sequence, Q must be either &A or &B, and that:
463
464 (Q == &A) implies (D == 1)
465 (Q == &B) implies (D == 4)
466
467But! CPU 2's perception of P may be updated _before_ its perception of B, thus
468leading to the following situation:
469
470 (Q == &B) and (D == 2) ????
471
472Whilst this may seem like a failure of coherency or causality maintenance, it
473isn't, and this behaviour can be observed on certain real CPUs (such as the DEC
474Alpha).
475
476To deal with this, a data dependency barrier or better must be inserted
477between the address load and the data load:
478
479 CPU 1 CPU 2
480 =============== ===============
481 { A == 1, B == 2, C = 3, P == &A, Q == &C }
482 B = 4;
483 <write barrier>
484 P = &B
485 Q = P;
486 <data dependency barrier>
487 D = *Q;
488
489This enforces the occurrence of one of the two implications, and prevents the
490third possibility from arising.
491
492[!] Note that this extremely counterintuitive situation arises most easily on
493machines with split caches, so that, for example, one cache bank processes
494even-numbered cache lines and the other bank processes odd-numbered cache
495lines. The pointer P might be stored in an odd-numbered cache line, and the
496variable B might be stored in an even-numbered cache line. Then, if the
497even-numbered bank of the reading CPU's cache is extremely busy while the
498odd-numbered bank is idle, one can see the new value of the pointer P (&B),
499but the old value of the variable B (2).
500
501
502Another example of where data dependency barriers might by required is where a
503number is read from memory and then used to calculate the index for an array
504access:
505
506 CPU 1 CPU 2
507 =============== ===============
508 { M[0] == 1, M[1] == 2, M[3] = 3, P == 0, Q == 3 }
509 M[1] = 4;
510 <write barrier>
511 P = 1
512 Q = P;
513 <data dependency barrier>
514 D = M[Q];
515
516
517The data dependency barrier is very important to the RCU system, for example.
518See rcu_dereference() in include/linux/rcupdate.h. This permits the current
519target of an RCU'd pointer to be replaced with a new modified target, without
520the replacement target appearing to be incompletely initialised.
521
522See also the subsection on "Cache Coherency" for a more thorough example.
523
524
525CONTROL DEPENDENCIES
526--------------------
527
528A control dependency requires a full read memory barrier, not simply a data
529dependency barrier to make it work correctly. Consider the following bit of
530code:
531
532 q = &a;
533 if (p)
534 q = &b;
535 <data dependency barrier>
536 x = *q;
537
538This will not have the desired effect because there is no actual data
539dependency, but rather a control dependency that the CPU may short-circuit by
540attempting to predict the outcome in advance. In such a case what's actually
541required is:
542
543 q = &a;
544 if (p)
545 q = &b;
546 <read barrier>
547 x = *q;
548
549
550SMP BARRIER PAIRING
551-------------------
552
553When dealing with CPU-CPU interactions, certain types of memory barrier should
554always be paired. A lack of appropriate pairing is almost certainly an error.
555
556A write barrier should always be paired with a data dependency barrier or read
557barrier, though a general barrier would also be viable. Similarly a read
558barrier or a data dependency barrier should always be paired with at least an
559write barrier, though, again, a general barrier is viable:
560
561 CPU 1 CPU 2
562 =============== ===============
563 a = 1;
564 <write barrier>
565 b = 2; x = b;
566 <read barrier>
567 y = a;
568
569Or:
570
571 CPU 1 CPU 2
572 =============== ===============================
573 a = 1;
574 <write barrier>
575 b = &a; x = b;
576 <data dependency barrier>
577 y = *x;
578
579Basically, the read barrier always has to be there, even though it can be of
580the "weaker" type.
581
582[!] Note that the stores before the write barrier would normally be expected to
583match the loads after the read barrier or the data dependency barrier, and vice
584versa:
585
586 CPU 1 CPU 2
587 =============== ===============
588 a = 1; }---- --->{ v = c
589 b = 2; } \ / { w = d
590 <write barrier> \ <read barrier>
591 c = 3; } / \ { x = a;
592 d = 4; }---- --->{ y = b;
593
594
595EXAMPLES OF MEMORY BARRIER SEQUENCES
596------------------------------------
597
598Firstly, write barriers act as partial orderings on store operations.
599Consider the following sequence of events:
600
601 CPU 1
602 =======================
603 STORE A = 1
604 STORE B = 2
605 STORE C = 3
606 <write barrier>
607 STORE D = 4
608 STORE E = 5
609
610This sequence of events is committed to the memory coherence system in an order
611that the rest of the system might perceive as the unordered set of { STORE A,
612STORE B, STORE C } all occurring before the unordered set of { STORE D, STORE E
613}:
614
615 +-------+ : :
616 | | +------+
617 | |------>| C=3 | } /\
618 | | : +------+ }----- \ -----> Events perceptible to
619 | | : | A=1 | } \/ the rest of the system
620 | | : +------+ }
621 | CPU 1 | : | B=2 | }
622 | | +------+ }
623 | | wwwwwwwwwwwwwwww } <--- At this point the write barrier
624 | | +------+ } requires all stores prior to the
625 | | : | E=5 | } barrier to be committed before
626 | | : +------+ } further stores may take place
627 | |------>| D=4 | }
628 | | +------+
629 +-------+ : :
630 |
631 | Sequence in which stores are committed to the
632 | memory system by CPU 1
633 V
634
635
636Secondly, data dependency barriers act as partial orderings on data-dependent
637loads. Consider the following sequence of events:
638
639 CPU 1 CPU 2
640 ======================= =======================
641 { B = 7; X = 9; Y = 8; C = &Y }
642 STORE A = 1
643 STORE B = 2
644 <write barrier>
645 STORE C = &B LOAD X
646 STORE D = 4 LOAD C (gets &B)
647 LOAD *C (reads B)
648
649Without intervention, CPU 2 may perceive the events on CPU 1 in some
650effectively random order, despite the write barrier issued by CPU 1:
651
652 +-------+ : : : :
653 | | +------+ +-------+ | Sequence of update
654 | |------>| B=2 |----- --->| Y->8 | | of perception on
655 | | : +------+ \ +-------+ | CPU 2
656 | CPU 1 | : | A=1 | \ --->| C->&Y | V
657 | | +------+ | +-------+
658 | | wwwwwwwwwwwwwwww | : :
659 | | +------+ | : :
660 | | : | C=&B |--- | : : +-------+
661 | | : +------+ \ | +-------+ | |
662 | |------>| D=4 | ----------->| C->&B |------>| |
663 | | +------+ | +-------+ | |
664 +-------+ : : | : : | |
665 | : : | |
666 | : : | CPU 2 |
667 | +-------+ | |
668 Apparently incorrect ---> | | B->7 |------>| |
669 perception of B (!) | +-------+ | |
670 | : : | |
671 | +-------+ | |
672 The load of X holds ---> \ | X->9 |------>| |
673 up the maintenance \ +-------+ | |
674 of coherence of B ----->| B->2 | +-------+
675 +-------+
676 : :
677
678
679In the above example, CPU 2 perceives that B is 7, despite the load of *C
680(which would be B) coming after the LOAD of C.
681
682If, however, a data dependency barrier were to be placed between the load of C
683and the load of *C (ie: B) on CPU 2:
684
685 CPU 1 CPU 2
686 ======================= =======================
687 { B = 7; X = 9; Y = 8; C = &Y }
688 STORE A = 1
689 STORE B = 2
690 <write barrier>
691 STORE C = &B LOAD X
692 STORE D = 4 LOAD C (gets &B)
693 <data dependency barrier>
694 LOAD *C (reads B)
695
696then the following will occur:
697
698 +-------+ : : : :
699 | | +------+ +-------+
700 | |------>| B=2 |----- --->| Y->8 |
701 | | : +------+ \ +-------+
702 | CPU 1 | : | A=1 | \ --->| C->&Y |
703 | | +------+ | +-------+
704 | | wwwwwwwwwwwwwwww | : :
705 | | +------+ | : :
706 | | : | C=&B |--- | : : +-------+
707 | | : +------+ \ | +-------+ | |
708 | |------>| D=4 | ----------->| C->&B |------>| |
709 | | +------+ | +-------+ | |
710 +-------+ : : | : : | |
711 | : : | |
712 | : : | CPU 2 |
713 | +-------+ | |
714 | | X->9 |------>| |
715 | +-------+ | |
716 Makes sure all effects ---> \ ddddddddddddddddd | |
717 prior to the store of C \ +-------+ | |
718 are perceptible to ----->| B->2 |------>| |
719 subsequent loads +-------+ | |
720 : : +-------+
721
722
723And thirdly, a read barrier acts as a partial order on loads. Consider the
724following sequence of events:
725
726 CPU 1 CPU 2
727 ======================= =======================
728 { A = 0, B = 9 }
729 STORE A=1
730 <write barrier>
731 STORE B=2
732 LOAD B
733 LOAD A
734
735Without intervention, CPU 2 may then choose to perceive the events on CPU 1 in
736some effectively random order, despite the write barrier issued by CPU 1:
737
738 +-------+ : : : :
739 | | +------+ +-------+
740 | |------>| A=1 |------ --->| A->0 |
741 | | +------+ \ +-------+
742 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
743 | | +------+ | +-------+
744 | |------>| B=2 |--- | : :
745 | | +------+ \ | : : +-------+
746 +-------+ : : \ | +-------+ | |
747 ---------->| B->2 |------>| |
748 | +-------+ | CPU 2 |
749 | | A->0 |------>| |
750 | +-------+ | |
751 | : : +-------+
752 \ : :
753 \ +-------+
754 ---->| A->1 |
755 +-------+
756 : :
757
758
759If, however, a read barrier were to be placed between the load of B and the
760load of A on CPU 2:
761
762 CPU 1 CPU 2
763 ======================= =======================
764 { A = 0, B = 9 }
765 STORE A=1
766 <write barrier>
767 STORE B=2
768 LOAD B
769 <read barrier>
770 LOAD A
771
772then the partial ordering imposed by CPU 1 will be perceived correctly by CPU
7732:
774
775 +-------+ : : : :
776 | | +------+ +-------+
777 | |------>| A=1 |------ --->| A->0 |
778 | | +------+ \ +-------+
779 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
780 | | +------+ | +-------+
781 | |------>| B=2 |--- | : :
782 | | +------+ \ | : : +-------+
783 +-------+ : : \ | +-------+ | |
784 ---------->| B->2 |------>| |
785 | +-------+ | CPU 2 |
786 | : : | |
787 | : : | |
788 At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
789 barrier causes all effects \ +-------+ | |
790 prior to the storage of B ---->| A->1 |------>| |
791 to be perceptible to CPU 2 +-------+ | |
792 : : +-------+
793
794
795To illustrate this more completely, consider what could happen if the code
796contained a load of A either side of the read barrier:
797
798 CPU 1 CPU 2
799 ======================= =======================
800 { A = 0, B = 9 }
801 STORE A=1
802 <write barrier>
803 STORE B=2
804 LOAD B
805 LOAD A [first load of A]
806 <read barrier>
807 LOAD A [second load of A]
808
809Even though the two loads of A both occur after the load of B, they may both
810come up with different values:
811
812 +-------+ : : : :
813 | | +------+ +-------+
814 | |------>| A=1 |------ --->| A->0 |
815 | | +------+ \ +-------+
816 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
817 | | +------+ | +-------+
818 | |------>| B=2 |--- | : :
819 | | +------+ \ | : : +-------+
820 +-------+ : : \ | +-------+ | |
821 ---------->| B->2 |------>| |
822 | +-------+ | CPU 2 |
823 | : : | |
824 | : : | |
825 | +-------+ | |
826 | | A->0 |------>| 1st |
827 | +-------+ | |
828 At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
829 barrier causes all effects \ +-------+ | |
830 prior to the storage of B ---->| A->1 |------>| 2nd |
831 to be perceptible to CPU 2 +-------+ | |
832 : : +-------+
833
834
835But it may be that the update to A from CPU 1 becomes perceptible to CPU 2
836before the read barrier completes anyway:
837
838 +-------+ : : : :
839 | | +------+ +-------+
840 | |------>| A=1 |------ --->| A->0 |
841 | | +------+ \ +-------+
842 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
843 | | +------+ | +-------+
844 | |------>| B=2 |--- | : :
845 | | +------+ \ | : : +-------+
846 +-------+ : : \ | +-------+ | |
847 ---------->| B->2 |------>| |
848 | +-------+ | CPU 2 |
849 | : : | |
850 \ : : | |
851 \ +-------+ | |
852 ---->| A->1 |------>| 1st |
853 +-------+ | |
854 rrrrrrrrrrrrrrrrr | |
855 +-------+ | |
856 | A->1 |------>| 2nd |
857 +-------+ | |
858 : : +-------+
859
860
861The guarantee is that the second load will always come up with A == 1 if the
862load of B came up with B == 2. No such guarantee exists for the first load of
863A; that may come up with either A == 0 or A == 1.
864
865
866READ MEMORY BARRIERS VS LOAD SPECULATION
867----------------------------------------
868
869Many CPUs speculate with loads: that is they see that they will need to load an
870item from memory, and they find a time where they're not using the bus for any
871other loads, and so do the load in advance - even though they haven't actually
872got to that point in the instruction execution flow yet. This permits the
873actual load instruction to potentially complete immediately because the CPU
874already has the value to hand.
875
876It may turn out that the CPU didn't actually need the value - perhaps because a
877branch circumvented the load - in which case it can discard the value or just
878cache it for later use.
879
880Consider:
881
882 CPU 1 CPU 2
883 ======================= =======================
884 LOAD B
885 DIVIDE } Divide instructions generally
886 DIVIDE } take a long time to perform
887 LOAD A
888
889Which might appear as this:
890
891 : : +-------+
892 +-------+ | |
893 --->| B->2 |------>| |
894 +-------+ | CPU 2 |
895 : :DIVIDE | |
896 +-------+ | |
897 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
898 division speculates on the +-------+ ~ | |
899 LOAD of A : : ~ | |
900 : :DIVIDE | |
901 : : ~ | |
902 Once the divisions are complete --> : : ~-->| |
903 the CPU can then perform the : : | |
904 LOAD with immediate effect : : +-------+
905
906
907Placing a read barrier or a data dependency barrier just before the second
908load:
909
910 CPU 1 CPU 2
911 ======================= =======================
912 LOAD B
913 DIVIDE
914 DIVIDE
915 <read barrier>
916 LOAD A
917
918will force any value speculatively obtained to be reconsidered to an extent
919dependent on the type of barrier used. If there was no change made to the
920speculated memory location, then the speculated value will just be used:
921
922 : : +-------+
923 +-------+ | |
924 --->| B->2 |------>| |
925 +-------+ | CPU 2 |
926 : :DIVIDE | |
927 +-------+ | |
928 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
929 division speculates on the +-------+ ~ | |
930 LOAD of A : : ~ | |
931 : :DIVIDE | |
932 : : ~ | |
933 : : ~ | |
934 rrrrrrrrrrrrrrrr~ | |
935 : : ~ | |
936 : : ~-->| |
937 : : | |
938 : : +-------+
939
940
941but if there was an update or an invalidation from another CPU pending, then
942the speculation will be cancelled and the value reloaded:
943
944 : : +-------+
945 +-------+ | |
946 --->| B->2 |------>| |
947 +-------+ | CPU 2 |
948 : :DIVIDE | |
949 +-------+ | |
950 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
951 division speculates on the +-------+ ~ | |
952 LOAD of A : : ~ | |
953 : :DIVIDE | |
954 : : ~ | |
955 : : ~ | |
956 rrrrrrrrrrrrrrrrr | |
957 +-------+ | |
958 The speculation is discarded ---> --->| A->1 |------>| |
959 and an updated value is +-------+ | |
960 retrieved : : +-------+
961
962
963TRANSITIVITY
964------------
965
966Transitivity is a deeply intuitive notion about ordering that is not
967always provided by real computer systems. The following example
968demonstrates transitivity (also called "cumulativity"):
969
970 CPU 1 CPU 2 CPU 3
971 ======================= ======================= =======================
972 { X = 0, Y = 0 }
973 STORE X=1 LOAD X STORE Y=1
974 <general barrier> <general barrier>
975 LOAD Y LOAD X
976
977Suppose that CPU 2's load from X returns 1 and its load from Y returns 0.
978This indicates that CPU 2's load from X in some sense follows CPU 1's
979store to X and that CPU 2's load from Y in some sense preceded CPU 3's
980store to Y. The question is then "Can CPU 3's load from X return 0?"
981
982Because CPU 2's load from X in some sense came after CPU 1's store, it
983is natural to expect that CPU 3's load from X must therefore return 1.
984This expectation is an example of transitivity: if a load executing on
985CPU A follows a load from the same variable executing on CPU B, then
986CPU A's load must either return the same value that CPU B's load did,
987or must return some later value.
988
989In the Linux kernel, use of general memory barriers guarantees
990transitivity. Therefore, in the above example, if CPU 2's load from X
991returns 1 and its load from Y returns 0, then CPU 3's load from X must
992also return 1.
993
994However, transitivity is -not- guaranteed for read or write barriers.
995For example, suppose that CPU 2's general barrier in the above example
996is changed to a read barrier as shown below:
997
998 CPU 1 CPU 2 CPU 3
999 ======================= ======================= =======================
1000 { X = 0, Y = 0 }
1001 STORE X=1 LOAD X STORE Y=1
1002 <read barrier> <general barrier>
1003 LOAD Y LOAD X
1004
1005This substitution destroys transitivity: in this example, it is perfectly
1006legal for CPU 2's load from X to return 1, its load from Y to return 0,
1007and CPU 3's load from X to return 0.
1008
1009The key point is that although CPU 2's read barrier orders its pair
1010of loads, it does not guarantee to order CPU 1's store. Therefore, if
1011this example runs on a system where CPUs 1 and 2 share a store buffer
1012or a level of cache, CPU 2 might have early access to CPU 1's writes.
1013General barriers are therefore required to ensure that all CPUs agree
1014on the combined order of CPU 1's and CPU 2's accesses.
1015
1016To reiterate, if your code requires transitivity, use general barriers
1017throughout.
1018
1019
1020========================
1021EXPLICIT KERNEL BARRIERS
1022========================
1023
1024The Linux kernel has a variety of different barriers that act at different
1025levels:
1026
1027 (*) Compiler barrier.
1028
1029 (*) CPU memory barriers.
1030
1031 (*) MMIO write barrier.
1032
1033
1034COMPILER BARRIER
1035----------------
1036
1037The Linux kernel has an explicit compiler barrier function that prevents the
1038compiler from moving the memory accesses either side of it to the other side:
1039
1040 barrier();
1041
1042This is a general barrier - lesser varieties of compiler barrier do not exist.
1043
1044The compiler barrier has no direct effect on the CPU, which may then reorder
1045things however it wishes.
1046
1047
1048CPU MEMORY BARRIERS
1049-------------------
1050
1051The Linux kernel has eight basic CPU memory barriers:
1052
1053 TYPE MANDATORY SMP CONDITIONAL
1054 =============== ======================= ===========================
1055 GENERAL mb() smp_mb()
1056 WRITE wmb() smp_wmb()
1057 READ rmb() smp_rmb()
1058 DATA DEPENDENCY read_barrier_depends() smp_read_barrier_depends()
1059
1060
1061All memory barriers except the data dependency barriers imply a compiler
1062barrier. Data dependencies do not impose any additional compiler ordering.
1063
1064Aside: In the case of data dependencies, the compiler would be expected to
1065issue the loads in the correct order (eg. `a[b]` would have to load the value
1066of b before loading a[b]), however there is no guarantee in the C specification
1067that the compiler may not speculate the value of b (eg. is equal to 1) and load
1068a before b (eg. tmp = a[1]; if (b != 1) tmp = a[b]; ). There is also the
1069problem of a compiler reloading b after having loaded a[b], thus having a newer
1070copy of b than a[b]. A consensus has not yet been reached about these problems,
1071however the ACCESS_ONCE macro is a good place to start looking.
1072
1073SMP memory barriers are reduced to compiler barriers on uniprocessor compiled
1074systems because it is assumed that a CPU will appear to be self-consistent,
1075and will order overlapping accesses correctly with respect to itself.
1076
1077[!] Note that SMP memory barriers _must_ be used to control the ordering of
1078references to shared memory on SMP systems, though the use of locking instead
1079is sufficient.
1080
1081Mandatory barriers should not be used to control SMP effects, since mandatory
1082barriers unnecessarily impose overhead on UP systems. They may, however, be
1083used to control MMIO effects on accesses through relaxed memory I/O windows.
1084These are required even on non-SMP systems as they affect the order in which
1085memory operations appear to a device by prohibiting both the compiler and the
1086CPU from reordering them.
1087
1088
1089There are some more advanced barrier functions:
1090
1091 (*) set_mb(var, value)
1092
1093 This assigns the value to the variable and then inserts a full memory
1094 barrier after it, depending on the function. It isn't guaranteed to
1095 insert anything more than a compiler barrier in a UP compilation.
1096
1097
1098 (*) smp_mb__before_atomic_dec();
1099 (*) smp_mb__after_atomic_dec();
1100 (*) smp_mb__before_atomic_inc();
1101 (*) smp_mb__after_atomic_inc();
1102
1103 These are for use with atomic add, subtract, increment and decrement
1104 functions that don't return a value, especially when used for reference
1105 counting. These functions do not imply memory barriers.
1106
1107 As an example, consider a piece of code that marks an object as being dead
1108 and then decrements the object's reference count:
1109
1110 obj->dead = 1;
1111 smp_mb__before_atomic_dec();
1112 atomic_dec(&obj->ref_count);
1113
1114 This makes sure that the death mark on the object is perceived to be set
1115 *before* the reference counter is decremented.
1116
1117 See Documentation/atomic_ops.txt for more information. See the "Atomic
1118 operations" subsection for information on where to use these.
1119
1120
1121 (*) smp_mb__before_clear_bit(void);
1122 (*) smp_mb__after_clear_bit(void);
1123
1124 These are for use similar to the atomic inc/dec barriers. These are
1125 typically used for bitwise unlocking operations, so care must be taken as
1126 there are no implicit memory barriers here either.
1127
1128 Consider implementing an unlock operation of some nature by clearing a
1129 locking bit. The clear_bit() would then need to be barriered like this:
1130
1131 smp_mb__before_clear_bit();
1132 clear_bit( ... );
1133
1134 This prevents memory operations before the clear leaking to after it. See
1135 the subsection on "Locking Functions" with reference to UNLOCK operation
1136 implications.
1137
1138 See Documentation/atomic_ops.txt for more information. See the "Atomic
1139 operations" subsection for information on where to use these.
1140
1141
1142MMIO WRITE BARRIER
1143------------------
1144
1145The Linux kernel also has a special barrier for use with memory-mapped I/O
1146writes:
1147
1148 mmiowb();
1149
1150This is a variation on the mandatory write barrier that causes writes to weakly
1151ordered I/O regions to be partially ordered. Its effects may go beyond the
1152CPU->Hardware interface and actually affect the hardware at some level.
1153
1154See the subsection "Locks vs I/O accesses" for more information.
1155
1156
1157===============================
1158IMPLICIT KERNEL MEMORY BARRIERS
1159===============================
1160
1161Some of the other functions in the linux kernel imply memory barriers, amongst
1162which are locking and scheduling functions.
1163
1164This specification is a _minimum_ guarantee; any particular architecture may
1165provide more substantial guarantees, but these may not be relied upon outside
1166of arch specific code.
1167
1168
1169LOCKING FUNCTIONS
1170-----------------
1171
1172The Linux kernel has a number of locking constructs:
1173
1174 (*) spin locks
1175 (*) R/W spin locks
1176 (*) mutexes
1177 (*) semaphores
1178 (*) R/W semaphores
1179 (*) RCU
1180
1181In all cases there are variants on "LOCK" operations and "UNLOCK" operations
1182for each construct. These operations all imply certain barriers:
1183
1184 (1) LOCK operation implication:
1185
1186 Memory operations issued after the LOCK will be completed after the LOCK
1187 operation has completed.
1188
1189 Memory operations issued before the LOCK may be completed after the LOCK
1190 operation has completed.
1191
1192 (2) UNLOCK operation implication:
1193
1194 Memory operations issued before the UNLOCK will be completed before the
1195 UNLOCK operation has completed.
1196
1197 Memory operations issued after the UNLOCK may be completed before the
1198 UNLOCK operation has completed.
1199
1200 (3) LOCK vs LOCK implication:
1201
1202 All LOCK operations issued before another LOCK operation will be completed
1203 before that LOCK operation.
1204
1205 (4) LOCK vs UNLOCK implication:
1206
1207 All LOCK operations issued before an UNLOCK operation will be completed
1208 before the UNLOCK operation.
1209
1210 All UNLOCK operations issued before a LOCK operation will be completed
1211 before the LOCK operation.
1212
1213 (5) Failed conditional LOCK implication:
1214
1215 Certain variants of the LOCK operation may fail, either due to being
1216 unable to get the lock immediately, or due to receiving an unblocked
1217 signal whilst asleep waiting for the lock to become available. Failed
1218 locks do not imply any sort of barrier.
1219
1220Therefore, from (1), (2) and (4) an UNLOCK followed by an unconditional LOCK is
1221equivalent to a full barrier, but a LOCK followed by an UNLOCK is not.
1222
1223[!] Note: one of the consequences of LOCKs and UNLOCKs being only one-way
1224 barriers is that the effects of instructions outside of a critical section
1225 may seep into the inside of the critical section.
1226
1227A LOCK followed by an UNLOCK may not be assumed to be full memory barrier
1228because it is possible for an access preceding the LOCK to happen after the
1229LOCK, and an access following the UNLOCK to happen before the UNLOCK, and the
1230two accesses can themselves then cross:
1231
1232 *A = a;
1233 LOCK
1234 UNLOCK
1235 *B = b;
1236
1237may occur as:
1238
1239 LOCK, STORE *B, STORE *A, UNLOCK
1240
1241Locks and semaphores may not provide any guarantee of ordering on UP compiled
1242systems, and so cannot be counted on in such a situation to actually achieve
1243anything at all - especially with respect to I/O accesses - unless combined
1244with interrupt disabling operations.
1245
1246See also the section on "Inter-CPU locking barrier effects".
1247
1248
1249As an example, consider the following:
1250
1251 *A = a;
1252 *B = b;
1253 LOCK
1254 *C = c;
1255 *D = d;
1256 UNLOCK
1257 *E = e;
1258 *F = f;
1259
1260The following sequence of events is acceptable:
1261
1262 LOCK, {*F,*A}, *E, {*C,*D}, *B, UNLOCK
1263
1264 [+] Note that {*F,*A} indicates a combined access.
1265
1266But none of the following are:
1267
1268 {*F,*A}, *B, LOCK, *C, *D, UNLOCK, *E
1269 *A, *B, *C, LOCK, *D, UNLOCK, *E, *F
1270 *A, *B, LOCK, *C, UNLOCK, *D, *E, *F
1271 *B, LOCK, *C, *D, UNLOCK, {*F,*A}, *E
1272
1273
1274
1275INTERRUPT DISABLING FUNCTIONS
1276-----------------------------
1277
1278Functions that disable interrupts (LOCK equivalent) and enable interrupts
1279(UNLOCK equivalent) will act as compiler barriers only. So if memory or I/O
1280barriers are required in such a situation, they must be provided from some
1281other means.
1282
1283
1284SLEEP AND WAKE-UP FUNCTIONS
1285---------------------------
1286
1287Sleeping and waking on an event flagged in global data can be viewed as an
1288interaction between two pieces of data: the task state of the task waiting for
1289the event and the global data used to indicate the event. To make sure that
1290these appear to happen in the right order, the primitives to begin the process
1291of going to sleep, and the primitives to initiate a wake up imply certain
1292barriers.
1293
1294Firstly, the sleeper normally follows something like this sequence of events:
1295
1296 for (;;) {
1297 set_current_state(TASK_UNINTERRUPTIBLE);
1298 if (event_indicated)
1299 break;
1300 schedule();
1301 }
1302
1303A general memory barrier is interpolated automatically by set_current_state()
1304after it has altered the task state:
1305
1306 CPU 1
1307 ===============================
1308 set_current_state();
1309 set_mb();
1310 STORE current->state
1311 <general barrier>
1312 LOAD event_indicated
1313
1314set_current_state() may be wrapped by:
1315
1316 prepare_to_wait();
1317 prepare_to_wait_exclusive();
1318
1319which therefore also imply a general memory barrier after setting the state.
1320The whole sequence above is available in various canned forms, all of which
1321interpolate the memory barrier in the right place:
1322
1323 wait_event();
1324 wait_event_interruptible();
1325 wait_event_interruptible_exclusive();
1326 wait_event_interruptible_timeout();
1327 wait_event_killable();
1328 wait_event_timeout();
1329 wait_on_bit();
1330 wait_on_bit_lock();
1331
1332
1333Secondly, code that performs a wake up normally follows something like this:
1334
1335 event_indicated = 1;
1336 wake_up(&event_wait_queue);
1337
1338or:
1339
1340 event_indicated = 1;
1341 wake_up_process(event_daemon);
1342
1343A write memory barrier is implied by wake_up() and co. if and only if they wake
1344something up. The barrier occurs before the task state is cleared, and so sits
1345between the STORE to indicate the event and the STORE to set TASK_RUNNING:
1346
1347 CPU 1 CPU 2
1348 =============================== ===============================
1349 set_current_state(); STORE event_indicated
1350 set_mb(); wake_up();
1351 STORE current->state <write barrier>
1352 <general barrier> STORE current->state
1353 LOAD event_indicated
1354
1355The available waker functions include:
1356
1357 complete();
1358 wake_up();
1359 wake_up_all();
1360 wake_up_bit();
1361 wake_up_interruptible();
1362 wake_up_interruptible_all();
1363 wake_up_interruptible_nr();
1364 wake_up_interruptible_poll();
1365 wake_up_interruptible_sync();
1366 wake_up_interruptible_sync_poll();
1367 wake_up_locked();
1368 wake_up_locked_poll();
1369 wake_up_nr();
1370 wake_up_poll();
1371 wake_up_process();
1372
1373
1374[!] Note that the memory barriers implied by the sleeper and the waker do _not_
1375order multiple stores before the wake-up with respect to loads of those stored
1376values after the sleeper has called set_current_state(). For instance, if the
1377sleeper does:
1378
1379 set_current_state(TASK_INTERRUPTIBLE);
1380 if (event_indicated)
1381 break;
1382 __set_current_state(TASK_RUNNING);
1383 do_something(my_data);
1384
1385and the waker does:
1386
1387 my_data = value;
1388 event_indicated = 1;
1389 wake_up(&event_wait_queue);
1390
1391there's no guarantee that the change to event_indicated will be perceived by
1392the sleeper as coming after the change to my_data. In such a circumstance, the
1393code on both sides must interpolate its own memory barriers between the
1394separate data accesses. Thus the above sleeper ought to do:
1395
1396 set_current_state(TASK_INTERRUPTIBLE);
1397 if (event_indicated) {
1398 smp_rmb();
1399 do_something(my_data);
1400 }
1401
1402and the waker should do:
1403
1404 my_data = value;
1405 smp_wmb();
1406 event_indicated = 1;
1407 wake_up(&event_wait_queue);
1408
1409
1410MISCELLANEOUS FUNCTIONS
1411-----------------------
1412
1413Other functions that imply barriers:
1414
1415 (*) schedule() and similar imply full memory barriers.
1416
1417
1418=================================
1419INTER-CPU LOCKING BARRIER EFFECTS
1420=================================
1421
1422On SMP systems locking primitives give a more substantial form of barrier: one
1423that does affect memory access ordering on other CPUs, within the context of
1424conflict on any particular lock.
1425
1426
1427LOCKS VS MEMORY ACCESSES
1428------------------------
1429
1430Consider the following: the system has a pair of spinlocks (M) and (Q), and
1431three CPUs; then should the following sequence of events occur:
1432
1433 CPU 1 CPU 2
1434 =============================== ===============================
1435 *A = a; *E = e;
1436 LOCK M LOCK Q
1437 *B = b; *F = f;
1438 *C = c; *G = g;
1439 UNLOCK M UNLOCK Q
1440 *D = d; *H = h;
1441
1442Then there is no guarantee as to what order CPU 3 will see the accesses to *A
1443through *H occur in, other than the constraints imposed by the separate locks
1444on the separate CPUs. It might, for example, see:
1445
1446 *E, LOCK M, LOCK Q, *G, *C, *F, *A, *B, UNLOCK Q, *D, *H, UNLOCK M
1447
1448But it won't see any of:
1449
1450 *B, *C or *D preceding LOCK M
1451 *A, *B or *C following UNLOCK M
1452 *F, *G or *H preceding LOCK Q
1453 *E, *F or *G following UNLOCK Q
1454
1455
1456However, if the following occurs:
1457
1458 CPU 1 CPU 2
1459 =============================== ===============================
1460 *A = a;
1461 LOCK M [1]
1462 *B = b;
1463 *C = c;
1464 UNLOCK M [1]
1465 *D = d; *E = e;
1466 LOCK M [2]
1467 *F = f;
1468 *G = g;
1469 UNLOCK M [2]
1470 *H = h;
1471
1472CPU 3 might see:
1473
1474 *E, LOCK M [1], *C, *B, *A, UNLOCK M [1],
1475 LOCK M [2], *H, *F, *G, UNLOCK M [2], *D
1476
1477But assuming CPU 1 gets the lock first, CPU 3 won't see any of:
1478
1479 *B, *C, *D, *F, *G or *H preceding LOCK M [1]
1480 *A, *B or *C following UNLOCK M [1]
1481 *F, *G or *H preceding LOCK M [2]
1482 *A, *B, *C, *E, *F or *G following UNLOCK M [2]
1483
1484
1485LOCKS VS I/O ACCESSES
1486---------------------
1487
1488Under certain circumstances (especially involving NUMA), I/O accesses within
1489two spinlocked sections on two different CPUs may be seen as interleaved by the
1490PCI bridge, because the PCI bridge does not necessarily participate in the
1491cache-coherence protocol, and is therefore incapable of issuing the required
1492read memory barriers.
1493
1494For example:
1495
1496 CPU 1 CPU 2
1497 =============================== ===============================
1498 spin_lock(Q)
1499 writel(0, ADDR)
1500 writel(1, DATA);
1501 spin_unlock(Q);
1502 spin_lock(Q);
1503 writel(4, ADDR);
1504 writel(5, DATA);
1505 spin_unlock(Q);
1506
1507may be seen by the PCI bridge as follows:
1508
1509 STORE *ADDR = 0, STORE *ADDR = 4, STORE *DATA = 1, STORE *DATA = 5
1510
1511which would probably cause the hardware to malfunction.
1512
1513
1514What is necessary here is to intervene with an mmiowb() before dropping the
1515spinlock, for example:
1516
1517 CPU 1 CPU 2
1518 =============================== ===============================
1519 spin_lock(Q)
1520 writel(0, ADDR)
1521 writel(1, DATA);
1522 mmiowb();
1523 spin_unlock(Q);
1524 spin_lock(Q);
1525 writel(4, ADDR);
1526 writel(5, DATA);
1527 mmiowb();
1528 spin_unlock(Q);
1529
1530this will ensure that the two stores issued on CPU 1 appear at the PCI bridge
1531before either of the stores issued on CPU 2.
1532
1533
1534Furthermore, following a store by a load from the same device obviates the need
1535for the mmiowb(), because the load forces the store to complete before the load
1536is performed:
1537
1538 CPU 1 CPU 2
1539 =============================== ===============================
1540 spin_lock(Q)
1541 writel(0, ADDR)
1542 a = readl(DATA);
1543 spin_unlock(Q);
1544 spin_lock(Q);
1545 writel(4, ADDR);
1546 b = readl(DATA);
1547 spin_unlock(Q);
1548
1549
1550See Documentation/DocBook/deviceiobook.tmpl for more information.
1551
1552
1553=================================
1554WHERE ARE MEMORY BARRIERS NEEDED?
1555=================================
1556
1557Under normal operation, memory operation reordering is generally not going to
1558be a problem as a single-threaded linear piece of code will still appear to
1559work correctly, even if it's in an SMP kernel. There are, however, four
1560circumstances in which reordering definitely _could_ be a problem:
1561
1562 (*) Interprocessor interaction.
1563
1564 (*) Atomic operations.
1565
1566 (*) Accessing devices.
1567
1568 (*) Interrupts.
1569
1570
1571INTERPROCESSOR INTERACTION
1572--------------------------
1573
1574When there's a system with more than one processor, more than one CPU in the
1575system may be working on the same data set at the same time. This can cause
1576synchronisation problems, and the usual way of dealing with them is to use
1577locks. Locks, however, are quite expensive, and so it may be preferable to
1578operate without the use of a lock if at all possible. In such a case
1579operations that affect both CPUs may have to be carefully ordered to prevent
1580a malfunction.
1581
1582Consider, for example, the R/W semaphore slow path. Here a waiting process is
1583queued on the semaphore, by virtue of it having a piece of its stack linked to
1584the semaphore's list of waiting processes:
1585
1586 struct rw_semaphore {
1587 ...
1588 spinlock_t lock;
1589 struct list_head waiters;
1590 };
1591
1592 struct rwsem_waiter {
1593 struct list_head list;
1594 struct task_struct *task;
1595 };
1596
1597To wake up a particular waiter, the up_read() or up_write() functions have to:
1598
1599 (1) read the next pointer from this waiter's record to know as to where the
1600 next waiter record is;
1601
1602 (2) read the pointer to the waiter's task structure;
1603
1604 (3) clear the task pointer to tell the waiter it has been given the semaphore;
1605
1606 (4) call wake_up_process() on the task; and
1607
1608 (5) release the reference held on the waiter's task struct.
1609
1610In other words, it has to perform this sequence of events:
1611
1612 LOAD waiter->list.next;
1613 LOAD waiter->task;
1614 STORE waiter->task;
1615 CALL wakeup
1616 RELEASE task
1617
1618and if any of these steps occur out of order, then the whole thing may
1619malfunction.
1620
1621Once it has queued itself and dropped the semaphore lock, the waiter does not
1622get the lock again; it instead just waits for its task pointer to be cleared
1623before proceeding. Since the record is on the waiter's stack, this means that
1624if the task pointer is cleared _before_ the next pointer in the list is read,
1625another CPU might start processing the waiter and might clobber the waiter's
1626stack before the up*() function has a chance to read the next pointer.
1627
1628Consider then what might happen to the above sequence of events:
1629
1630 CPU 1 CPU 2
1631 =============================== ===============================
1632 down_xxx()
1633 Queue waiter
1634 Sleep
1635 up_yyy()
1636 LOAD waiter->task;
1637 STORE waiter->task;
1638 Woken up by other event
1639 <preempt>
1640 Resume processing
1641 down_xxx() returns
1642 call foo()
1643 foo() clobbers *waiter
1644 </preempt>
1645 LOAD waiter->list.next;
1646 --- OOPS ---
1647
1648This could be dealt with using the semaphore lock, but then the down_xxx()
1649function has to needlessly get the spinlock again after being woken up.
1650
1651The way to deal with this is to insert a general SMP memory barrier:
1652
1653 LOAD waiter->list.next;
1654 LOAD waiter->task;
1655 smp_mb();
1656 STORE waiter->task;
1657 CALL wakeup
1658 RELEASE task
1659
1660In this case, the barrier makes a guarantee that all memory accesses before the
1661barrier will appear to happen before all the memory accesses after the barrier
1662with respect to the other CPUs on the system. It does _not_ guarantee that all
1663the memory accesses before the barrier will be complete by the time the barrier
1664instruction itself is complete.
1665
1666On a UP system - where this wouldn't be a problem - the smp_mb() is just a
1667compiler barrier, thus making sure the compiler emits the instructions in the
1668right order without actually intervening in the CPU. Since there's only one
1669CPU, that CPU's dependency ordering logic will take care of everything else.
1670
1671
1672ATOMIC OPERATIONS
1673-----------------
1674
1675Whilst they are technically interprocessor interaction considerations, atomic
1676operations are noted specially as some of them imply full memory barriers and
1677some don't, but they're very heavily relied on as a group throughout the
1678kernel.
1679
1680Any atomic operation that modifies some state in memory and returns information
1681about the state (old or new) implies an SMP-conditional general memory barrier
1682(smp_mb()) on each side of the actual operation (with the exception of
1683explicit lock operations, described later). These include:
1684
1685 xchg();
1686 cmpxchg();
1687 atomic_cmpxchg();
1688 atomic_inc_return();
1689 atomic_dec_return();
1690 atomic_add_return();
1691 atomic_sub_return();
1692 atomic_inc_and_test();
1693 atomic_dec_and_test();
1694 atomic_sub_and_test();
1695 atomic_add_negative();
1696 atomic_add_unless(); /* when succeeds (returns 1) */
1697 test_and_set_bit();
1698 test_and_clear_bit();
1699 test_and_change_bit();
1700
1701These are used for such things as implementing LOCK-class and UNLOCK-class
1702operations and adjusting reference counters towards object destruction, and as
1703such the implicit memory barrier effects are necessary.
1704
1705
1706The following operations are potential problems as they do _not_ imply memory
1707barriers, but might be used for implementing such things as UNLOCK-class
1708operations:
1709
1710 atomic_set();
1711 set_bit();
1712 clear_bit();
1713 change_bit();
1714
1715With these the appropriate explicit memory barrier should be used if necessary
1716(smp_mb__before_clear_bit() for instance).
1717
1718
1719The following also do _not_ imply memory barriers, and so may require explicit
1720memory barriers under some circumstances (smp_mb__before_atomic_dec() for
1721instance):
1722
1723 atomic_add();
1724 atomic_sub();
1725 atomic_inc();
1726 atomic_dec();
1727
1728If they're used for statistics generation, then they probably don't need memory
1729barriers, unless there's a coupling between statistical data.
1730
1731If they're used for reference counting on an object to control its lifetime,
1732they probably don't need memory barriers because either the reference count
1733will be adjusted inside a locked section, or the caller will already hold
1734sufficient references to make the lock, and thus a memory barrier unnecessary.
1735
1736If they're used for constructing a lock of some description, then they probably
1737do need memory barriers as a lock primitive generally has to do things in a
1738specific order.
1739
1740Basically, each usage case has to be carefully considered as to whether memory
1741barriers are needed or not.
1742
1743The following operations are special locking primitives:
1744
1745 test_and_set_bit_lock();
1746 clear_bit_unlock();
1747 __clear_bit_unlock();
1748
1749These implement LOCK-class and UNLOCK-class operations. These should be used in
1750preference to other operations when implementing locking primitives, because
1751their implementations can be optimised on many architectures.
1752
1753[!] Note that special memory barrier primitives are available for these
1754situations because on some CPUs the atomic instructions used imply full memory
1755barriers, and so barrier instructions are superfluous in conjunction with them,
1756and in such cases the special barrier primitives will be no-ops.
1757
1758See Documentation/atomic_ops.txt for more information.
1759
1760
1761ACCESSING DEVICES
1762-----------------
1763
1764Many devices can be memory mapped, and so appear to the CPU as if they're just
1765a set of memory locations. To control such a device, the driver usually has to
1766make the right memory accesses in exactly the right order.
1767
1768However, having a clever CPU or a clever compiler creates a potential problem
1769in that the carefully sequenced accesses in the driver code won't reach the
1770device in the requisite order if the CPU or the compiler thinks it is more
1771efficient to reorder, combine or merge accesses - something that would cause
1772the device to malfunction.
1773
1774Inside of the Linux kernel, I/O should be done through the appropriate accessor
1775routines - such as inb() or writel() - which know how to make such accesses
1776appropriately sequential. Whilst this, for the most part, renders the explicit
1777use of memory barriers unnecessary, there are a couple of situations where they
1778might be needed:
1779
1780 (1) On some systems, I/O stores are not strongly ordered across all CPUs, and
1781 so for _all_ general drivers locks should be used and mmiowb() must be
1782 issued prior to unlocking the critical section.
1783
1784 (2) If the accessor functions are used to refer to an I/O memory window with
1785 relaxed memory access properties, then _mandatory_ memory barriers are
1786 required to enforce ordering.
1787
1788See Documentation/DocBook/deviceiobook.tmpl for more information.
1789
1790
1791INTERRUPTS
1792----------
1793
1794A driver may be interrupted by its own interrupt service routine, and thus the
1795two parts of the driver may interfere with each other's attempts to control or
1796access the device.
1797
1798This may be alleviated - at least in part - by disabling local interrupts (a
1799form of locking), such that the critical operations are all contained within
1800the interrupt-disabled section in the driver. Whilst the driver's interrupt
1801routine is executing, the driver's core may not run on the same CPU, and its
1802interrupt is not permitted to happen again until the current interrupt has been
1803handled, thus the interrupt handler does not need to lock against that.
1804
1805However, consider a driver that was talking to an ethernet card that sports an
1806address register and a data register. If that driver's core talks to the card
1807under interrupt-disablement and then the driver's interrupt handler is invoked:
1808
1809 LOCAL IRQ DISABLE
1810 writew(ADDR, 3);
1811 writew(DATA, y);
1812 LOCAL IRQ ENABLE
1813 <interrupt>
1814 writew(ADDR, 4);
1815 q = readw(DATA);
1816 </interrupt>
1817
1818The store to the data register might happen after the second store to the
1819address register if ordering rules are sufficiently relaxed:
1820
1821 STORE *ADDR = 3, STORE *ADDR = 4, STORE *DATA = y, q = LOAD *DATA
1822
1823
1824If ordering rules are relaxed, it must be assumed that accesses done inside an
1825interrupt disabled section may leak outside of it and may interleave with
1826accesses performed in an interrupt - and vice versa - unless implicit or
1827explicit barriers are used.
1828
1829Normally this won't be a problem because the I/O accesses done inside such
1830sections will include synchronous load operations on strictly ordered I/O
1831registers that form implicit I/O barriers. If this isn't sufficient then an
1832mmiowb() may need to be used explicitly.
1833
1834
1835A similar situation may occur between an interrupt routine and two routines
1836running on separate CPUs that communicate with each other. If such a case is
1837likely, then interrupt-disabling locks should be used to guarantee ordering.
1838
1839
1840==========================
1841KERNEL I/O BARRIER EFFECTS
1842==========================
1843
1844When accessing I/O memory, drivers should use the appropriate accessor
1845functions:
1846
1847 (*) inX(), outX():
1848
1849 These are intended to talk to I/O space rather than memory space, but
1850 that's primarily a CPU-specific concept. The i386 and x86_64 processors do
1851 indeed have special I/O space access cycles and instructions, but many
1852 CPUs don't have such a concept.
1853
1854 The PCI bus, amongst others, defines an I/O space concept which - on such
1855 CPUs as i386 and x86_64 - readily maps to the CPU's concept of I/O
1856 space. However, it may also be mapped as a virtual I/O space in the CPU's
1857 memory map, particularly on those CPUs that don't support alternate I/O
1858 spaces.
1859
1860 Accesses to this space may be fully synchronous (as on i386), but
1861 intermediary bridges (such as the PCI host bridge) may not fully honour
1862 that.
1863
1864 They are guaranteed to be fully ordered with respect to each other.
1865
1866 They are not guaranteed to be fully ordered with respect to other types of
1867 memory and I/O operation.
1868
1869 (*) readX(), writeX():
1870
1871 Whether these are guaranteed to be fully ordered and uncombined with
1872 respect to each other on the issuing CPU depends on the characteristics
1873 defined for the memory window through which they're accessing. On later
1874 i386 architecture machines, for example, this is controlled by way of the
1875 MTRR registers.
1876
1877 Ordinarily, these will be guaranteed to be fully ordered and uncombined,
1878 provided they're not accessing a prefetchable device.
1879
1880 However, intermediary hardware (such as a PCI bridge) may indulge in
1881 deferral if it so wishes; to flush a store, a load from the same location
1882 is preferred[*], but a load from the same device or from configuration
1883 space should suffice for PCI.
1884
1885 [*] NOTE! attempting to load from the same location as was written to may
1886 cause a malfunction - consider the 16550 Rx/Tx serial registers for
1887 example.
1888
1889 Used with prefetchable I/O memory, an mmiowb() barrier may be required to
1890 force stores to be ordered.
1891
1892 Please refer to the PCI specification for more information on interactions
1893 between PCI transactions.
1894
1895 (*) readX_relaxed()
1896
1897 These are similar to readX(), but are not guaranteed to be ordered in any
1898 way. Be aware that there is no I/O read barrier available.
1899
1900 (*) ioreadX(), iowriteX()
1901
1902 These will perform appropriately for the type of access they're actually
1903 doing, be it inX()/outX() or readX()/writeX().
1904
1905
1906========================================
1907ASSUMED MINIMUM EXECUTION ORDERING MODEL
1908========================================
1909
1910It has to be assumed that the conceptual CPU is weakly-ordered but that it will
1911maintain the appearance of program causality with respect to itself. Some CPUs
1912(such as i386 or x86_64) are more constrained than others (such as powerpc or
1913frv), and so the most relaxed case (namely DEC Alpha) must be assumed outside
1914of arch-specific code.
1915
1916This means that it must be considered that the CPU will execute its instruction
1917stream in any order it feels like - or even in parallel - provided that if an
1918instruction in the stream depends on an earlier instruction, then that
1919earlier instruction must be sufficiently complete[*] before the later
1920instruction may proceed; in other words: provided that the appearance of
1921causality is maintained.
1922
1923 [*] Some instructions have more than one effect - such as changing the
1924 condition codes, changing registers or changing memory - and different
1925 instructions may depend on different effects.
1926
1927A CPU may also discard any instruction sequence that winds up having no
1928ultimate effect. For example, if two adjacent instructions both load an
1929immediate value into the same register, the first may be discarded.
1930
1931
1932Similarly, it has to be assumed that compiler might reorder the instruction
1933stream in any way it sees fit, again provided the appearance of causality is
1934maintained.
1935
1936
1937============================
1938THE EFFECTS OF THE CPU CACHE
1939============================
1940
1941The way cached memory operations are perceived across the system is affected to
1942a certain extent by the caches that lie between CPUs and memory, and by the
1943memory coherence system that maintains the consistency of state in the system.
1944
1945As far as the way a CPU interacts with another part of the system through the
1946caches goes, the memory system has to include the CPU's caches, and memory
1947barriers for the most part act at the interface between the CPU and its cache
1948(memory barriers logically act on the dotted line in the following diagram):
1949
1950 <--- CPU ---> : <----------- Memory ----------->
1951 :
1952 +--------+ +--------+ : +--------+ +-----------+
1953 | | | | : | | | | +--------+
1954 | CPU | | Memory | : | CPU | | | | |
1955 | Core |--->| Access |----->| Cache |<-->| | | |
1956 | | | Queue | : | | | |--->| Memory |
1957 | | | | : | | | | | |
1958 +--------+ +--------+ : +--------+ | | | |
1959 : | Cache | +--------+
1960 : | Coherency |
1961 : | Mechanism | +--------+
1962 +--------+ +--------+ : +--------+ | | | |
1963 | | | | : | | | | | |
1964 | CPU | | Memory | : | CPU | | |--->| Device |
1965 | Core |--->| Access |----->| Cache |<-->| | | |
1966 | | | Queue | : | | | | | |
1967 | | | | : | | | | +--------+
1968 +--------+ +--------+ : +--------+ +-----------+
1969 :
1970 :
1971
1972Although any particular load or store may not actually appear outside of the
1973CPU that issued it since it may have been satisfied within the CPU's own cache,
1974it will still appear as if the full memory access had taken place as far as the
1975other CPUs are concerned since the cache coherency mechanisms will migrate the
1976cacheline over to the accessing CPU and propagate the effects upon conflict.
1977
1978The CPU core may execute instructions in any order it deems fit, provided the
1979expected program causality appears to be maintained. Some of the instructions
1980generate load and store operations which then go into the queue of memory
1981accesses to be performed. The core may place these in the queue in any order
1982it wishes, and continue execution until it is forced to wait for an instruction
1983to complete.
1984
1985What memory barriers are concerned with is controlling the order in which
1986accesses cross from the CPU side of things to the memory side of things, and
1987the order in which the effects are perceived to happen by the other observers
1988in the system.
1989
1990[!] Memory barriers are _not_ needed within a given CPU, as CPUs always see
1991their own loads and stores as if they had happened in program order.
1992
1993[!] MMIO or other device accesses may bypass the cache system. This depends on
1994the properties of the memory window through which devices are accessed and/or
1995the use of any special device communication instructions the CPU may have.
1996
1997
1998CACHE COHERENCY
1999---------------
2000
2001Life isn't quite as simple as it may appear above, however: for while the
2002caches are expected to be coherent, there's no guarantee that that coherency
2003will be ordered. This means that whilst changes made on one CPU will
2004eventually become visible on all CPUs, there's no guarantee that they will
2005become apparent in the same order on those other CPUs.
2006
2007
2008Consider dealing with a system that has a pair of CPUs (1 & 2), each of which
2009has a pair of parallel data caches (CPU 1 has A/B, and CPU 2 has C/D):
2010
2011 :
2012 : +--------+
2013 : +---------+ | |
2014 +--------+ : +--->| Cache A |<------->| |
2015 | | : | +---------+ | |
2016 | CPU 1 |<---+ | |
2017 | | : | +---------+ | |
2018 +--------+ : +--->| Cache B |<------->| |
2019 : +---------+ | |
2020 : | Memory |
2021 : +---------+ | System |
2022 +--------+ : +--->| Cache C |<------->| |
2023 | | : | +---------+ | |
2024 | CPU 2 |<---+ | |
2025 | | : | +---------+ | |
2026 +--------+ : +--->| Cache D |<------->| |
2027 : +---------+ | |
2028 : +--------+
2029 :
2030
2031Imagine the system has the following properties:
2032
2033 (*) an odd-numbered cache line may be in cache A, cache C or it may still be
2034 resident in memory;
2035
2036 (*) an even-numbered cache line may be in cache B, cache D or it may still be
2037 resident in memory;
2038
2039 (*) whilst the CPU core is interrogating one cache, the other cache may be
2040 making use of the bus to access the rest of the system - perhaps to
2041 displace a dirty cacheline or to do a speculative load;
2042
2043 (*) each cache has a queue of operations that need to be applied to that cache
2044 to maintain coherency with the rest of the system;
2045
2046 (*) the coherency queue is not flushed by normal loads to lines already
2047 present in the cache, even though the contents of the queue may
2048 potentially affect those loads.
2049
2050Imagine, then, that two writes are made on the first CPU, with a write barrier
2051between them to guarantee that they will appear to reach that CPU's caches in
2052the requisite order:
2053
2054 CPU 1 CPU 2 COMMENT
2055 =============== =============== =======================================
2056 u == 0, v == 1 and p == &u, q == &u
2057 v = 2;
2058 smp_wmb(); Make sure change to v is visible before
2059 change to p
2060 <A:modify v=2> v is now in cache A exclusively
2061 p = &v;
2062 <B:modify p=&v> p is now in cache B exclusively
2063
2064The write memory barrier forces the other CPUs in the system to perceive that
2065the local CPU's caches have apparently been updated in the correct order. But
2066now imagine that the second CPU wants to read those values:
2067
2068 CPU 1 CPU 2 COMMENT
2069 =============== =============== =======================================
2070 ...
2071 q = p;
2072 x = *q;
2073
2074The above pair of reads may then fail to happen in the expected order, as the
2075cacheline holding p may get updated in one of the second CPU's caches whilst
2076the update to the cacheline holding v is delayed in the other of the second
2077CPU's caches by some other cache event:
2078
2079 CPU 1 CPU 2 COMMENT
2080 =============== =============== =======================================
2081 u == 0, v == 1 and p == &u, q == &u
2082 v = 2;
2083 smp_wmb();
2084 <A:modify v=2> <C:busy>
2085 <C:queue v=2>
2086 p = &v; q = p;
2087 <D:request p>
2088 <B:modify p=&v> <D:commit p=&v>
2089 <D:read p>
2090 x = *q;
2091 <C:read *q> Reads from v before v updated in cache
2092 <C:unbusy>
2093 <C:commit v=2>
2094
2095Basically, whilst both cachelines will be updated on CPU 2 eventually, there's
2096no guarantee that, without intervention, the order of update will be the same
2097as that committed on CPU 1.
2098
2099
2100To intervene, we need to interpolate a data dependency barrier or a read
2101barrier between the loads. This will force the cache to commit its coherency
2102queue before processing any further requests:
2103
2104 CPU 1 CPU 2 COMMENT
2105 =============== =============== =======================================
2106 u == 0, v == 1 and p == &u, q == &u
2107 v = 2;
2108 smp_wmb();
2109 <A:modify v=2> <C:busy>
2110 <C:queue v=2>
2111 p = &v; q = p;
2112 <D:request p>
2113 <B:modify p=&v> <D:commit p=&v>
2114 <D:read p>
2115 smp_read_barrier_depends()
2116 <C:unbusy>
2117 <C:commit v=2>
2118 x = *q;
2119 <C:read *q> Reads from v after v updated in cache
2120
2121
2122This sort of problem can be encountered on DEC Alpha processors as they have a
2123split cache that improves performance by making better use of the data bus.
2124Whilst most CPUs do imply a data dependency barrier on the read when a memory
2125access depends on a read, not all do, so it may not be relied on.
2126
2127Other CPUs may also have split caches, but must coordinate between the various
2128cachelets for normal memory accesses. The semantics of the Alpha removes the
2129need for coordination in the absence of memory barriers.
2130
2131
2132CACHE COHERENCY VS DMA
2133----------------------
2134
2135Not all systems maintain cache coherency with respect to devices doing DMA. In
2136such cases, a device attempting DMA may obtain stale data from RAM because
2137dirty cache lines may be resident in the caches of various CPUs, and may not
2138have been written back to RAM yet. To deal with this, the appropriate part of
2139the kernel must flush the overlapping bits of cache on each CPU (and maybe
2140invalidate them as well).
2141
2142In addition, the data DMA'd to RAM by a device may be overwritten by dirty
2143cache lines being written back to RAM from a CPU's cache after the device has
2144installed its own data, or cache lines present in the CPU's cache may simply
2145obscure the fact that RAM has been updated, until at such time as the cacheline
2146is discarded from the CPU's cache and reloaded. To deal with this, the
2147appropriate part of the kernel must invalidate the overlapping bits of the
2148cache on each CPU.
2149
2150See Documentation/cachetlb.txt for more information on cache management.
2151
2152
2153CACHE COHERENCY VS MMIO
2154-----------------------
2155
2156Memory mapped I/O usually takes place through memory locations that are part of
2157a window in the CPU's memory space that has different properties assigned than
2158the usual RAM directed window.
2159
2160Amongst these properties is usually the fact that such accesses bypass the
2161caching entirely and go directly to the device buses. This means MMIO accesses
2162may, in effect, overtake accesses to cached memory that were emitted earlier.
2163A memory barrier isn't sufficient in such a case, but rather the cache must be
2164flushed between the cached memory write and the MMIO access if the two are in
2165any way dependent.
2166
2167
2168=========================
2169THE THINGS CPUS GET UP TO
2170=========================
2171
2172A programmer might take it for granted that the CPU will perform memory
2173operations in exactly the order specified, so that if the CPU is, for example,
2174given the following piece of code to execute:
2175
2176 a = *A;
2177 *B = b;
2178 c = *C;
2179 d = *D;
2180 *E = e;
2181
2182they would then expect that the CPU will complete the memory operation for each
2183instruction before moving on to the next one, leading to a definite sequence of
2184operations as seen by external observers in the system:
2185
2186 LOAD *A, STORE *B, LOAD *C, LOAD *D, STORE *E.
2187
2188
2189Reality is, of course, much messier. With many CPUs and compilers, the above
2190assumption doesn't hold because:
2191
2192 (*) loads are more likely to need to be completed immediately to permit
2193 execution progress, whereas stores can often be deferred without a
2194 problem;
2195
2196 (*) loads may be done speculatively, and the result discarded should it prove
2197 to have been unnecessary;
2198
2199 (*) loads may be done speculatively, leading to the result having been fetched
2200 at the wrong time in the expected sequence of events;
2201
2202 (*) the order of the memory accesses may be rearranged to promote better use
2203 of the CPU buses and caches;
2204
2205 (*) loads and stores may be combined to improve performance when talking to
2206 memory or I/O hardware that can do batched accesses of adjacent locations,
2207 thus cutting down on transaction setup costs (memory and PCI devices may
2208 both be able to do this); and
2209
2210 (*) the CPU's data cache may affect the ordering, and whilst cache-coherency
2211 mechanisms may alleviate this - once the store has actually hit the cache
2212 - there's no guarantee that the coherency management will be propagated in
2213 order to other CPUs.
2214
2215So what another CPU, say, might actually observe from the above piece of code
2216is:
2217
2218 LOAD *A, ..., LOAD {*C,*D}, STORE *E, STORE *B
2219
2220 (Where "LOAD {*C,*D}" is a combined load)
2221
2222
2223However, it is guaranteed that a CPU will be self-consistent: it will see its
2224_own_ accesses appear to be correctly ordered, without the need for a memory
2225barrier. For instance with the following code:
2226
2227 U = *A;
2228 *A = V;
2229 *A = W;
2230 X = *A;
2231 *A = Y;
2232 Z = *A;
2233
2234and assuming no intervention by an external influence, it can be assumed that
2235the final result will appear to be:
2236
2237 U == the original value of *A
2238 X == W
2239 Z == Y
2240 *A == Y
2241
2242The code above may cause the CPU to generate the full sequence of memory
2243accesses:
2244
2245 U=LOAD *A, STORE *A=V, STORE *A=W, X=LOAD *A, STORE *A=Y, Z=LOAD *A
2246
2247in that order, but, without intervention, the sequence may have almost any
2248combination of elements combined or discarded, provided the program's view of
2249the world remains consistent.
2250
2251The compiler may also combine, discard or defer elements of the sequence before
2252the CPU even sees them.
2253
2254For instance:
2255
2256 *A = V;
2257 *A = W;
2258
2259may be reduced to:
2260
2261 *A = W;
2262
2263since, without a write barrier, it can be assumed that the effect of the
2264storage of V to *A is lost. Similarly:
2265
2266 *A = Y;
2267 Z = *A;
2268
2269may, without a memory barrier, be reduced to:
2270
2271 *A = Y;
2272 Z = Y;
2273
2274and the LOAD operation never appear outside of the CPU.
2275
2276
2277AND THEN THERE'S THE ALPHA
2278--------------------------
2279
2280The DEC Alpha CPU is one of the most relaxed CPUs there is. Not only that,
2281some versions of the Alpha CPU have a split data cache, permitting them to have
2282two semantically-related cache lines updated at separate times. This is where
2283the data dependency barrier really becomes necessary as this synchronises both
2284caches with the memory coherence system, thus making it seem like pointer
2285changes vs new data occur in the right order.
2286
2287The Alpha defines the Linux kernel's memory barrier model.
2288
2289See the subsection on "Cache Coherency" above.
2290
2291
2292============
2293EXAMPLE USES
2294============
2295
2296CIRCULAR BUFFERS
2297----------------
2298
2299Memory barriers can be used to implement circular buffering without the need
2300of a lock to serialise the producer with the consumer. See:
2301
2302 Documentation/circular-buffers.txt
2303
2304for details.
2305
2306
2307==========
2308REFERENCES
2309==========
2310
2311Alpha AXP Architecture Reference Manual, Second Edition (Sites & Witek,
2312Digital Press)
2313 Chapter 5.2: Physical Address Space Characteristics
2314 Chapter 5.4: Caches and Write Buffers
2315 Chapter 5.5: Data Sharing
2316 Chapter 5.6: Read/Write Ordering
2317
2318AMD64 Architecture Programmer's Manual Volume 2: System Programming
2319 Chapter 7.1: Memory-Access Ordering
2320 Chapter 7.4: Buffering and Combining Memory Writes
2321
2322IA-32 Intel Architecture Software Developer's Manual, Volume 3:
2323System Programming Guide
2324 Chapter 7.1: Locked Atomic Operations
2325 Chapter 7.2: Memory Ordering
2326 Chapter 7.4: Serializing Instructions
2327
2328The SPARC Architecture Manual, Version 9
2329 Chapter 8: Memory Models
2330 Appendix D: Formal Specification of the Memory Models
2331 Appendix J: Programming with the Memory Models
2332
2333UltraSPARC Programmer Reference Manual
2334 Chapter 5: Memory Accesses and Cacheability
2335 Chapter 15: Sparc-V9 Memory Models
2336
2337UltraSPARC III Cu User's Manual
2338 Chapter 9: Memory Models
2339
2340UltraSPARC IIIi Processor User's Manual
2341 Chapter 8: Memory Models
2342
2343UltraSPARC Architecture 2005
2344 Chapter 9: Memory
2345 Appendix D: Formal Specifications of the Memory Models
2346
2347UltraSPARC T1 Supplement to the UltraSPARC Architecture 2005
2348 Chapter 8: Memory Models
2349 Appendix F: Caches and Cache Coherency
2350
2351Solaris Internals, Core Kernel Architecture, p63-68:
2352 Chapter 3.3: Hardware Considerations for Locks and
2353 Synchronization
2354
2355Unix Systems for Modern Architectures, Symmetric Multiprocessing and Caching
2356for Kernel Programmers:
2357 Chapter 13: Other Memory Models
2358
2359Intel Itanium Architecture Software Developer's Manual: Volume 1:
2360 Section 2.6: Speculation
2361 Section 4.4: Memory Access