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1// SPDX-License-Identifier: GPL-2.0
2//
3// ak4642.c -- AK4642/AK4643 ALSA Soc Audio driver
4//
5// Copyright (C) 2009 Renesas Solutions Corp.
6// Kuninori Morimoto <morimoto.kuninori@renesas.com>
7//
8// Based on wm8731.c by Richard Purdie
9// Based on ak4535.c by Richard Purdie
10// Based on wm8753.c by Liam Girdwood
11
12/* ** CAUTION **
13 *
14 * This is very simple driver.
15 * It can use headphone output / stereo input only
16 *
17 * AK4642 is tested.
18 * AK4643 is tested.
19 * AK4648 is tested.
20 */
21
22#include <linux/clk.h>
23#include <linux/clk-provider.h>
24#include <linux/delay.h>
25#include <linux/i2c.h>
26#include <linux/slab.h>
27#include <linux/of.h>
28#include <linux/module.h>
29#include <linux/regmap.h>
30#include <sound/soc.h>
31#include <sound/initval.h>
32#include <sound/tlv.h>
33
34#define PW_MGMT1 0x00
35#define PW_MGMT2 0x01
36#define SG_SL1 0x02
37#define SG_SL2 0x03
38#define MD_CTL1 0x04
39#define MD_CTL2 0x05
40#define TIMER 0x06
41#define ALC_CTL1 0x07
42#define ALC_CTL2 0x08
43#define L_IVC 0x09
44#define L_DVC 0x0a
45#define ALC_CTL3 0x0b
46#define R_IVC 0x0c
47#define R_DVC 0x0d
48#define MD_CTL3 0x0e
49#define MD_CTL4 0x0f
50#define PW_MGMT3 0x10
51#define DF_S 0x11
52#define FIL3_0 0x12
53#define FIL3_1 0x13
54#define FIL3_2 0x14
55#define FIL3_3 0x15
56#define EQ_0 0x16
57#define EQ_1 0x17
58#define EQ_2 0x18
59#define EQ_3 0x19
60#define EQ_4 0x1a
61#define EQ_5 0x1b
62#define FIL1_0 0x1c
63#define FIL1_1 0x1d
64#define FIL1_2 0x1e
65#define FIL1_3 0x1f /* The maximum valid register for ak4642 */
66#define PW_MGMT4 0x20
67#define MD_CTL5 0x21
68#define LO_MS 0x22
69#define HP_MS 0x23
70#define SPK_MS 0x24 /* The maximum valid register for ak4643 */
71#define EQ_FBEQAB 0x25
72#define EQ_FBEQCD 0x26
73#define EQ_FBEQE 0x27 /* The maximum valid register for ak4648 */
74
75/* PW_MGMT1*/
76#define PMVCM (1 << 6) /* VCOM Power Management */
77#define PMMIN (1 << 5) /* MIN Input Power Management */
78#define PMDAC (1 << 2) /* DAC Power Management */
79#define PMADL (1 << 0) /* MIC Amp Lch and ADC Lch Power Management */
80
81/* PW_MGMT2 */
82#define HPMTN (1 << 6)
83#define PMHPL (1 << 5)
84#define PMHPR (1 << 4)
85#define MS (1 << 3) /* master/slave select */
86#define MCKO (1 << 1)
87#define PMPLL (1 << 0)
88
89#define PMHP_MASK (PMHPL | PMHPR)
90#define PMHP PMHP_MASK
91
92/* PW_MGMT3 */
93#define PMADR (1 << 0) /* MIC L / ADC R Power Management */
94
95/* SG_SL1 */
96#define MINS (1 << 6) /* Switch from MIN to Speaker */
97#define DACL (1 << 4) /* Switch from DAC to Stereo or Receiver */
98#define PMMP (1 << 2) /* MPWR pin Power Management */
99#define MGAIN0 (1 << 0) /* MIC amp gain*/
100
101/* SG_SL2 */
102#define LOPS (1 << 6) /* Stero Line-out Power Save Mode */
103
104/* TIMER */
105#define ZTM(param) ((param & 0x3) << 4) /* ALC Zero Crossing TimeOut */
106#define WTM(param) (((param & 0x4) << 4) | ((param & 0x3) << 2))
107
108/* ALC_CTL1 */
109#define ALC (1 << 5) /* ALC Enable */
110#define LMTH0 (1 << 0) /* ALC Limiter / Recovery Level */
111
112/* MD_CTL1 */
113#define PLL3 (1 << 7)
114#define PLL2 (1 << 6)
115#define PLL1 (1 << 5)
116#define PLL0 (1 << 4)
117#define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0)
118
119#define BCKO_MASK (1 << 3)
120#define BCKO_64 BCKO_MASK
121
122#define DIF_MASK (3 << 0)
123#define DSP (0 << 0)
124#define RIGHT_J (1 << 0)
125#define LEFT_J (2 << 0)
126#define I2S (3 << 0)
127
128/* MD_CTL2 */
129#define FSs(val) (((val & 0x7) << 0) | ((val & 0x8) << 2))
130#define PSs(val) ((val & 0x3) << 6)
131
132/* MD_CTL3 */
133#define BST1 (1 << 3)
134
135/* MD_CTL4 */
136#define DACH (1 << 0)
137
138struct ak4642_drvdata {
139 const struct regmap_config *regmap_config;
140 int extended_frequencies;
141};
142
143struct ak4642_priv {
144 const struct ak4642_drvdata *drvdata;
145 struct clk *mcko;
146};
147
148/*
149 * Playback Volume (table 39)
150 *
151 * max : 0x00 : +12.0 dB
152 * ( 0.5 dB step )
153 * min : 0xFE : -115.0 dB
154 * mute: 0xFF
155 */
156static const DECLARE_TLV_DB_SCALE(out_tlv, -11550, 50, 1);
157
158static const struct snd_kcontrol_new ak4642_snd_controls[] = {
159
160 SOC_DOUBLE_R_TLV("Digital Playback Volume", L_DVC, R_DVC,
161 0, 0xFF, 1, out_tlv),
162 SOC_SINGLE("ALC Capture Switch", ALC_CTL1, 5, 1, 0),
163 SOC_SINGLE("ALC Capture ZC Switch", ALC_CTL1, 4, 1, 1),
164};
165
166static const struct snd_kcontrol_new ak4642_headphone_control =
167 SOC_DAPM_SINGLE("Switch", PW_MGMT2, 6, 1, 0);
168
169static const struct snd_kcontrol_new ak4642_lout_mixer_controls[] = {
170 SOC_DAPM_SINGLE("DACL", SG_SL1, 4, 1, 0),
171};
172
173/* event handlers */
174static int ak4642_lout_event(struct snd_soc_dapm_widget *w,
175 struct snd_kcontrol *kcontrol, int event)
176{
177 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
178
179 switch (event) {
180 case SND_SOC_DAPM_PRE_PMD:
181 case SND_SOC_DAPM_PRE_PMU:
182 /* Power save mode ON */
183 snd_soc_component_update_bits(component, SG_SL2, LOPS, LOPS);
184 break;
185 case SND_SOC_DAPM_POST_PMU:
186 case SND_SOC_DAPM_POST_PMD:
187 /* Power save mode OFF */
188 msleep(300);
189 snd_soc_component_update_bits(component, SG_SL2, LOPS, 0);
190 break;
191 }
192
193 return 0;
194}
195
196static const struct snd_soc_dapm_widget ak4642_dapm_widgets[] = {
197
198 /* Outputs */
199 SND_SOC_DAPM_OUTPUT("HPOUTL"),
200 SND_SOC_DAPM_OUTPUT("HPOUTR"),
201 SND_SOC_DAPM_OUTPUT("LINEOUT"),
202
203 SND_SOC_DAPM_PGA("HPL Out", PW_MGMT2, 5, 0, NULL, 0),
204 SND_SOC_DAPM_PGA("HPR Out", PW_MGMT2, 4, 0, NULL, 0),
205 SND_SOC_DAPM_SWITCH("Headphone Enable", SND_SOC_NOPM, 0, 0,
206 &ak4642_headphone_control),
207
208 SND_SOC_DAPM_PGA("DACH", MD_CTL4, 0, 0, NULL, 0),
209
210 SND_SOC_DAPM_MIXER_E("LINEOUT Mixer", PW_MGMT1, 3, 0,
211 &ak4642_lout_mixer_controls[0],
212 ARRAY_SIZE(ak4642_lout_mixer_controls),
213 ak4642_lout_event,
214 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
215 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
216
217 /* DAC */
218 SND_SOC_DAPM_DAC("DAC", NULL, PW_MGMT1, 2, 0),
219};
220
221static const struct snd_soc_dapm_route ak4642_intercon[] = {
222
223 /* Outputs */
224 {"HPOUTL", NULL, "HPL Out"},
225 {"HPOUTR", NULL, "HPR Out"},
226 {"LINEOUT", NULL, "LINEOUT Mixer"},
227
228 {"HPL Out", NULL, "Headphone Enable"},
229 {"HPR Out", NULL, "Headphone Enable"},
230
231 {"Headphone Enable", "Switch", "DACH"},
232
233 {"DACH", NULL, "DAC"},
234
235 {"LINEOUT Mixer", "DACL", "DAC"},
236
237 { "DAC", NULL, "Playback" },
238};
239
240/*
241 * ak4642 register cache
242 */
243static const struct reg_default ak4643_reg[] = {
244 { 0, 0x00 }, { 1, 0x00 }, { 2, 0x01 }, { 3, 0x00 },
245 { 4, 0x02 }, { 5, 0x00 }, { 6, 0x00 }, { 7, 0x00 },
246 { 8, 0xe1 }, { 9, 0xe1 }, { 10, 0x18 }, { 11, 0x00 },
247 { 12, 0xe1 }, { 13, 0x18 }, { 14, 0x11 }, { 15, 0x08 },
248 { 16, 0x00 }, { 17, 0x00 }, { 18, 0x00 }, { 19, 0x00 },
249 { 20, 0x00 }, { 21, 0x00 }, { 22, 0x00 }, { 23, 0x00 },
250 { 24, 0x00 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0x00 },
251 { 28, 0x00 }, { 29, 0x00 }, { 30, 0x00 }, { 31, 0x00 },
252 { 32, 0x00 }, { 33, 0x00 }, { 34, 0x00 }, { 35, 0x00 },
253 { 36, 0x00 },
254};
255
256/* The default settings for 0x0 ~ 0x1f registers are the same for ak4642
257 and ak4643. So we reuse the ak4643 reg_default for ak4642.
258 The valid registers for ak4642 are 0x0 ~ 0x1f which is a subset of ak4643,
259 so define NUM_AK4642_REG_DEFAULTS for ak4642.
260*/
261#define ak4642_reg ak4643_reg
262#define NUM_AK4642_REG_DEFAULTS (FIL1_3 + 1)
263
264static const struct reg_default ak4648_reg[] = {
265 { 0, 0x00 }, { 1, 0x00 }, { 2, 0x01 }, { 3, 0x00 },
266 { 4, 0x02 }, { 5, 0x00 }, { 6, 0x00 }, { 7, 0x00 },
267 { 8, 0xe1 }, { 9, 0xe1 }, { 10, 0x18 }, { 11, 0x00 },
268 { 12, 0xe1 }, { 13, 0x18 }, { 14, 0x11 }, { 15, 0xb8 },
269 { 16, 0x00 }, { 17, 0x00 }, { 18, 0x00 }, { 19, 0x00 },
270 { 20, 0x00 }, { 21, 0x00 }, { 22, 0x00 }, { 23, 0x00 },
271 { 24, 0x00 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0x00 },
272 { 28, 0x00 }, { 29, 0x00 }, { 30, 0x00 }, { 31, 0x00 },
273 { 32, 0x00 }, { 33, 0x00 }, { 34, 0x00 }, { 35, 0x00 },
274 { 36, 0x00 }, { 37, 0x88 }, { 38, 0x88 }, { 39, 0x08 },
275};
276
277static int ak4642_dai_startup(struct snd_pcm_substream *substream,
278 struct snd_soc_dai *dai)
279{
280 int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
281 struct snd_soc_component *component = dai->component;
282
283 if (is_play) {
284 /*
285 * start headphone output
286 *
287 * PLL, Master Mode
288 * Audio I/F Format :MSB justified (ADC & DAC)
289 * Bass Boost Level : Middle
290 *
291 * This operation came from example code of
292 * "ASAHI KASEI AK4642" (japanese) manual p97.
293 */
294 snd_soc_component_write(component, L_IVC, 0x91); /* volume */
295 snd_soc_component_write(component, R_IVC, 0x91); /* volume */
296 } else {
297 /*
298 * start stereo input
299 *
300 * PLL Master Mode
301 * Audio I/F Format:MSB justified (ADC & DAC)
302 * Pre MIC AMP:+20dB
303 * MIC Power On
304 * ALC setting:Refer to Table 35
305 * ALC bit=“1”
306 *
307 * This operation came from example code of
308 * "ASAHI KASEI AK4642" (japanese) manual p94.
309 */
310 snd_soc_component_update_bits(component, SG_SL1, PMMP | MGAIN0, PMMP | MGAIN0);
311 snd_soc_component_write(component, TIMER, ZTM(0x3) | WTM(0x3));
312 snd_soc_component_write(component, ALC_CTL1, ALC | LMTH0);
313 snd_soc_component_update_bits(component, PW_MGMT1, PMADL, PMADL);
314 snd_soc_component_update_bits(component, PW_MGMT3, PMADR, PMADR);
315 }
316
317 return 0;
318}
319
320static void ak4642_dai_shutdown(struct snd_pcm_substream *substream,
321 struct snd_soc_dai *dai)
322{
323 int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
324 struct snd_soc_component *component = dai->component;
325
326 if (is_play) {
327 } else {
328 /* stop stereo input */
329 snd_soc_component_update_bits(component, PW_MGMT1, PMADL, 0);
330 snd_soc_component_update_bits(component, PW_MGMT3, PMADR, 0);
331 snd_soc_component_update_bits(component, ALC_CTL1, ALC, 0);
332 }
333}
334
335static int ak4642_dai_set_sysclk(struct snd_soc_dai *codec_dai,
336 int clk_id, unsigned int freq, int dir)
337{
338 struct snd_soc_component *component = codec_dai->component;
339 struct ak4642_priv *priv = snd_soc_component_get_drvdata(component);
340 u8 pll;
341 int extended_freq = 0;
342
343 switch (freq) {
344 case 11289600:
345 pll = PLL2;
346 break;
347 case 12288000:
348 pll = PLL2 | PLL0;
349 break;
350 case 12000000:
351 pll = PLL2 | PLL1;
352 break;
353 case 24000000:
354 pll = PLL2 | PLL1 | PLL0;
355 break;
356 case 13500000:
357 pll = PLL3 | PLL2;
358 break;
359 case 27000000:
360 pll = PLL3 | PLL2 | PLL0;
361 break;
362 case 19200000:
363 pll = PLL3;
364 extended_freq = 1;
365 break;
366 case 13000000:
367 pll = PLL3 | PLL2 | PLL1;
368 extended_freq = 1;
369 break;
370 case 26000000:
371 pll = PLL3 | PLL2 | PLL1 | PLL0;
372 extended_freq = 1;
373 break;
374 default:
375 return -EINVAL;
376 }
377
378 if (extended_freq && !priv->drvdata->extended_frequencies)
379 return -EINVAL;
380
381 snd_soc_component_update_bits(component, MD_CTL1, PLL_MASK, pll);
382
383 return 0;
384}
385
386static int ak4642_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
387{
388 struct snd_soc_component *component = dai->component;
389 u8 data;
390 u8 bcko;
391
392 data = MCKO | PMPLL; /* use MCKO */
393 bcko = 0;
394
395 /* set clocking for audio interface */
396 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
397 case SND_SOC_DAIFMT_CBP_CFP:
398 data |= MS;
399 bcko = BCKO_64;
400 break;
401 case SND_SOC_DAIFMT_CBC_CFC:
402 break;
403 default:
404 return -EINVAL;
405 }
406 snd_soc_component_update_bits(component, PW_MGMT2, MS | MCKO | PMPLL, data);
407 snd_soc_component_update_bits(component, MD_CTL1, BCKO_MASK, bcko);
408
409 /* format type */
410 data = 0;
411 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
412 case SND_SOC_DAIFMT_LEFT_J:
413 data = LEFT_J;
414 break;
415 case SND_SOC_DAIFMT_I2S:
416 data = I2S;
417 break;
418 /* FIXME
419 * Please add RIGHT_J / DSP support here
420 */
421 default:
422 return -EINVAL;
423 }
424 snd_soc_component_update_bits(component, MD_CTL1, DIF_MASK, data);
425
426 return 0;
427}
428
429static int ak4642_set_mcko(struct snd_soc_component *component,
430 u32 frequency)
431{
432 static const u32 fs_list[] = {
433 [0] = 8000,
434 [1] = 12000,
435 [2] = 16000,
436 [3] = 24000,
437 [4] = 7350,
438 [5] = 11025,
439 [6] = 14700,
440 [7] = 22050,
441 [10] = 32000,
442 [11] = 48000,
443 [14] = 29400,
444 [15] = 44100,
445 };
446 static const u32 ps_list[] = {
447 [0] = 256,
448 [1] = 128,
449 [2] = 64,
450 [3] = 32
451 };
452 int ps, fs;
453
454 for (ps = 0; ps < ARRAY_SIZE(ps_list); ps++) {
455 for (fs = 0; fs < ARRAY_SIZE(fs_list); fs++) {
456 if (frequency == ps_list[ps] * fs_list[fs]) {
457 snd_soc_component_write(component, MD_CTL2,
458 PSs(ps) | FSs(fs));
459 return 0;
460 }
461 }
462 }
463
464 return 0;
465}
466
467static int ak4642_dai_hw_params(struct snd_pcm_substream *substream,
468 struct snd_pcm_hw_params *params,
469 struct snd_soc_dai *dai)
470{
471 struct snd_soc_component *component = dai->component;
472 struct ak4642_priv *priv = snd_soc_component_get_drvdata(component);
473 u32 rate = clk_get_rate(priv->mcko);
474
475 if (!rate)
476 rate = params_rate(params) * 256;
477
478 return ak4642_set_mcko(component, rate);
479}
480
481static int ak4642_set_bias_level(struct snd_soc_component *component,
482 enum snd_soc_bias_level level)
483{
484 switch (level) {
485 case SND_SOC_BIAS_OFF:
486 snd_soc_component_write(component, PW_MGMT1, 0x00);
487 break;
488 default:
489 snd_soc_component_update_bits(component, PW_MGMT1, PMVCM, PMVCM);
490 break;
491 }
492
493 return 0;
494}
495
496static const struct snd_soc_dai_ops ak4642_dai_ops = {
497 .startup = ak4642_dai_startup,
498 .shutdown = ak4642_dai_shutdown,
499 .set_sysclk = ak4642_dai_set_sysclk,
500 .set_fmt = ak4642_dai_set_fmt,
501 .hw_params = ak4642_dai_hw_params,
502};
503
504static struct snd_soc_dai_driver ak4642_dai = {
505 .name = "ak4642-hifi",
506 .playback = {
507 .stream_name = "Playback",
508 .channels_min = 2,
509 .channels_max = 2,
510 .rates = SNDRV_PCM_RATE_8000_48000,
511 .formats = SNDRV_PCM_FMTBIT_S16_LE },
512 .capture = {
513 .stream_name = "Capture",
514 .channels_min = 2,
515 .channels_max = 2,
516 .rates = SNDRV_PCM_RATE_8000_48000,
517 .formats = SNDRV_PCM_FMTBIT_S16_LE },
518 .ops = &ak4642_dai_ops,
519 .symmetric_rate = 1,
520};
521
522static int ak4642_suspend(struct snd_soc_component *component)
523{
524 struct regmap *regmap = dev_get_regmap(component->dev, NULL);
525
526 regcache_cache_only(regmap, true);
527 regcache_mark_dirty(regmap);
528 return 0;
529}
530
531static int ak4642_resume(struct snd_soc_component *component)
532{
533 struct regmap *regmap = dev_get_regmap(component->dev, NULL);
534
535 regcache_cache_only(regmap, false);
536 regcache_sync(regmap);
537 return 0;
538}
539static int ak4642_probe(struct snd_soc_component *component)
540{
541 struct ak4642_priv *priv = snd_soc_component_get_drvdata(component);
542
543 if (priv->mcko)
544 ak4642_set_mcko(component, clk_get_rate(priv->mcko));
545
546 return 0;
547}
548
549static const struct snd_soc_component_driver soc_component_dev_ak4642 = {
550 .probe = ak4642_probe,
551 .suspend = ak4642_suspend,
552 .resume = ak4642_resume,
553 .set_bias_level = ak4642_set_bias_level,
554 .controls = ak4642_snd_controls,
555 .num_controls = ARRAY_SIZE(ak4642_snd_controls),
556 .dapm_widgets = ak4642_dapm_widgets,
557 .num_dapm_widgets = ARRAY_SIZE(ak4642_dapm_widgets),
558 .dapm_routes = ak4642_intercon,
559 .num_dapm_routes = ARRAY_SIZE(ak4642_intercon),
560 .idle_bias_on = 1,
561 .endianness = 1,
562};
563
564static const struct regmap_config ak4642_regmap = {
565 .reg_bits = 8,
566 .val_bits = 8,
567 .max_register = FIL1_3,
568 .reg_defaults = ak4642_reg,
569 .num_reg_defaults = NUM_AK4642_REG_DEFAULTS,
570 .cache_type = REGCACHE_RBTREE,
571};
572
573static const struct regmap_config ak4643_regmap = {
574 .reg_bits = 8,
575 .val_bits = 8,
576 .max_register = SPK_MS,
577 .reg_defaults = ak4643_reg,
578 .num_reg_defaults = ARRAY_SIZE(ak4643_reg),
579 .cache_type = REGCACHE_RBTREE,
580};
581
582static const struct regmap_config ak4648_regmap = {
583 .reg_bits = 8,
584 .val_bits = 8,
585 .max_register = EQ_FBEQE,
586 .reg_defaults = ak4648_reg,
587 .num_reg_defaults = ARRAY_SIZE(ak4648_reg),
588 .cache_type = REGCACHE_RBTREE,
589};
590
591static const struct ak4642_drvdata ak4642_drvdata = {
592 .regmap_config = &ak4642_regmap,
593};
594
595static const struct ak4642_drvdata ak4643_drvdata = {
596 .regmap_config = &ak4643_regmap,
597};
598
599static const struct ak4642_drvdata ak4648_drvdata = {
600 .regmap_config = &ak4648_regmap,
601 .extended_frequencies = 1,
602};
603
604#ifdef CONFIG_COMMON_CLK
605static struct clk *ak4642_of_parse_mcko(struct device *dev)
606{
607 struct device_node *np = dev->of_node;
608 struct clk *clk;
609 const char *clk_name = np->name;
610 const char *parent_clk_name = NULL;
611 u32 rate;
612
613 if (of_property_read_u32(np, "clock-frequency", &rate))
614 return NULL;
615
616 if (of_property_read_bool(np, "clocks"))
617 parent_clk_name = of_clk_get_parent_name(np, 0);
618
619 of_property_read_string(np, "clock-output-names", &clk_name);
620
621 clk = clk_register_fixed_rate(dev, clk_name, parent_clk_name, 0, rate);
622 if (!IS_ERR(clk))
623 of_clk_add_provider(np, of_clk_src_simple_get, clk);
624
625 return clk;
626}
627#else
628#define ak4642_of_parse_mcko(d) 0
629#endif
630
631static int ak4642_i2c_probe(struct i2c_client *i2c)
632{
633 struct device *dev = &i2c->dev;
634 const struct ak4642_drvdata *drvdata;
635 struct regmap *regmap;
636 struct ak4642_priv *priv;
637 struct clk *mcko = NULL;
638
639 if (dev_fwnode(dev)) {
640 mcko = ak4642_of_parse_mcko(dev);
641 if (IS_ERR(mcko))
642 mcko = NULL;
643 }
644
645 drvdata = i2c_get_match_data(i2c);
646 if (!drvdata)
647 return dev_err_probe(dev, -EINVAL, "Unknown device type\n");
648
649 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
650 if (!priv)
651 return -ENOMEM;
652
653 priv->drvdata = drvdata;
654 priv->mcko = mcko;
655
656 i2c_set_clientdata(i2c, priv);
657
658 regmap = devm_regmap_init_i2c(i2c, drvdata->regmap_config);
659 if (IS_ERR(regmap))
660 return PTR_ERR(regmap);
661
662 return devm_snd_soc_register_component(dev,
663 &soc_component_dev_ak4642, &ak4642_dai, 1);
664}
665
666static const struct of_device_id ak4642_of_match[] = {
667 { .compatible = "asahi-kasei,ak4642", .data = &ak4642_drvdata},
668 { .compatible = "asahi-kasei,ak4643", .data = &ak4643_drvdata},
669 { .compatible = "asahi-kasei,ak4648", .data = &ak4648_drvdata},
670 {}
671};
672MODULE_DEVICE_TABLE(of, ak4642_of_match);
673
674static const struct i2c_device_id ak4642_i2c_id[] = {
675 { "ak4642", (kernel_ulong_t)&ak4642_drvdata },
676 { "ak4643", (kernel_ulong_t)&ak4643_drvdata },
677 { "ak4648", (kernel_ulong_t)&ak4648_drvdata },
678 {}
679};
680MODULE_DEVICE_TABLE(i2c, ak4642_i2c_id);
681
682static struct i2c_driver ak4642_i2c_driver = {
683 .driver = {
684 .name = "ak4642-codec",
685 .of_match_table = ak4642_of_match,
686 },
687 .probe = ak4642_i2c_probe,
688 .id_table = ak4642_i2c_id,
689};
690
691module_i2c_driver(ak4642_i2c_driver);
692
693MODULE_DESCRIPTION("Soc AK4642 driver");
694MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
695MODULE_LICENSE("GPL v2");
1/*
2 * ak4642.c -- AK4642/AK4643 ALSA Soc Audio driver
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on wm8731.c by Richard Purdie
8 * Based on ak4535.c by Richard Purdie
9 * Based on wm8753.c by Liam Girdwood
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16/* ** CAUTION **
17 *
18 * This is very simple driver.
19 * It can use headphone output / stereo input only
20 *
21 * AK4642 is not tested.
22 * AK4643 is tested.
23 */
24
25#include <linux/delay.h>
26#include <linux/i2c.h>
27#include <linux/platform_device.h>
28#include <linux/slab.h>
29#include <sound/soc.h>
30#include <sound/initval.h>
31#include <sound/tlv.h>
32
33#define AK4642_VERSION "0.0.1"
34
35#define PW_MGMT1 0x00
36#define PW_MGMT2 0x01
37#define SG_SL1 0x02
38#define SG_SL2 0x03
39#define MD_CTL1 0x04
40#define MD_CTL2 0x05
41#define TIMER 0x06
42#define ALC_CTL1 0x07
43#define ALC_CTL2 0x08
44#define L_IVC 0x09
45#define L_DVC 0x0a
46#define ALC_CTL3 0x0b
47#define R_IVC 0x0c
48#define R_DVC 0x0d
49#define MD_CTL3 0x0e
50#define MD_CTL4 0x0f
51#define PW_MGMT3 0x10
52#define DF_S 0x11
53#define FIL3_0 0x12
54#define FIL3_1 0x13
55#define FIL3_2 0x14
56#define FIL3_3 0x15
57#define EQ_0 0x16
58#define EQ_1 0x17
59#define EQ_2 0x18
60#define EQ_3 0x19
61#define EQ_4 0x1a
62#define EQ_5 0x1b
63#define FIL1_0 0x1c
64#define FIL1_1 0x1d
65#define FIL1_2 0x1e
66#define FIL1_3 0x1f
67#define PW_MGMT4 0x20
68#define MD_CTL5 0x21
69#define LO_MS 0x22
70#define HP_MS 0x23
71#define SPK_MS 0x24
72
73#define AK4642_CACHEREGNUM 0x25
74
75/* PW_MGMT1*/
76#define PMVCM (1 << 6) /* VCOM Power Management */
77#define PMMIN (1 << 5) /* MIN Input Power Management */
78#define PMDAC (1 << 2) /* DAC Power Management */
79#define PMADL (1 << 0) /* MIC Amp Lch and ADC Lch Power Management */
80
81/* PW_MGMT2 */
82#define HPMTN (1 << 6)
83#define PMHPL (1 << 5)
84#define PMHPR (1 << 4)
85#define MS (1 << 3) /* master/slave select */
86#define MCKO (1 << 1)
87#define PMPLL (1 << 0)
88
89#define PMHP_MASK (PMHPL | PMHPR)
90#define PMHP PMHP_MASK
91
92/* PW_MGMT3 */
93#define PMADR (1 << 0) /* MIC L / ADC R Power Management */
94
95/* SG_SL1 */
96#define MINS (1 << 6) /* Switch from MIN to Speaker */
97#define DACL (1 << 4) /* Switch from DAC to Stereo or Receiver */
98#define PMMP (1 << 2) /* MPWR pin Power Management */
99#define MGAIN0 (1 << 0) /* MIC amp gain*/
100
101/* TIMER */
102#define ZTM(param) ((param & 0x3) << 4) /* ALC Zoro Crossing TimeOut */
103#define WTM(param) (((param & 0x4) << 4) | ((param & 0x3) << 2))
104
105/* ALC_CTL1 */
106#define ALC (1 << 5) /* ALC Enable */
107#define LMTH0 (1 << 0) /* ALC Limiter / Recovery Level */
108
109/* MD_CTL1 */
110#define PLL3 (1 << 7)
111#define PLL2 (1 << 6)
112#define PLL1 (1 << 5)
113#define PLL0 (1 << 4)
114#define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0)
115
116#define BCKO_MASK (1 << 3)
117#define BCKO_64 BCKO_MASK
118
119#define DIF_MASK (3 << 0)
120#define DSP (0 << 0)
121#define RIGHT_J (1 << 0)
122#define LEFT_J (2 << 0)
123#define I2S (3 << 0)
124
125/* MD_CTL2 */
126#define FS0 (1 << 0)
127#define FS1 (1 << 1)
128#define FS2 (1 << 2)
129#define FS3 (1 << 5)
130#define FS_MASK (FS0 | FS1 | FS2 | FS3)
131
132/* MD_CTL3 */
133#define BST1 (1 << 3)
134
135/* MD_CTL4 */
136#define DACH (1 << 0)
137
138/*
139 * Playback Volume (table 39)
140 *
141 * max : 0x00 : +12.0 dB
142 * ( 0.5 dB step )
143 * min : 0xFE : -115.0 dB
144 * mute: 0xFF
145 */
146static const DECLARE_TLV_DB_SCALE(out_tlv, -11500, 50, 1);
147
148static const struct snd_kcontrol_new ak4642_snd_controls[] = {
149
150 SOC_DOUBLE_R_TLV("Digital Playback Volume", L_DVC, R_DVC,
151 0, 0xFF, 1, out_tlv),
152};
153
154
155/* codec private data */
156struct ak4642_priv {
157 unsigned int sysclk;
158 enum snd_soc_control_type control_type;
159 void *control_data;
160};
161
162/*
163 * ak4642 register cache
164 */
165static const u16 ak4642_reg[AK4642_CACHEREGNUM] = {
166 0x0000, 0x0000, 0x0001, 0x0000,
167 0x0002, 0x0000, 0x0000, 0x0000,
168 0x00e1, 0x00e1, 0x0018, 0x0000,
169 0x00e1, 0x0018, 0x0011, 0x0008,
170 0x0000, 0x0000, 0x0000, 0x0000,
171 0x0000, 0x0000, 0x0000, 0x0000,
172 0x0000, 0x0000, 0x0000, 0x0000,
173 0x0000, 0x0000, 0x0000, 0x0000,
174 0x0000, 0x0000, 0x0000, 0x0000,
175 0x0000,
176};
177
178/*
179 * read ak4642 register cache
180 */
181static inline unsigned int ak4642_read_reg_cache(struct snd_soc_codec *codec,
182 unsigned int reg)
183{
184 u16 *cache = codec->reg_cache;
185 if (reg >= AK4642_CACHEREGNUM)
186 return -1;
187 return cache[reg];
188}
189
190/*
191 * write ak4642 register cache
192 */
193static inline void ak4642_write_reg_cache(struct snd_soc_codec *codec,
194 u16 reg, unsigned int value)
195{
196 u16 *cache = codec->reg_cache;
197 if (reg >= AK4642_CACHEREGNUM)
198 return;
199
200 cache[reg] = value;
201}
202
203/*
204 * write to the AK4642 register space
205 */
206static int ak4642_write(struct snd_soc_codec *codec, unsigned int reg,
207 unsigned int value)
208{
209 u8 data[2];
210
211 /* data is
212 * D15..D8 AK4642 register offset
213 * D7...D0 register data
214 */
215 data[0] = reg & 0xff;
216 data[1] = value & 0xff;
217
218 if (codec->hw_write(codec->control_data, data, 2) == 2) {
219 ak4642_write_reg_cache(codec, reg, value);
220 return 0;
221 } else
222 return -EIO;
223}
224
225static int ak4642_sync(struct snd_soc_codec *codec)
226{
227 u16 *cache = codec->reg_cache;
228 int i, r = 0;
229
230 for (i = 0; i < AK4642_CACHEREGNUM; i++)
231 r |= ak4642_write(codec, i, cache[i]);
232
233 return r;
234};
235
236static int ak4642_dai_startup(struct snd_pcm_substream *substream,
237 struct snd_soc_dai *dai)
238{
239 int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
240 struct snd_soc_codec *codec = dai->codec;
241
242 if (is_play) {
243 /*
244 * start headphone output
245 *
246 * PLL, Master Mode
247 * Audio I/F Format :MSB justified (ADC & DAC)
248 * Bass Boost Level : Middle
249 *
250 * This operation came from example code of
251 * "ASAHI KASEI AK4642" (japanese) manual p97.
252 */
253 snd_soc_update_bits(codec, MD_CTL4, DACH, DACH);
254 snd_soc_update_bits(codec, MD_CTL3, BST1, BST1);
255 ak4642_write(codec, L_IVC, 0x91); /* volume */
256 ak4642_write(codec, R_IVC, 0x91); /* volume */
257 snd_soc_update_bits(codec, PW_MGMT1, PMVCM | PMMIN | PMDAC,
258 PMVCM | PMMIN | PMDAC);
259 snd_soc_update_bits(codec, PW_MGMT2, PMHP_MASK, PMHP);
260 snd_soc_update_bits(codec, PW_MGMT2, HPMTN, HPMTN);
261 } else {
262 /*
263 * start stereo input
264 *
265 * PLL Master Mode
266 * Audio I/F Format:MSB justified (ADC & DAC)
267 * Pre MIC AMP:+20dB
268 * MIC Power On
269 * ALC setting:Refer to Table 35
270 * ALC bit=“1”
271 *
272 * This operation came from example code of
273 * "ASAHI KASEI AK4642" (japanese) manual p94.
274 */
275 ak4642_write(codec, SG_SL1, PMMP | MGAIN0);
276 ak4642_write(codec, TIMER, ZTM(0x3) | WTM(0x3));
277 ak4642_write(codec, ALC_CTL1, ALC | LMTH0);
278 snd_soc_update_bits(codec, PW_MGMT1, PMVCM | PMADL,
279 PMVCM | PMADL);
280 snd_soc_update_bits(codec, PW_MGMT3, PMADR, PMADR);
281 }
282
283 return 0;
284}
285
286static void ak4642_dai_shutdown(struct snd_pcm_substream *substream,
287 struct snd_soc_dai *dai)
288{
289 int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
290 struct snd_soc_codec *codec = dai->codec;
291
292 if (is_play) {
293 /* stop headphone output */
294 snd_soc_update_bits(codec, PW_MGMT2, HPMTN, 0);
295 snd_soc_update_bits(codec, PW_MGMT2, PMHP_MASK, 0);
296 snd_soc_update_bits(codec, PW_MGMT1, PMMIN | PMDAC, 0);
297 snd_soc_update_bits(codec, MD_CTL3, BST1, 0);
298 snd_soc_update_bits(codec, MD_CTL4, DACH, 0);
299 } else {
300 /* stop stereo input */
301 snd_soc_update_bits(codec, PW_MGMT1, PMADL, 0);
302 snd_soc_update_bits(codec, PW_MGMT3, PMADR, 0);
303 snd_soc_update_bits(codec, ALC_CTL1, ALC, 0);
304 }
305}
306
307static int ak4642_dai_set_sysclk(struct snd_soc_dai *codec_dai,
308 int clk_id, unsigned int freq, int dir)
309{
310 struct snd_soc_codec *codec = codec_dai->codec;
311 u8 pll;
312
313 switch (freq) {
314 case 11289600:
315 pll = PLL2;
316 break;
317 case 12288000:
318 pll = PLL2 | PLL0;
319 break;
320 case 12000000:
321 pll = PLL2 | PLL1;
322 break;
323 case 24000000:
324 pll = PLL2 | PLL1 | PLL0;
325 break;
326 case 13500000:
327 pll = PLL3 | PLL2;
328 break;
329 case 27000000:
330 pll = PLL3 | PLL2 | PLL0;
331 break;
332 default:
333 return -EINVAL;
334 }
335 snd_soc_update_bits(codec, MD_CTL1, PLL_MASK, pll);
336
337 return 0;
338}
339
340static int ak4642_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
341{
342 struct snd_soc_codec *codec = dai->codec;
343 u8 data;
344 u8 bcko;
345
346 data = MCKO | PMPLL; /* use MCKO */
347 bcko = 0;
348
349 /* set master/slave audio interface */
350 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
351 case SND_SOC_DAIFMT_CBM_CFM:
352 data |= MS;
353 bcko = BCKO_64;
354 break;
355 case SND_SOC_DAIFMT_CBS_CFS:
356 break;
357 default:
358 return -EINVAL;
359 }
360 snd_soc_update_bits(codec, PW_MGMT2, MS | MCKO | PMPLL, data);
361 snd_soc_update_bits(codec, MD_CTL1, BCKO_MASK, bcko);
362
363 /* format type */
364 data = 0;
365 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
366 case SND_SOC_DAIFMT_LEFT_J:
367 data = LEFT_J;
368 break;
369 case SND_SOC_DAIFMT_I2S:
370 data = I2S;
371 break;
372 /* FIXME
373 * Please add RIGHT_J / DSP support here
374 */
375 default:
376 return -EINVAL;
377 break;
378 }
379 snd_soc_update_bits(codec, MD_CTL1, DIF_MASK, data);
380
381 return 0;
382}
383
384static int ak4642_dai_hw_params(struct snd_pcm_substream *substream,
385 struct snd_pcm_hw_params *params,
386 struct snd_soc_dai *dai)
387{
388 struct snd_soc_codec *codec = dai->codec;
389 u8 rate;
390
391 switch (params_rate(params)) {
392 case 7350:
393 rate = FS2;
394 break;
395 case 8000:
396 rate = 0;
397 break;
398 case 11025:
399 rate = FS2 | FS0;
400 break;
401 case 12000:
402 rate = FS0;
403 break;
404 case 14700:
405 rate = FS2 | FS1;
406 break;
407 case 16000:
408 rate = FS1;
409 break;
410 case 22050:
411 rate = FS2 | FS1 | FS0;
412 break;
413 case 24000:
414 rate = FS1 | FS0;
415 break;
416 case 29400:
417 rate = FS3 | FS2 | FS1;
418 break;
419 case 32000:
420 rate = FS3 | FS1;
421 break;
422 case 44100:
423 rate = FS3 | FS2 | FS1 | FS0;
424 break;
425 case 48000:
426 rate = FS3 | FS1 | FS0;
427 break;
428 default:
429 return -EINVAL;
430 break;
431 }
432 snd_soc_update_bits(codec, MD_CTL2, FS_MASK, rate);
433
434 return 0;
435}
436
437static struct snd_soc_dai_ops ak4642_dai_ops = {
438 .startup = ak4642_dai_startup,
439 .shutdown = ak4642_dai_shutdown,
440 .set_sysclk = ak4642_dai_set_sysclk,
441 .set_fmt = ak4642_dai_set_fmt,
442 .hw_params = ak4642_dai_hw_params,
443};
444
445static struct snd_soc_dai_driver ak4642_dai = {
446 .name = "ak4642-hifi",
447 .playback = {
448 .stream_name = "Playback",
449 .channels_min = 1,
450 .channels_max = 2,
451 .rates = SNDRV_PCM_RATE_8000_48000,
452 .formats = SNDRV_PCM_FMTBIT_S16_LE },
453 .capture = {
454 .stream_name = "Capture",
455 .channels_min = 1,
456 .channels_max = 2,
457 .rates = SNDRV_PCM_RATE_8000_48000,
458 .formats = SNDRV_PCM_FMTBIT_S16_LE },
459 .ops = &ak4642_dai_ops,
460 .symmetric_rates = 1,
461};
462
463static int ak4642_resume(struct snd_soc_codec *codec)
464{
465 ak4642_sync(codec);
466 return 0;
467}
468
469
470static int ak4642_probe(struct snd_soc_codec *codec)
471{
472 struct ak4642_priv *ak4642 = snd_soc_codec_get_drvdata(codec);
473
474 dev_info(codec->dev, "AK4642 Audio Codec %s", AK4642_VERSION);
475
476 codec->hw_write = (hw_write_t)i2c_master_send;
477 codec->control_data = ak4642->control_data;
478
479 snd_soc_add_controls(codec, ak4642_snd_controls,
480 ARRAY_SIZE(ak4642_snd_controls));
481
482 return 0;
483}
484
485static struct snd_soc_codec_driver soc_codec_dev_ak4642 = {
486 .probe = ak4642_probe,
487 .resume = ak4642_resume,
488 .read = ak4642_read_reg_cache,
489 .write = ak4642_write,
490 .reg_cache_size = ARRAY_SIZE(ak4642_reg),
491 .reg_word_size = sizeof(u8),
492 .reg_cache_default = ak4642_reg,
493};
494
495#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
496static __devinit int ak4642_i2c_probe(struct i2c_client *i2c,
497 const struct i2c_device_id *id)
498{
499 struct ak4642_priv *ak4642;
500 int ret;
501
502 ak4642 = kzalloc(sizeof(struct ak4642_priv), GFP_KERNEL);
503 if (!ak4642)
504 return -ENOMEM;
505
506 i2c_set_clientdata(i2c, ak4642);
507 ak4642->control_data = i2c;
508 ak4642->control_type = SND_SOC_I2C;
509
510 ret = snd_soc_register_codec(&i2c->dev,
511 &soc_codec_dev_ak4642, &ak4642_dai, 1);
512 if (ret < 0)
513 kfree(ak4642);
514 return ret;
515}
516
517static __devexit int ak4642_i2c_remove(struct i2c_client *client)
518{
519 snd_soc_unregister_codec(&client->dev);
520 kfree(i2c_get_clientdata(client));
521 return 0;
522}
523
524static const struct i2c_device_id ak4642_i2c_id[] = {
525 { "ak4642", 0 },
526 { "ak4643", 0 },
527 { }
528};
529MODULE_DEVICE_TABLE(i2c, ak4642_i2c_id);
530
531static struct i2c_driver ak4642_i2c_driver = {
532 .driver = {
533 .name = "ak4642-codec",
534 .owner = THIS_MODULE,
535 },
536 .probe = ak4642_i2c_probe,
537 .remove = __devexit_p(ak4642_i2c_remove),
538 .id_table = ak4642_i2c_id,
539};
540#endif
541
542static int __init ak4642_modinit(void)
543{
544 int ret = 0;
545#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
546 ret = i2c_add_driver(&ak4642_i2c_driver);
547#endif
548 return ret;
549
550}
551module_init(ak4642_modinit);
552
553static void __exit ak4642_exit(void)
554{
555#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
556 i2c_del_driver(&ak4642_i2c_driver);
557#endif
558
559}
560module_exit(ak4642_exit);
561
562MODULE_DESCRIPTION("Soc AK4642 driver");
563MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
564MODULE_LICENSE("GPL");