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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Timberdale FPGA GPIO driver
4 * Author: Mocean Laboratories
5 * Copyright (c) 2009 Intel Corporation
6 */
7
8/* Supports:
9 * Timberdale FPGA GPIO
10 */
11
12#include <linux/init.h>
13#include <linux/gpio/driver.h>
14#include <linux/platform_device.h>
15#include <linux/irq.h>
16#include <linux/io.h>
17#include <linux/timb_gpio.h>
18#include <linux/interrupt.h>
19#include <linux/slab.h>
20
21#define DRIVER_NAME "timb-gpio"
22
23#define TGPIOVAL 0x00
24#define TGPIODIR 0x04
25#define TGPIO_IER 0x08
26#define TGPIO_ISR 0x0c
27#define TGPIO_IPR 0x10
28#define TGPIO_ICR 0x14
29#define TGPIO_FLR 0x18
30#define TGPIO_LVR 0x1c
31#define TGPIO_VER 0x20
32#define TGPIO_BFLR 0x24
33
34struct timbgpio {
35 void __iomem *membase;
36 spinlock_t lock; /* mutual exclusion */
37 struct gpio_chip gpio;
38 int irq_base;
39 unsigned long last_ier;
40};
41
42static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index,
43 unsigned offset, bool enabled)
44{
45 struct timbgpio *tgpio = gpiochip_get_data(gpio);
46 unsigned long flags;
47 u32 reg;
48
49 spin_lock_irqsave(&tgpio->lock, flags);
50 reg = ioread32(tgpio->membase + offset);
51
52 if (enabled)
53 reg |= (1 << index);
54 else
55 reg &= ~(1 << index);
56
57 iowrite32(reg, tgpio->membase + offset);
58 spin_unlock_irqrestore(&tgpio->lock, flags);
59
60 return 0;
61}
62
63static int timbgpio_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
64{
65 return timbgpio_update_bit(gpio, nr, TGPIODIR, true);
66}
67
68static int timbgpio_gpio_get(struct gpio_chip *gpio, unsigned nr)
69{
70 struct timbgpio *tgpio = gpiochip_get_data(gpio);
71 u32 value;
72
73 value = ioread32(tgpio->membase + TGPIOVAL);
74 return (value & (1 << nr)) ? 1 : 0;
75}
76
77static int timbgpio_gpio_direction_output(struct gpio_chip *gpio,
78 unsigned nr, int val)
79{
80 return timbgpio_update_bit(gpio, nr, TGPIODIR, false);
81}
82
83static void timbgpio_gpio_set(struct gpio_chip *gpio,
84 unsigned nr, int val)
85{
86 timbgpio_update_bit(gpio, nr, TGPIOVAL, val != 0);
87}
88
89static int timbgpio_to_irq(struct gpio_chip *gpio, unsigned offset)
90{
91 struct timbgpio *tgpio = gpiochip_get_data(gpio);
92
93 if (tgpio->irq_base <= 0)
94 return -EINVAL;
95
96 return tgpio->irq_base + offset;
97}
98
99/*
100 * GPIO IRQ
101 */
102static void timbgpio_irq_disable(struct irq_data *d)
103{
104 struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
105 int offset = d->irq - tgpio->irq_base;
106 unsigned long flags;
107
108 spin_lock_irqsave(&tgpio->lock, flags);
109 tgpio->last_ier &= ~(1UL << offset);
110 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
111 spin_unlock_irqrestore(&tgpio->lock, flags);
112}
113
114static void timbgpio_irq_enable(struct irq_data *d)
115{
116 struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
117 int offset = d->irq - tgpio->irq_base;
118 unsigned long flags;
119
120 spin_lock_irqsave(&tgpio->lock, flags);
121 tgpio->last_ier |= 1UL << offset;
122 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
123 spin_unlock_irqrestore(&tgpio->lock, flags);
124}
125
126static int timbgpio_irq_type(struct irq_data *d, unsigned trigger)
127{
128 struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
129 int offset = d->irq - tgpio->irq_base;
130 unsigned long flags;
131 u32 lvr, flr, bflr = 0;
132 u32 ver;
133 int ret = 0;
134
135 if (offset < 0 || offset > tgpio->gpio.ngpio)
136 return -EINVAL;
137
138 ver = ioread32(tgpio->membase + TGPIO_VER);
139
140 spin_lock_irqsave(&tgpio->lock, flags);
141
142 lvr = ioread32(tgpio->membase + TGPIO_LVR);
143 flr = ioread32(tgpio->membase + TGPIO_FLR);
144 if (ver > 2)
145 bflr = ioread32(tgpio->membase + TGPIO_BFLR);
146
147 if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
148 bflr &= ~(1 << offset);
149 flr &= ~(1 << offset);
150 if (trigger & IRQ_TYPE_LEVEL_HIGH)
151 lvr |= 1 << offset;
152 else
153 lvr &= ~(1 << offset);
154 }
155
156 if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
157 if (ver < 3) {
158 ret = -EINVAL;
159 goto out;
160 } else {
161 flr |= 1 << offset;
162 bflr |= 1 << offset;
163 }
164 } else {
165 bflr &= ~(1 << offset);
166 flr |= 1 << offset;
167 if (trigger & IRQ_TYPE_EDGE_FALLING)
168 lvr &= ~(1 << offset);
169 else
170 lvr |= 1 << offset;
171 }
172
173 iowrite32(lvr, tgpio->membase + TGPIO_LVR);
174 iowrite32(flr, tgpio->membase + TGPIO_FLR);
175 if (ver > 2)
176 iowrite32(bflr, tgpio->membase + TGPIO_BFLR);
177
178 iowrite32(1 << offset, tgpio->membase + TGPIO_ICR);
179
180out:
181 spin_unlock_irqrestore(&tgpio->lock, flags);
182 return ret;
183}
184
185static void timbgpio_irq(struct irq_desc *desc)
186{
187 struct timbgpio *tgpio = irq_desc_get_handler_data(desc);
188 struct irq_data *data = irq_desc_get_irq_data(desc);
189 unsigned long ipr;
190 int offset;
191
192 data->chip->irq_ack(data);
193 ipr = ioread32(tgpio->membase + TGPIO_IPR);
194 iowrite32(ipr, tgpio->membase + TGPIO_ICR);
195
196 /*
197 * Some versions of the hardware trash the IER register if more than
198 * one interrupt is received simultaneously.
199 */
200 iowrite32(0, tgpio->membase + TGPIO_IER);
201
202 for_each_set_bit(offset, &ipr, tgpio->gpio.ngpio)
203 generic_handle_irq(timbgpio_to_irq(&tgpio->gpio, offset));
204
205 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
206}
207
208static struct irq_chip timbgpio_irqchip = {
209 .name = "GPIO",
210 .irq_enable = timbgpio_irq_enable,
211 .irq_disable = timbgpio_irq_disable,
212 .irq_set_type = timbgpio_irq_type,
213};
214
215static int timbgpio_probe(struct platform_device *pdev)
216{
217 int err, i;
218 struct device *dev = &pdev->dev;
219 struct gpio_chip *gc;
220 struct timbgpio *tgpio;
221 struct timbgpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
222 int irq = platform_get_irq(pdev, 0);
223
224 if (!pdata || pdata->nr_pins > 32) {
225 dev_err(dev, "Invalid platform data\n");
226 return -EINVAL;
227 }
228
229 tgpio = devm_kzalloc(dev, sizeof(*tgpio), GFP_KERNEL);
230 if (!tgpio)
231 return -EINVAL;
232
233 tgpio->irq_base = pdata->irq_base;
234
235 spin_lock_init(&tgpio->lock);
236
237 tgpio->membase = devm_platform_ioremap_resource(pdev, 0);
238 if (IS_ERR(tgpio->membase))
239 return PTR_ERR(tgpio->membase);
240
241 gc = &tgpio->gpio;
242
243 gc->label = dev_name(&pdev->dev);
244 gc->owner = THIS_MODULE;
245 gc->parent = &pdev->dev;
246 gc->direction_input = timbgpio_gpio_direction_input;
247 gc->get = timbgpio_gpio_get;
248 gc->direction_output = timbgpio_gpio_direction_output;
249 gc->set = timbgpio_gpio_set;
250 gc->to_irq = (irq >= 0 && tgpio->irq_base > 0) ? timbgpio_to_irq : NULL;
251 gc->dbg_show = NULL;
252 gc->base = pdata->gpio_base;
253 gc->ngpio = pdata->nr_pins;
254 gc->can_sleep = false;
255
256 err = devm_gpiochip_add_data(&pdev->dev, gc, tgpio);
257 if (err)
258 return err;
259
260 /* make sure to disable interrupts */
261 iowrite32(0x0, tgpio->membase + TGPIO_IER);
262
263 if (irq < 0 || tgpio->irq_base <= 0)
264 return 0;
265
266 for (i = 0; i < pdata->nr_pins; i++) {
267 irq_set_chip_and_handler(tgpio->irq_base + i,
268 &timbgpio_irqchip, handle_simple_irq);
269 irq_set_chip_data(tgpio->irq_base + i, tgpio);
270 irq_clear_status_flags(tgpio->irq_base + i, IRQ_NOREQUEST | IRQ_NOPROBE);
271 }
272
273 irq_set_chained_handler_and_data(irq, timbgpio_irq, tgpio);
274
275 return 0;
276}
277
278static struct platform_driver timbgpio_platform_driver = {
279 .driver = {
280 .name = DRIVER_NAME,
281 .suppress_bind_attrs = true,
282 },
283 .probe = timbgpio_probe,
284};
285
286/*--------------------------------------------------------------------------*/
287
288builtin_platform_driver(timbgpio_platform_driver);
1/*
2 * Timberdale FPGA GPIO driver
3 * Copyright (c) 2009 Intel Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19/* Supports:
20 * Timberdale FPGA GPIO
21 */
22
23#include <linux/module.h>
24#include <linux/gpio.h>
25#include <linux/platform_device.h>
26#include <linux/irq.h>
27#include <linux/io.h>
28#include <linux/timb_gpio.h>
29#include <linux/interrupt.h>
30#include <linux/slab.h>
31
32#define DRIVER_NAME "timb-gpio"
33
34#define TGPIOVAL 0x00
35#define TGPIODIR 0x04
36#define TGPIO_IER 0x08
37#define TGPIO_ISR 0x0c
38#define TGPIO_IPR 0x10
39#define TGPIO_ICR 0x14
40#define TGPIO_FLR 0x18
41#define TGPIO_LVR 0x1c
42#define TGPIO_VER 0x20
43#define TGPIO_BFLR 0x24
44
45struct timbgpio {
46 void __iomem *membase;
47 spinlock_t lock; /* mutual exclusion */
48 struct gpio_chip gpio;
49 int irq_base;
50 unsigned long last_ier;
51};
52
53static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index,
54 unsigned offset, bool enabled)
55{
56 struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio);
57 u32 reg;
58
59 spin_lock(&tgpio->lock);
60 reg = ioread32(tgpio->membase + offset);
61
62 if (enabled)
63 reg |= (1 << index);
64 else
65 reg &= ~(1 << index);
66
67 iowrite32(reg, tgpio->membase + offset);
68 spin_unlock(&tgpio->lock);
69
70 return 0;
71}
72
73static int timbgpio_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
74{
75 return timbgpio_update_bit(gpio, nr, TGPIODIR, true);
76}
77
78static int timbgpio_gpio_get(struct gpio_chip *gpio, unsigned nr)
79{
80 struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio);
81 u32 value;
82
83 value = ioread32(tgpio->membase + TGPIOVAL);
84 return (value & (1 << nr)) ? 1 : 0;
85}
86
87static int timbgpio_gpio_direction_output(struct gpio_chip *gpio,
88 unsigned nr, int val)
89{
90 return timbgpio_update_bit(gpio, nr, TGPIODIR, false);
91}
92
93static void timbgpio_gpio_set(struct gpio_chip *gpio,
94 unsigned nr, int val)
95{
96 timbgpio_update_bit(gpio, nr, TGPIOVAL, val != 0);
97}
98
99static int timbgpio_to_irq(struct gpio_chip *gpio, unsigned offset)
100{
101 struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio);
102
103 if (tgpio->irq_base <= 0)
104 return -EINVAL;
105
106 return tgpio->irq_base + offset;
107}
108
109/*
110 * GPIO IRQ
111 */
112static void timbgpio_irq_disable(struct irq_data *d)
113{
114 struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
115 int offset = d->irq - tgpio->irq_base;
116 unsigned long flags;
117
118 spin_lock_irqsave(&tgpio->lock, flags);
119 tgpio->last_ier &= ~(1 << offset);
120 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
121 spin_unlock_irqrestore(&tgpio->lock, flags);
122}
123
124static void timbgpio_irq_enable(struct irq_data *d)
125{
126 struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
127 int offset = d->irq - tgpio->irq_base;
128 unsigned long flags;
129
130 spin_lock_irqsave(&tgpio->lock, flags);
131 tgpio->last_ier |= 1 << offset;
132 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
133 spin_unlock_irqrestore(&tgpio->lock, flags);
134}
135
136static int timbgpio_irq_type(struct irq_data *d, unsigned trigger)
137{
138 struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
139 int offset = d->irq - tgpio->irq_base;
140 unsigned long flags;
141 u32 lvr, flr, bflr = 0;
142 u32 ver;
143 int ret = 0;
144
145 if (offset < 0 || offset > tgpio->gpio.ngpio)
146 return -EINVAL;
147
148 ver = ioread32(tgpio->membase + TGPIO_VER);
149
150 spin_lock_irqsave(&tgpio->lock, flags);
151
152 lvr = ioread32(tgpio->membase + TGPIO_LVR);
153 flr = ioread32(tgpio->membase + TGPIO_FLR);
154 if (ver > 2)
155 bflr = ioread32(tgpio->membase + TGPIO_BFLR);
156
157 if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
158 bflr &= ~(1 << offset);
159 flr &= ~(1 << offset);
160 if (trigger & IRQ_TYPE_LEVEL_HIGH)
161 lvr |= 1 << offset;
162 else
163 lvr &= ~(1 << offset);
164 }
165
166 if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
167 if (ver < 3) {
168 ret = -EINVAL;
169 goto out;
170 }
171 else {
172 flr |= 1 << offset;
173 bflr |= 1 << offset;
174 }
175 } else {
176 bflr &= ~(1 << offset);
177 flr |= 1 << offset;
178 if (trigger & IRQ_TYPE_EDGE_FALLING)
179 lvr &= ~(1 << offset);
180 else
181 lvr |= 1 << offset;
182 }
183
184 iowrite32(lvr, tgpio->membase + TGPIO_LVR);
185 iowrite32(flr, tgpio->membase + TGPIO_FLR);
186 if (ver > 2)
187 iowrite32(bflr, tgpio->membase + TGPIO_BFLR);
188
189 iowrite32(1 << offset, tgpio->membase + TGPIO_ICR);
190
191out:
192 spin_unlock_irqrestore(&tgpio->lock, flags);
193 return ret;
194}
195
196static void timbgpio_irq(unsigned int irq, struct irq_desc *desc)
197{
198 struct timbgpio *tgpio = irq_get_handler_data(irq);
199 unsigned long ipr;
200 int offset;
201
202 desc->irq_data.chip->irq_ack(irq_get_irq_data(irq));
203 ipr = ioread32(tgpio->membase + TGPIO_IPR);
204 iowrite32(ipr, tgpio->membase + TGPIO_ICR);
205
206 /*
207 * Some versions of the hardware trash the IER register if more than
208 * one interrupt is received simultaneously.
209 */
210 iowrite32(0, tgpio->membase + TGPIO_IER);
211
212 for_each_set_bit(offset, &ipr, tgpio->gpio.ngpio)
213 generic_handle_irq(timbgpio_to_irq(&tgpio->gpio, offset));
214
215 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
216}
217
218static struct irq_chip timbgpio_irqchip = {
219 .name = "GPIO",
220 .irq_enable = timbgpio_irq_enable,
221 .irq_disable = timbgpio_irq_disable,
222 .irq_set_type = timbgpio_irq_type,
223};
224
225static int __devinit timbgpio_probe(struct platform_device *pdev)
226{
227 int err, i;
228 struct gpio_chip *gc;
229 struct timbgpio *tgpio;
230 struct resource *iomem;
231 struct timbgpio_platform_data *pdata = pdev->dev.platform_data;
232 int irq = platform_get_irq(pdev, 0);
233
234 if (!pdata || pdata->nr_pins > 32) {
235 err = -EINVAL;
236 goto err_mem;
237 }
238
239 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
240 if (!iomem) {
241 err = -EINVAL;
242 goto err_mem;
243 }
244
245 tgpio = kzalloc(sizeof(*tgpio), GFP_KERNEL);
246 if (!tgpio) {
247 err = -EINVAL;
248 goto err_mem;
249 }
250 tgpio->irq_base = pdata->irq_base;
251
252 spin_lock_init(&tgpio->lock);
253
254 if (!request_mem_region(iomem->start, resource_size(iomem),
255 DRIVER_NAME)) {
256 err = -EBUSY;
257 goto err_request;
258 }
259
260 tgpio->membase = ioremap(iomem->start, resource_size(iomem));
261 if (!tgpio->membase) {
262 err = -ENOMEM;
263 goto err_ioremap;
264 }
265
266 gc = &tgpio->gpio;
267
268 gc->label = dev_name(&pdev->dev);
269 gc->owner = THIS_MODULE;
270 gc->dev = &pdev->dev;
271 gc->direction_input = timbgpio_gpio_direction_input;
272 gc->get = timbgpio_gpio_get;
273 gc->direction_output = timbgpio_gpio_direction_output;
274 gc->set = timbgpio_gpio_set;
275 gc->to_irq = (irq >= 0 && tgpio->irq_base > 0) ? timbgpio_to_irq : NULL;
276 gc->dbg_show = NULL;
277 gc->base = pdata->gpio_base;
278 gc->ngpio = pdata->nr_pins;
279 gc->can_sleep = 0;
280
281 err = gpiochip_add(gc);
282 if (err)
283 goto err_chipadd;
284
285 platform_set_drvdata(pdev, tgpio);
286
287 /* make sure to disable interrupts */
288 iowrite32(0x0, tgpio->membase + TGPIO_IER);
289
290 if (irq < 0 || tgpio->irq_base <= 0)
291 return 0;
292
293 for (i = 0; i < pdata->nr_pins; i++) {
294 irq_set_chip_and_handler_name(tgpio->irq_base + i,
295 &timbgpio_irqchip, handle_simple_irq, "mux");
296 irq_set_chip_data(tgpio->irq_base + i, tgpio);
297#ifdef CONFIG_ARM
298 set_irq_flags(tgpio->irq_base + i, IRQF_VALID | IRQF_PROBE);
299#endif
300 }
301
302 irq_set_handler_data(irq, tgpio);
303 irq_set_chained_handler(irq, timbgpio_irq);
304
305 return 0;
306
307err_chipadd:
308 iounmap(tgpio->membase);
309err_ioremap:
310 release_mem_region(iomem->start, resource_size(iomem));
311err_request:
312 kfree(tgpio);
313err_mem:
314 printk(KERN_ERR DRIVER_NAME": Failed to register GPIOs: %d\n", err);
315
316 return err;
317}
318
319static int __devexit timbgpio_remove(struct platform_device *pdev)
320{
321 int err;
322 struct timbgpio_platform_data *pdata = pdev->dev.platform_data;
323 struct timbgpio *tgpio = platform_get_drvdata(pdev);
324 struct resource *iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
325 int irq = platform_get_irq(pdev, 0);
326
327 if (irq >= 0 && tgpio->irq_base > 0) {
328 int i;
329 for (i = 0; i < pdata->nr_pins; i++) {
330 irq_set_chip(tgpio->irq_base + i, NULL);
331 irq_set_chip_data(tgpio->irq_base + i, NULL);
332 }
333
334 irq_set_handler(irq, NULL);
335 irq_set_handler_data(irq, NULL);
336 }
337
338 err = gpiochip_remove(&tgpio->gpio);
339 if (err)
340 printk(KERN_ERR DRIVER_NAME": failed to remove gpio_chip\n");
341
342 iounmap(tgpio->membase);
343 release_mem_region(iomem->start, resource_size(iomem));
344 kfree(tgpio);
345
346 platform_set_drvdata(pdev, NULL);
347
348 return 0;
349}
350
351static struct platform_driver timbgpio_platform_driver = {
352 .driver = {
353 .name = DRIVER_NAME,
354 .owner = THIS_MODULE,
355 },
356 .probe = timbgpio_probe,
357 .remove = timbgpio_remove,
358};
359
360/*--------------------------------------------------------------------------*/
361
362static int __init timbgpio_init(void)
363{
364 return platform_driver_register(&timbgpio_platform_driver);
365}
366
367static void __exit timbgpio_exit(void)
368{
369 platform_driver_unregister(&timbgpio_platform_driver);
370}
371
372module_init(timbgpio_init);
373module_exit(timbgpio_exit);
374
375MODULE_DESCRIPTION("Timberdale GPIO driver");
376MODULE_LICENSE("GPL v2");
377MODULE_AUTHOR("Mocean Laboratories");
378MODULE_ALIAS("platform:"DRIVER_NAME);
379