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1# SPDX-License-Identifier: GPL-2.0-only
2#
3# FPGA framework configuration
4#
5
6menuconfig FPGA
7 tristate "FPGA Configuration Framework"
8 help
9 Say Y here if you want support for configuring FPGAs from the
10 kernel. The FPGA framework adds an FPGA manager class and FPGA
11 manager drivers.
12
13if FPGA
14
15config FPGA_MGR_SOCFPGA
16 tristate "Altera SOCFPGA FPGA Manager"
17 depends on ARCH_INTEL_SOCFPGA || COMPILE_TEST
18 help
19 FPGA manager driver support for Altera SOCFPGA.
20
21config FPGA_MGR_SOCFPGA_A10
22 tristate "Altera SoCFPGA Arria10"
23 depends on ARCH_INTEL_SOCFPGA || COMPILE_TEST
24 select REGMAP_MMIO
25 help
26 FPGA manager driver support for Altera Arria10 SoCFPGA.
27
28config ALTERA_PR_IP_CORE
29 tristate "Altera Partial Reconfiguration IP Core"
30 help
31 Core driver support for Altera Partial Reconfiguration IP component
32
33config ALTERA_PR_IP_CORE_PLAT
34 tristate "Platform support of Altera Partial Reconfiguration IP Core"
35 depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM
36 help
37 Platform driver support for Altera Partial Reconfiguration IP
38 component
39
40config FPGA_MGR_ALTERA_PS_SPI
41 tristate "Altera FPGA Passive Serial over SPI"
42 depends on SPI
43 select BITREVERSE
44 help
45 FPGA manager driver support for Altera Arria/Cyclone/Stratix
46 using the passive serial interface over SPI.
47
48config FPGA_MGR_ALTERA_CVP
49 tristate "Altera CvP FPGA Manager"
50 depends on PCI
51 help
52 FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V,
53 Arria 10 and Stratix10 Altera FPGAs using the CvP interface over PCIe.
54
55config FPGA_MGR_ZYNQ_FPGA
56 tristate "Xilinx Zynq FPGA"
57 depends on ARCH_ZYNQ || COMPILE_TEST
58 help
59 FPGA manager driver support for Xilinx Zynq FPGAs.
60
61config FPGA_MGR_STRATIX10_SOC
62 tristate "Intel Stratix10 SoC FPGA Manager"
63 depends on (ARCH_INTEL_SOCFPGA && INTEL_STRATIX10_SERVICE)
64 help
65 FPGA manager driver support for the Intel Stratix10 SoC.
66
67config FPGA_MGR_XILINX_CORE
68 tristate
69
70config FPGA_MGR_XILINX_SELECTMAP
71 tristate "Xilinx Configuration over SelectMAP"
72 depends on HAS_IOMEM
73 select FPGA_MGR_XILINX_CORE
74 help
75 FPGA manager driver support for Xilinx FPGA configuration
76 over SelectMAP interface.
77
78config FPGA_MGR_XILINX_SPI
79 tristate "Xilinx Configuration over Slave Serial (SPI)"
80 depends on SPI
81 select FPGA_MGR_XILINX_CORE
82 help
83 FPGA manager driver support for Xilinx FPGA configuration
84 over slave serial interface.
85
86config FPGA_MGR_ICE40_SPI
87 tristate "Lattice iCE40 SPI"
88 depends on OF && SPI
89 help
90 FPGA manager driver support for Lattice iCE40 FPGAs over SPI.
91
92config FPGA_MGR_MACHXO2_SPI
93 tristate "Lattice MachXO2 SPI"
94 depends on SPI
95 help
96 FPGA manager driver support for Lattice MachXO2 configuration
97 over slave SPI interface.
98
99config FPGA_MGR_TS73XX
100 tristate "Technologic Systems TS-73xx SBC FPGA Manager"
101 depends on ARCH_EP93XX && MACH_TS72XX
102 help
103 FPGA manager driver support for the Altera Cyclone II FPGA
104 present on the TS-73xx SBC boards.
105
106config FPGA_BRIDGE
107 tristate "FPGA Bridge Framework"
108 help
109 Say Y here if you want to support bridges connected between host
110 processors and FPGAs or between FPGAs.
111
112config SOCFPGA_FPGA_BRIDGE
113 tristate "Altera SoCFPGA FPGA Bridges"
114 depends on ARCH_INTEL_SOCFPGA && FPGA_BRIDGE
115 help
116 Say Y to enable drivers for FPGA bridges for Altera SOCFPGA
117 devices.
118
119config ALTERA_FREEZE_BRIDGE
120 tristate "Altera FPGA Freeze Bridge"
121 depends on FPGA_BRIDGE && HAS_IOMEM
122 help
123 Say Y to enable drivers for Altera FPGA Freeze bridges. A
124 freeze bridge is a bridge that exists in the FPGA fabric to
125 isolate one region of the FPGA from the busses while that
126 region is being reprogrammed.
127
128config XILINX_PR_DECOUPLER
129 tristate "Xilinx LogiCORE PR Decoupler"
130 depends on FPGA_BRIDGE
131 depends on HAS_IOMEM
132 help
133 Say Y to enable drivers for Xilinx LogiCORE PR Decoupler
134 or Xilinx Dynamic Function eXchange AIX Shutdown Manager.
135 The PR Decoupler exists in the FPGA fabric to isolate one
136 region of the FPGA from the busses while that region is
137 being reprogrammed during partial reconfig.
138 The Dynamic Function eXchange AXI shutdown manager prevents
139 AXI traffic from passing through the bridge. The controller
140 safely handles AXI4MM and AXI4-Lite interfaces on a
141 Reconfigurable Partition when it is undergoing dynamic
142 reconfiguration, preventing the system deadlock that can
143 occur if AXI transactions are interrupted by DFX.
144
145config FPGA_REGION
146 tristate "FPGA Region"
147 depends on FPGA_BRIDGE
148 help
149 FPGA Region common code. An FPGA Region controls an FPGA Manager
150 and the FPGA Bridges associated with either a reconfigurable
151 region of an FPGA or a whole FPGA.
152
153config OF_FPGA_REGION
154 tristate "FPGA Region Device Tree Overlay Support"
155 depends on OF && FPGA_REGION
156 help
157 Support for loading FPGA images by applying a Device Tree
158 overlay.
159
160config FPGA_DFL
161 tristate "FPGA Device Feature List (DFL) support"
162 select FPGA_BRIDGE
163 select FPGA_REGION
164 depends on HAS_IOMEM
165 help
166 Device Feature List (DFL) defines a feature list structure that
167 creates a linked list of feature headers within the MMIO space
168 to provide an extensible way of adding features for FPGA.
169 Driver can walk through the feature headers to enumerate feature
170 devices (e.g. FPGA Management Engine, Port and Accelerator
171 Function Unit) and their private features for target FPGA devices.
172
173 Select this option to enable common support for Field-Programmable
174 Gate Array (FPGA) solutions which implement Device Feature List.
175 It provides enumeration APIs and feature device infrastructure.
176
177config FPGA_DFL_FME
178 tristate "FPGA DFL FME Driver"
179 depends on FPGA_DFL && HWMON && PERF_EVENTS
180 help
181 The FPGA Management Engine (FME) is a feature device implemented
182 under Device Feature List (DFL) framework. Select this option to
183 enable the platform device driver for FME which implements all
184 FPGA platform level management features. There shall be one FME
185 per DFL based FPGA device.
186
187config FPGA_DFL_FME_MGR
188 tristate "FPGA DFL FME Manager Driver"
189 depends on FPGA_DFL_FME && HAS_IOMEM
190 help
191 Say Y to enable FPGA Manager driver for FPGA Management Engine.
192
193config FPGA_DFL_FME_BRIDGE
194 tristate "FPGA DFL FME Bridge Driver"
195 depends on FPGA_DFL_FME && HAS_IOMEM
196 help
197 Say Y to enable FPGA Bridge driver for FPGA Management Engine.
198
199config FPGA_DFL_FME_REGION
200 tristate "FPGA DFL FME Region Driver"
201 depends on FPGA_DFL_FME && HAS_IOMEM
202 help
203 Say Y to enable FPGA Region driver for FPGA Management Engine.
204
205config FPGA_DFL_AFU
206 tristate "FPGA DFL AFU Driver"
207 depends on FPGA_DFL
208 help
209 This is the driver for FPGA Accelerated Function Unit (AFU) which
210 implements AFU and Port management features. A User AFU connects
211 to the FPGA infrastructure via a Port. There may be more than one
212 Port/AFU per DFL based FPGA device.
213
214config FPGA_DFL_NIOS_INTEL_PAC_N3000
215 tristate "FPGA DFL NIOS Driver for Intel PAC N3000"
216 depends on FPGA_DFL
217 select REGMAP
218 help
219 This is the driver for the N3000 Nios private feature on Intel
220 PAC (Programmable Acceleration Card) N3000. It communicates
221 with the embedded Nios processor to configure the retimers on
222 the card. It also instantiates the SPI master (spi-altera) for
223 the card's BMC (Board Management Controller).
224
225config FPGA_DFL_PCI
226 tristate "FPGA DFL PCIe Device Driver"
227 depends on PCI && FPGA_DFL
228 help
229 Select this option to enable PCIe driver for PCIe-based
230 Field-Programmable Gate Array (FPGA) solutions which implement
231 the Device Feature List (DFL). This driver provides interfaces
232 for userspace applications to configure, enumerate, open and access
233 FPGA accelerators on the FPGA DFL devices, enables system level
234 management functions such as FPGA partial reconfiguration, power
235 management and virtualization with DFL framework and DFL feature
236 device drivers.
237
238 To compile this as a module, choose M here.
239
240config FPGA_MGR_ZYNQMP_FPGA
241 tristate "Xilinx ZynqMP FPGA"
242 depends on ZYNQMP_FIRMWARE || (!ZYNQMP_FIRMWARE && COMPILE_TEST)
243 help
244 FPGA manager driver support for Xilinx ZynqMP FPGAs.
245 This driver uses the processor configuration port(PCAP)
246 to configure the programmable logic(PL) through PS
247 on ZynqMP SoC.
248
249config FPGA_MGR_VERSAL_FPGA
250 tristate "Xilinx Versal FPGA"
251 depends on ARCH_ZYNQMP || COMPILE_TEST
252 help
253 Select this option to enable FPGA manager driver support for
254 Xilinx Versal SoC. This driver uses the firmware interface to
255 configure the programmable logic(PL).
256
257 To compile this as a module, choose M here.
258
259config FPGA_M10_BMC_SEC_UPDATE
260 tristate "Intel MAX10 BMC Secure Update driver"
261 depends on MFD_INTEL_M10_BMC_CORE
262 select FW_LOADER
263 select FW_UPLOAD
264 help
265 Secure update support for the Intel MAX10 board management
266 controller.
267
268 This is a subdriver of the Intel MAX10 board management controller
269 (BMC) and provides support for secure updates for the BMC image,
270 the FPGA image, the Root Entry Hashes, etc.
271
272config FPGA_MGR_MICROCHIP_SPI
273 tristate "Microchip Polarfire SPI FPGA manager"
274 depends on SPI
275 help
276 FPGA manager driver support for Microchip Polarfire FPGAs
277 programming over slave SPI interface with .dat formatted
278 bitstream image.
279
280config FPGA_MGR_LATTICE_SYSCONFIG
281 tristate
282
283config FPGA_MGR_LATTICE_SYSCONFIG_SPI
284 tristate "Lattice sysCONFIG SPI FPGA manager"
285 depends on SPI
286 select FPGA_MGR_LATTICE_SYSCONFIG
287 help
288 FPGA manager driver support for Lattice FPGAs programming over slave
289 SPI sysCONFIG interface.
290
291source "drivers/fpga/tests/Kconfig"
292
293endif # FPGA