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1/* SPDX-License-Identifier: BSD-3-Clause */
2/*
3 * Freescale SEC (talitos) device register and descriptor header defines
4 *
5 * Copyright (c) 2006-2011 Freescale Semiconductor, Inc.
6 */
7
8#define TALITOS_TIMEOUT 100000
9#define TALITOS1_MAX_DATA_LEN 32768
10#define TALITOS2_MAX_DATA_LEN 65535
11
12#define DESC_TYPE(desc_hdr) ((be32_to_cpu(desc_hdr) >> 3) & 0x1f)
13#define PRIMARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 28) & 0xf)
14#define SECONDARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 16) & 0xf)
15
16/* descriptor pointer entry */
17struct talitos_ptr {
18 union {
19 struct { /* SEC2 format */
20 __be16 len; /* length */
21 u8 j_extent; /* jump to sg link table and/or extent*/
22 u8 eptr; /* extended address */
23 };
24 struct { /* SEC1 format */
25 __be16 res;
26 __be16 len1; /* length */
27 };
28 };
29 __be32 ptr; /* address */
30};
31
32/* descriptor */
33struct talitos_desc {
34 __be32 hdr; /* header high bits */
35 union {
36 __be32 hdr_lo; /* header low bits */
37 __be32 hdr1; /* header for SEC1 */
38 };
39 struct talitos_ptr ptr[7]; /* ptr/len pair array */
40 __be32 next_desc; /* next descriptor (SEC1) */
41};
42
43#define TALITOS_DESC_SIZE (sizeof(struct talitos_desc) - sizeof(__be32))
44
45/*
46 * talitos_edesc - s/w-extended descriptor
47 * @src_nents: number of segments in input scatterlist
48 * @dst_nents: number of segments in output scatterlist
49 * @iv_dma: dma address of iv for checking continuity and link table
50 * @dma_len: length of dma mapped link_tbl space
51 * @dma_link_tbl: bus physical address of link_tbl/buf
52 * @desc: h/w descriptor
53 * @link_tbl: input and output h/w link tables (if {src,dst}_nents > 1) (SEC2)
54 * @buf: input and output buffeur (if {src,dst}_nents > 1) (SEC1)
55 *
56 * if decrypting (with authcheck), or either one of src_nents or dst_nents
57 * is greater than 1, an integrity check value is concatenated to the end
58 * of link_tbl data
59 */
60struct talitos_edesc {
61 int src_nents;
62 int dst_nents;
63 dma_addr_t iv_dma;
64 int dma_len;
65 dma_addr_t dma_link_tbl;
66 struct talitos_desc desc;
67 union {
68 DECLARE_FLEX_ARRAY(struct talitos_ptr, link_tbl);
69 DECLARE_FLEX_ARRAY(u8, buf);
70 };
71};
72
73/**
74 * talitos_request - descriptor submission request
75 * @desc: descriptor pointer (kernel virtual)
76 * @dma_desc: descriptor's physical bus address
77 * @callback: whom to call when descriptor processing is done
78 * @context: caller context (optional)
79 */
80struct talitos_request {
81 struct talitos_desc *desc;
82 dma_addr_t dma_desc;
83 void (*callback) (struct device *dev, struct talitos_desc *desc,
84 void *context, int error);
85 void *context;
86};
87
88/* per-channel fifo management */
89struct talitos_channel {
90 void __iomem *reg;
91
92 /* request fifo */
93 struct talitos_request *fifo;
94
95 /* number of requests pending in channel h/w fifo */
96 atomic_t submit_count ____cacheline_aligned;
97
98 /* request submission (head) lock */
99 spinlock_t head_lock ____cacheline_aligned;
100 /* index to next free descriptor request */
101 int head;
102
103 /* request release (tail) lock */
104 spinlock_t tail_lock ____cacheline_aligned;
105 /* index to next in-progress/done descriptor request */
106 int tail;
107};
108
109struct talitos_private {
110 struct device *dev;
111 struct platform_device *ofdev;
112 void __iomem *reg;
113 void __iomem *reg_deu;
114 void __iomem *reg_aesu;
115 void __iomem *reg_mdeu;
116 void __iomem *reg_afeu;
117 void __iomem *reg_rngu;
118 void __iomem *reg_pkeu;
119 void __iomem *reg_keu;
120 void __iomem *reg_crcu;
121 int irq[2];
122
123 /* SEC global registers lock */
124 spinlock_t reg_lock ____cacheline_aligned;
125
126 /* SEC version geometry (from device tree node) */
127 unsigned int num_channels;
128 unsigned int chfifo_len;
129 unsigned int exec_units;
130 unsigned int desc_types;
131
132 /* SEC Compatibility info */
133 unsigned long features;
134
135 /*
136 * length of the request fifo
137 * fifo_len is chfifo_len rounded up to next power of 2
138 * so we can use bitwise ops to wrap
139 */
140 unsigned int fifo_len;
141
142 struct talitos_channel *chan;
143
144 /* next channel to be assigned next incoming descriptor */
145 atomic_t last_chan ____cacheline_aligned;
146
147 /* request callback tasklet */
148 struct tasklet_struct done_task[2];
149
150 /* list of registered algorithms */
151 struct list_head alg_list;
152
153 /* hwrng device */
154 struct hwrng rng;
155 bool rng_registered;
156};
157
158/* .features flag */
159#define TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT 0x00000001
160#define TALITOS_FTR_HW_AUTH_CHECK 0x00000002
161#define TALITOS_FTR_SHA224_HWINIT 0x00000004
162#define TALITOS_FTR_HMAC_OK 0x00000008
163#define TALITOS_FTR_SEC1 0x00000010
164
165/*
166 * If both CONFIG_CRYPTO_DEV_TALITOS1 and CONFIG_CRYPTO_DEV_TALITOS2 are
167 * defined, we check the features which are set according to the device tree.
168 * Otherwise, we answer true or false directly
169 */
170static inline bool has_ftr_sec1(struct talitos_private *priv)
171{
172 if (IS_ENABLED(CONFIG_CRYPTO_DEV_TALITOS1) &&
173 IS_ENABLED(CONFIG_CRYPTO_DEV_TALITOS2))
174 return priv->features & TALITOS_FTR_SEC1;
175
176 return IS_ENABLED(CONFIG_CRYPTO_DEV_TALITOS1);
177}
178
179/*
180 * TALITOS_xxx_LO addresses point to the low data bits (32-63) of the register
181 */
182
183#define ISR1_FORMAT(x) (((x) << 28) | ((x) << 16))
184#define ISR2_FORMAT(x) (((x) << 4) | (x))
185
186/* global register offset addresses */
187#define TALITOS_MCR 0x1030 /* master control register */
188#define TALITOS_MCR_RCA0 (1 << 15) /* remap channel 0 */
189#define TALITOS_MCR_RCA1 (1 << 14) /* remap channel 1 */
190#define TALITOS_MCR_RCA2 (1 << 13) /* remap channel 2 */
191#define TALITOS_MCR_RCA3 (1 << 12) /* remap channel 3 */
192#define TALITOS1_MCR_SWR 0x1000000 /* s/w reset */
193#define TALITOS2_MCR_SWR 0x1 /* s/w reset */
194#define TALITOS_MCR_LO 0x1034
195#define TALITOS_IMR 0x1008 /* interrupt mask register */
196/* enable channel IRQs */
197#define TALITOS1_IMR_INIT ISR1_FORMAT(0xf)
198#define TALITOS1_IMR_DONE ISR1_FORMAT(0x5) /* done IRQs */
199/* enable channel IRQs */
200#define TALITOS2_IMR_INIT (ISR2_FORMAT(0xf) | 0x10000)
201#define TALITOS2_IMR_DONE ISR1_FORMAT(0x5) /* done IRQs */
202#define TALITOS_IMR_LO 0x100C
203#define TALITOS1_IMR_LO_INIT 0x2000000 /* allow RNGU error IRQs */
204#define TALITOS2_IMR_LO_INIT 0x20000 /* allow RNGU error IRQs */
205#define TALITOS_ISR 0x1010 /* interrupt status register */
206#define TALITOS1_ISR_4CHERR ISR1_FORMAT(0xa) /* 4 ch errors mask */
207#define TALITOS1_ISR_4CHDONE ISR1_FORMAT(0x5) /* 4 ch done mask */
208#define TALITOS1_ISR_CH_0_ERR (2 << 28) /* ch 0 errors mask */
209#define TALITOS1_ISR_CH_0_DONE (1 << 28) /* ch 0 done mask */
210#define TALITOS1_ISR_TEA_ERR 0x00000040
211#define TALITOS2_ISR_4CHERR ISR2_FORMAT(0xa) /* 4 ch errors mask */
212#define TALITOS2_ISR_4CHDONE ISR2_FORMAT(0x5) /* 4 ch done mask */
213#define TALITOS2_ISR_CH_0_ERR 2 /* ch 0 errors mask */
214#define TALITOS2_ISR_CH_0_DONE 1 /* ch 0 done mask */
215#define TALITOS2_ISR_CH_0_2_ERR ISR2_FORMAT(0x2) /* ch 0, 2 err mask */
216#define TALITOS2_ISR_CH_0_2_DONE ISR2_FORMAT(0x1) /* ch 0, 2 done mask */
217#define TALITOS2_ISR_CH_1_3_ERR ISR2_FORMAT(0x8) /* ch 1, 3 err mask */
218#define TALITOS2_ISR_CH_1_3_DONE ISR2_FORMAT(0x4) /* ch 1, 3 done mask */
219#define TALITOS_ISR_LO 0x1014
220#define TALITOS_ICR 0x1018 /* interrupt clear register */
221#define TALITOS_ICR_LO 0x101C
222
223/* channel register address stride */
224#define TALITOS_CH_BASE_OFFSET 0x1000 /* default channel map base */
225#define TALITOS1_CH_STRIDE 0x1000
226#define TALITOS2_CH_STRIDE 0x100
227
228/* channel configuration register */
229#define TALITOS_CCCR 0x8
230#define TALITOS2_CCCR_CONT 0x2 /* channel continue on SEC2 */
231#define TALITOS2_CCCR_RESET 0x1 /* channel reset on SEC2 */
232#define TALITOS_CCCR_LO 0xc
233#define TALITOS_CCCR_LO_IWSE 0x80 /* chan. ICCR writeback enab. */
234#define TALITOS_CCCR_LO_EAE 0x20 /* extended address enable */
235#define TALITOS_CCCR_LO_CDWE 0x10 /* chan. done writeback enab. */
236#define TALITOS_CCCR_LO_NE 0x8 /* fetch next descriptor enab. */
237#define TALITOS_CCCR_LO_NT 0x4 /* notification type */
238#define TALITOS_CCCR_LO_CDIE 0x2 /* channel done IRQ enable */
239#define TALITOS1_CCCR_LO_RESET 0x1 /* channel reset on SEC1 */
240
241/* CCPSR: channel pointer status register */
242#define TALITOS_CCPSR 0x10
243#define TALITOS_CCPSR_LO 0x14
244#define TALITOS_CCPSR_LO_DOF 0x8000 /* double FF write oflow error */
245#define TALITOS_CCPSR_LO_SOF 0x4000 /* single FF write oflow error */
246#define TALITOS_CCPSR_LO_MDTE 0x2000 /* master data transfer error */
247#define TALITOS_CCPSR_LO_SGDLZ 0x1000 /* s/g data len zero error */
248#define TALITOS_CCPSR_LO_FPZ 0x0800 /* fetch ptr zero error */
249#define TALITOS_CCPSR_LO_IDH 0x0400 /* illegal desc hdr error */
250#define TALITOS_CCPSR_LO_IEU 0x0200 /* invalid EU error */
251#define TALITOS_CCPSR_LO_EU 0x0100 /* EU error detected */
252#define TALITOS_CCPSR_LO_GB 0x0080 /* gather boundary error */
253#define TALITOS_CCPSR_LO_GRL 0x0040 /* gather return/length error */
254#define TALITOS_CCPSR_LO_SB 0x0020 /* scatter boundary error */
255#define TALITOS_CCPSR_LO_SRL 0x0010 /* scatter return/length error */
256
257/* channel fetch fifo register */
258#define TALITOS_FF 0x48
259#define TALITOS_FF_LO 0x4c
260
261/* current descriptor pointer register */
262#define TALITOS_CDPR 0x40
263#define TALITOS_CDPR_LO 0x44
264
265/* descriptor buffer register */
266#define TALITOS_DESCBUF 0x80
267#define TALITOS_DESCBUF_LO 0x84
268
269/* gather link table */
270#define TALITOS_GATHER 0xc0
271#define TALITOS_GATHER_LO 0xc4
272
273/* scatter link table */
274#define TALITOS_SCATTER 0xe0
275#define TALITOS_SCATTER_LO 0xe4
276
277/* execution unit registers base */
278#define TALITOS2_DEU 0x2000
279#define TALITOS2_AESU 0x4000
280#define TALITOS2_MDEU 0x6000
281#define TALITOS2_AFEU 0x8000
282#define TALITOS2_RNGU 0xa000
283#define TALITOS2_PKEU 0xc000
284#define TALITOS2_KEU 0xe000
285#define TALITOS2_CRCU 0xf000
286
287#define TALITOS12_AESU 0x4000
288#define TALITOS12_DEU 0x5000
289#define TALITOS12_MDEU 0x6000
290
291#define TALITOS10_AFEU 0x8000
292#define TALITOS10_DEU 0xa000
293#define TALITOS10_MDEU 0xc000
294#define TALITOS10_RNGU 0xe000
295#define TALITOS10_PKEU 0x10000
296#define TALITOS10_AESU 0x12000
297
298/* execution unit interrupt status registers */
299#define TALITOS_EUDSR 0x10 /* data size */
300#define TALITOS_EUDSR_LO 0x14
301#define TALITOS_EURCR 0x18 /* reset control*/
302#define TALITOS_EURCR_LO 0x1c
303#define TALITOS_EUSR 0x28 /* rng status */
304#define TALITOS_EUSR_LO 0x2c
305#define TALITOS_EUISR 0x30
306#define TALITOS_EUISR_LO 0x34
307#define TALITOS_EUICR 0x38 /* int. control */
308#define TALITOS_EUICR_LO 0x3c
309#define TALITOS_EU_FIFO 0x800 /* output FIFO */
310#define TALITOS_EU_FIFO_LO 0x804 /* output FIFO */
311/* DES unit */
312#define TALITOS1_DEUICR_KPE 0x00200000 /* Key Parity Error */
313/* message digest unit */
314#define TALITOS_MDEUICR_LO_ICE 0x4000 /* integrity check IRQ enable */
315/* random number unit */
316#define TALITOS_RNGUSR_LO_RD 0x1 /* reset done */
317#define TALITOS_RNGUSR_LO_OFL 0xff0000/* output FIFO length */
318#define TALITOS_RNGURCR_LO_SR 0x1 /* software reset */
319
320#define TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256 0x28
321#define TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512 0x48
322
323/*
324 * talitos descriptor header (hdr) bits
325 */
326
327/* written back when done */
328#define DESC_HDR_DONE cpu_to_be32(0xff000000)
329#define DESC_HDR_LO_ICCR1_MASK cpu_to_be32(0x00180000)
330#define DESC_HDR_LO_ICCR1_PASS cpu_to_be32(0x00080000)
331#define DESC_HDR_LO_ICCR1_FAIL cpu_to_be32(0x00100000)
332
333/* primary execution unit select */
334#define DESC_HDR_SEL0_MASK cpu_to_be32(0xf0000000)
335#define DESC_HDR_SEL0_AFEU cpu_to_be32(0x10000000)
336#define DESC_HDR_SEL0_DEU cpu_to_be32(0x20000000)
337#define DESC_HDR_SEL0_MDEUA cpu_to_be32(0x30000000)
338#define DESC_HDR_SEL0_MDEUB cpu_to_be32(0xb0000000)
339#define DESC_HDR_SEL0_RNG cpu_to_be32(0x40000000)
340#define DESC_HDR_SEL0_PKEU cpu_to_be32(0x50000000)
341#define DESC_HDR_SEL0_AESU cpu_to_be32(0x60000000)
342#define DESC_HDR_SEL0_KEU cpu_to_be32(0x70000000)
343#define DESC_HDR_SEL0_CRCU cpu_to_be32(0x80000000)
344
345/* primary execution unit mode (MODE0) and derivatives */
346#define DESC_HDR_MODE0_ENCRYPT cpu_to_be32(0x00100000)
347#define DESC_HDR_MODE0_AESU_MASK cpu_to_be32(0x00600000)
348#define DESC_HDR_MODE0_AESU_CBC cpu_to_be32(0x00200000)
349#define DESC_HDR_MODE0_AESU_CTR cpu_to_be32(0x00600000)
350#define DESC_HDR_MODE0_DEU_CBC cpu_to_be32(0x00400000)
351#define DESC_HDR_MODE0_DEU_3DES cpu_to_be32(0x00200000)
352#define DESC_HDR_MODE0_MDEU_CONT cpu_to_be32(0x08000000)
353#define DESC_HDR_MODE0_MDEU_INIT cpu_to_be32(0x01000000)
354#define DESC_HDR_MODE0_MDEU_HMAC cpu_to_be32(0x00800000)
355#define DESC_HDR_MODE0_MDEU_PAD cpu_to_be32(0x00400000)
356#define DESC_HDR_MODE0_MDEU_SHA224 cpu_to_be32(0x00300000)
357#define DESC_HDR_MODE0_MDEU_MD5 cpu_to_be32(0x00200000)
358#define DESC_HDR_MODE0_MDEU_SHA256 cpu_to_be32(0x00100000)
359#define DESC_HDR_MODE0_MDEU_SHA1 cpu_to_be32(0x00000000)
360#define DESC_HDR_MODE0_MDEUB_SHA384 cpu_to_be32(0x00000000)
361#define DESC_HDR_MODE0_MDEUB_SHA512 cpu_to_be32(0x00200000)
362#define DESC_HDR_MODE0_MDEU_MD5_HMAC (DESC_HDR_MODE0_MDEU_MD5 | \
363 DESC_HDR_MODE0_MDEU_HMAC)
364#define DESC_HDR_MODE0_MDEU_SHA256_HMAC (DESC_HDR_MODE0_MDEU_SHA256 | \
365 DESC_HDR_MODE0_MDEU_HMAC)
366#define DESC_HDR_MODE0_MDEU_SHA1_HMAC (DESC_HDR_MODE0_MDEU_SHA1 | \
367 DESC_HDR_MODE0_MDEU_HMAC)
368
369/* secondary execution unit select (SEL1) */
370#define DESC_HDR_SEL1_MASK cpu_to_be32(0x000f0000)
371#define DESC_HDR_SEL1_MDEUA cpu_to_be32(0x00030000)
372#define DESC_HDR_SEL1_MDEUB cpu_to_be32(0x000b0000)
373#define DESC_HDR_SEL1_CRCU cpu_to_be32(0x00080000)
374
375/* secondary execution unit mode (MODE1) and derivatives */
376#define DESC_HDR_MODE1_MDEU_CICV cpu_to_be32(0x00004000)
377#define DESC_HDR_MODE1_MDEU_INIT cpu_to_be32(0x00001000)
378#define DESC_HDR_MODE1_MDEU_HMAC cpu_to_be32(0x00000800)
379#define DESC_HDR_MODE1_MDEU_PAD cpu_to_be32(0x00000400)
380#define DESC_HDR_MODE1_MDEU_SHA224 cpu_to_be32(0x00000300)
381#define DESC_HDR_MODE1_MDEU_MD5 cpu_to_be32(0x00000200)
382#define DESC_HDR_MODE1_MDEU_SHA256 cpu_to_be32(0x00000100)
383#define DESC_HDR_MODE1_MDEU_SHA1 cpu_to_be32(0x00000000)
384#define DESC_HDR_MODE1_MDEUB_SHA384 cpu_to_be32(0x00000000)
385#define DESC_HDR_MODE1_MDEUB_SHA512 cpu_to_be32(0x00000200)
386#define DESC_HDR_MODE1_MDEU_MD5_HMAC (DESC_HDR_MODE1_MDEU_MD5 | \
387 DESC_HDR_MODE1_MDEU_HMAC)
388#define DESC_HDR_MODE1_MDEU_SHA256_HMAC (DESC_HDR_MODE1_MDEU_SHA256 | \
389 DESC_HDR_MODE1_MDEU_HMAC)
390#define DESC_HDR_MODE1_MDEU_SHA1_HMAC (DESC_HDR_MODE1_MDEU_SHA1 | \
391 DESC_HDR_MODE1_MDEU_HMAC)
392#define DESC_HDR_MODE1_MDEU_SHA224_HMAC (DESC_HDR_MODE1_MDEU_SHA224 | \
393 DESC_HDR_MODE1_MDEU_HMAC)
394#define DESC_HDR_MODE1_MDEUB_SHA384_HMAC (DESC_HDR_MODE1_MDEUB_SHA384 | \
395 DESC_HDR_MODE1_MDEU_HMAC)
396#define DESC_HDR_MODE1_MDEUB_SHA512_HMAC (DESC_HDR_MODE1_MDEUB_SHA512 | \
397 DESC_HDR_MODE1_MDEU_HMAC)
398
399/* direction of overall data flow (DIR) */
400#define DESC_HDR_DIR_INBOUND cpu_to_be32(0x00000002)
401
402/* request done notification (DN) */
403#define DESC_HDR_DONE_NOTIFY cpu_to_be32(0x00000001)
404
405/* descriptor types */
406#define DESC_HDR_TYPE_AESU_CTR_NONSNOOP cpu_to_be32(0 << 3)
407#define DESC_HDR_TYPE_IPSEC_ESP cpu_to_be32(1 << 3)
408#define DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU cpu_to_be32(2 << 3)
409#define DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU cpu_to_be32(4 << 3)
410
411/* link table extent field bits */
412#define DESC_PTR_LNKTBL_JUMP 0x80
413#define DESC_PTR_LNKTBL_RET 0x02
414#define DESC_PTR_LNKTBL_NEXT 0x01
1/*
2 * Freescale SEC (talitos) device register and descriptor header defines
3 *
4 * Copyright (c) 2006-2010 Freescale Semiconductor, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 */
30
31/*
32 * TALITOS_xxx_LO addresses point to the low data bits (32-63) of the register
33 */
34
35/* global register offset addresses */
36#define TALITOS_MCR 0x1030 /* master control register */
37#define TALITOS_MCR_LO 0x1038
38#define TALITOS_MCR_SWR 0x1 /* s/w reset */
39#define TALITOS_IMR 0x1008 /* interrupt mask register */
40#define TALITOS_IMR_INIT 0x100ff /* enable channel IRQs */
41#define TALITOS_IMR_DONE 0x00055 /* done IRQs */
42#define TALITOS_IMR_LO 0x100C
43#define TALITOS_IMR_LO_INIT 0x20000 /* allow RNGU error IRQs */
44#define TALITOS_ISR 0x1010 /* interrupt status register */
45#define TALITOS_ISR_CHERR 0xaa /* channel errors mask */
46#define TALITOS_ISR_CHDONE 0x55 /* channel done mask */
47#define TALITOS_ISR_LO 0x1014
48#define TALITOS_ICR 0x1018 /* interrupt clear register */
49#define TALITOS_ICR_LO 0x101C
50
51/* channel register address stride */
52#define TALITOS_CH_STRIDE 0x100
53
54/* channel configuration register */
55#define TALITOS_CCCR(ch) (ch * TALITOS_CH_STRIDE + 0x1108)
56#define TALITOS_CCCR_CONT 0x2 /* channel continue */
57#define TALITOS_CCCR_RESET 0x1 /* channel reset */
58#define TALITOS_CCCR_LO(ch) (ch * TALITOS_CH_STRIDE + 0x110c)
59#define TALITOS_CCCR_LO_IWSE 0x80 /* chan. ICCR writeback enab. */
60#define TALITOS_CCCR_LO_EAE 0x20 /* extended address enable */
61#define TALITOS_CCCR_LO_CDWE 0x10 /* chan. done writeback enab. */
62#define TALITOS_CCCR_LO_NT 0x4 /* notification type */
63#define TALITOS_CCCR_LO_CDIE 0x2 /* channel done IRQ enable */
64
65/* CCPSR: channel pointer status register */
66#define TALITOS_CCPSR(ch) (ch * TALITOS_CH_STRIDE + 0x1110)
67#define TALITOS_CCPSR_LO(ch) (ch * TALITOS_CH_STRIDE + 0x1114)
68#define TALITOS_CCPSR_LO_DOF 0x8000 /* double FF write oflow error */
69#define TALITOS_CCPSR_LO_SOF 0x4000 /* single FF write oflow error */
70#define TALITOS_CCPSR_LO_MDTE 0x2000 /* master data transfer error */
71#define TALITOS_CCPSR_LO_SGDLZ 0x1000 /* s/g data len zero error */
72#define TALITOS_CCPSR_LO_FPZ 0x0800 /* fetch ptr zero error */
73#define TALITOS_CCPSR_LO_IDH 0x0400 /* illegal desc hdr error */
74#define TALITOS_CCPSR_LO_IEU 0x0200 /* invalid EU error */
75#define TALITOS_CCPSR_LO_EU 0x0100 /* EU error detected */
76#define TALITOS_CCPSR_LO_GB 0x0080 /* gather boundary error */
77#define TALITOS_CCPSR_LO_GRL 0x0040 /* gather return/length error */
78#define TALITOS_CCPSR_LO_SB 0x0020 /* scatter boundary error */
79#define TALITOS_CCPSR_LO_SRL 0x0010 /* scatter return/length error */
80
81/* channel fetch fifo register */
82#define TALITOS_FF(ch) (ch * TALITOS_CH_STRIDE + 0x1148)
83#define TALITOS_FF_LO(ch) (ch * TALITOS_CH_STRIDE + 0x114c)
84
85/* current descriptor pointer register */
86#define TALITOS_CDPR(ch) (ch * TALITOS_CH_STRIDE + 0x1140)
87#define TALITOS_CDPR_LO(ch) (ch * TALITOS_CH_STRIDE + 0x1144)
88
89/* descriptor buffer register */
90#define TALITOS_DESCBUF(ch) (ch * TALITOS_CH_STRIDE + 0x1180)
91#define TALITOS_DESCBUF_LO(ch) (ch * TALITOS_CH_STRIDE + 0x1184)
92
93/* gather link table */
94#define TALITOS_GATHER(ch) (ch * TALITOS_CH_STRIDE + 0x11c0)
95#define TALITOS_GATHER_LO(ch) (ch * TALITOS_CH_STRIDE + 0x11c4)
96
97/* scatter link table */
98#define TALITOS_SCATTER(ch) (ch * TALITOS_CH_STRIDE + 0x11e0)
99#define TALITOS_SCATTER_LO(ch) (ch * TALITOS_CH_STRIDE + 0x11e4)
100
101/* execution unit interrupt status registers */
102#define TALITOS_DEUISR 0x2030 /* DES unit */
103#define TALITOS_DEUISR_LO 0x2034
104#define TALITOS_AESUISR 0x4030 /* AES unit */
105#define TALITOS_AESUISR_LO 0x4034
106#define TALITOS_MDEUISR 0x6030 /* message digest unit */
107#define TALITOS_MDEUISR_LO 0x6034
108#define TALITOS_MDEUICR 0x6038 /* interrupt control */
109#define TALITOS_MDEUICR_LO 0x603c
110#define TALITOS_MDEUICR_LO_ICE 0x4000 /* integrity check IRQ enable */
111#define TALITOS_AFEUISR 0x8030 /* arc4 unit */
112#define TALITOS_AFEUISR_LO 0x8034
113#define TALITOS_RNGUISR 0xa030 /* random number unit */
114#define TALITOS_RNGUISR_LO 0xa034
115#define TALITOS_RNGUSR 0xa028 /* rng status */
116#define TALITOS_RNGUSR_LO 0xa02c
117#define TALITOS_RNGUSR_LO_RD 0x1 /* reset done */
118#define TALITOS_RNGUSR_LO_OFL 0xff0000/* output FIFO length */
119#define TALITOS_RNGUDSR 0xa010 /* data size */
120#define TALITOS_RNGUDSR_LO 0xa014
121#define TALITOS_RNGU_FIFO 0xa800 /* output FIFO */
122#define TALITOS_RNGU_FIFO_LO 0xa804 /* output FIFO */
123#define TALITOS_RNGURCR 0xa018 /* reset control */
124#define TALITOS_RNGURCR_LO 0xa01c
125#define TALITOS_RNGURCR_LO_SR 0x1 /* software reset */
126#define TALITOS_PKEUISR 0xc030 /* public key unit */
127#define TALITOS_PKEUISR_LO 0xc034
128#define TALITOS_KEUISR 0xe030 /* kasumi unit */
129#define TALITOS_KEUISR_LO 0xe034
130#define TALITOS_CRCUISR 0xf030 /* cyclic redundancy check unit*/
131#define TALITOS_CRCUISR_LO 0xf034
132
133#define TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256 0x28
134#define TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512 0x48
135
136/*
137 * talitos descriptor header (hdr) bits
138 */
139
140/* written back when done */
141#define DESC_HDR_DONE cpu_to_be32(0xff000000)
142#define DESC_HDR_LO_ICCR1_MASK cpu_to_be32(0x00180000)
143#define DESC_HDR_LO_ICCR1_PASS cpu_to_be32(0x00080000)
144#define DESC_HDR_LO_ICCR1_FAIL cpu_to_be32(0x00100000)
145
146/* primary execution unit select */
147#define DESC_HDR_SEL0_MASK cpu_to_be32(0xf0000000)
148#define DESC_HDR_SEL0_AFEU cpu_to_be32(0x10000000)
149#define DESC_HDR_SEL0_DEU cpu_to_be32(0x20000000)
150#define DESC_HDR_SEL0_MDEUA cpu_to_be32(0x30000000)
151#define DESC_HDR_SEL0_MDEUB cpu_to_be32(0xb0000000)
152#define DESC_HDR_SEL0_RNG cpu_to_be32(0x40000000)
153#define DESC_HDR_SEL0_PKEU cpu_to_be32(0x50000000)
154#define DESC_HDR_SEL0_AESU cpu_to_be32(0x60000000)
155#define DESC_HDR_SEL0_KEU cpu_to_be32(0x70000000)
156#define DESC_HDR_SEL0_CRCU cpu_to_be32(0x80000000)
157
158/* primary execution unit mode (MODE0) and derivatives */
159#define DESC_HDR_MODE0_ENCRYPT cpu_to_be32(0x00100000)
160#define DESC_HDR_MODE0_AESU_CBC cpu_to_be32(0x00200000)
161#define DESC_HDR_MODE0_DEU_CBC cpu_to_be32(0x00400000)
162#define DESC_HDR_MODE0_DEU_3DES cpu_to_be32(0x00200000)
163#define DESC_HDR_MODE0_MDEU_CONT cpu_to_be32(0x08000000)
164#define DESC_HDR_MODE0_MDEU_INIT cpu_to_be32(0x01000000)
165#define DESC_HDR_MODE0_MDEU_HMAC cpu_to_be32(0x00800000)
166#define DESC_HDR_MODE0_MDEU_PAD cpu_to_be32(0x00400000)
167#define DESC_HDR_MODE0_MDEU_SHA224 cpu_to_be32(0x00300000)
168#define DESC_HDR_MODE0_MDEU_MD5 cpu_to_be32(0x00200000)
169#define DESC_HDR_MODE0_MDEU_SHA256 cpu_to_be32(0x00100000)
170#define DESC_HDR_MODE0_MDEU_SHA1 cpu_to_be32(0x00000000)
171#define DESC_HDR_MODE0_MDEUB_SHA384 cpu_to_be32(0x00000000)
172#define DESC_HDR_MODE0_MDEUB_SHA512 cpu_to_be32(0x00200000)
173#define DESC_HDR_MODE0_MDEU_MD5_HMAC (DESC_HDR_MODE0_MDEU_MD5 | \
174 DESC_HDR_MODE0_MDEU_HMAC)
175#define DESC_HDR_MODE0_MDEU_SHA256_HMAC (DESC_HDR_MODE0_MDEU_SHA256 | \
176 DESC_HDR_MODE0_MDEU_HMAC)
177#define DESC_HDR_MODE0_MDEU_SHA1_HMAC (DESC_HDR_MODE0_MDEU_SHA1 | \
178 DESC_HDR_MODE0_MDEU_HMAC)
179
180/* secondary execution unit select (SEL1) */
181#define DESC_HDR_SEL1_MASK cpu_to_be32(0x000f0000)
182#define DESC_HDR_SEL1_MDEUA cpu_to_be32(0x00030000)
183#define DESC_HDR_SEL1_MDEUB cpu_to_be32(0x000b0000)
184#define DESC_HDR_SEL1_CRCU cpu_to_be32(0x00080000)
185
186/* secondary execution unit mode (MODE1) and derivatives */
187#define DESC_HDR_MODE1_MDEU_CICV cpu_to_be32(0x00004000)
188#define DESC_HDR_MODE1_MDEU_INIT cpu_to_be32(0x00001000)
189#define DESC_HDR_MODE1_MDEU_HMAC cpu_to_be32(0x00000800)
190#define DESC_HDR_MODE1_MDEU_PAD cpu_to_be32(0x00000400)
191#define DESC_HDR_MODE1_MDEU_SHA224 cpu_to_be32(0x00000300)
192#define DESC_HDR_MODE1_MDEU_MD5 cpu_to_be32(0x00000200)
193#define DESC_HDR_MODE1_MDEU_SHA256 cpu_to_be32(0x00000100)
194#define DESC_HDR_MODE1_MDEU_SHA1 cpu_to_be32(0x00000000)
195#define DESC_HDR_MODE1_MDEUB_SHA384 cpu_to_be32(0x00000000)
196#define DESC_HDR_MODE1_MDEUB_SHA512 cpu_to_be32(0x00000200)
197#define DESC_HDR_MODE1_MDEU_MD5_HMAC (DESC_HDR_MODE1_MDEU_MD5 | \
198 DESC_HDR_MODE1_MDEU_HMAC)
199#define DESC_HDR_MODE1_MDEU_SHA256_HMAC (DESC_HDR_MODE1_MDEU_SHA256 | \
200 DESC_HDR_MODE1_MDEU_HMAC)
201#define DESC_HDR_MODE1_MDEU_SHA1_HMAC (DESC_HDR_MODE1_MDEU_SHA1 | \
202 DESC_HDR_MODE1_MDEU_HMAC)
203
204/* direction of overall data flow (DIR) */
205#define DESC_HDR_DIR_INBOUND cpu_to_be32(0x00000002)
206
207/* request done notification (DN) */
208#define DESC_HDR_DONE_NOTIFY cpu_to_be32(0x00000001)
209
210/* descriptor types */
211#define DESC_HDR_TYPE_AESU_CTR_NONSNOOP cpu_to_be32(0 << 3)
212#define DESC_HDR_TYPE_IPSEC_ESP cpu_to_be32(1 << 3)
213#define DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU cpu_to_be32(2 << 3)
214#define DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU cpu_to_be32(4 << 3)
215
216/* link table extent field bits */
217#define DESC_PTR_LNKTBL_JUMP 0x80
218#define DESC_PTR_LNKTBL_RETURN 0x02
219#define DESC_PTR_LNKTBL_NEXT 0x01