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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * copyright (c) 2013 Freescale Semiconductor, Inc.
4 * Freescale IMX AHCI SATA platform driver
5 *
6 * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
7 */
8
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/platform_device.h>
12#include <linux/property.h>
13#include <linux/regmap.h>
14#include <linux/ahci_platform.h>
15#include <linux/gpio/consumer.h>
16#include <linux/of.h>
17#include <linux/mfd/syscon.h>
18#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
19#include <linux/libata.h>
20#include <linux/hwmon.h>
21#include <linux/hwmon-sysfs.h>
22#include <linux/phy/phy.h>
23#include <linux/thermal.h>
24#include "ahci.h"
25
26#define DRV_NAME "ahci-imx"
27
28enum {
29 /* Timer 1-ms Register */
30 IMX_TIMER1MS = 0x00e0,
31 /* Port0 PHY Control Register */
32 IMX_P0PHYCR = 0x0178,
33 IMX_P0PHYCR_TEST_PDDQ = 1 << 20,
34 IMX_P0PHYCR_CR_READ = 1 << 19,
35 IMX_P0PHYCR_CR_WRITE = 1 << 18,
36 IMX_P0PHYCR_CR_CAP_DATA = 1 << 17,
37 IMX_P0PHYCR_CR_CAP_ADDR = 1 << 16,
38 /* Port0 PHY Status Register */
39 IMX_P0PHYSR = 0x017c,
40 IMX_P0PHYSR_CR_ACK = 1 << 18,
41 IMX_P0PHYSR_CR_DATA_OUT = 0xffff << 0,
42 /* Lane0 Output Status Register */
43 IMX_LANE0_OUT_STAT = 0x2003,
44 IMX_LANE0_OUT_STAT_RX_PLL_STATE = 1 << 1,
45 /* Clock Reset Register */
46 IMX_CLOCK_RESET = 0x7f3f,
47 IMX_CLOCK_RESET_RESET = 1 << 0,
48 /* IMX8QM SATA specific control registers */
49 IMX8QM_SATA_AHCI_PTC = 0xc8,
50 IMX8QM_SATA_AHCI_PTC_RXWM_MASK = GENMASK(6, 0),
51 IMX8QM_SATA_AHCI_PTC_RXWM = 0x29,
52};
53
54enum ahci_imx_type {
55 AHCI_IMX53,
56 AHCI_IMX6Q,
57 AHCI_IMX6QP,
58 AHCI_IMX8QM,
59};
60
61struct imx_ahci_priv {
62 struct platform_device *ahci_pdev;
63 enum ahci_imx_type type;
64 struct clk *sata_clk;
65 struct clk *sata_ref_clk;
66 struct clk *ahb_clk;
67 struct regmap *gpr;
68 struct phy *sata_phy;
69 struct phy *cali_phy0;
70 struct phy *cali_phy1;
71 bool no_device;
72 bool first_time;
73 u32 phy_params;
74 u32 imped_ratio;
75};
76
77static int ahci_imx_hotplug;
78module_param_named(hotplug, ahci_imx_hotplug, int, 0644);
79MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support)");
80
81static void ahci_imx_host_stop(struct ata_host *host);
82
83static int imx_phy_crbit_assert(void __iomem *mmio, u32 bit, bool assert)
84{
85 int timeout = 10;
86 u32 crval;
87 u32 srval;
88
89 /* Assert or deassert the bit */
90 crval = readl(mmio + IMX_P0PHYCR);
91 if (assert)
92 crval |= bit;
93 else
94 crval &= ~bit;
95 writel(crval, mmio + IMX_P0PHYCR);
96
97 /* Wait for the cr_ack signal */
98 do {
99 srval = readl(mmio + IMX_P0PHYSR);
100 if ((assert ? srval : ~srval) & IMX_P0PHYSR_CR_ACK)
101 break;
102 usleep_range(100, 200);
103 } while (--timeout);
104
105 return timeout ? 0 : -ETIMEDOUT;
106}
107
108static int imx_phy_reg_addressing(u16 addr, void __iomem *mmio)
109{
110 u32 crval = addr;
111 int ret;
112
113 /* Supply the address on cr_data_in */
114 writel(crval, mmio + IMX_P0PHYCR);
115
116 /* Assert the cr_cap_addr signal */
117 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, true);
118 if (ret)
119 return ret;
120
121 /* Deassert cr_cap_addr */
122 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, false);
123 if (ret)
124 return ret;
125
126 return 0;
127}
128
129static int imx_phy_reg_write(u16 val, void __iomem *mmio)
130{
131 u32 crval = val;
132 int ret;
133
134 /* Supply the data on cr_data_in */
135 writel(crval, mmio + IMX_P0PHYCR);
136
137 /* Assert the cr_cap_data signal */
138 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, true);
139 if (ret)
140 return ret;
141
142 /* Deassert cr_cap_data */
143 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, false);
144 if (ret)
145 return ret;
146
147 if (val & IMX_CLOCK_RESET_RESET) {
148 /*
149 * In case we're resetting the phy, it's unable to acknowledge,
150 * so we return immediately here.
151 */
152 crval |= IMX_P0PHYCR_CR_WRITE;
153 writel(crval, mmio + IMX_P0PHYCR);
154 goto out;
155 }
156
157 /* Assert the cr_write signal */
158 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, true);
159 if (ret)
160 return ret;
161
162 /* Deassert cr_write */
163 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, false);
164 if (ret)
165 return ret;
166
167out:
168 return 0;
169}
170
171static int imx_phy_reg_read(u16 *val, void __iomem *mmio)
172{
173 int ret;
174
175 /* Assert the cr_read signal */
176 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, true);
177 if (ret)
178 return ret;
179
180 /* Capture the data from cr_data_out[] */
181 *val = readl(mmio + IMX_P0PHYSR) & IMX_P0PHYSR_CR_DATA_OUT;
182
183 /* Deassert cr_read */
184 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, false);
185 if (ret)
186 return ret;
187
188 return 0;
189}
190
191static int imx_sata_phy_reset(struct ahci_host_priv *hpriv)
192{
193 struct imx_ahci_priv *imxpriv = hpriv->plat_data;
194 void __iomem *mmio = hpriv->mmio;
195 int timeout = 10;
196 u16 val;
197 int ret;
198
199 if (imxpriv->type == AHCI_IMX6QP) {
200 /* 6qp adds the sata reset mechanism, use it for 6qp sata */
201 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5,
202 IMX6Q_GPR5_SATA_SW_PD, 0);
203
204 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5,
205 IMX6Q_GPR5_SATA_SW_RST, 0);
206 udelay(50);
207 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5,
208 IMX6Q_GPR5_SATA_SW_RST,
209 IMX6Q_GPR5_SATA_SW_RST);
210 return 0;
211 }
212
213 /* Reset SATA PHY by setting RESET bit of PHY register CLOCK_RESET */
214 ret = imx_phy_reg_addressing(IMX_CLOCK_RESET, mmio);
215 if (ret)
216 return ret;
217 ret = imx_phy_reg_write(IMX_CLOCK_RESET_RESET, mmio);
218 if (ret)
219 return ret;
220
221 /* Wait for PHY RX_PLL to be stable */
222 do {
223 usleep_range(100, 200);
224 ret = imx_phy_reg_addressing(IMX_LANE0_OUT_STAT, mmio);
225 if (ret)
226 return ret;
227 ret = imx_phy_reg_read(&val, mmio);
228 if (ret)
229 return ret;
230 if (val & IMX_LANE0_OUT_STAT_RX_PLL_STATE)
231 break;
232 } while (--timeout);
233
234 return timeout ? 0 : -ETIMEDOUT;
235}
236
237enum {
238 /* SATA PHY Register */
239 SATA_PHY_CR_CLOCK_CRCMP_LT_LIMIT = 0x0001,
240 SATA_PHY_CR_CLOCK_DAC_CTL = 0x0008,
241 SATA_PHY_CR_CLOCK_RTUNE_CTL = 0x0009,
242 SATA_PHY_CR_CLOCK_ADC_OUT = 0x000A,
243 SATA_PHY_CR_CLOCK_MPLL_TST = 0x0017,
244};
245
246static int read_adc_sum(void *dev, u16 rtune_ctl_reg, void __iomem * mmio)
247{
248 u16 adc_out_reg, read_sum;
249 u32 index, read_attempt;
250 const u32 attempt_limit = 200;
251
252 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_RTUNE_CTL, mmio);
253 imx_phy_reg_write(rtune_ctl_reg, mmio);
254
255 /* two dummy read */
256 index = 0;
257 read_attempt = 0;
258 adc_out_reg = 0;
259 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_ADC_OUT, mmio);
260 while (index < 2) {
261 imx_phy_reg_read(&adc_out_reg, mmio);
262 /* check if valid */
263 if (adc_out_reg & 0x400)
264 index++;
265
266 read_attempt++;
267 if (read_attempt > attempt_limit) {
268 dev_err(dev, "Read REG more than %d times!\n",
269 attempt_limit);
270 break;
271 }
272 }
273
274 index = 0;
275 read_attempt = 0;
276 read_sum = 0;
277 while (index < 80) {
278 imx_phy_reg_read(&adc_out_reg, mmio);
279 if (adc_out_reg & 0x400) {
280 read_sum = read_sum + (adc_out_reg & 0x3FF);
281 index++;
282 }
283 read_attempt++;
284 if (read_attempt > attempt_limit) {
285 dev_err(dev, "Read REG more than %d times!\n",
286 attempt_limit);
287 break;
288 }
289 }
290
291 /* Use the U32 to make 1000 precision */
292 return (read_sum * 1000) / 80;
293}
294
295/* SATA AHCI temperature monitor */
296static int __sata_ahci_read_temperature(void *dev, int *temp)
297{
298 u16 mpll_test_reg, rtune_ctl_reg, dac_ctl_reg, read_sum;
299 u32 str1, str2, str3, str4;
300 int m1, m2, a;
301 struct ahci_host_priv *hpriv = dev_get_drvdata(dev);
302 void __iomem *mmio = hpriv->mmio;
303
304 /* check rd-wr to reg */
305 read_sum = 0;
306 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_CRCMP_LT_LIMIT, mmio);
307 imx_phy_reg_write(read_sum, mmio);
308 imx_phy_reg_read(&read_sum, mmio);
309 if ((read_sum & 0xffff) != 0)
310 dev_err(dev, "Read/Write REG error, 0x%x!\n", read_sum);
311
312 imx_phy_reg_write(0x5A5A, mmio);
313 imx_phy_reg_read(&read_sum, mmio);
314 if ((read_sum & 0xffff) != 0x5A5A)
315 dev_err(dev, "Read/Write REG error, 0x%x!\n", read_sum);
316
317 imx_phy_reg_write(0x1234, mmio);
318 imx_phy_reg_read(&read_sum, mmio);
319 if ((read_sum & 0xffff) != 0x1234)
320 dev_err(dev, "Read/Write REG error, 0x%x!\n", read_sum);
321
322 /* start temperature test */
323 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_MPLL_TST, mmio);
324 imx_phy_reg_read(&mpll_test_reg, mmio);
325 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_RTUNE_CTL, mmio);
326 imx_phy_reg_read(&rtune_ctl_reg, mmio);
327 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_DAC_CTL, mmio);
328 imx_phy_reg_read(&dac_ctl_reg, mmio);
329
330 /* mpll_tst.meas_iv ([12:2]) */
331 str1 = (mpll_test_reg >> 2) & 0x7FF;
332 /* rtune_ctl.mode ([1:0]) */
333 str2 = (rtune_ctl_reg) & 0x3;
334 /* dac_ctl.dac_mode ([14:12]) */
335 str3 = (dac_ctl_reg >> 12) & 0x7;
336 /* rtune_ctl.sel_atbp ([4]) */
337 str4 = (rtune_ctl_reg >> 4);
338
339 /* Calculate the m1 */
340 /* mpll_tst.meas_iv */
341 mpll_test_reg = (mpll_test_reg & 0xE03) | (512) << 2;
342 /* rtune_ctl.mode */
343 rtune_ctl_reg = (rtune_ctl_reg & 0xFFC) | (1);
344 /* dac_ctl.dac_mode */
345 dac_ctl_reg = (dac_ctl_reg & 0x8FF) | (4) << 12;
346 /* rtune_ctl.sel_atbp */
347 rtune_ctl_reg = (rtune_ctl_reg & 0xFEF) | (0) << 4;
348 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_MPLL_TST, mmio);
349 imx_phy_reg_write(mpll_test_reg, mmio);
350 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_DAC_CTL, mmio);
351 imx_phy_reg_write(dac_ctl_reg, mmio);
352 m1 = read_adc_sum(dev, rtune_ctl_reg, mmio);
353
354 /* Calculate the m2 */
355 /* rtune_ctl.sel_atbp */
356 rtune_ctl_reg = (rtune_ctl_reg & 0xFEF) | (1) << 4;
357 m2 = read_adc_sum(dev, rtune_ctl_reg, mmio);
358
359 /* restore the status */
360 /* mpll_tst.meas_iv */
361 mpll_test_reg = (mpll_test_reg & 0xE03) | (str1) << 2;
362 /* rtune_ctl.mode */
363 rtune_ctl_reg = (rtune_ctl_reg & 0xFFC) | (str2);
364 /* dac_ctl.dac_mode */
365 dac_ctl_reg = (dac_ctl_reg & 0x8FF) | (str3) << 12;
366 /* rtune_ctl.sel_atbp */
367 rtune_ctl_reg = (rtune_ctl_reg & 0xFEF) | (str4) << 4;
368
369 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_MPLL_TST, mmio);
370 imx_phy_reg_write(mpll_test_reg, mmio);
371 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_DAC_CTL, mmio);
372 imx_phy_reg_write(dac_ctl_reg, mmio);
373 imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_RTUNE_CTL, mmio);
374 imx_phy_reg_write(rtune_ctl_reg, mmio);
375
376 /* Compute temperature */
377 if (!(m2 / 1000))
378 m2 = 1000;
379 a = (m2 - m1) / (m2/1000);
380 *temp = ((-559) * a * a) / 1000 + (1379) * a + (-458000);
381
382 return 0;
383}
384
385static int sata_ahci_read_temperature(struct thermal_zone_device *tz, int *temp)
386{
387 return __sata_ahci_read_temperature(thermal_zone_device_priv(tz), temp);
388}
389
390static ssize_t sata_ahci_show_temp(struct device *dev,
391 struct device_attribute *da,
392 char *buf)
393{
394 unsigned int temp = 0;
395 int err;
396
397 err = __sata_ahci_read_temperature(dev, &temp);
398 if (err < 0)
399 return err;
400
401 return sprintf(buf, "%u\n", temp);
402}
403
404static const struct thermal_zone_device_ops fsl_sata_ahci_of_thermal_ops = {
405 .get_temp = sata_ahci_read_temperature,
406};
407
408static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, sata_ahci_show_temp, NULL, 0);
409
410static struct attribute *fsl_sata_ahci_attrs[] = {
411 &sensor_dev_attr_temp1_input.dev_attr.attr,
412 NULL
413};
414ATTRIBUTE_GROUPS(fsl_sata_ahci);
415
416static int imx8_sata_enable(struct ahci_host_priv *hpriv)
417{
418 u32 val;
419 int ret;
420 struct imx_ahci_priv *imxpriv = hpriv->plat_data;
421 struct device *dev = &imxpriv->ahci_pdev->dev;
422
423 /*
424 * Since "REXT" pin is only present for first lane of i.MX8QM
425 * PHY, its calibration results will be stored, passed through
426 * to the second lane PHY, and shared with all three lane PHYs.
427 *
428 * Initialize the first two lane PHYs here, although only the
429 * third lane PHY is used by SATA.
430 */
431 ret = phy_init(imxpriv->cali_phy0);
432 if (ret) {
433 dev_err(dev, "cali PHY init failed\n");
434 return ret;
435 }
436 ret = phy_power_on(imxpriv->cali_phy0);
437 if (ret) {
438 dev_err(dev, "cali PHY power on failed\n");
439 goto err_cali_phy0_exit;
440 }
441 ret = phy_init(imxpriv->cali_phy1);
442 if (ret) {
443 dev_err(dev, "cali PHY1 init failed\n");
444 goto err_cali_phy0_off;
445 }
446 ret = phy_power_on(imxpriv->cali_phy1);
447 if (ret) {
448 dev_err(dev, "cali PHY1 power on failed\n");
449 goto err_cali_phy1_exit;
450 }
451 ret = phy_init(imxpriv->sata_phy);
452 if (ret) {
453 dev_err(dev, "sata PHY init failed\n");
454 goto err_cali_phy1_off;
455 }
456 ret = phy_set_mode(imxpriv->sata_phy, PHY_MODE_SATA);
457 if (ret) {
458 dev_err(dev, "unable to set SATA PHY mode\n");
459 goto err_sata_phy_exit;
460 }
461 ret = phy_power_on(imxpriv->sata_phy);
462 if (ret) {
463 dev_err(dev, "sata PHY power up failed\n");
464 goto err_sata_phy_exit;
465 }
466
467 /* The cali_phy# can be turned off after SATA PHY is initialized. */
468 phy_power_off(imxpriv->cali_phy1);
469 phy_exit(imxpriv->cali_phy1);
470 phy_power_off(imxpriv->cali_phy0);
471 phy_exit(imxpriv->cali_phy0);
472
473 /* RxWaterMark setting */
474 val = readl(hpriv->mmio + IMX8QM_SATA_AHCI_PTC);
475 val &= ~IMX8QM_SATA_AHCI_PTC_RXWM_MASK;
476 val |= IMX8QM_SATA_AHCI_PTC_RXWM;
477 writel(val, hpriv->mmio + IMX8QM_SATA_AHCI_PTC);
478
479 return 0;
480
481err_sata_phy_exit:
482 phy_exit(imxpriv->sata_phy);
483err_cali_phy1_off:
484 phy_power_off(imxpriv->cali_phy1);
485err_cali_phy1_exit:
486 phy_exit(imxpriv->cali_phy1);
487err_cali_phy0_off:
488 phy_power_off(imxpriv->cali_phy0);
489err_cali_phy0_exit:
490 phy_exit(imxpriv->cali_phy0);
491
492 return ret;
493}
494
495static int imx_sata_enable(struct ahci_host_priv *hpriv)
496{
497 struct imx_ahci_priv *imxpriv = hpriv->plat_data;
498 struct device *dev = &imxpriv->ahci_pdev->dev;
499 int ret;
500
501 if (imxpriv->no_device)
502 return 0;
503
504 ret = ahci_platform_enable_regulators(hpriv);
505 if (ret)
506 return ret;
507
508 ret = clk_prepare_enable(imxpriv->sata_ref_clk);
509 if (ret < 0)
510 goto disable_regulator;
511
512 if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) {
513 /*
514 * set PHY Parameters, two steps to configure the GPR13,
515 * one write for rest of parameters, mask of first write
516 * is 0x07ffffff, and the other one write for setting
517 * the mpll_clk_en.
518 */
519 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
520 IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK |
521 IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK |
522 IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK |
523 IMX6Q_GPR13_SATA_SPD_MODE_MASK |
524 IMX6Q_GPR13_SATA_MPLL_SS_EN |
525 IMX6Q_GPR13_SATA_TX_ATTEN_MASK |
526 IMX6Q_GPR13_SATA_TX_BOOST_MASK |
527 IMX6Q_GPR13_SATA_TX_LVL_MASK |
528 IMX6Q_GPR13_SATA_MPLL_CLK_EN |
529 IMX6Q_GPR13_SATA_TX_EDGE_RATE,
530 imxpriv->phy_params);
531 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
532 IMX6Q_GPR13_SATA_MPLL_CLK_EN,
533 IMX6Q_GPR13_SATA_MPLL_CLK_EN);
534
535 usleep_range(100, 200);
536
537 ret = imx_sata_phy_reset(hpriv);
538 if (ret) {
539 dev_err(dev, "failed to reset phy: %d\n", ret);
540 goto disable_clk;
541 }
542 } else if (imxpriv->type == AHCI_IMX8QM) {
543 ret = imx8_sata_enable(hpriv);
544 if (ret)
545 goto disable_clk;
546
547 }
548
549 usleep_range(1000, 2000);
550
551 return 0;
552
553disable_clk:
554 clk_disable_unprepare(imxpriv->sata_ref_clk);
555disable_regulator:
556 ahci_platform_disable_regulators(hpriv);
557
558 return ret;
559}
560
561static void imx_sata_disable(struct ahci_host_priv *hpriv)
562{
563 struct imx_ahci_priv *imxpriv = hpriv->plat_data;
564
565 if (imxpriv->no_device)
566 return;
567
568 switch (imxpriv->type) {
569 case AHCI_IMX6QP:
570 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5,
571 IMX6Q_GPR5_SATA_SW_PD,
572 IMX6Q_GPR5_SATA_SW_PD);
573 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
574 IMX6Q_GPR13_SATA_MPLL_CLK_EN,
575 !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
576 break;
577
578 case AHCI_IMX6Q:
579 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
580 IMX6Q_GPR13_SATA_MPLL_CLK_EN,
581 !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
582 break;
583
584 case AHCI_IMX8QM:
585 if (imxpriv->sata_phy) {
586 phy_power_off(imxpriv->sata_phy);
587 phy_exit(imxpriv->sata_phy);
588 }
589 break;
590
591 default:
592 break;
593 }
594
595 clk_disable_unprepare(imxpriv->sata_ref_clk);
596
597 ahci_platform_disable_regulators(hpriv);
598}
599
600static void ahci_imx_error_handler(struct ata_port *ap)
601{
602 u32 reg_val;
603 struct ata_device *dev;
604 struct ata_host *host = dev_get_drvdata(ap->dev);
605 struct ahci_host_priv *hpriv = host->private_data;
606 void __iomem *mmio = hpriv->mmio;
607 struct imx_ahci_priv *imxpriv = hpriv->plat_data;
608
609 ahci_error_handler(ap);
610
611 if (imxpriv->type == AHCI_IMX8QM)
612 return;
613
614 if (!(imxpriv->first_time) || ahci_imx_hotplug)
615 return;
616
617 imxpriv->first_time = false;
618
619 ata_for_each_dev(dev, &ap->link, ENABLED)
620 return;
621 /*
622 * Disable link to save power. An imx ahci port can't be recovered
623 * without full reset once the pddq mode is enabled making it
624 * impossible to use as part of libata LPM.
625 */
626 reg_val = readl(mmio + IMX_P0PHYCR);
627 writel(reg_val | IMX_P0PHYCR_TEST_PDDQ, mmio + IMX_P0PHYCR);
628 imx_sata_disable(hpriv);
629 imxpriv->no_device = true;
630
631 dev_info(ap->dev, "no device found, disabling link.\n");
632 dev_info(ap->dev, "pass " MODULE_PARAM_PREFIX ".hotplug=1 to enable hotplug\n");
633}
634
635static int ahci_imx_softreset(struct ata_link *link, unsigned int *class,
636 unsigned long deadline)
637{
638 struct ata_port *ap = link->ap;
639 struct ata_host *host = dev_get_drvdata(ap->dev);
640 struct ahci_host_priv *hpriv = host->private_data;
641 struct imx_ahci_priv *imxpriv = hpriv->plat_data;
642 int ret;
643
644 if (imxpriv->type == AHCI_IMX53)
645 ret = ahci_pmp_retry_srst_ops.softreset(link, class, deadline);
646 else
647 ret = ahci_ops.softreset(link, class, deadline);
648
649 return ret;
650}
651
652static struct ata_port_operations ahci_imx_ops = {
653 .inherits = &ahci_ops,
654 .host_stop = ahci_imx_host_stop,
655 .error_handler = ahci_imx_error_handler,
656 .softreset = ahci_imx_softreset,
657};
658
659static const struct ata_port_info ahci_imx_port_info = {
660 .flags = AHCI_FLAG_COMMON,
661 .pio_mask = ATA_PIO4,
662 .udma_mask = ATA_UDMA6,
663 .port_ops = &ahci_imx_ops,
664};
665
666static const struct of_device_id imx_ahci_of_match[] = {
667 { .compatible = "fsl,imx53-ahci", .data = (void *)AHCI_IMX53 },
668 { .compatible = "fsl,imx6q-ahci", .data = (void *)AHCI_IMX6Q },
669 { .compatible = "fsl,imx6qp-ahci", .data = (void *)AHCI_IMX6QP },
670 { .compatible = "fsl,imx8qm-ahci", .data = (void *)AHCI_IMX8QM },
671 { /* sentinel */ }
672};
673MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
674
675struct reg_value {
676 u32 of_value;
677 u32 reg_value;
678};
679
680struct reg_property {
681 const char *name;
682 const struct reg_value *values;
683 size_t num_values;
684 u32 def_value;
685 u32 set_value;
686};
687
688static const struct reg_value gpr13_tx_level[] = {
689 { 937, IMX6Q_GPR13_SATA_TX_LVL_0_937_V },
690 { 947, IMX6Q_GPR13_SATA_TX_LVL_0_947_V },
691 { 957, IMX6Q_GPR13_SATA_TX_LVL_0_957_V },
692 { 966, IMX6Q_GPR13_SATA_TX_LVL_0_966_V },
693 { 976, IMX6Q_GPR13_SATA_TX_LVL_0_976_V },
694 { 986, IMX6Q_GPR13_SATA_TX_LVL_0_986_V },
695 { 996, IMX6Q_GPR13_SATA_TX_LVL_0_996_V },
696 { 1005, IMX6Q_GPR13_SATA_TX_LVL_1_005_V },
697 { 1015, IMX6Q_GPR13_SATA_TX_LVL_1_015_V },
698 { 1025, IMX6Q_GPR13_SATA_TX_LVL_1_025_V },
699 { 1035, IMX6Q_GPR13_SATA_TX_LVL_1_035_V },
700 { 1045, IMX6Q_GPR13_SATA_TX_LVL_1_045_V },
701 { 1054, IMX6Q_GPR13_SATA_TX_LVL_1_054_V },
702 { 1064, IMX6Q_GPR13_SATA_TX_LVL_1_064_V },
703 { 1074, IMX6Q_GPR13_SATA_TX_LVL_1_074_V },
704 { 1084, IMX6Q_GPR13_SATA_TX_LVL_1_084_V },
705 { 1094, IMX6Q_GPR13_SATA_TX_LVL_1_094_V },
706 { 1104, IMX6Q_GPR13_SATA_TX_LVL_1_104_V },
707 { 1113, IMX6Q_GPR13_SATA_TX_LVL_1_113_V },
708 { 1123, IMX6Q_GPR13_SATA_TX_LVL_1_123_V },
709 { 1133, IMX6Q_GPR13_SATA_TX_LVL_1_133_V },
710 { 1143, IMX6Q_GPR13_SATA_TX_LVL_1_143_V },
711 { 1152, IMX6Q_GPR13_SATA_TX_LVL_1_152_V },
712 { 1162, IMX6Q_GPR13_SATA_TX_LVL_1_162_V },
713 { 1172, IMX6Q_GPR13_SATA_TX_LVL_1_172_V },
714 { 1182, IMX6Q_GPR13_SATA_TX_LVL_1_182_V },
715 { 1191, IMX6Q_GPR13_SATA_TX_LVL_1_191_V },
716 { 1201, IMX6Q_GPR13_SATA_TX_LVL_1_201_V },
717 { 1211, IMX6Q_GPR13_SATA_TX_LVL_1_211_V },
718 { 1221, IMX6Q_GPR13_SATA_TX_LVL_1_221_V },
719 { 1230, IMX6Q_GPR13_SATA_TX_LVL_1_230_V },
720 { 1240, IMX6Q_GPR13_SATA_TX_LVL_1_240_V }
721};
722
723static const struct reg_value gpr13_tx_boost[] = {
724 { 0, IMX6Q_GPR13_SATA_TX_BOOST_0_00_DB },
725 { 370, IMX6Q_GPR13_SATA_TX_BOOST_0_37_DB },
726 { 740, IMX6Q_GPR13_SATA_TX_BOOST_0_74_DB },
727 { 1110, IMX6Q_GPR13_SATA_TX_BOOST_1_11_DB },
728 { 1480, IMX6Q_GPR13_SATA_TX_BOOST_1_48_DB },
729 { 1850, IMX6Q_GPR13_SATA_TX_BOOST_1_85_DB },
730 { 2220, IMX6Q_GPR13_SATA_TX_BOOST_2_22_DB },
731 { 2590, IMX6Q_GPR13_SATA_TX_BOOST_2_59_DB },
732 { 2960, IMX6Q_GPR13_SATA_TX_BOOST_2_96_DB },
733 { 3330, IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB },
734 { 3700, IMX6Q_GPR13_SATA_TX_BOOST_3_70_DB },
735 { 4070, IMX6Q_GPR13_SATA_TX_BOOST_4_07_DB },
736 { 4440, IMX6Q_GPR13_SATA_TX_BOOST_4_44_DB },
737 { 4810, IMX6Q_GPR13_SATA_TX_BOOST_4_81_DB },
738 { 5280, IMX6Q_GPR13_SATA_TX_BOOST_5_28_DB },
739 { 5750, IMX6Q_GPR13_SATA_TX_BOOST_5_75_DB }
740};
741
742static const struct reg_value gpr13_tx_atten[] = {
743 { 8, IMX6Q_GPR13_SATA_TX_ATTEN_8_16 },
744 { 9, IMX6Q_GPR13_SATA_TX_ATTEN_9_16 },
745 { 10, IMX6Q_GPR13_SATA_TX_ATTEN_10_16 },
746 { 12, IMX6Q_GPR13_SATA_TX_ATTEN_12_16 },
747 { 14, IMX6Q_GPR13_SATA_TX_ATTEN_14_16 },
748 { 16, IMX6Q_GPR13_SATA_TX_ATTEN_16_16 },
749};
750
751static const struct reg_value gpr13_rx_eq[] = {
752 { 500, IMX6Q_GPR13_SATA_RX_EQ_VAL_0_5_DB },
753 { 1000, IMX6Q_GPR13_SATA_RX_EQ_VAL_1_0_DB },
754 { 1500, IMX6Q_GPR13_SATA_RX_EQ_VAL_1_5_DB },
755 { 2000, IMX6Q_GPR13_SATA_RX_EQ_VAL_2_0_DB },
756 { 2500, IMX6Q_GPR13_SATA_RX_EQ_VAL_2_5_DB },
757 { 3000, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB },
758 { 3500, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_5_DB },
759 { 4000, IMX6Q_GPR13_SATA_RX_EQ_VAL_4_0_DB },
760};
761
762static const struct reg_property gpr13_props[] = {
763 {
764 .name = "fsl,transmit-level-mV",
765 .values = gpr13_tx_level,
766 .num_values = ARRAY_SIZE(gpr13_tx_level),
767 .def_value = IMX6Q_GPR13_SATA_TX_LVL_1_025_V,
768 }, {
769 .name = "fsl,transmit-boost-mdB",
770 .values = gpr13_tx_boost,
771 .num_values = ARRAY_SIZE(gpr13_tx_boost),
772 .def_value = IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB,
773 }, {
774 .name = "fsl,transmit-atten-16ths",
775 .values = gpr13_tx_atten,
776 .num_values = ARRAY_SIZE(gpr13_tx_atten),
777 .def_value = IMX6Q_GPR13_SATA_TX_ATTEN_9_16,
778 }, {
779 .name = "fsl,receive-eq-mdB",
780 .values = gpr13_rx_eq,
781 .num_values = ARRAY_SIZE(gpr13_rx_eq),
782 .def_value = IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB,
783 }, {
784 .name = "fsl,no-spread-spectrum",
785 .def_value = IMX6Q_GPR13_SATA_MPLL_SS_EN,
786 .set_value = 0,
787 },
788};
789
790static u32 imx_ahci_parse_props(struct device *dev,
791 const struct reg_property *prop, size_t num)
792{
793 struct device_node *np = dev->of_node;
794 u32 reg_value = 0;
795 int i, j;
796
797 for (i = 0; i < num; i++, prop++) {
798 u32 of_val;
799
800 if (prop->num_values == 0) {
801 if (of_property_read_bool(np, prop->name))
802 reg_value |= prop->set_value;
803 else
804 reg_value |= prop->def_value;
805 continue;
806 }
807
808 if (of_property_read_u32(np, prop->name, &of_val)) {
809 dev_info(dev, "%s not specified, using %08x\n",
810 prop->name, prop->def_value);
811 reg_value |= prop->def_value;
812 continue;
813 }
814
815 for (j = 0; j < prop->num_values; j++) {
816 if (prop->values[j].of_value == of_val) {
817 dev_info(dev, "%s value %u, using %08x\n",
818 prop->name, of_val, prop->values[j].reg_value);
819 reg_value |= prop->values[j].reg_value;
820 break;
821 }
822 }
823
824 if (j == prop->num_values) {
825 dev_err(dev, "DT property %s is not a valid value\n",
826 prop->name);
827 reg_value |= prop->def_value;
828 }
829 }
830
831 return reg_value;
832}
833
834static const struct scsi_host_template ahci_platform_sht = {
835 AHCI_SHT(DRV_NAME),
836};
837
838static int imx8_sata_probe(struct device *dev, struct imx_ahci_priv *imxpriv)
839{
840 imxpriv->sata_phy = devm_phy_get(dev, "sata-phy");
841 if (IS_ERR(imxpriv->sata_phy))
842 return dev_err_probe(dev, PTR_ERR(imxpriv->sata_phy),
843 "Failed to get sata_phy\n");
844
845 imxpriv->cali_phy0 = devm_phy_get(dev, "cali-phy0");
846 if (IS_ERR(imxpriv->cali_phy0))
847 return dev_err_probe(dev, PTR_ERR(imxpriv->cali_phy0),
848 "Failed to get cali_phy0\n");
849 imxpriv->cali_phy1 = devm_phy_get(dev, "cali-phy1");
850 if (IS_ERR(imxpriv->cali_phy1))
851 return dev_err_probe(dev, PTR_ERR(imxpriv->cali_phy1),
852 "Failed to get cali_phy1\n");
853 return 0;
854}
855
856static int imx_ahci_probe(struct platform_device *pdev)
857{
858 struct device *dev = &pdev->dev;
859 struct ahci_host_priv *hpriv;
860 struct imx_ahci_priv *imxpriv;
861 unsigned int reg_val;
862 int ret;
863
864 imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
865 if (!imxpriv)
866 return -ENOMEM;
867
868 imxpriv->ahci_pdev = pdev;
869 imxpriv->no_device = false;
870 imxpriv->first_time = true;
871 imxpriv->type = (enum ahci_imx_type)device_get_match_data(dev);
872
873 imxpriv->sata_clk = devm_clk_get(dev, "sata");
874 if (IS_ERR(imxpriv->sata_clk)) {
875 dev_err(dev, "can't get sata clock.\n");
876 return PTR_ERR(imxpriv->sata_clk);
877 }
878
879 imxpriv->sata_ref_clk = devm_clk_get(dev, "sata_ref");
880 if (IS_ERR(imxpriv->sata_ref_clk)) {
881 dev_err(dev, "can't get sata_ref clock.\n");
882 return PTR_ERR(imxpriv->sata_ref_clk);
883 }
884
885 if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) {
886 u32 reg_value;
887
888 imxpriv->gpr = syscon_regmap_lookup_by_compatible(
889 "fsl,imx6q-iomuxc-gpr");
890 if (IS_ERR(imxpriv->gpr)) {
891 dev_err(dev,
892 "failed to find fsl,imx6q-iomux-gpr regmap\n");
893 return PTR_ERR(imxpriv->gpr);
894 }
895
896 reg_value = imx_ahci_parse_props(dev, gpr13_props,
897 ARRAY_SIZE(gpr13_props));
898
899 imxpriv->phy_params =
900 IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M |
901 IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F |
902 IMX6Q_GPR13_SATA_SPD_MODE_3P0G |
903 reg_value;
904 } else if (imxpriv->type == AHCI_IMX8QM) {
905 ret = imx8_sata_probe(dev, imxpriv);
906 if (ret)
907 return ret;
908 }
909
910 hpriv = ahci_platform_get_resources(pdev, 0);
911 if (IS_ERR(hpriv))
912 return PTR_ERR(hpriv);
913
914 hpriv->plat_data = imxpriv;
915
916 ret = clk_prepare_enable(imxpriv->sata_clk);
917 if (ret)
918 return ret;
919
920 if (imxpriv->type == AHCI_IMX53 &&
921 IS_ENABLED(CONFIG_HWMON)) {
922 /* Add the temperature monitor */
923 struct device *hwmon_dev;
924
925 hwmon_dev =
926 devm_hwmon_device_register_with_groups(dev,
927 "sata_ahci",
928 hpriv,
929 fsl_sata_ahci_groups);
930 if (IS_ERR(hwmon_dev)) {
931 ret = PTR_ERR(hwmon_dev);
932 goto disable_clk;
933 }
934 devm_thermal_of_zone_register(hwmon_dev, 0, hwmon_dev,
935 &fsl_sata_ahci_of_thermal_ops);
936 dev_info(dev, "%s: sensor 'sata_ahci'\n", dev_name(hwmon_dev));
937 }
938
939 ret = imx_sata_enable(hpriv);
940 if (ret)
941 goto disable_clk;
942
943 /*
944 * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL.
945 * Set CAP_SSS (support stagered spin up) and Implement the port0.
946 */
947 reg_val = readl(hpriv->mmio + HOST_CAP);
948 if (!(reg_val & HOST_CAP_SSS)) {
949 reg_val |= HOST_CAP_SSS;
950 writel(reg_val, hpriv->mmio + HOST_CAP);
951 }
952 reg_val = readl(hpriv->mmio + HOST_PORTS_IMPL);
953 if (!(reg_val & 0x1)) {
954 reg_val |= 0x1;
955 writel(reg_val, hpriv->mmio + HOST_PORTS_IMPL);
956 }
957
958 if (imxpriv->type != AHCI_IMX8QM) {
959 /*
960 * Get AHB clock rate and configure the vendor specified
961 * TIMER1MS register on i.MX53, i.MX6Q and i.MX6QP only.
962 */
963 imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
964 if (IS_ERR(imxpriv->ahb_clk)) {
965 dev_err(dev, "Failed to get ahb clock\n");
966 ret = PTR_ERR(imxpriv->ahb_clk);
967 goto disable_sata;
968 }
969 reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
970 writel(reg_val, hpriv->mmio + IMX_TIMER1MS);
971 }
972
973 ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info,
974 &ahci_platform_sht);
975 if (ret)
976 goto disable_sata;
977
978 return 0;
979
980disable_sata:
981 imx_sata_disable(hpriv);
982disable_clk:
983 clk_disable_unprepare(imxpriv->sata_clk);
984 return ret;
985}
986
987static void ahci_imx_host_stop(struct ata_host *host)
988{
989 struct ahci_host_priv *hpriv = host->private_data;
990 struct imx_ahci_priv *imxpriv = hpriv->plat_data;
991
992 imx_sata_disable(hpriv);
993 clk_disable_unprepare(imxpriv->sata_clk);
994}
995
996#ifdef CONFIG_PM_SLEEP
997static int imx_ahci_suspend(struct device *dev)
998{
999 struct ata_host *host = dev_get_drvdata(dev);
1000 struct ahci_host_priv *hpriv = host->private_data;
1001 int ret;
1002
1003 ret = ahci_platform_suspend_host(dev);
1004 if (ret)
1005 return ret;
1006
1007 imx_sata_disable(hpriv);
1008
1009 return 0;
1010}
1011
1012static int imx_ahci_resume(struct device *dev)
1013{
1014 struct ata_host *host = dev_get_drvdata(dev);
1015 struct ahci_host_priv *hpriv = host->private_data;
1016 int ret;
1017
1018 ret = imx_sata_enable(hpriv);
1019 if (ret)
1020 return ret;
1021
1022 return ahci_platform_resume_host(dev);
1023}
1024#endif
1025
1026static SIMPLE_DEV_PM_OPS(ahci_imx_pm_ops, imx_ahci_suspend, imx_ahci_resume);
1027
1028static struct platform_driver imx_ahci_driver = {
1029 .probe = imx_ahci_probe,
1030 .remove = ata_platform_remove_one,
1031 .driver = {
1032 .name = DRV_NAME,
1033 .of_match_table = imx_ahci_of_match,
1034 .pm = &ahci_imx_pm_ops,
1035 },
1036};
1037module_platform_driver(imx_ahci_driver);
1038
1039MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver");
1040MODULE_AUTHOR("Richard Zhu <hongxing.zhu@nxp.com>");
1041MODULE_LICENSE("GPL");
1042MODULE_ALIAS("platform:" DRV_NAME);