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1/*
2 * arch/arm/mach-at91/at91sam9rl.c
3 *
4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2007 Atmel Corporation
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive for
9 * more details.
10 */
11
12#include <linux/module.h>
13#include <linux/pm.h>
14
15#include <asm/irq.h>
16#include <asm/mach/arch.h>
17#include <asm/mach/map.h>
18#include <mach/cpu.h>
19#include <mach/at91_dbgu.h>
20#include <mach/at91sam9rl.h>
21#include <mach/at91_pmc.h>
22#include <mach/at91_rstc.h>
23#include <mach/at91_shdwc.h>
24
25#include "soc.h"
26#include "generic.h"
27#include "clock.h"
28
29/* --------------------------------------------------------------------
30 * Clocks
31 * -------------------------------------------------------------------- */
32
33/*
34 * The peripheral clocks.
35 */
36static struct clk pioA_clk = {
37 .name = "pioA_clk",
38 .pmc_mask = 1 << AT91SAM9RL_ID_PIOA,
39 .type = CLK_TYPE_PERIPHERAL,
40};
41static struct clk pioB_clk = {
42 .name = "pioB_clk",
43 .pmc_mask = 1 << AT91SAM9RL_ID_PIOB,
44 .type = CLK_TYPE_PERIPHERAL,
45};
46static struct clk pioC_clk = {
47 .name = "pioC_clk",
48 .pmc_mask = 1 << AT91SAM9RL_ID_PIOC,
49 .type = CLK_TYPE_PERIPHERAL,
50};
51static struct clk pioD_clk = {
52 .name = "pioD_clk",
53 .pmc_mask = 1 << AT91SAM9RL_ID_PIOD,
54 .type = CLK_TYPE_PERIPHERAL,
55};
56static struct clk usart0_clk = {
57 .name = "usart0_clk",
58 .pmc_mask = 1 << AT91SAM9RL_ID_US0,
59 .type = CLK_TYPE_PERIPHERAL,
60};
61static struct clk usart1_clk = {
62 .name = "usart1_clk",
63 .pmc_mask = 1 << AT91SAM9RL_ID_US1,
64 .type = CLK_TYPE_PERIPHERAL,
65};
66static struct clk usart2_clk = {
67 .name = "usart2_clk",
68 .pmc_mask = 1 << AT91SAM9RL_ID_US2,
69 .type = CLK_TYPE_PERIPHERAL,
70};
71static struct clk usart3_clk = {
72 .name = "usart3_clk",
73 .pmc_mask = 1 << AT91SAM9RL_ID_US3,
74 .type = CLK_TYPE_PERIPHERAL,
75};
76static struct clk mmc_clk = {
77 .name = "mci_clk",
78 .pmc_mask = 1 << AT91SAM9RL_ID_MCI,
79 .type = CLK_TYPE_PERIPHERAL,
80};
81static struct clk twi0_clk = {
82 .name = "twi0_clk",
83 .pmc_mask = 1 << AT91SAM9RL_ID_TWI0,
84 .type = CLK_TYPE_PERIPHERAL,
85};
86static struct clk twi1_clk = {
87 .name = "twi1_clk",
88 .pmc_mask = 1 << AT91SAM9RL_ID_TWI1,
89 .type = CLK_TYPE_PERIPHERAL,
90};
91static struct clk spi_clk = {
92 .name = "spi_clk",
93 .pmc_mask = 1 << AT91SAM9RL_ID_SPI,
94 .type = CLK_TYPE_PERIPHERAL,
95};
96static struct clk ssc0_clk = {
97 .name = "ssc0_clk",
98 .pmc_mask = 1 << AT91SAM9RL_ID_SSC0,
99 .type = CLK_TYPE_PERIPHERAL,
100};
101static struct clk ssc1_clk = {
102 .name = "ssc1_clk",
103 .pmc_mask = 1 << AT91SAM9RL_ID_SSC1,
104 .type = CLK_TYPE_PERIPHERAL,
105};
106static struct clk tc0_clk = {
107 .name = "tc0_clk",
108 .pmc_mask = 1 << AT91SAM9RL_ID_TC0,
109 .type = CLK_TYPE_PERIPHERAL,
110};
111static struct clk tc1_clk = {
112 .name = "tc1_clk",
113 .pmc_mask = 1 << AT91SAM9RL_ID_TC1,
114 .type = CLK_TYPE_PERIPHERAL,
115};
116static struct clk tc2_clk = {
117 .name = "tc2_clk",
118 .pmc_mask = 1 << AT91SAM9RL_ID_TC2,
119 .type = CLK_TYPE_PERIPHERAL,
120};
121static struct clk pwm_clk = {
122 .name = "pwm_clk",
123 .pmc_mask = 1 << AT91SAM9RL_ID_PWMC,
124 .type = CLK_TYPE_PERIPHERAL,
125};
126static struct clk tsc_clk = {
127 .name = "tsc_clk",
128 .pmc_mask = 1 << AT91SAM9RL_ID_TSC,
129 .type = CLK_TYPE_PERIPHERAL,
130};
131static struct clk dma_clk = {
132 .name = "dma_clk",
133 .pmc_mask = 1 << AT91SAM9RL_ID_DMA,
134 .type = CLK_TYPE_PERIPHERAL,
135};
136static struct clk udphs_clk = {
137 .name = "udphs_clk",
138 .pmc_mask = 1 << AT91SAM9RL_ID_UDPHS,
139 .type = CLK_TYPE_PERIPHERAL,
140};
141static struct clk lcdc_clk = {
142 .name = "lcdc_clk",
143 .pmc_mask = 1 << AT91SAM9RL_ID_LCDC,
144 .type = CLK_TYPE_PERIPHERAL,
145};
146static struct clk ac97_clk = {
147 .name = "ac97_clk",
148 .pmc_mask = 1 << AT91SAM9RL_ID_AC97C,
149 .type = CLK_TYPE_PERIPHERAL,
150};
151
152static struct clk *periph_clocks[] __initdata = {
153 &pioA_clk,
154 &pioB_clk,
155 &pioC_clk,
156 &pioD_clk,
157 &usart0_clk,
158 &usart1_clk,
159 &usart2_clk,
160 &usart3_clk,
161 &mmc_clk,
162 &twi0_clk,
163 &twi1_clk,
164 &spi_clk,
165 &ssc0_clk,
166 &ssc1_clk,
167 &tc0_clk,
168 &tc1_clk,
169 &tc2_clk,
170 &pwm_clk,
171 &tsc_clk,
172 &dma_clk,
173 &udphs_clk,
174 &lcdc_clk,
175 &ac97_clk,
176 // irq0
177};
178
179static struct clk_lookup periph_clocks_lookups[] = {
180 CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
181 CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
182 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
183 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
184 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
185 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
186 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
187};
188
189static struct clk_lookup usart_clocks_lookups[] = {
190 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
191 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
192 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
193 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
194 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
195};
196
197/*
198 * The two programmable clocks.
199 * You must configure pin multiplexing to bring these signals out.
200 */
201static struct clk pck0 = {
202 .name = "pck0",
203 .pmc_mask = AT91_PMC_PCK0,
204 .type = CLK_TYPE_PROGRAMMABLE,
205 .id = 0,
206};
207static struct clk pck1 = {
208 .name = "pck1",
209 .pmc_mask = AT91_PMC_PCK1,
210 .type = CLK_TYPE_PROGRAMMABLE,
211 .id = 1,
212};
213
214static void __init at91sam9rl_register_clocks(void)
215{
216 int i;
217
218 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
219 clk_register(periph_clocks[i]);
220
221 clkdev_add_table(periph_clocks_lookups,
222 ARRAY_SIZE(periph_clocks_lookups));
223 clkdev_add_table(usart_clocks_lookups,
224 ARRAY_SIZE(usart_clocks_lookups));
225
226 clk_register(&pck0);
227 clk_register(&pck1);
228}
229
230static struct clk_lookup console_clock_lookup;
231
232void __init at91sam9rl_set_console_clock(int id)
233{
234 if (id >= ARRAY_SIZE(usart_clocks_lookups))
235 return;
236
237 console_clock_lookup.con_id = "usart";
238 console_clock_lookup.clk = usart_clocks_lookups[id].clk;
239 clkdev_add(&console_clock_lookup);
240}
241
242/* --------------------------------------------------------------------
243 * GPIO
244 * -------------------------------------------------------------------- */
245
246static struct at91_gpio_bank at91sam9rl_gpio[] = {
247 {
248 .id = AT91SAM9RL_ID_PIOA,
249 .offset = AT91_PIOA,
250 .clock = &pioA_clk,
251 }, {
252 .id = AT91SAM9RL_ID_PIOB,
253 .offset = AT91_PIOB,
254 .clock = &pioB_clk,
255 }, {
256 .id = AT91SAM9RL_ID_PIOC,
257 .offset = AT91_PIOC,
258 .clock = &pioC_clk,
259 }, {
260 .id = AT91SAM9RL_ID_PIOD,
261 .offset = AT91_PIOD,
262 .clock = &pioD_clk,
263 }
264};
265
266static void at91sam9rl_poweroff(void)
267{
268 at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
269}
270
271
272/* --------------------------------------------------------------------
273 * AT91SAM9RL processor initialization
274 * -------------------------------------------------------------------- */
275
276static void __init at91sam9rl_map_io(void)
277{
278 unsigned long sram_size;
279
280 switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
281 case AT91_CIDR_SRAMSIZ_32K:
282 sram_size = 2 * SZ_16K;
283 break;
284 case AT91_CIDR_SRAMSIZ_16K:
285 default:
286 sram_size = SZ_16K;
287 }
288
289 /* Map SRAM */
290 at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size);
291}
292
293static void __init at91sam9rl_initialize(void)
294{
295 at91_arch_reset = at91sam9_alt_reset;
296 pm_power_off = at91sam9rl_poweroff;
297 at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
298
299 /* Register GPIO subsystem */
300 at91_gpio_init(at91sam9rl_gpio, 4);
301}
302
303/* --------------------------------------------------------------------
304 * Interrupt initialization
305 * -------------------------------------------------------------------- */
306
307/*
308 * The default interrupt priority levels (0 = lowest, 7 = highest).
309 */
310static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
311 7, /* Advanced Interrupt Controller */
312 7, /* System Peripherals */
313 1, /* Parallel IO Controller A */
314 1, /* Parallel IO Controller B */
315 1, /* Parallel IO Controller C */
316 1, /* Parallel IO Controller D */
317 5, /* USART 0 */
318 5, /* USART 1 */
319 5, /* USART 2 */
320 5, /* USART 3 */
321 0, /* Multimedia Card Interface */
322 6, /* Two-Wire Interface 0 */
323 6, /* Two-Wire Interface 1 */
324 5, /* Serial Peripheral Interface */
325 4, /* Serial Synchronous Controller 0 */
326 4, /* Serial Synchronous Controller 1 */
327 0, /* Timer Counter 0 */
328 0, /* Timer Counter 1 */
329 0, /* Timer Counter 2 */
330 0,
331 0, /* Touch Screen Controller */
332 0, /* DMA Controller */
333 2, /* USB Device High speed port */
334 2, /* LCD Controller */
335 6, /* AC97 Controller */
336 0,
337 0,
338 0,
339 0,
340 0,
341 0,
342 0, /* Advanced Interrupt Controller */
343};
344
345struct at91_init_soc __initdata at91sam9rl_soc = {
346 .map_io = at91sam9rl_map_io,
347 .default_irq_priority = at91sam9rl_default_irq_priority,
348 .register_clocks = at91sam9rl_register_clocks,
349 .init = at91sam9rl_initialize,
350};