Loading...
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * arch/arm/include/asm/tlbflush.h
4 *
5 * Copyright (C) 1999-2003 Russell King
6 */
7#ifndef _ASMARM_TLBFLUSH_H
8#define _ASMARM_TLBFLUSH_H
9
10#ifndef __ASSEMBLY__
11# include <linux/mm_types.h>
12#endif
13
14#ifdef CONFIG_MMU
15
16#include <asm/glue.h>
17
18#define TLB_V4_U_PAGE (1 << 1)
19#define TLB_V4_D_PAGE (1 << 2)
20#define TLB_V4_I_PAGE (1 << 3)
21#define TLB_V6_U_PAGE (1 << 4)
22#define TLB_V6_D_PAGE (1 << 5)
23#define TLB_V6_I_PAGE (1 << 6)
24
25#define TLB_V4_U_FULL (1 << 9)
26#define TLB_V4_D_FULL (1 << 10)
27#define TLB_V4_I_FULL (1 << 11)
28#define TLB_V6_U_FULL (1 << 12)
29#define TLB_V6_D_FULL (1 << 13)
30#define TLB_V6_I_FULL (1 << 14)
31
32#define TLB_V6_U_ASID (1 << 16)
33#define TLB_V6_D_ASID (1 << 17)
34#define TLB_V6_I_ASID (1 << 18)
35
36#define TLB_V6_BP (1 << 19)
37
38/* Unified Inner Shareable TLB operations (ARMv7 MP extensions) */
39#define TLB_V7_UIS_PAGE (1 << 20)
40#define TLB_V7_UIS_FULL (1 << 21)
41#define TLB_V7_UIS_ASID (1 << 22)
42#define TLB_V7_UIS_BP (1 << 23)
43
44#define TLB_BARRIER (1 << 28)
45#define TLB_L2CLEAN_FR (1 << 29) /* Feroceon */
46#define TLB_DCLEAN (1 << 30)
47#define TLB_WB (1 << 31)
48
49/*
50 * MMU TLB Model
51 * =============
52 *
53 * We have the following to choose from:
54 * v4 - ARMv4 without write buffer
55 * v4wb - ARMv4 with write buffer without I TLB flush entry instruction
56 * v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
57 * fr - Feroceon (v4wbi with non-outer-cacheable page table walks)
58 * fa - Faraday (v4 with write buffer with UTLB)
59 * v6wbi - ARMv6 with write buffer with I TLB flush entry instruction
60 * v7wbi - identical to v6wbi
61 */
62#undef _TLB
63#undef MULTI_TLB
64
65#ifdef CONFIG_SMP_ON_UP
66#define MULTI_TLB 1
67#endif
68
69#define v4_tlb_flags (TLB_V4_U_FULL | TLB_V4_U_PAGE)
70
71#ifdef CONFIG_CPU_TLB_V4WT
72# define v4_possible_flags v4_tlb_flags
73# define v4_always_flags v4_tlb_flags
74# ifdef _TLB
75# define MULTI_TLB 1
76# else
77# define _TLB v4
78# endif
79#else
80# define v4_possible_flags 0
81# define v4_always_flags (-1UL)
82#endif
83
84#define fa_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
85 TLB_V4_U_FULL | TLB_V4_U_PAGE)
86
87#ifdef CONFIG_CPU_TLB_FA
88# define fa_possible_flags fa_tlb_flags
89# define fa_always_flags fa_tlb_flags
90# ifdef _TLB
91# define MULTI_TLB 1
92# else
93# define _TLB fa
94# endif
95#else
96# define fa_possible_flags 0
97# define fa_always_flags (-1UL)
98#endif
99
100#define v4wbi_tlb_flags (TLB_WB | TLB_DCLEAN | \
101 TLB_V4_I_FULL | TLB_V4_D_FULL | \
102 TLB_V4_I_PAGE | TLB_V4_D_PAGE)
103
104#ifdef CONFIG_CPU_TLB_V4WBI
105# define v4wbi_possible_flags v4wbi_tlb_flags
106# define v4wbi_always_flags v4wbi_tlb_flags
107# ifdef _TLB
108# define MULTI_TLB 1
109# else
110# define _TLB v4wbi
111# endif
112#else
113# define v4wbi_possible_flags 0
114# define v4wbi_always_flags (-1UL)
115#endif
116
117#define fr_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_L2CLEAN_FR | \
118 TLB_V4_I_FULL | TLB_V4_D_FULL | \
119 TLB_V4_I_PAGE | TLB_V4_D_PAGE)
120
121#ifdef CONFIG_CPU_TLB_FEROCEON
122# define fr_possible_flags fr_tlb_flags
123# define fr_always_flags fr_tlb_flags
124# ifdef _TLB
125# define MULTI_TLB 1
126# else
127# define _TLB v4wbi
128# endif
129#else
130# define fr_possible_flags 0
131# define fr_always_flags (-1UL)
132#endif
133
134#define v4wb_tlb_flags (TLB_WB | TLB_DCLEAN | \
135 TLB_V4_I_FULL | TLB_V4_D_FULL | \
136 TLB_V4_D_PAGE)
137
138#ifdef CONFIG_CPU_TLB_V4WB
139# define v4wb_possible_flags v4wb_tlb_flags
140# define v4wb_always_flags v4wb_tlb_flags
141# ifdef _TLB
142# define MULTI_TLB 1
143# else
144# define _TLB v4wb
145# endif
146#else
147# define v4wb_possible_flags 0
148# define v4wb_always_flags (-1UL)
149#endif
150
151#define v6wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
152 TLB_V6_I_FULL | TLB_V6_D_FULL | \
153 TLB_V6_I_PAGE | TLB_V6_D_PAGE | \
154 TLB_V6_I_ASID | TLB_V6_D_ASID | \
155 TLB_V6_BP)
156
157#ifdef CONFIG_CPU_TLB_V6
158# define v6wbi_possible_flags v6wbi_tlb_flags
159# define v6wbi_always_flags v6wbi_tlb_flags
160# ifdef _TLB
161# define MULTI_TLB 1
162# else
163# define _TLB v6wbi
164# endif
165#else
166# define v6wbi_possible_flags 0
167# define v6wbi_always_flags (-1UL)
168#endif
169
170#define v7wbi_tlb_flags_smp (TLB_WB | TLB_BARRIER | \
171 TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | \
172 TLB_V7_UIS_ASID | TLB_V7_UIS_BP)
173#define v7wbi_tlb_flags_up (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
174 TLB_V6_U_FULL | TLB_V6_U_PAGE | \
175 TLB_V6_U_ASID | TLB_V6_BP)
176
177#ifdef CONFIG_CPU_TLB_V7
178
179# ifdef CONFIG_SMP_ON_UP
180# define v7wbi_possible_flags (v7wbi_tlb_flags_smp | v7wbi_tlb_flags_up)
181# define v7wbi_always_flags (v7wbi_tlb_flags_smp & v7wbi_tlb_flags_up)
182# elif defined(CONFIG_SMP)
183# define v7wbi_possible_flags v7wbi_tlb_flags_smp
184# define v7wbi_always_flags v7wbi_tlb_flags_smp
185# else
186# define v7wbi_possible_flags v7wbi_tlb_flags_up
187# define v7wbi_always_flags v7wbi_tlb_flags_up
188# endif
189# ifdef _TLB
190# define MULTI_TLB 1
191# else
192# define _TLB v7wbi
193# endif
194#else
195# define v7wbi_possible_flags 0
196# define v7wbi_always_flags (-1UL)
197#endif
198
199#ifndef _TLB
200#error Unknown TLB model
201#endif
202
203#ifndef __ASSEMBLY__
204
205#include <linux/sched.h>
206
207struct cpu_tlb_fns {
208 void (*flush_user_range)(unsigned long, unsigned long, struct vm_area_struct *);
209 void (*flush_kern_range)(unsigned long, unsigned long);
210 unsigned long tlb_flags;
211};
212
213/*
214 * Select the calling method
215 */
216#ifdef MULTI_TLB
217
218#define __cpu_flush_user_tlb_range cpu_tlb.flush_user_range
219#define __cpu_flush_kern_tlb_range cpu_tlb.flush_kern_range
220
221#else
222
223#define __cpu_flush_user_tlb_range __glue(_TLB,_flush_user_tlb_range)
224#define __cpu_flush_kern_tlb_range __glue(_TLB,_flush_kern_tlb_range)
225
226extern void __cpu_flush_user_tlb_range(unsigned long, unsigned long, struct vm_area_struct *);
227extern void __cpu_flush_kern_tlb_range(unsigned long, unsigned long);
228
229#endif
230
231extern struct cpu_tlb_fns cpu_tlb;
232
233#define __cpu_tlb_flags cpu_tlb.tlb_flags
234
235/*
236 * TLB Management
237 * ==============
238 *
239 * The arch/arm/mm/tlb-*.S files implement these methods.
240 *
241 * The TLB specific code is expected to perform whatever tests it
242 * needs to determine if it should invalidate the TLB for each
243 * call. Start addresses are inclusive and end addresses are
244 * exclusive; it is safe to round these addresses down.
245 *
246 * flush_tlb_all()
247 *
248 * Invalidate the entire TLB.
249 *
250 * flush_tlb_mm(mm)
251 *
252 * Invalidate all TLB entries in a particular address
253 * space.
254 * - mm - mm_struct describing address space
255 *
256 * flush_tlb_range(vma,start,end)
257 *
258 * Invalidate a range of TLB entries in the specified
259 * address space.
260 * - mm - mm_struct describing address space
261 * - start - start address (may not be aligned)
262 * - end - end address (exclusive, may not be aligned)
263 *
264 * flush_tlb_page(vma, uaddr)
265 *
266 * Invalidate the specified page in the specified address range.
267 * - vma - vm_area_struct describing address range
268 * - vaddr - virtual address (may not be aligned)
269 */
270
271/*
272 * We optimise the code below by:
273 * - building a set of TLB flags that might be set in __cpu_tlb_flags
274 * - building a set of TLB flags that will always be set in __cpu_tlb_flags
275 * - if we're going to need __cpu_tlb_flags, access it once and only once
276 *
277 * This allows us to build optimal assembly for the single-CPU type case,
278 * and as close to optimal given the compiler constrants for multi-CPU
279 * case. We could do better for the multi-CPU case if the compiler
280 * implemented the "%?" method, but this has been discontinued due to too
281 * many people getting it wrong.
282 */
283#define possible_tlb_flags (v4_possible_flags | \
284 v4wbi_possible_flags | \
285 fr_possible_flags | \
286 v4wb_possible_flags | \
287 fa_possible_flags | \
288 v6wbi_possible_flags | \
289 v7wbi_possible_flags)
290
291#define always_tlb_flags (v4_always_flags & \
292 v4wbi_always_flags & \
293 fr_always_flags & \
294 v4wb_always_flags & \
295 fa_always_flags & \
296 v6wbi_always_flags & \
297 v7wbi_always_flags)
298
299#define tlb_flag(f) ((always_tlb_flags & (f)) || (__tlb_flag & possible_tlb_flags & (f)))
300
301#define __tlb_op(f, insnarg, arg) \
302 do { \
303 if (always_tlb_flags & (f)) \
304 asm("mcr " insnarg \
305 : : "r" (arg) : "cc"); \
306 else if (possible_tlb_flags & (f)) \
307 asm("tst %1, %2\n\t" \
308 "mcrne " insnarg \
309 : : "r" (arg), "r" (__tlb_flag), "Ir" (f) \
310 : "cc"); \
311 } while (0)
312
313#define tlb_op(f, regs, arg) __tlb_op(f, "p15, 0, %0, " regs, arg)
314#define tlb_l2_op(f, regs, arg) __tlb_op(f, "p15, 1, %0, " regs, arg)
315
316static inline void __local_flush_tlb_all(void)
317{
318 const int zero = 0;
319 const unsigned int __tlb_flag = __cpu_tlb_flags;
320
321 tlb_op(TLB_V4_U_FULL | TLB_V6_U_FULL, "c8, c7, 0", zero);
322 tlb_op(TLB_V4_D_FULL | TLB_V6_D_FULL, "c8, c6, 0", zero);
323 tlb_op(TLB_V4_I_FULL | TLB_V6_I_FULL, "c8, c5, 0", zero);
324}
325
326static inline void local_flush_tlb_all(void)
327{
328 const int zero = 0;
329 const unsigned int __tlb_flag = __cpu_tlb_flags;
330
331 if (tlb_flag(TLB_WB))
332 dsb(nshst);
333
334 __local_flush_tlb_all();
335 tlb_op(TLB_V7_UIS_FULL, "c8, c7, 0", zero);
336
337 if (tlb_flag(TLB_BARRIER)) {
338 dsb(nsh);
339 isb();
340 }
341}
342
343static inline void __flush_tlb_all(void)
344{
345 const int zero = 0;
346 const unsigned int __tlb_flag = __cpu_tlb_flags;
347
348 if (tlb_flag(TLB_WB))
349 dsb(ishst);
350
351 __local_flush_tlb_all();
352 tlb_op(TLB_V7_UIS_FULL, "c8, c3, 0", zero);
353
354 if (tlb_flag(TLB_BARRIER)) {
355 dsb(ish);
356 isb();
357 }
358}
359
360static inline void __local_flush_tlb_mm(struct mm_struct *mm)
361{
362 const int zero = 0;
363 const int asid = ASID(mm);
364 const unsigned int __tlb_flag = __cpu_tlb_flags;
365
366 if (possible_tlb_flags & (TLB_V4_U_FULL|TLB_V4_D_FULL|TLB_V4_I_FULL)) {
367 if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm))) {
368 tlb_op(TLB_V4_U_FULL, "c8, c7, 0", zero);
369 tlb_op(TLB_V4_D_FULL, "c8, c6, 0", zero);
370 tlb_op(TLB_V4_I_FULL, "c8, c5, 0", zero);
371 }
372 }
373
374 tlb_op(TLB_V6_U_ASID, "c8, c7, 2", asid);
375 tlb_op(TLB_V6_D_ASID, "c8, c6, 2", asid);
376 tlb_op(TLB_V6_I_ASID, "c8, c5, 2", asid);
377}
378
379static inline void local_flush_tlb_mm(struct mm_struct *mm)
380{
381 const int asid = ASID(mm);
382 const unsigned int __tlb_flag = __cpu_tlb_flags;
383
384 if (tlb_flag(TLB_WB))
385 dsb(nshst);
386
387 __local_flush_tlb_mm(mm);
388 tlb_op(TLB_V7_UIS_ASID, "c8, c7, 2", asid);
389
390 if (tlb_flag(TLB_BARRIER))
391 dsb(nsh);
392}
393
394static inline void __flush_tlb_mm(struct mm_struct *mm)
395{
396 const unsigned int __tlb_flag = __cpu_tlb_flags;
397
398 if (tlb_flag(TLB_WB))
399 dsb(ishst);
400
401 __local_flush_tlb_mm(mm);
402#ifdef CONFIG_ARM_ERRATA_720789
403 tlb_op(TLB_V7_UIS_ASID, "c8, c3, 0", 0);
404#else
405 tlb_op(TLB_V7_UIS_ASID, "c8, c3, 2", ASID(mm));
406#endif
407
408 if (tlb_flag(TLB_BARRIER))
409 dsb(ish);
410}
411
412static inline void
413__local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
414{
415 const int zero = 0;
416 const unsigned int __tlb_flag = __cpu_tlb_flags;
417
418 uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm);
419
420 if (possible_tlb_flags & (TLB_V4_U_PAGE|TLB_V4_D_PAGE|TLB_V4_I_PAGE|TLB_V4_I_FULL) &&
421 cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
422 tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", uaddr);
423 tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", uaddr);
424 tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", uaddr);
425 if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
426 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
427 }
428
429 tlb_op(TLB_V6_U_PAGE, "c8, c7, 1", uaddr);
430 tlb_op(TLB_V6_D_PAGE, "c8, c6, 1", uaddr);
431 tlb_op(TLB_V6_I_PAGE, "c8, c5, 1", uaddr);
432}
433
434static inline void
435local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
436{
437 const unsigned int __tlb_flag = __cpu_tlb_flags;
438
439 uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm);
440
441 if (tlb_flag(TLB_WB))
442 dsb(nshst);
443
444 __local_flush_tlb_page(vma, uaddr);
445 tlb_op(TLB_V7_UIS_PAGE, "c8, c7, 1", uaddr);
446
447 if (tlb_flag(TLB_BARRIER))
448 dsb(nsh);
449}
450
451static inline void
452__flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
453{
454 const unsigned int __tlb_flag = __cpu_tlb_flags;
455
456 uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm);
457
458 if (tlb_flag(TLB_WB))
459 dsb(ishst);
460
461 __local_flush_tlb_page(vma, uaddr);
462#ifdef CONFIG_ARM_ERRATA_720789
463 tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 3", uaddr & PAGE_MASK);
464#else
465 tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 1", uaddr);
466#endif
467
468 if (tlb_flag(TLB_BARRIER))
469 dsb(ish);
470}
471
472static inline void __local_flush_tlb_kernel_page(unsigned long kaddr)
473{
474 const int zero = 0;
475 const unsigned int __tlb_flag = __cpu_tlb_flags;
476
477 tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", kaddr);
478 tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", kaddr);
479 tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", kaddr);
480 if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
481 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
482
483 tlb_op(TLB_V6_U_PAGE, "c8, c7, 1", kaddr);
484 tlb_op(TLB_V6_D_PAGE, "c8, c6, 1", kaddr);
485 tlb_op(TLB_V6_I_PAGE, "c8, c5, 1", kaddr);
486}
487
488static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
489{
490 const unsigned int __tlb_flag = __cpu_tlb_flags;
491
492 kaddr &= PAGE_MASK;
493
494 if (tlb_flag(TLB_WB))
495 dsb(nshst);
496
497 __local_flush_tlb_kernel_page(kaddr);
498 tlb_op(TLB_V7_UIS_PAGE, "c8, c7, 1", kaddr);
499
500 if (tlb_flag(TLB_BARRIER)) {
501 dsb(nsh);
502 isb();
503 }
504}
505
506static inline void __flush_tlb_kernel_page(unsigned long kaddr)
507{
508 const unsigned int __tlb_flag = __cpu_tlb_flags;
509
510 kaddr &= PAGE_MASK;
511
512 if (tlb_flag(TLB_WB))
513 dsb(ishst);
514
515 __local_flush_tlb_kernel_page(kaddr);
516 tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 1", kaddr);
517
518 if (tlb_flag(TLB_BARRIER)) {
519 dsb(ish);
520 isb();
521 }
522}
523
524/*
525 * Branch predictor maintenance is paired with full TLB invalidation, so
526 * there is no need for any barriers here.
527 */
528static inline void __local_flush_bp_all(void)
529{
530 const int zero = 0;
531 const unsigned int __tlb_flag = __cpu_tlb_flags;
532
533 if (tlb_flag(TLB_V6_BP))
534 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero));
535}
536
537static inline void local_flush_bp_all(void)
538{
539 const int zero = 0;
540 const unsigned int __tlb_flag = __cpu_tlb_flags;
541
542 __local_flush_bp_all();
543 if (tlb_flag(TLB_V7_UIS_BP))
544 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero));
545}
546
547static inline void __flush_bp_all(void)
548{
549 const int zero = 0;
550 const unsigned int __tlb_flag = __cpu_tlb_flags;
551
552 __local_flush_bp_all();
553 if (tlb_flag(TLB_V7_UIS_BP))
554 asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero));
555}
556
557/*
558 * flush_pmd_entry
559 *
560 * Flush a PMD entry (word aligned, or double-word aligned) to
561 * RAM if the TLB for the CPU we are running on requires this.
562 * This is typically used when we are creating PMD entries.
563 *
564 * clean_pmd_entry
565 *
566 * Clean (but don't drain the write buffer) if the CPU requires
567 * these operations. This is typically used when we are removing
568 * PMD entries.
569 */
570static inline void flush_pmd_entry(void *pmd)
571{
572 const unsigned int __tlb_flag = __cpu_tlb_flags;
573
574 tlb_op(TLB_DCLEAN, "c7, c10, 1 @ flush_pmd", pmd);
575 tlb_l2_op(TLB_L2CLEAN_FR, "c15, c9, 1 @ L2 flush_pmd", pmd);
576
577 if (tlb_flag(TLB_WB))
578 dsb(ishst);
579}
580
581static inline void clean_pmd_entry(void *pmd)
582{
583 const unsigned int __tlb_flag = __cpu_tlb_flags;
584
585 tlb_op(TLB_DCLEAN, "c7, c10, 1 @ flush_pmd", pmd);
586 tlb_l2_op(TLB_L2CLEAN_FR, "c15, c9, 1 @ L2 flush_pmd", pmd);
587}
588
589#undef tlb_op
590#undef tlb_flag
591#undef always_tlb_flags
592#undef possible_tlb_flags
593
594/*
595 * Convert calls to our calling convention.
596 */
597#define local_flush_tlb_range(vma,start,end) __cpu_flush_user_tlb_range(start,end,vma)
598#define local_flush_tlb_kernel_range(s,e) __cpu_flush_kern_tlb_range(s,e)
599
600#ifndef CONFIG_SMP
601#define flush_tlb_all local_flush_tlb_all
602#define flush_tlb_mm local_flush_tlb_mm
603#define flush_tlb_page local_flush_tlb_page
604#define flush_tlb_kernel_page local_flush_tlb_kernel_page
605#define flush_tlb_range local_flush_tlb_range
606#define flush_tlb_kernel_range local_flush_tlb_kernel_range
607#define flush_bp_all local_flush_bp_all
608#else
609extern void flush_tlb_all(void);
610extern void flush_tlb_mm(struct mm_struct *mm);
611extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr);
612extern void flush_tlb_kernel_page(unsigned long kaddr);
613extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
614extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
615extern void flush_bp_all(void);
616#endif
617
618/*
619 * If PG_dcache_clean is not set for the page, we need to ensure that any
620 * cache entries for the kernels virtual memory range are written
621 * back to the page. On ARMv6 and later, the cache coherency is handled via
622 * the set_ptes() function.
623 */
624#if __LINUX_ARM_ARCH__ < 6
625void update_mmu_cache_range(struct vm_fault *vmf, struct vm_area_struct *vma,
626 unsigned long addr, pte_t *ptep, unsigned int nr);
627#else
628static inline void update_mmu_cache_range(struct vm_fault *vmf,
629 struct vm_area_struct *vma, unsigned long addr, pte_t *ptep,
630 unsigned int nr)
631{
632}
633#endif
634
635#define update_mmu_cache(vma, addr, ptep) \
636 update_mmu_cache_range(NULL, vma, addr, ptep, 1)
637
638#define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
639
640#endif
641
642#elif defined(CONFIG_SMP) /* !CONFIG_MMU */
643
644#ifndef __ASSEMBLY__
645static inline void local_flush_tlb_all(void) { }
646static inline void local_flush_tlb_mm(struct mm_struct *mm) { }
647static inline void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) { }
648static inline void local_flush_tlb_kernel_page(unsigned long kaddr) { }
649static inline void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { }
650static inline void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) { }
651static inline void local_flush_bp_all(void) { }
652
653extern void flush_tlb_all(void);
654extern void flush_tlb_mm(struct mm_struct *mm);
655extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr);
656extern void flush_tlb_kernel_page(unsigned long kaddr);
657extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
658extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
659extern void flush_bp_all(void);
660#endif /* __ASSEMBLY__ */
661
662#endif
663
664#ifndef __ASSEMBLY__
665#ifdef CONFIG_ARM_ERRATA_798181
666extern void erratum_a15_798181_init(void);
667#else
668static inline void erratum_a15_798181_init(void) {}
669#endif
670extern bool (*erratum_a15_798181_handler)(void);
671
672static inline bool erratum_a15_798181(void)
673{
674 if (unlikely(IS_ENABLED(CONFIG_ARM_ERRATA_798181) &&
675 erratum_a15_798181_handler))
676 return erratum_a15_798181_handler();
677 return false;
678}
679#endif
680
681#endif
1/*
2 * arch/arm/include/asm/tlbflush.h
3 *
4 * Copyright (C) 1999-2003 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef _ASMARM_TLBFLUSH_H
11#define _ASMARM_TLBFLUSH_H
12
13#ifdef CONFIG_MMU
14
15#include <asm/glue.h>
16
17#define TLB_V3_PAGE (1 << 0)
18#define TLB_V4_U_PAGE (1 << 1)
19#define TLB_V4_D_PAGE (1 << 2)
20#define TLB_V4_I_PAGE (1 << 3)
21#define TLB_V6_U_PAGE (1 << 4)
22#define TLB_V6_D_PAGE (1 << 5)
23#define TLB_V6_I_PAGE (1 << 6)
24
25#define TLB_V3_FULL (1 << 8)
26#define TLB_V4_U_FULL (1 << 9)
27#define TLB_V4_D_FULL (1 << 10)
28#define TLB_V4_I_FULL (1 << 11)
29#define TLB_V6_U_FULL (1 << 12)
30#define TLB_V6_D_FULL (1 << 13)
31#define TLB_V6_I_FULL (1 << 14)
32
33#define TLB_V6_U_ASID (1 << 16)
34#define TLB_V6_D_ASID (1 << 17)
35#define TLB_V6_I_ASID (1 << 18)
36
37/* Unified Inner Shareable TLB operations (ARMv7 MP extensions) */
38#define TLB_V7_UIS_PAGE (1 << 19)
39#define TLB_V7_UIS_FULL (1 << 20)
40#define TLB_V7_UIS_ASID (1 << 21)
41
42#define TLB_BARRIER (1 << 28)
43#define TLB_L2CLEAN_FR (1 << 29) /* Feroceon */
44#define TLB_DCLEAN (1 << 30)
45#define TLB_WB (1 << 31)
46
47/*
48 * MMU TLB Model
49 * =============
50 *
51 * We have the following to choose from:
52 * v3 - ARMv3
53 * v4 - ARMv4 without write buffer
54 * v4wb - ARMv4 with write buffer without I TLB flush entry instruction
55 * v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
56 * fr - Feroceon (v4wbi with non-outer-cacheable page table walks)
57 * fa - Faraday (v4 with write buffer with UTLB)
58 * v6wbi - ARMv6 with write buffer with I TLB flush entry instruction
59 * v7wbi - identical to v6wbi
60 */
61#undef _TLB
62#undef MULTI_TLB
63
64#ifdef CONFIG_SMP_ON_UP
65#define MULTI_TLB 1
66#endif
67
68#define v3_tlb_flags (TLB_V3_FULL | TLB_V3_PAGE)
69
70#ifdef CONFIG_CPU_TLB_V3
71# define v3_possible_flags v3_tlb_flags
72# define v3_always_flags v3_tlb_flags
73# ifdef _TLB
74# define MULTI_TLB 1
75# else
76# define _TLB v3
77# endif
78#else
79# define v3_possible_flags 0
80# define v3_always_flags (-1UL)
81#endif
82
83#define v4_tlb_flags (TLB_V4_U_FULL | TLB_V4_U_PAGE)
84
85#ifdef CONFIG_CPU_TLB_V4WT
86# define v4_possible_flags v4_tlb_flags
87# define v4_always_flags v4_tlb_flags
88# ifdef _TLB
89# define MULTI_TLB 1
90# else
91# define _TLB v4
92# endif
93#else
94# define v4_possible_flags 0
95# define v4_always_flags (-1UL)
96#endif
97
98#define fa_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
99 TLB_V4_U_FULL | TLB_V4_U_PAGE)
100
101#ifdef CONFIG_CPU_TLB_FA
102# define fa_possible_flags fa_tlb_flags
103# define fa_always_flags fa_tlb_flags
104# ifdef _TLB
105# define MULTI_TLB 1
106# else
107# define _TLB fa
108# endif
109#else
110# define fa_possible_flags 0
111# define fa_always_flags (-1UL)
112#endif
113
114#define v4wbi_tlb_flags (TLB_WB | TLB_DCLEAN | \
115 TLB_V4_I_FULL | TLB_V4_D_FULL | \
116 TLB_V4_I_PAGE | TLB_V4_D_PAGE)
117
118#ifdef CONFIG_CPU_TLB_V4WBI
119# define v4wbi_possible_flags v4wbi_tlb_flags
120# define v4wbi_always_flags v4wbi_tlb_flags
121# ifdef _TLB
122# define MULTI_TLB 1
123# else
124# define _TLB v4wbi
125# endif
126#else
127# define v4wbi_possible_flags 0
128# define v4wbi_always_flags (-1UL)
129#endif
130
131#define fr_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_L2CLEAN_FR | \
132 TLB_V4_I_FULL | TLB_V4_D_FULL | \
133 TLB_V4_I_PAGE | TLB_V4_D_PAGE)
134
135#ifdef CONFIG_CPU_TLB_FEROCEON
136# define fr_possible_flags fr_tlb_flags
137# define fr_always_flags fr_tlb_flags
138# ifdef _TLB
139# define MULTI_TLB 1
140# else
141# define _TLB v4wbi
142# endif
143#else
144# define fr_possible_flags 0
145# define fr_always_flags (-1UL)
146#endif
147
148#define v4wb_tlb_flags (TLB_WB | TLB_DCLEAN | \
149 TLB_V4_I_FULL | TLB_V4_D_FULL | \
150 TLB_V4_D_PAGE)
151
152#ifdef CONFIG_CPU_TLB_V4WB
153# define v4wb_possible_flags v4wb_tlb_flags
154# define v4wb_always_flags v4wb_tlb_flags
155# ifdef _TLB
156# define MULTI_TLB 1
157# else
158# define _TLB v4wb
159# endif
160#else
161# define v4wb_possible_flags 0
162# define v4wb_always_flags (-1UL)
163#endif
164
165#define v6wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
166 TLB_V6_I_FULL | TLB_V6_D_FULL | \
167 TLB_V6_I_PAGE | TLB_V6_D_PAGE | \
168 TLB_V6_I_ASID | TLB_V6_D_ASID)
169
170#ifdef CONFIG_CPU_TLB_V6
171# define v6wbi_possible_flags v6wbi_tlb_flags
172# define v6wbi_always_flags v6wbi_tlb_flags
173# ifdef _TLB
174# define MULTI_TLB 1
175# else
176# define _TLB v6wbi
177# endif
178#else
179# define v6wbi_possible_flags 0
180# define v6wbi_always_flags (-1UL)
181#endif
182
183#define v7wbi_tlb_flags_smp (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
184 TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID)
185#define v7wbi_tlb_flags_up (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
186 TLB_V6_U_FULL | TLB_V6_U_PAGE | TLB_V6_U_ASID)
187
188#ifdef CONFIG_CPU_TLB_V7
189
190# ifdef CONFIG_SMP_ON_UP
191# define v7wbi_possible_flags (v7wbi_tlb_flags_smp | v7wbi_tlb_flags_up)
192# define v7wbi_always_flags (v7wbi_tlb_flags_smp & v7wbi_tlb_flags_up)
193# elif defined(CONFIG_SMP)
194# define v7wbi_possible_flags v7wbi_tlb_flags_smp
195# define v7wbi_always_flags v7wbi_tlb_flags_smp
196# else
197# define v7wbi_possible_flags v7wbi_tlb_flags_up
198# define v7wbi_always_flags v7wbi_tlb_flags_up
199# endif
200# ifdef _TLB
201# define MULTI_TLB 1
202# else
203# define _TLB v7wbi
204# endif
205#else
206# define v7wbi_possible_flags 0
207# define v7wbi_always_flags (-1UL)
208#endif
209
210#ifndef _TLB
211#error Unknown TLB model
212#endif
213
214#ifndef __ASSEMBLY__
215
216#include <linux/sched.h>
217
218struct cpu_tlb_fns {
219 void (*flush_user_range)(unsigned long, unsigned long, struct vm_area_struct *);
220 void (*flush_kern_range)(unsigned long, unsigned long);
221 unsigned long tlb_flags;
222};
223
224/*
225 * Select the calling method
226 */
227#ifdef MULTI_TLB
228
229#define __cpu_flush_user_tlb_range cpu_tlb.flush_user_range
230#define __cpu_flush_kern_tlb_range cpu_tlb.flush_kern_range
231
232#else
233
234#define __cpu_flush_user_tlb_range __glue(_TLB,_flush_user_tlb_range)
235#define __cpu_flush_kern_tlb_range __glue(_TLB,_flush_kern_tlb_range)
236
237extern void __cpu_flush_user_tlb_range(unsigned long, unsigned long, struct vm_area_struct *);
238extern void __cpu_flush_kern_tlb_range(unsigned long, unsigned long);
239
240#endif
241
242extern struct cpu_tlb_fns cpu_tlb;
243
244#define __cpu_tlb_flags cpu_tlb.tlb_flags
245
246/*
247 * TLB Management
248 * ==============
249 *
250 * The arch/arm/mm/tlb-*.S files implement these methods.
251 *
252 * The TLB specific code is expected to perform whatever tests it
253 * needs to determine if it should invalidate the TLB for each
254 * call. Start addresses are inclusive and end addresses are
255 * exclusive; it is safe to round these addresses down.
256 *
257 * flush_tlb_all()
258 *
259 * Invalidate the entire TLB.
260 *
261 * flush_tlb_mm(mm)
262 *
263 * Invalidate all TLB entries in a particular address
264 * space.
265 * - mm - mm_struct describing address space
266 *
267 * flush_tlb_range(mm,start,end)
268 *
269 * Invalidate a range of TLB entries in the specified
270 * address space.
271 * - mm - mm_struct describing address space
272 * - start - start address (may not be aligned)
273 * - end - end address (exclusive, may not be aligned)
274 *
275 * flush_tlb_page(vaddr,vma)
276 *
277 * Invalidate the specified page in the specified address range.
278 * - vaddr - virtual address (may not be aligned)
279 * - vma - vma_struct describing address range
280 *
281 * flush_kern_tlb_page(kaddr)
282 *
283 * Invalidate the TLB entry for the specified page. The address
284 * will be in the kernels virtual memory space. Current uses
285 * only require the D-TLB to be invalidated.
286 * - kaddr - Kernel virtual memory address
287 */
288
289/*
290 * We optimise the code below by:
291 * - building a set of TLB flags that might be set in __cpu_tlb_flags
292 * - building a set of TLB flags that will always be set in __cpu_tlb_flags
293 * - if we're going to need __cpu_tlb_flags, access it once and only once
294 *
295 * This allows us to build optimal assembly for the single-CPU type case,
296 * and as close to optimal given the compiler constrants for multi-CPU
297 * case. We could do better for the multi-CPU case if the compiler
298 * implemented the "%?" method, but this has been discontinued due to too
299 * many people getting it wrong.
300 */
301#define possible_tlb_flags (v3_possible_flags | \
302 v4_possible_flags | \
303 v4wbi_possible_flags | \
304 fr_possible_flags | \
305 v4wb_possible_flags | \
306 fa_possible_flags | \
307 v6wbi_possible_flags | \
308 v7wbi_possible_flags)
309
310#define always_tlb_flags (v3_always_flags & \
311 v4_always_flags & \
312 v4wbi_always_flags & \
313 fr_always_flags & \
314 v4wb_always_flags & \
315 fa_always_flags & \
316 v6wbi_always_flags & \
317 v7wbi_always_flags)
318
319#define tlb_flag(f) ((always_tlb_flags & (f)) || (__tlb_flag & possible_tlb_flags & (f)))
320
321static inline void local_flush_tlb_all(void)
322{
323 const int zero = 0;
324 const unsigned int __tlb_flag = __cpu_tlb_flags;
325
326 if (tlb_flag(TLB_WB))
327 dsb();
328
329 if (tlb_flag(TLB_V3_FULL))
330 asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc");
331 if (tlb_flag(TLB_V4_U_FULL | TLB_V6_U_FULL))
332 asm("mcr p15, 0, %0, c8, c7, 0" : : "r" (zero) : "cc");
333 if (tlb_flag(TLB_V4_D_FULL | TLB_V6_D_FULL))
334 asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc");
335 if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL))
336 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
337 if (tlb_flag(TLB_V7_UIS_FULL))
338 asm("mcr p15, 0, %0, c8, c3, 0" : : "r" (zero) : "cc");
339
340 if (tlb_flag(TLB_BARRIER)) {
341 dsb();
342 isb();
343 }
344}
345
346static inline void local_flush_tlb_mm(struct mm_struct *mm)
347{
348 const int zero = 0;
349 const int asid = ASID(mm);
350 const unsigned int __tlb_flag = __cpu_tlb_flags;
351
352 if (tlb_flag(TLB_WB))
353 dsb();
354
355 if (cpumask_test_cpu(get_cpu(), mm_cpumask(mm))) {
356 if (tlb_flag(TLB_V3_FULL))
357 asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc");
358 if (tlb_flag(TLB_V4_U_FULL))
359 asm("mcr p15, 0, %0, c8, c7, 0" : : "r" (zero) : "cc");
360 if (tlb_flag(TLB_V4_D_FULL))
361 asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc");
362 if (tlb_flag(TLB_V4_I_FULL))
363 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
364 }
365 put_cpu();
366
367 if (tlb_flag(TLB_V6_U_ASID))
368 asm("mcr p15, 0, %0, c8, c7, 2" : : "r" (asid) : "cc");
369 if (tlb_flag(TLB_V6_D_ASID))
370 asm("mcr p15, 0, %0, c8, c6, 2" : : "r" (asid) : "cc");
371 if (tlb_flag(TLB_V6_I_ASID))
372 asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc");
373 if (tlb_flag(TLB_V7_UIS_ASID))
374#ifdef CONFIG_ARM_ERRATA_720789
375 asm("mcr p15, 0, %0, c8, c3, 0" : : "r" (zero) : "cc");
376#else
377 asm("mcr p15, 0, %0, c8, c3, 2" : : "r" (asid) : "cc");
378#endif
379
380 if (tlb_flag(TLB_BARRIER))
381 dsb();
382}
383
384static inline void
385local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
386{
387 const int zero = 0;
388 const unsigned int __tlb_flag = __cpu_tlb_flags;
389
390 uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm);
391
392 if (tlb_flag(TLB_WB))
393 dsb();
394
395 if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
396 if (tlb_flag(TLB_V3_PAGE))
397 asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (uaddr) : "cc");
398 if (tlb_flag(TLB_V4_U_PAGE))
399 asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (uaddr) : "cc");
400 if (tlb_flag(TLB_V4_D_PAGE))
401 asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
402 if (tlb_flag(TLB_V4_I_PAGE))
403 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
404 if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
405 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
406 }
407
408 if (tlb_flag(TLB_V6_U_PAGE))
409 asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (uaddr) : "cc");
410 if (tlb_flag(TLB_V6_D_PAGE))
411 asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
412 if (tlb_flag(TLB_V6_I_PAGE))
413 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
414 if (tlb_flag(TLB_V7_UIS_PAGE))
415#ifdef CONFIG_ARM_ERRATA_720789
416 asm("mcr p15, 0, %0, c8, c3, 3" : : "r" (uaddr & PAGE_MASK) : "cc");
417#else
418 asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (uaddr) : "cc");
419#endif
420
421 if (tlb_flag(TLB_BARRIER))
422 dsb();
423}
424
425static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
426{
427 const int zero = 0;
428 const unsigned int __tlb_flag = __cpu_tlb_flags;
429
430 kaddr &= PAGE_MASK;
431
432 if (tlb_flag(TLB_WB))
433 dsb();
434
435 if (tlb_flag(TLB_V3_PAGE))
436 asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (kaddr) : "cc");
437 if (tlb_flag(TLB_V4_U_PAGE))
438 asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (kaddr) : "cc");
439 if (tlb_flag(TLB_V4_D_PAGE))
440 asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc");
441 if (tlb_flag(TLB_V4_I_PAGE))
442 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
443 if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
444 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
445
446 if (tlb_flag(TLB_V6_U_PAGE))
447 asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (kaddr) : "cc");
448 if (tlb_flag(TLB_V6_D_PAGE))
449 asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc");
450 if (tlb_flag(TLB_V6_I_PAGE))
451 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
452 if (tlb_flag(TLB_V7_UIS_PAGE))
453 asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (kaddr) : "cc");
454
455 if (tlb_flag(TLB_BARRIER)) {
456 dsb();
457 isb();
458 }
459}
460
461/*
462 * flush_pmd_entry
463 *
464 * Flush a PMD entry (word aligned, or double-word aligned) to
465 * RAM if the TLB for the CPU we are running on requires this.
466 * This is typically used when we are creating PMD entries.
467 *
468 * clean_pmd_entry
469 *
470 * Clean (but don't drain the write buffer) if the CPU requires
471 * these operations. This is typically used when we are removing
472 * PMD entries.
473 */
474static inline void flush_pmd_entry(pmd_t *pmd)
475{
476 const unsigned int __tlb_flag = __cpu_tlb_flags;
477
478 if (tlb_flag(TLB_DCLEAN))
479 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd"
480 : : "r" (pmd) : "cc");
481
482 if (tlb_flag(TLB_L2CLEAN_FR))
483 asm("mcr p15, 1, %0, c15, c9, 1 @ L2 flush_pmd"
484 : : "r" (pmd) : "cc");
485
486 if (tlb_flag(TLB_WB))
487 dsb();
488}
489
490static inline void clean_pmd_entry(pmd_t *pmd)
491{
492 const unsigned int __tlb_flag = __cpu_tlb_flags;
493
494 if (tlb_flag(TLB_DCLEAN))
495 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd"
496 : : "r" (pmd) : "cc");
497
498 if (tlb_flag(TLB_L2CLEAN_FR))
499 asm("mcr p15, 1, %0, c15, c9, 1 @ L2 flush_pmd"
500 : : "r" (pmd) : "cc");
501}
502
503#undef tlb_flag
504#undef always_tlb_flags
505#undef possible_tlb_flags
506
507/*
508 * Convert calls to our calling convention.
509 */
510#define local_flush_tlb_range(vma,start,end) __cpu_flush_user_tlb_range(start,end,vma)
511#define local_flush_tlb_kernel_range(s,e) __cpu_flush_kern_tlb_range(s,e)
512
513#ifndef CONFIG_SMP
514#define flush_tlb_all local_flush_tlb_all
515#define flush_tlb_mm local_flush_tlb_mm
516#define flush_tlb_page local_flush_tlb_page
517#define flush_tlb_kernel_page local_flush_tlb_kernel_page
518#define flush_tlb_range local_flush_tlb_range
519#define flush_tlb_kernel_range local_flush_tlb_kernel_range
520#else
521extern void flush_tlb_all(void);
522extern void flush_tlb_mm(struct mm_struct *mm);
523extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr);
524extern void flush_tlb_kernel_page(unsigned long kaddr);
525extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
526extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
527#endif
528
529/*
530 * If PG_dcache_clean is not set for the page, we need to ensure that any
531 * cache entries for the kernels virtual memory range are written
532 * back to the page. On ARMv6 and later, the cache coherency is handled via
533 * the set_pte_at() function.
534 */
535#if __LINUX_ARM_ARCH__ < 6
536extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
537 pte_t *ptep);
538#else
539static inline void update_mmu_cache(struct vm_area_struct *vma,
540 unsigned long addr, pte_t *ptep)
541{
542}
543#endif
544
545#endif
546
547#endif /* CONFIG_MMU */
548
549#endif