1/* SPDX-License-Identifier: GPL-2.0 */
 2#ifndef ASMARM_PCI_H
 3#define ASMARM_PCI_H
 4
 5#ifdef __KERNEL__
 
 
 
 6#include <asm/mach/pci.h> /* for pci_sys_data */
 7
 8extern unsigned long pcibios_min_io;
 9#define PCIBIOS_MIN_IO pcibios_min_io
10extern unsigned long pcibios_min_mem;
11#define PCIBIOS_MIN_MEM pcibios_min_mem
12
13#define pcibios_assign_all_busses()	pci_has_flag(PCI_REASSIGN_ALL_BUS)
 
 
 
14
15#ifdef CONFIG_PCI_DOMAINS
 
 
 
 
 
 
 
16static inline int pci_proc_domain(struct pci_bus *bus)
17{
18	return pci_domain_nr(bus);
19}
20#endif /* CONFIG_PCI_DOMAINS */
21
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
22#define HAVE_PCI_MMAP
23#define ARCH_GENERIC_PCI_MMAP_RESOURCE
 
24
25extern void pcibios_report_status(unsigned int status_mask, int warn);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
26
27#endif /* __KERNEL__ */
 
28#endif

 
 1#ifndef ASMARM_PCI_H
 2#define ASMARM_PCI_H
 3
 4#ifdef __KERNEL__
 5#include <asm-generic/pci-dma-compat.h>
 6#include <asm-generic/pci-bridge.h>
 7
 8#include <asm/mach/pci.h> /* for pci_sys_data */
 9
10extern unsigned long pcibios_min_io;
11#define PCIBIOS_MIN_IO pcibios_min_io
12extern unsigned long pcibios_min_mem;
13#define PCIBIOS_MIN_MEM pcibios_min_mem
14
15static inline int pcibios_assign_all_busses(void)
16{
17	return pci_has_flag(PCI_REASSIGN_ALL_RSRC);
18}
19
20#ifdef CONFIG_PCI_DOMAINS
21static inline int pci_domain_nr(struct pci_bus *bus)
22{
23	struct pci_sys_data *root = bus->sysdata;
24
25	return root->domain;
26}
27
28static inline int pci_proc_domain(struct pci_bus *bus)
29{
30	return pci_domain_nr(bus);
31}
32#endif /* CONFIG_PCI_DOMAINS */
33
34#ifdef CONFIG_PCI_HOST_ITE8152
35/* ITE bridge requires setting latency timer to avoid early bus access
36   termination by PIC bus mater devices
37*/
38extern void pcibios_set_master(struct pci_dev *dev);
39#else
40static inline void pcibios_set_master(struct pci_dev *dev)
41{
42	/* No special bus mastering setup handling */
43}
44#endif
45
46static inline void pcibios_penalize_isa_irq(int irq, int active)
47{
48	/* We don't do dynamic PCI IRQ allocation */
49}
50
51/*
52 * The PCI address space does equal the physical memory address space.
53 * The networking and block device layers use this boolean for bounce
54 * buffer decisions.
55 */
56#define PCI_DMA_BUS_IS_PHYS     (1)
57
58#ifdef CONFIG_PCI
59static inline void pci_dma_burst_advice(struct pci_dev *pdev,
60					enum pci_dma_burst_strategy *strat,
61					unsigned long *strategy_parameter)
62{
63	*strat = PCI_DMA_BURST_INFINITY;
64	*strategy_parameter = ~0UL;
65}
66#endif
67
68#define HAVE_PCI_MMAP
69extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
70                               enum pci_mmap_state mmap_state, int write_combine);
71
72extern void
73pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
74			 struct resource *res);
75
76extern void
77pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
78			struct pci_bus_region *region);
79
80/*
81 * Dummy implementation; always return 0.
82 */
83static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
84{
85	return 0;
86}
87
88#endif /* __KERNEL__ */
89 
90#endif