1/*
  2 * Copyright 2018 Red Hat Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 */
 22#include "nv50.h"
 23#include "head.h"
 24#include "ior.h"
 25#include "channv50.h"
 26#include "rootnv50.h"
 27
 28#include <core/gpuobj.h>
 29#include <subdev/timer.h>
 30
 31static int
 32tu102_disp_init(struct nv50_disp *disp)
 33{
 34	struct nvkm_device *device = disp->base.engine.subdev.device;
 35	struct nvkm_head *head;
 36	int i, j;
 37	u32 tmp;
 38
 39	/* Claim ownership of display. */
 40	if (nvkm_rd32(device, 0x6254e8) & 0x00000002) {
 41		nvkm_mask(device, 0x6254e8, 0x00000001, 0x00000000);
 42		if (nvkm_msec(device, 2000,
 43			if (!(nvkm_rd32(device, 0x6254e8) & 0x00000002))
 44				break;
 45		) < 0)
 46			return -EBUSY;
 47	}
 48
 49	/* Lock pin capabilities. */
 50	tmp = 0x00000021; /*XXX*/
 51	nvkm_wr32(device, 0x640008, tmp);
 52
 53	/* SOR capabilities. */
 54	for (i = 0; i < disp->sor.nr; i++) {
 55		tmp = nvkm_rd32(device, 0x61c000 + (i * 0x800));
 56		nvkm_mask(device, 0x640000, 0x00000100 << i, 0x00000100 << i);
 57		nvkm_wr32(device, 0x640144 + (i * 0x08), tmp);
 58	}
 59
 60	/* Head capabilities. */
 61	list_for_each_entry(head, &disp->base.head, head) {
 62		const int id = head->id;
 63
 64		/* RG. */
 65		tmp = nvkm_rd32(device, 0x616300 + (id * 0x800));
 66		nvkm_wr32(device, 0x640048 + (id * 0x020), tmp);
 67
 68		/* POSTCOMP. */
 69		for (j = 0; j < 5 * 4; j += 4) {
 70			tmp = nvkm_rd32(device, 0x616140 + (id * 0x800) + j);
 71			nvkm_wr32(device, 0x640680 + (id * 0x20) + j, tmp);
 72		}
 73	}
 74
 75	/* Window capabilities. */
 76	for (i = 0; i < disp->wndw.nr; i++) {
 77		nvkm_mask(device, 0x640004, 1 << i, 1 << i);
 78		for (j = 0; j < 6 * 4; j += 4) {
 79			tmp = nvkm_rd32(device, 0x630100 + (i * 0x800) + j);
 80			nvkm_mask(device, 0x640780 + (i * 0x20) + j, 0xffffffff, tmp);
 81		}
 82		nvkm_mask(device, 0x64000c, 0x00000100, 0x00000100);
 83	}
 84
 85	/* IHUB capabilities. */
 86	for (i = 0; i < 3; i++) {
 87		tmp = nvkm_rd32(device, 0x62e000 + (i * 0x04));
 88		nvkm_wr32(device, 0x640010 + (i * 0x04), tmp);
 89	}
 90
 91	nvkm_mask(device, 0x610078, 0x00000001, 0x00000001);
 92
 93	/* Setup instance memory. */
 94	switch (nvkm_memory_target(disp->inst->memory)) {
 95	case NVKM_MEM_TARGET_VRAM: tmp = 0x00000001; break;
 96	case NVKM_MEM_TARGET_NCOH: tmp = 0x00000002; break;
 97	case NVKM_MEM_TARGET_HOST: tmp = 0x00000003; break;
 98	default:
 99		break;
100	}
101	nvkm_wr32(device, 0x610010, 0x00000008 | tmp);
102	nvkm_wr32(device, 0x610014, disp->inst->addr >> 16);
103
104	/* CTRL_DISP: AWAKEN, ERROR, SUPERVISOR[1-3]. */
105	nvkm_wr32(device, 0x611cf0, 0x00000187); /* MSK. */
106	nvkm_wr32(device, 0x611db0, 0x00000187); /* EN. */
107
108	/* EXC_OTHER: CURSn, CORE. */
109	nvkm_wr32(device, 0x611cec, disp->head.mask << 16 |
110				    0x00000001); /* MSK. */
111	nvkm_wr32(device, 0x611dac, 0x00000000); /* EN. */
112
113	/* EXC_WINIM. */
114	nvkm_wr32(device, 0x611ce8, disp->wndw.mask); /* MSK. */
115	nvkm_wr32(device, 0x611da8, 0x00000000); /* EN. */
116
117	/* EXC_WIN. */
118	nvkm_wr32(device, 0x611ce4, disp->wndw.mask); /* MSK. */
119	nvkm_wr32(device, 0x611da4, 0x00000000); /* EN. */
120
121	/* HEAD_TIMING(n): VBLANK. */
122	list_for_each_entry(head, &disp->base.head, head) {
123		const u32 hoff = head->id * 4;
124		nvkm_wr32(device, 0x611cc0 + hoff, 0x00000004); /* MSK. */
125		nvkm_wr32(device, 0x611d80 + hoff, 0x00000000); /* EN. */
126	}
127
128	/* OR. */
129	nvkm_wr32(device, 0x611cf4, 0x00000000); /* MSK. */
130	nvkm_wr32(device, 0x611db4, 0x00000000); /* EN. */
131	return 0;
132}
133
134static const struct nv50_disp_func
135tu102_disp = {
136	.init = tu102_disp_init,
137	.fini = gv100_disp_fini,
138	.intr = gv100_disp_intr,
139	.uevent = &gv100_disp_chan_uevent,
140	.super = gv100_disp_super,
141	.root = &tu102_disp_root_oclass,
142	.wndw = { .cnt = gv100_disp_wndw_cnt },
143	.head = { .cnt = gv100_head_cnt, .new = gv100_head_new },
144	.sor = { .cnt = gv100_sor_cnt, .new = tu102_sor_new },
145	.ramht_size = 0x2000,
146};
147
148int
149tu102_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp)
150{
151	return nv50_disp_new_(&tu102_disp, device, index, pdisp);
152}