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1/*
2 * Allwinner SoCs SRAM Controller Driver
3 *
4 * Copyright (C) 2015 Maxime Ripard
5 *
6 * Author: Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/debugfs.h>
14#include <linux/io.h>
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18#include <linux/of_device.h>
19#include <linux/platform_device.h>
20#include <linux/regmap.h>
21
22#include <linux/soc/sunxi/sunxi_sram.h>
23
24struct sunxi_sram_func {
25 char *func;
26 u8 val;
27 u32 reg_val;
28};
29
30struct sunxi_sram_data {
31 char *name;
32 u8 reg;
33 u8 offset;
34 u8 width;
35 struct sunxi_sram_func *func;
36 struct list_head list;
37};
38
39struct sunxi_sram_desc {
40 struct sunxi_sram_data data;
41 bool claimed;
42};
43
44#define SUNXI_SRAM_MAP(_reg_val, _val, _func) \
45 { \
46 .func = _func, \
47 .val = _val, \
48 .reg_val = _reg_val, \
49 }
50
51#define SUNXI_SRAM_DATA(_name, _reg, _off, _width, ...) \
52 { \
53 .name = _name, \
54 .reg = _reg, \
55 .offset = _off, \
56 .width = _width, \
57 .func = (struct sunxi_sram_func[]){ \
58 __VA_ARGS__, { } }, \
59 }
60
61static struct sunxi_sram_desc sun4i_a10_sram_a3_a4 = {
62 .data = SUNXI_SRAM_DATA("A3-A4", 0x4, 0x4, 2,
63 SUNXI_SRAM_MAP(0, 0, "cpu"),
64 SUNXI_SRAM_MAP(1, 1, "emac")),
65};
66
67static struct sunxi_sram_desc sun4i_a10_sram_c1 = {
68 .data = SUNXI_SRAM_DATA("C1", 0x0, 0x0, 31,
69 SUNXI_SRAM_MAP(0, 0, "cpu"),
70 SUNXI_SRAM_MAP(0x7fffffff, 1, "ve")),
71};
72
73static struct sunxi_sram_desc sun4i_a10_sram_d = {
74 .data = SUNXI_SRAM_DATA("D", 0x4, 0x0, 1,
75 SUNXI_SRAM_MAP(0, 0, "cpu"),
76 SUNXI_SRAM_MAP(1, 1, "usb-otg")),
77};
78
79static struct sunxi_sram_desc sun50i_a64_sram_c = {
80 .data = SUNXI_SRAM_DATA("C", 0x4, 24, 1,
81 SUNXI_SRAM_MAP(0, 1, "cpu"),
82 SUNXI_SRAM_MAP(1, 0, "de2")),
83};
84
85static const struct of_device_id sunxi_sram_dt_ids[] = {
86 {
87 .compatible = "allwinner,sun4i-a10-sram-a3-a4",
88 .data = &sun4i_a10_sram_a3_a4.data,
89 },
90 {
91 .compatible = "allwinner,sun4i-a10-sram-c1",
92 .data = &sun4i_a10_sram_c1.data,
93 },
94 {
95 .compatible = "allwinner,sun4i-a10-sram-d",
96 .data = &sun4i_a10_sram_d.data,
97 },
98 {
99 .compatible = "allwinner,sun50i-a64-sram-c",
100 .data = &sun50i_a64_sram_c.data,
101 },
102 {}
103};
104
105static struct device *sram_dev;
106static LIST_HEAD(claimed_sram);
107static DEFINE_SPINLOCK(sram_lock);
108static void __iomem *base;
109
110static int sunxi_sram_show(struct seq_file *s, void *data)
111{
112 struct device_node *sram_node, *section_node;
113 const struct sunxi_sram_data *sram_data;
114 const struct of_device_id *match;
115 struct sunxi_sram_func *func;
116 const __be32 *sram_addr_p, *section_addr_p;
117 u32 val;
118
119 seq_puts(s, "Allwinner sunXi SRAM\n");
120 seq_puts(s, "--------------------\n\n");
121
122 for_each_child_of_node(sram_dev->of_node, sram_node) {
123 sram_addr_p = of_get_address(sram_node, 0, NULL, NULL);
124
125 seq_printf(s, "sram@%08x\n",
126 be32_to_cpu(*sram_addr_p));
127
128 for_each_child_of_node(sram_node, section_node) {
129 match = of_match_node(sunxi_sram_dt_ids, section_node);
130 if (!match)
131 continue;
132 sram_data = match->data;
133
134 section_addr_p = of_get_address(section_node, 0,
135 NULL, NULL);
136
137 seq_printf(s, "\tsection@%04x\t(%s)\n",
138 be32_to_cpu(*section_addr_p),
139 sram_data->name);
140
141 val = readl(base + sram_data->reg);
142 val >>= sram_data->offset;
143 val &= GENMASK(sram_data->width - 1, 0);
144
145 for (func = sram_data->func; func->func; func++) {
146 seq_printf(s, "\t\t%s%c\n", func->func,
147 func->reg_val == val ?
148 '*' : ' ');
149 }
150 }
151
152 seq_puts(s, "\n");
153 }
154
155 return 0;
156}
157
158DEFINE_SHOW_ATTRIBUTE(sunxi_sram);
159
160static inline struct sunxi_sram_desc *to_sram_desc(const struct sunxi_sram_data *data)
161{
162 return container_of(data, struct sunxi_sram_desc, data);
163}
164
165static const struct sunxi_sram_data *sunxi_sram_of_parse(struct device_node *node,
166 unsigned int *reg_value)
167{
168 const struct of_device_id *match;
169 const struct sunxi_sram_data *data;
170 struct sunxi_sram_func *func;
171 struct of_phandle_args args;
172 u8 val;
173 int ret;
174
175 ret = of_parse_phandle_with_fixed_args(node, "allwinner,sram", 1, 0,
176 &args);
177 if (ret)
178 return ERR_PTR(ret);
179
180 if (!of_device_is_available(args.np)) {
181 ret = -EBUSY;
182 goto err;
183 }
184
185 val = args.args[0];
186
187 match = of_match_node(sunxi_sram_dt_ids, args.np);
188 if (!match) {
189 ret = -EINVAL;
190 goto err;
191 }
192
193 data = match->data;
194 if (!data) {
195 ret = -EINVAL;
196 goto err;
197 };
198
199 for (func = data->func; func->func; func++) {
200 if (val == func->val) {
201 if (reg_value)
202 *reg_value = func->reg_val;
203
204 break;
205 }
206 }
207
208 if (!func->func) {
209 ret = -EINVAL;
210 goto err;
211 }
212
213 of_node_put(args.np);
214 return match->data;
215
216err:
217 of_node_put(args.np);
218 return ERR_PTR(ret);
219}
220
221int sunxi_sram_claim(struct device *dev)
222{
223 const struct sunxi_sram_data *sram_data;
224 struct sunxi_sram_desc *sram_desc;
225 unsigned int device;
226 u32 val, mask;
227
228 if (IS_ERR(base))
229 return PTR_ERR(base);
230
231 if (!base)
232 return -EPROBE_DEFER;
233
234 if (!dev || !dev->of_node)
235 return -EINVAL;
236
237 sram_data = sunxi_sram_of_parse(dev->of_node, &device);
238 if (IS_ERR(sram_data))
239 return PTR_ERR(sram_data);
240
241 sram_desc = to_sram_desc(sram_data);
242
243 spin_lock(&sram_lock);
244
245 if (sram_desc->claimed) {
246 spin_unlock(&sram_lock);
247 return -EBUSY;
248 }
249
250 mask = GENMASK(sram_data->offset + sram_data->width - 1,
251 sram_data->offset);
252 val = readl(base + sram_data->reg);
253 val &= ~mask;
254 writel(val | ((device << sram_data->offset) & mask),
255 base + sram_data->reg);
256
257 spin_unlock(&sram_lock);
258
259 return 0;
260}
261EXPORT_SYMBOL(sunxi_sram_claim);
262
263int sunxi_sram_release(struct device *dev)
264{
265 const struct sunxi_sram_data *sram_data;
266 struct sunxi_sram_desc *sram_desc;
267
268 if (!dev || !dev->of_node)
269 return -EINVAL;
270
271 sram_data = sunxi_sram_of_parse(dev->of_node, NULL);
272 if (IS_ERR(sram_data))
273 return -EINVAL;
274
275 sram_desc = to_sram_desc(sram_data);
276
277 spin_lock(&sram_lock);
278 sram_desc->claimed = false;
279 spin_unlock(&sram_lock);
280
281 return 0;
282}
283EXPORT_SYMBOL(sunxi_sram_release);
284
285struct sunxi_sramc_variant {
286 bool has_emac_clock;
287};
288
289static const struct sunxi_sramc_variant sun4i_a10_sramc_variant = {
290 /* Nothing special */
291};
292
293static const struct sunxi_sramc_variant sun8i_h3_sramc_variant = {
294 .has_emac_clock = true,
295};
296
297static const struct sunxi_sramc_variant sun50i_a64_sramc_variant = {
298 .has_emac_clock = true,
299};
300
301#define SUNXI_SRAM_EMAC_CLOCK_REG 0x30
302static bool sunxi_sram_regmap_accessible_reg(struct device *dev,
303 unsigned int reg)
304{
305 if (reg == SUNXI_SRAM_EMAC_CLOCK_REG)
306 return true;
307 return false;
308}
309
310static struct regmap_config sunxi_sram_emac_clock_regmap = {
311 .reg_bits = 32,
312 .val_bits = 32,
313 .reg_stride = 4,
314 /* last defined register */
315 .max_register = SUNXI_SRAM_EMAC_CLOCK_REG,
316 /* other devices have no business accessing other registers */
317 .readable_reg = sunxi_sram_regmap_accessible_reg,
318 .writeable_reg = sunxi_sram_regmap_accessible_reg,
319};
320
321static int sunxi_sram_probe(struct platform_device *pdev)
322{
323 struct resource *res;
324 struct dentry *d;
325 struct regmap *emac_clock;
326 const struct sunxi_sramc_variant *variant;
327
328 sram_dev = &pdev->dev;
329
330 variant = of_device_get_match_data(&pdev->dev);
331 if (!variant)
332 return -EINVAL;
333
334 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
335 base = devm_ioremap_resource(&pdev->dev, res);
336 if (IS_ERR(base))
337 return PTR_ERR(base);
338
339 of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
340
341 d = debugfs_create_file("sram", S_IRUGO, NULL, NULL,
342 &sunxi_sram_fops);
343 if (!d)
344 return -ENOMEM;
345
346 if (variant->has_emac_clock) {
347 emac_clock = devm_regmap_init_mmio(&pdev->dev, base,
348 &sunxi_sram_emac_clock_regmap);
349
350 if (IS_ERR(emac_clock))
351 return PTR_ERR(emac_clock);
352 }
353
354 return 0;
355}
356
357static const struct of_device_id sunxi_sram_dt_match[] = {
358 {
359 .compatible = "allwinner,sun4i-a10-sram-controller",
360 .data = &sun4i_a10_sramc_variant,
361 },
362 {
363 .compatible = "allwinner,sun4i-a10-system-control",
364 .data = &sun4i_a10_sramc_variant,
365 },
366 {
367 .compatible = "allwinner,sun5i-a13-system-control",
368 .data = &sun4i_a10_sramc_variant,
369 },
370 {
371 .compatible = "allwinner,sun8i-a23-system-control",
372 .data = &sun4i_a10_sramc_variant,
373 },
374 {
375 .compatible = "allwinner,sun8i-h3-system-control",
376 .data = &sun8i_h3_sramc_variant,
377 },
378 {
379 .compatible = "allwinner,sun50i-a64-sram-controller",
380 .data = &sun50i_a64_sramc_variant,
381 },
382 {
383 .compatible = "allwinner,sun50i-a64-system-control",
384 .data = &sun50i_a64_sramc_variant,
385 },
386 {
387 .compatible = "allwinner,sun50i-h5-system-control",
388 .data = &sun50i_a64_sramc_variant,
389 },
390 { },
391};
392MODULE_DEVICE_TABLE(of, sunxi_sram_dt_match);
393
394static struct platform_driver sunxi_sram_driver = {
395 .driver = {
396 .name = "sunxi-sram",
397 .of_match_table = sunxi_sram_dt_match,
398 },
399 .probe = sunxi_sram_probe,
400};
401module_platform_driver(sunxi_sram_driver);
402
403MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
404MODULE_DESCRIPTION("Allwinner sunXi SRAM Controller Driver");
405MODULE_LICENSE("GPL");
1/*
2 * Allwinner SoCs SRAM Controller Driver
3 *
4 * Copyright (C) 2015 Maxime Ripard
5 *
6 * Author: Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/debugfs.h>
14#include <linux/io.h>
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18#include <linux/of_platform.h>
19#include <linux/platform_device.h>
20#include <linux/regmap.h>
21
22#include <linux/soc/sunxi/sunxi_sram.h>
23
24struct sunxi_sram_func {
25 char *func;
26 u8 val;
27 u32 reg_val;
28};
29
30struct sunxi_sram_data {
31 char *name;
32 u8 reg;
33 u8 offset;
34 u8 width;
35 struct sunxi_sram_func *func;
36 struct list_head list;
37};
38
39struct sunxi_sram_desc {
40 struct sunxi_sram_data data;
41 bool claimed;
42};
43
44#define SUNXI_SRAM_MAP(_reg_val, _val, _func) \
45 { \
46 .func = _func, \
47 .val = _val, \
48 .reg_val = _reg_val, \
49 }
50
51#define SUNXI_SRAM_DATA(_name, _reg, _off, _width, ...) \
52 { \
53 .name = _name, \
54 .reg = _reg, \
55 .offset = _off, \
56 .width = _width, \
57 .func = (struct sunxi_sram_func[]){ \
58 __VA_ARGS__, { } }, \
59 }
60
61static struct sunxi_sram_desc sun4i_a10_sram_a3_a4 = {
62 .data = SUNXI_SRAM_DATA("A3-A4", 0x4, 0x4, 2,
63 SUNXI_SRAM_MAP(0, 0, "cpu"),
64 SUNXI_SRAM_MAP(1, 1, "emac")),
65};
66
67static struct sunxi_sram_desc sun4i_a10_sram_c1 = {
68 .data = SUNXI_SRAM_DATA("C1", 0x0, 0x0, 31,
69 SUNXI_SRAM_MAP(0, 0, "cpu"),
70 SUNXI_SRAM_MAP(0x7fffffff, 1, "ve")),
71};
72
73static struct sunxi_sram_desc sun4i_a10_sram_d = {
74 .data = SUNXI_SRAM_DATA("D", 0x4, 0x0, 1,
75 SUNXI_SRAM_MAP(0, 0, "cpu"),
76 SUNXI_SRAM_MAP(1, 1, "usb-otg")),
77};
78
79static struct sunxi_sram_desc sun50i_a64_sram_c = {
80 .data = SUNXI_SRAM_DATA("C", 0x4, 24, 1,
81 SUNXI_SRAM_MAP(1, 0, "cpu"),
82 SUNXI_SRAM_MAP(0, 1, "de2")),
83};
84
85static const struct of_device_id sunxi_sram_dt_ids[] = {
86 {
87 .compatible = "allwinner,sun4i-a10-sram-a3-a4",
88 .data = &sun4i_a10_sram_a3_a4.data,
89 },
90 {
91 .compatible = "allwinner,sun4i-a10-sram-c1",
92 .data = &sun4i_a10_sram_c1.data,
93 },
94 {
95 .compatible = "allwinner,sun4i-a10-sram-d",
96 .data = &sun4i_a10_sram_d.data,
97 },
98 {
99 .compatible = "allwinner,sun50i-a64-sram-c",
100 .data = &sun50i_a64_sram_c.data,
101 },
102 {}
103};
104
105static struct device *sram_dev;
106static LIST_HEAD(claimed_sram);
107static DEFINE_SPINLOCK(sram_lock);
108static void __iomem *base;
109
110static int sunxi_sram_show(struct seq_file *s, void *data)
111{
112 struct device_node *sram_node, *section_node;
113 const struct sunxi_sram_data *sram_data;
114 const struct of_device_id *match;
115 struct sunxi_sram_func *func;
116 const __be32 *sram_addr_p, *section_addr_p;
117 u32 val;
118
119 seq_puts(s, "Allwinner sunXi SRAM\n");
120 seq_puts(s, "--------------------\n\n");
121
122 for_each_child_of_node(sram_dev->of_node, sram_node) {
123 if (!of_device_is_compatible(sram_node, "mmio-sram"))
124 continue;
125
126 sram_addr_p = of_get_address(sram_node, 0, NULL, NULL);
127
128 seq_printf(s, "sram@%08x\n",
129 be32_to_cpu(*sram_addr_p));
130
131 for_each_child_of_node(sram_node, section_node) {
132 match = of_match_node(sunxi_sram_dt_ids, section_node);
133 if (!match)
134 continue;
135 sram_data = match->data;
136
137 section_addr_p = of_get_address(section_node, 0,
138 NULL, NULL);
139
140 seq_printf(s, "\tsection@%04x\t(%s)\n",
141 be32_to_cpu(*section_addr_p),
142 sram_data->name);
143
144 val = readl(base + sram_data->reg);
145 val >>= sram_data->offset;
146 val &= GENMASK(sram_data->width - 1, 0);
147
148 for (func = sram_data->func; func->func; func++) {
149 seq_printf(s, "\t\t%s%c\n", func->func,
150 func->reg_val == val ?
151 '*' : ' ');
152 }
153 }
154
155 seq_puts(s, "\n");
156 }
157
158 return 0;
159}
160
161DEFINE_SHOW_ATTRIBUTE(sunxi_sram);
162
163static inline struct sunxi_sram_desc *to_sram_desc(const struct sunxi_sram_data *data)
164{
165 return container_of(data, struct sunxi_sram_desc, data);
166}
167
168static const struct sunxi_sram_data *sunxi_sram_of_parse(struct device_node *node,
169 unsigned int *reg_value)
170{
171 const struct of_device_id *match;
172 const struct sunxi_sram_data *data;
173 struct sunxi_sram_func *func;
174 struct of_phandle_args args;
175 u8 val;
176 int ret;
177
178 ret = of_parse_phandle_with_fixed_args(node, "allwinner,sram", 1, 0,
179 &args);
180 if (ret)
181 return ERR_PTR(ret);
182
183 if (!of_device_is_available(args.np)) {
184 ret = -EBUSY;
185 goto err;
186 }
187
188 val = args.args[0];
189
190 match = of_match_node(sunxi_sram_dt_ids, args.np);
191 if (!match) {
192 ret = -EINVAL;
193 goto err;
194 }
195
196 data = match->data;
197 if (!data) {
198 ret = -EINVAL;
199 goto err;
200 }
201
202 for (func = data->func; func->func; func++) {
203 if (val == func->val) {
204 if (reg_value)
205 *reg_value = func->reg_val;
206
207 break;
208 }
209 }
210
211 if (!func->func) {
212 ret = -EINVAL;
213 goto err;
214 }
215
216 of_node_put(args.np);
217 return match->data;
218
219err:
220 of_node_put(args.np);
221 return ERR_PTR(ret);
222}
223
224int sunxi_sram_claim(struct device *dev)
225{
226 const struct sunxi_sram_data *sram_data;
227 struct sunxi_sram_desc *sram_desc;
228 unsigned int device;
229 u32 val, mask;
230
231 if (IS_ERR(base))
232 return PTR_ERR(base);
233
234 if (!base)
235 return -EPROBE_DEFER;
236
237 if (!dev || !dev->of_node)
238 return -EINVAL;
239
240 sram_data = sunxi_sram_of_parse(dev->of_node, &device);
241 if (IS_ERR(sram_data))
242 return PTR_ERR(sram_data);
243
244 sram_desc = to_sram_desc(sram_data);
245
246 spin_lock(&sram_lock);
247
248 if (sram_desc->claimed) {
249 spin_unlock(&sram_lock);
250 return -EBUSY;
251 }
252
253 mask = GENMASK(sram_data->offset + sram_data->width - 1,
254 sram_data->offset);
255 val = readl(base + sram_data->reg);
256 val &= ~mask;
257 writel(val | ((device << sram_data->offset) & mask),
258 base + sram_data->reg);
259
260 sram_desc->claimed = true;
261 spin_unlock(&sram_lock);
262
263 return 0;
264}
265EXPORT_SYMBOL(sunxi_sram_claim);
266
267void sunxi_sram_release(struct device *dev)
268{
269 const struct sunxi_sram_data *sram_data;
270 struct sunxi_sram_desc *sram_desc;
271
272 if (!dev || !dev->of_node)
273 return;
274
275 sram_data = sunxi_sram_of_parse(dev->of_node, NULL);
276 if (IS_ERR(sram_data))
277 return;
278
279 sram_desc = to_sram_desc(sram_data);
280
281 spin_lock(&sram_lock);
282 sram_desc->claimed = false;
283 spin_unlock(&sram_lock);
284}
285EXPORT_SYMBOL(sunxi_sram_release);
286
287struct sunxi_sramc_variant {
288 int num_emac_clocks;
289 bool has_ldo_ctrl;
290 bool has_ths_offset;
291};
292
293static const struct sunxi_sramc_variant sun4i_a10_sramc_variant = {
294 /* Nothing special */
295};
296
297static const struct sunxi_sramc_variant sun8i_h3_sramc_variant = {
298 .num_emac_clocks = 1,
299};
300
301static const struct sunxi_sramc_variant sun20i_d1_sramc_variant = {
302 .num_emac_clocks = 1,
303 .has_ldo_ctrl = true,
304};
305
306static const struct sunxi_sramc_variant sun50i_a64_sramc_variant = {
307 .num_emac_clocks = 1,
308};
309
310static const struct sunxi_sramc_variant sun50i_h616_sramc_variant = {
311 .num_emac_clocks = 2,
312 .has_ths_offset = true,
313};
314
315#define SUNXI_SRAM_THS_OFFSET_REG 0x0
316#define SUNXI_SRAM_EMAC_CLOCK_REG 0x30
317#define SUNXI_SYS_LDO_CTRL_REG 0x150
318
319static bool sunxi_sram_regmap_accessible_reg(struct device *dev,
320 unsigned int reg)
321{
322 const struct sunxi_sramc_variant *variant = dev_get_drvdata(dev);
323
324 if (reg == SUNXI_SRAM_THS_OFFSET_REG && variant->has_ths_offset)
325 return true;
326 if (reg >= SUNXI_SRAM_EMAC_CLOCK_REG &&
327 reg < SUNXI_SRAM_EMAC_CLOCK_REG + variant->num_emac_clocks * 4)
328 return true;
329 if (reg == SUNXI_SYS_LDO_CTRL_REG && variant->has_ldo_ctrl)
330 return true;
331
332 return false;
333}
334
335static void sunxi_sram_lock(void *_lock)
336{
337 spinlock_t *lock = _lock;
338
339 spin_lock(lock);
340}
341
342static void sunxi_sram_unlock(void *_lock)
343{
344 spinlock_t *lock = _lock;
345
346 spin_unlock(lock);
347}
348
349static struct regmap_config sunxi_sram_regmap_config = {
350 .reg_bits = 32,
351 .val_bits = 32,
352 .reg_stride = 4,
353 /* last defined register */
354 .max_register = SUNXI_SYS_LDO_CTRL_REG,
355 /* other devices have no business accessing other registers */
356 .readable_reg = sunxi_sram_regmap_accessible_reg,
357 .writeable_reg = sunxi_sram_regmap_accessible_reg,
358 .lock = sunxi_sram_lock,
359 .unlock = sunxi_sram_unlock,
360 .lock_arg = &sram_lock,
361};
362
363static int __init sunxi_sram_probe(struct platform_device *pdev)
364{
365 const struct sunxi_sramc_variant *variant;
366 struct device *dev = &pdev->dev;
367 struct regmap *regmap;
368
369 sram_dev = &pdev->dev;
370
371 variant = of_device_get_match_data(&pdev->dev);
372 if (!variant)
373 return -EINVAL;
374
375 dev_set_drvdata(dev, (struct sunxi_sramc_variant *)variant);
376
377 base = devm_platform_ioremap_resource(pdev, 0);
378 if (IS_ERR(base))
379 return PTR_ERR(base);
380
381 if (variant->num_emac_clocks || variant->has_ldo_ctrl) {
382 regmap = devm_regmap_init_mmio(dev, base, &sunxi_sram_regmap_config);
383 if (IS_ERR(regmap))
384 return PTR_ERR(regmap);
385 }
386
387 of_platform_populate(dev->of_node, NULL, NULL, dev);
388
389 debugfs_create_file("sram", 0444, NULL, NULL, &sunxi_sram_fops);
390
391 return 0;
392}
393
394static const struct of_device_id sunxi_sram_dt_match[] = {
395 {
396 .compatible = "allwinner,sun4i-a10-sram-controller",
397 .data = &sun4i_a10_sramc_variant,
398 },
399 {
400 .compatible = "allwinner,sun4i-a10-system-control",
401 .data = &sun4i_a10_sramc_variant,
402 },
403 {
404 .compatible = "allwinner,sun5i-a13-system-control",
405 .data = &sun4i_a10_sramc_variant,
406 },
407 {
408 .compatible = "allwinner,sun8i-a23-system-control",
409 .data = &sun4i_a10_sramc_variant,
410 },
411 {
412 .compatible = "allwinner,sun8i-h3-system-control",
413 .data = &sun8i_h3_sramc_variant,
414 },
415 {
416 .compatible = "allwinner,sun20i-d1-system-control",
417 .data = &sun20i_d1_sramc_variant,
418 },
419 {
420 .compatible = "allwinner,sun50i-a64-sram-controller",
421 .data = &sun50i_a64_sramc_variant,
422 },
423 {
424 .compatible = "allwinner,sun50i-a64-system-control",
425 .data = &sun50i_a64_sramc_variant,
426 },
427 {
428 .compatible = "allwinner,sun50i-h5-system-control",
429 .data = &sun50i_a64_sramc_variant,
430 },
431 {
432 .compatible = "allwinner,sun50i-h616-system-control",
433 .data = &sun50i_h616_sramc_variant,
434 },
435 { },
436};
437MODULE_DEVICE_TABLE(of, sunxi_sram_dt_match);
438
439static struct platform_driver sunxi_sram_driver = {
440 .driver = {
441 .name = "sunxi-sram",
442 .of_match_table = sunxi_sram_dt_match,
443 },
444};
445builtin_platform_driver_probe(sunxi_sram_driver, sunxi_sram_probe);
446
447MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
448MODULE_DESCRIPTION("Allwinner sunXi SRAM Controller Driver");