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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4 */
5
6#ifndef QCOM_PHY_QMP_H_
7#define QCOM_PHY_QMP_H_
8
9/* Only for QMP V2 PHY - QSERDES COM registers */
10#define QSERDES_COM_BG_TIMER 0x00c
11#define QSERDES_COM_SSC_EN_CENTER 0x010
12#define QSERDES_COM_SSC_ADJ_PER1 0x014
13#define QSERDES_COM_SSC_ADJ_PER2 0x018
14#define QSERDES_COM_SSC_PER1 0x01c
15#define QSERDES_COM_SSC_PER2 0x020
16#define QSERDES_COM_SSC_STEP_SIZE1 0x024
17#define QSERDES_COM_SSC_STEP_SIZE2 0x028
18#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034
19#define QSERDES_COM_CLK_ENABLE1 0x038
20#define QSERDES_COM_SYS_CLK_CTRL 0x03c
21#define QSERDES_COM_SYSCLK_BUF_ENABLE 0x040
22#define QSERDES_COM_PLL_IVCO 0x048
23#define QSERDES_COM_LOCK_CMP1_MODE0 0x04c
24#define QSERDES_COM_LOCK_CMP2_MODE0 0x050
25#define QSERDES_COM_LOCK_CMP3_MODE0 0x054
26#define QSERDES_COM_LOCK_CMP1_MODE1 0x058
27#define QSERDES_COM_LOCK_CMP2_MODE1 0x05c
28#define QSERDES_COM_LOCK_CMP3_MODE1 0x060
29#define QSERDES_COM_BG_TRIM 0x070
30#define QSERDES_COM_CLK_EP_DIV 0x074
31#define QSERDES_COM_CP_CTRL_MODE0 0x078
32#define QSERDES_COM_CP_CTRL_MODE1 0x07c
33#define QSERDES_COM_PLL_RCTRL_MODE0 0x084
34#define QSERDES_COM_PLL_RCTRL_MODE1 0x088
35#define QSERDES_COM_PLL_CCTRL_MODE0 0x090
36#define QSERDES_COM_PLL_CCTRL_MODE1 0x094
37#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x0a8
38#define QSERDES_COM_SYSCLK_EN_SEL 0x0ac
39#define QSERDES_COM_RESETSM_CNTRL 0x0b4
40#define QSERDES_COM_RESTRIM_CTRL 0x0bc
41#define QSERDES_COM_RESCODE_DIV_NUM 0x0c4
42#define QSERDES_COM_LOCK_CMP_EN 0x0c8
43#define QSERDES_COM_LOCK_CMP_CFG 0x0cc
44#define QSERDES_COM_DEC_START_MODE0 0x0d0
45#define QSERDES_COM_DEC_START_MODE1 0x0d4
46#define QSERDES_COM_DIV_FRAC_START1_MODE0 0x0dc
47#define QSERDES_COM_DIV_FRAC_START2_MODE0 0x0e0
48#define QSERDES_COM_DIV_FRAC_START3_MODE0 0x0e4
49#define QSERDES_COM_DIV_FRAC_START1_MODE1 0x0e8
50#define QSERDES_COM_DIV_FRAC_START2_MODE1 0x0ec
51#define QSERDES_COM_DIV_FRAC_START3_MODE1 0x0f0
52#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x108
53#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10c
54#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x110
55#define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x114
56#define QSERDES_COM_VCO_TUNE_CTRL 0x124
57#define QSERDES_COM_VCO_TUNE_MAP 0x128
58#define QSERDES_COM_VCO_TUNE1_MODE0 0x12c
59#define QSERDES_COM_VCO_TUNE2_MODE0 0x130
60#define QSERDES_COM_VCO_TUNE1_MODE1 0x134
61#define QSERDES_COM_VCO_TUNE2_MODE1 0x138
62#define QSERDES_COM_VCO_TUNE_TIMER1 0x144
63#define QSERDES_COM_VCO_TUNE_TIMER2 0x148
64#define QSERDES_COM_BG_CTRL 0x170
65#define QSERDES_COM_CLK_SELECT 0x174
66#define QSERDES_COM_HSCLK_SEL 0x178
67#define QSERDES_COM_CORECLK_DIV 0x184
68#define QSERDES_COM_CORE_CLK_EN 0x18c
69#define QSERDES_COM_C_READY_STATUS 0x190
70#define QSERDES_COM_CMN_CONFIG 0x194
71#define QSERDES_COM_SVS_MODE_CLK_SEL 0x19c
72#define QSERDES_COM_DEBUG_BUS0 0x1a0
73#define QSERDES_COM_DEBUG_BUS1 0x1a4
74#define QSERDES_COM_DEBUG_BUS2 0x1a8
75#define QSERDES_COM_DEBUG_BUS3 0x1ac
76#define QSERDES_COM_DEBUG_BUS_SEL 0x1b0
77#define QSERDES_COM_CORECLK_DIV_MODE1 0x1bc
78
79/* Only for QMP V2 PHY - TX registers */
80#define QSERDES_TX_EMP_POST1_LVL 0x018
81#define QSERDES_TX_SLEW_CNTL 0x040
82#define QSERDES_TX_RES_CODE_LANE_OFFSET 0x054
83#define QSERDES_TX_DEBUG_BUS_SEL 0x064
84#define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x068
85#define QSERDES_TX_LANE_MODE 0x094
86#define QSERDES_TX_RCV_DETECT_LVL_2 0x0ac
87
88/* Only for QMP V2 PHY - RX registers */
89#define QSERDES_RX_UCDR_SO_GAIN_HALF 0x010
90#define QSERDES_RX_UCDR_SO_GAIN 0x01c
91#define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x040
92#define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x048
93#define QSERDES_RX_RX_TERM_BW 0x090
94#define QSERDES_RX_RX_EQ_GAIN1_LSB 0x0c4
95#define QSERDES_RX_RX_EQ_GAIN1_MSB 0x0c8
96#define QSERDES_RX_RX_EQ_GAIN2_LSB 0x0cc
97#define QSERDES_RX_RX_EQ_GAIN2_MSB 0x0d0
98#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d8
99#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x0dc
100#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0e0
101#define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x108
102#define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x10c
103#define QSERDES_RX_SIGDET_ENABLES 0x110
104#define QSERDES_RX_SIGDET_CNTRL 0x114
105#define QSERDES_RX_SIGDET_LVL 0x118
106#define QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x11c
107#define QSERDES_RX_RX_BAND 0x120
108#define QSERDES_RX_RX_INTERFACE_MODE 0x12c
109
110/* Only for QMP V2 PHY - PCS registers */
111#define QPHY_POWER_DOWN_CONTROL 0x04
112#define QPHY_TXDEEMPH_M6DB_V0 0x24
113#define QPHY_TXDEEMPH_M3P5DB_V0 0x28
114#define QPHY_ENDPOINT_REFCLK_DRIVE 0x54
115#define QPHY_RX_IDLE_DTCT_CNTRL 0x58
116#define QPHY_POWER_STATE_CONFIG1 0x60
117#define QPHY_POWER_STATE_CONFIG2 0x64
118#define QPHY_POWER_STATE_CONFIG4 0x6c
119#define QPHY_LOCK_DETECT_CONFIG1 0x80
120#define QPHY_LOCK_DETECT_CONFIG2 0x84
121#define QPHY_LOCK_DETECT_CONFIG3 0x88
122#define QPHY_PWRUP_RESET_DLY_TIME_AUXCLK 0xa0
123#define QPHY_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4
124#define QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1A8
125#define QPHY_OSC_DTCT_ACTIONS 0x1AC
126#define QPHY_RX_SIGDET_LVL 0x1D8
127#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1DC
128#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1E0
129
130/* Only for QMP V3 & V4 PHY - DP COM registers */
131#define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00
132#define QPHY_V3_DP_COM_SW_RESET 0x04
133#define QPHY_V3_DP_COM_POWER_DOWN_CTRL 0x08
134#define QPHY_V3_DP_COM_SWI_CTRL 0x0c
135#define QPHY_V3_DP_COM_TYPEC_CTRL 0x10
136#define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL 0x14
137#define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c
138
139/* Only for QMP V3 PHY - QSERDES COM registers */
140#define QSERDES_V3_COM_BG_TIMER 0x00c
141#define QSERDES_V3_COM_SSC_EN_CENTER 0x010
142#define QSERDES_V3_COM_SSC_ADJ_PER1 0x014
143#define QSERDES_V3_COM_SSC_ADJ_PER2 0x018
144#define QSERDES_V3_COM_SSC_PER1 0x01c
145#define QSERDES_V3_COM_SSC_PER2 0x020
146#define QSERDES_V3_COM_SSC_STEP_SIZE1 0x024
147#define QSERDES_V3_COM_SSC_STEP_SIZE2 0x028
148#define QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN 0x034
149#define QSERDES_V3_COM_CLK_ENABLE1 0x038
150#define QSERDES_V3_COM_SYS_CLK_CTRL 0x03c
151#define QSERDES_V3_COM_SYSCLK_BUF_ENABLE 0x040
152#define QSERDES_V3_COM_PLL_IVCO 0x048
153#define QSERDES_V3_COM_LOCK_CMP1_MODE0 0x098
154#define QSERDES_V3_COM_LOCK_CMP2_MODE0 0x09c
155#define QSERDES_V3_COM_LOCK_CMP3_MODE0 0x0a0
156#define QSERDES_V3_COM_LOCK_CMP1_MODE1 0x0a4
157#define QSERDES_V3_COM_LOCK_CMP2_MODE1 0x0a8
158#define QSERDES_V3_COM_LOCK_CMP3_MODE1 0x0ac
159#define QSERDES_V3_COM_CLK_EP_DIV 0x05c
160#define QSERDES_V3_COM_CP_CTRL_MODE0 0x060
161#define QSERDES_V3_COM_CP_CTRL_MODE1 0x064
162#define QSERDES_V3_COM_PLL_RCTRL_MODE0 0x068
163#define QSERDES_V3_COM_PLL_RCTRL_MODE1 0x06c
164#define QSERDES_V3_COM_PLL_CCTRL_MODE0 0x070
165#define QSERDES_V3_COM_PLL_CCTRL_MODE1 0x074
166#define QSERDES_V3_COM_SYSCLK_EN_SEL 0x080
167#define QSERDES_V3_COM_RESETSM_CNTRL 0x088
168#define QSERDES_V3_COM_RESETSM_CNTRL2 0x08c
169#define QSERDES_V3_COM_LOCK_CMP_EN 0x090
170#define QSERDES_V3_COM_LOCK_CMP_CFG 0x094
171#define QSERDES_V3_COM_DEC_START_MODE0 0x0b0
172#define QSERDES_V3_COM_DEC_START_MODE1 0x0b4
173#define QSERDES_V3_COM_DIV_FRAC_START1_MODE0 0x0b8
174#define QSERDES_V3_COM_DIV_FRAC_START2_MODE0 0x0bc
175#define QSERDES_V3_COM_DIV_FRAC_START3_MODE0 0x0c0
176#define QSERDES_V3_COM_DIV_FRAC_START1_MODE1 0x0c4
177#define QSERDES_V3_COM_DIV_FRAC_START2_MODE1 0x0c8
178#define QSERDES_V3_COM_DIV_FRAC_START3_MODE1 0x0cc
179#define QSERDES_V3_COM_INTEGLOOP_INITVAL 0x0d0
180#define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0 0x0d8
181#define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0 0x0dc
182#define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1 0x0e0
183#define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1 0x0e4
184#define QSERDES_V3_COM_VCO_TUNE_CTRL 0x0ec
185#define QSERDES_V3_COM_VCO_TUNE_MAP 0x0f0
186#define QSERDES_V3_COM_VCO_TUNE1_MODE0 0x0f4
187#define QSERDES_V3_COM_VCO_TUNE2_MODE0 0x0f8
188#define QSERDES_V3_COM_VCO_TUNE1_MODE1 0x0fc
189#define QSERDES_V3_COM_VCO_TUNE2_MODE1 0x100
190#define QSERDES_V3_COM_VCO_TUNE_INITVAL1 0x104
191#define QSERDES_V3_COM_VCO_TUNE_INITVAL2 0x108
192#define QSERDES_V3_COM_VCO_TUNE_TIMER1 0x11c
193#define QSERDES_V3_COM_VCO_TUNE_TIMER2 0x120
194#define QSERDES_V3_COM_CLK_SELECT 0x138
195#define QSERDES_V3_COM_HSCLK_SEL 0x13c
196#define QSERDES_V3_COM_CORECLK_DIV_MODE0 0x148
197#define QSERDES_V3_COM_CORECLK_DIV_MODE1 0x14c
198#define QSERDES_V3_COM_CORE_CLK_EN 0x154
199#define QSERDES_V3_COM_C_READY_STATUS 0x158
200#define QSERDES_V3_COM_CMN_CONFIG 0x15c
201#define QSERDES_V3_COM_SVS_MODE_CLK_SEL 0x164
202#define QSERDES_V3_COM_DEBUG_BUS0 0x168
203#define QSERDES_V3_COM_DEBUG_BUS1 0x16c
204#define QSERDES_V3_COM_DEBUG_BUS2 0x170
205#define QSERDES_V3_COM_DEBUG_BUS3 0x174
206#define QSERDES_V3_COM_DEBUG_BUS_SEL 0x178
207#define QSERDES_V3_COM_CMN_MODE 0x184
208
209/* Only for QMP V3 PHY - TX registers */
210#define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX 0x044
211#define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX 0x048
212#define QSERDES_V3_TX_DEBUG_BUS_SEL 0x058
213#define QSERDES_V3_TX_HIGHZ_DRVR_EN 0x060
214#define QSERDES_V3_TX_LANE_MODE_1 0x08c
215#define QSERDES_V3_TX_RCV_DETECT_LVL_2 0x0a4
216
217/* Only for QMP V3 PHY - RX registers */
218#define QSERDES_V3_RX_UCDR_FO_GAIN 0x008
219#define QSERDES_V3_RX_UCDR_SO_GAIN_HALF 0x00c
220#define QSERDES_V3_RX_UCDR_SO_GAIN 0x014
221#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF 0x024
222#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028
223#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN 0x02c
224#define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN 0x030
225#define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034
226#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c
227#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040
228#define QSERDES_V3_RX_UCDR_PI_CONTROLS 0x044
229#define QSERDES_V3_RX_RX_TERM_BW 0x07c
230#define QSERDES_V3_RX_VGA_CAL_CNTRL1 0x0bc
231#define QSERDES_V3_RX_VGA_CAL_CNTRL2 0x0c0
232#define QSERDES_V3_RX_RX_EQ_GAIN2_LSB 0x0c8
233#define QSERDES_V3_RX_RX_EQ_GAIN2_MSB 0x0cc
234#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d4
235#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3 0x0d8
236#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4 0x0dc
237#define QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x0f8
238#define QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x0fc
239#define QSERDES_V3_RX_SIGDET_ENABLES 0x100
240#define QSERDES_V3_RX_SIGDET_CNTRL 0x104
241#define QSERDES_V3_RX_SIGDET_LVL 0x108
242#define QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL 0x10c
243#define QSERDES_V3_RX_RX_BAND 0x110
244#define QSERDES_V3_RX_RX_INTERFACE_MODE 0x11c
245#define QSERDES_V3_RX_RX_MODE_00 0x164
246#define QSERDES_V3_RX_RX_MODE_01 0x168
247
248/* Only for QMP V3 PHY - PCS registers */
249#define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004
250#define QPHY_V3_PCS_TXMGN_V0 0x00c
251#define QPHY_V3_PCS_TXMGN_V1 0x010
252#define QPHY_V3_PCS_TXMGN_V2 0x014
253#define QPHY_V3_PCS_TXMGN_V3 0x018
254#define QPHY_V3_PCS_TXMGN_V4 0x01c
255#define QPHY_V3_PCS_TXMGN_LS 0x020
256#define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL 0x02c
257#define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL 0x034
258#define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024
259#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 0x028
260#define QPHY_V3_PCS_TXDEEMPH_M6DB_V1 0x02c
261#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1 0x030
262#define QPHY_V3_PCS_TXDEEMPH_M6DB_V2 0x034
263#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2 0x038
264#define QPHY_V3_PCS_TXDEEMPH_M6DB_V3 0x03c
265#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3 0x040
266#define QPHY_V3_PCS_TXDEEMPH_M6DB_V4 0x044
267#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4 0x048
268#define QPHY_V3_PCS_TXDEEMPH_M6DB_LS 0x04c
269#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS 0x050
270#define QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE 0x054
271#define QPHY_V3_PCS_RX_IDLE_DTCT_CNTRL 0x058
272#define QPHY_V3_PCS_RATE_SLEW_CNTRL 0x05c
273#define QPHY_V3_PCS_POWER_STATE_CONFIG1 0x060
274#define QPHY_V3_PCS_POWER_STATE_CONFIG2 0x064
275#define QPHY_V3_PCS_POWER_STATE_CONFIG4 0x06c
276#define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L 0x070
277#define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H 0x074
278#define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L 0x078
279#define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H 0x07c
280#define QPHY_V3_PCS_LOCK_DETECT_CONFIG1 0x080
281#define QPHY_V3_PCS_LOCK_DETECT_CONFIG2 0x084
282#define QPHY_V3_PCS_LOCK_DETECT_CONFIG3 0x088
283#define QPHY_V3_PCS_TSYNC_RSYNC_TIME 0x08c
284#define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0
285#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4
286#define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8
287#define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK 0x0b0
288#define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME 0x0b8
289#define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME 0x0bc
290#define QPHY_V3_PCS_FLL_CNTRL1 0x0c4
291#define QPHY_V3_PCS_FLL_CNTRL2 0x0c8
292#define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc
293#define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0
294#define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4
295#define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL 0x134
296#define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME 0x138
297#define QPHY_V3_PCS_RX_SIGDET_CTRL1 0x13c
298#define QPHY_V3_PCS_RX_SIGDET_CTRL2 0x140
299#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1a8
300#define QPHY_V3_PCS_OSC_DTCT_ACTIONS 0x1ac
301#define QPHY_V3_PCS_SIGDET_CNTRL 0x1b0
302#define QPHY_V3_PCS_TX_MID_TERM_CTRL1 0x1bc
303#define QPHY_V3_PCS_MULTI_LANE_CTRL1 0x1c4
304#define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8
305#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc
306#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0
307#define QPHY_V3_PCS_REFGEN_REQ_CONFIG1 0x20c
308#define QPHY_V3_PCS_REFGEN_REQ_CONFIG2 0x210
309
310/* Only for QMP V3 PHY - PCS_MISC registers */
311#define QPHY_V3_PCS_MISC_CLAMP_ENABLE 0x0c
312#define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2 0x2c
313#define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1 0x44
314#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2 0x54
315#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c
316#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60
317
318/* Only for QMP V4 PHY - QSERDES COM registers */
319#define QSERDES_V4_COM_SSC_EN_CENTER 0x010
320#define QSERDES_V4_COM_SSC_PER1 0x01c
321#define QSERDES_V4_COM_SSC_PER2 0x020
322#define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 0x024
323#define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0 0x028
324#define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1 0x030
325#define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1 0x034
326#define QSERDES_V4_COM_SYSCLK_BUF_ENABLE 0x050
327#define QSERDES_V4_COM_PLL_IVCO 0x058
328#define QSERDES_V4_COM_CMN_IPTRIM 0x060
329#define QSERDES_V4_COM_CP_CTRL_MODE0 0x074
330#define QSERDES_V4_COM_CP_CTRL_MODE1 0x078
331#define QSERDES_V4_COM_PLL_RCTRL_MODE0 0x07c
332#define QSERDES_V4_COM_PLL_RCTRL_MODE1 0x080
333#define QSERDES_V4_COM_PLL_CCTRL_MODE0 0x084
334#define QSERDES_V4_COM_PLL_CCTRL_MODE1 0x088
335#define QSERDES_V4_COM_SYSCLK_EN_SEL 0x094
336#define QSERDES_V4_COM_LOCK_CMP_EN 0x0a4
337#define QSERDES_V4_COM_LOCK_CMP1_MODE0 0x0ac
338#define QSERDES_V4_COM_LOCK_CMP2_MODE0 0x0b0
339#define QSERDES_V4_COM_LOCK_CMP1_MODE1 0x0b4
340#define QSERDES_V4_COM_DEC_START_MODE0 0x0bc
341#define QSERDES_V4_COM_LOCK_CMP2_MODE1 0x0b8
342#define QSERDES_V4_COM_DEC_START_MODE1 0x0c4
343#define QSERDES_V4_COM_DIV_FRAC_START1_MODE0 0x0cc
344#define QSERDES_V4_COM_DIV_FRAC_START2_MODE0 0x0d0
345#define QSERDES_V4_COM_DIV_FRAC_START3_MODE0 0x0d4
346#define QSERDES_V4_COM_DIV_FRAC_START1_MODE1 0x0d8
347#define QSERDES_V4_COM_DIV_FRAC_START2_MODE1 0x0dc
348#define QSERDES_V4_COM_DIV_FRAC_START3_MODE1 0x0e0
349#define QSERDES_V4_COM_VCO_TUNE_MAP 0x10c
350#define QSERDES_V4_COM_VCO_TUNE1_MODE0 0x110
351#define QSERDES_V4_COM_VCO_TUNE2_MODE0 0x114
352#define QSERDES_V4_COM_VCO_TUNE1_MODE1 0x118
353#define QSERDES_V4_COM_VCO_TUNE2_MODE1 0x11c
354#define QSERDES_V4_COM_VCO_TUNE_INITVAL2 0x124
355#define QSERDES_V4_COM_HSCLK_SEL 0x158
356#define QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL 0x15c
357#define QSERDES_V4_COM_CORECLK_DIV_MODE1 0x16c
358#define QSERDES_V4_COM_SVS_MODE_CLK_SEL 0x184
359#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac
360#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0
361#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4
362#define QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc
363#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8
364
365/* Only for QMP V4 PHY - TX registers */
366#define QSERDES_V4_TX_RES_CODE_LANE_TX 0x34
367#define QSERDES_V4_TX_RES_CODE_LANE_RX 0x38
368#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX 0x3c
369#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 0x40
370#define QSERDES_V4_TX_LANE_MODE_1 0x84
371#define QSERDES_V4_TX_LANE_MODE_2 0x88
372#define QSERDES_V4_TX_RCV_DETECT_LVL_2 0x9c
373#define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0xd8
374#define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0xdC
375#define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0xe0
376#define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0xe4
377#define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0xb8
378#define QSERDES_V4_TX_PI_QEC_CTRL 0x104
379
380/* Only for QMP V4 PHY - RX registers */
381#define QSERDES_V4_RX_UCDR_FO_GAIN 0x008
382#define QSERDES_V4_RX_UCDR_SO_GAIN 0x014
383#define QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN 0x030
384#define QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034
385#define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c
386#define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040
387#define QSERDES_V4_RX_UCDR_PI_CONTROLS 0x044
388#define QSERDES_V4_RX_UCDR_PI_CTRL2 0x048
389#define QSERDES_V4_RX_UCDR_SB2_THRESH1 0x04c
390#define QSERDES_V4_RX_UCDR_SB2_THRESH2 0x050
391#define QSERDES_V4_RX_UCDR_SB2_GAIN1 0x054
392#define QSERDES_V4_RX_UCDR_SB2_GAIN2 0x058
393#define QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE 0x060
394#define QSERDES_V4_RX_AC_JTAG_ENABLE 0x068
395#define QSERDES_V4_RX_AC_JTAG_MODE 0x078
396#define QSERDES_V4_RX_RX_TERM_BW 0x080
397#define QSERDES_V4_RX_VGA_CAL_CNTRL1 0x0d4
398#define QSERDES_V4_RX_VGA_CAL_CNTRL2 0x0d8
399#define QSERDES_V4_RX_GM_CAL 0x0dc
400#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec
401#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0
402#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4
403#define QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW 0x0f8
404#define QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH 0x0fc
405#define QSERDES_V4_RX_RX_IDAC_MEASURE_TIME 0x100
406#define QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110
407#define QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114
408#define QSERDES_V4_RX_SIGDET_CNTRL 0x11c
409#define QSERDES_V4_RX_SIGDET_LVL 0x120
410#define QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL 0x124
411#define QSERDES_V4_RX_RX_BAND 0x128
412#define QSERDES_V4_RX_RX_MODE_00_LOW 0x170
413#define QSERDES_V4_RX_RX_MODE_00_HIGH 0x174
414#define QSERDES_V4_RX_RX_MODE_00_HIGH2 0x178
415#define QSERDES_V4_RX_RX_MODE_00_HIGH3 0x17c
416#define QSERDES_V4_RX_RX_MODE_00_HIGH4 0x180
417#define QSERDES_V4_RX_RX_MODE_01_LOW 0x184
418#define QSERDES_V4_RX_RX_MODE_01_HIGH 0x188
419#define QSERDES_V4_RX_RX_MODE_01_HIGH2 0x18c
420#define QSERDES_V4_RX_RX_MODE_01_HIGH3 0x190
421#define QSERDES_V4_RX_RX_MODE_01_HIGH4 0x194
422#define QSERDES_V4_RX_RX_MODE_10_LOW 0x198
423#define QSERDES_V4_RX_RX_MODE_10_HIGH 0x19c
424#define QSERDES_V4_RX_RX_MODE_10_HIGH2 0x1a0
425#define QSERDES_V4_RX_RX_MODE_10_HIGH3 0x1a4
426#define QSERDES_V4_RX_RX_MODE_10_HIGH4 0x1a8
427#define QSERDES_V4_RX_DFE_EN_TIMER 0x1b4
428#define QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET 0x1b8
429#define QSERDES_V4_RX_DCC_CTRL1 0x1bc
430#define QSERDES_V4_RX_VTH_CODE 0x1c4
431
432/* Only for QMP V4 PHY - UFS PCS registers */
433#define QPHY_V4_PCS_UFS_PHY_START 0x000
434#define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004
435#define QPHY_V4_PCS_UFS_SW_RESET 0x008
436#define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
437#define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
438#define QPHY_V4_PCS_UFS_PLL_CNTL 0x02c
439#define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
440#define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
441#define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
442#define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
443#define QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4
444#define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL 0x124
445#define QPHY_V4_PCS_UFS_LINECFG_DISABLE 0x148
446#define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150
447#define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2 0x158
448#define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND 0x160
449#define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND 0x168
450#define QPHY_V4_PCS_UFS_READY_STATUS 0x180
451#define QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8
452#define QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1 0x1e0
453
454/* PCIE GEN3 COM registers */
455#define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14
456#define PCIE_GEN3_QHP_COM_SSC_PER1 0x20
457#define PCIE_GEN3_QHP_COM_SSC_PER2 0x24
458#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28
459#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c
460#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34
461#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38
462#define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54
463#define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58
464#define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c
465#define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0 0x70
466#define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1 0x78
467#define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1 0x7c
468#define PCIE_GEN3_QHP_COM_BGV_TRIM 0x98
469#define PCIE_GEN3_QHP_COM_CP_CTRL_MODE0 0xb4
470#define PCIE_GEN3_QHP_COM_CP_CTRL_MODE1 0xb8
471#define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0 0xc0
472#define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1 0xc4
473#define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0 0xcc
474#define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1 0xd0
475#define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL 0xdc
476#define PCIE_GEN3_QHP_COM_RESTRIM_CTRL2 0xf0
477#define PCIE_GEN3_QHP_COM_LOCK_CMP_EN 0xf8
478#define PCIE_GEN3_QHP_COM_DEC_START_MODE0 0x100
479#define PCIE_GEN3_QHP_COM_DEC_START_MODE1 0x108
480#define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0 0x11c
481#define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0 0x120
482#define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0 0x124
483#define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1 0x128
484#define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1 0x12c
485#define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1 0x130
486#define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0 0x150
487#define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1 0x158
488#define PCIE_GEN3_QHP_COM_VCO_TUNE_MAP 0x178
489#define PCIE_GEN3_QHP_COM_BG_CTRL 0x1c8
490#define PCIE_GEN3_QHP_COM_CLK_SELECT 0x1cc
491#define PCIE_GEN3_QHP_COM_HSCLK_SEL1 0x1d0
492#define PCIE_GEN3_QHP_COM_CORECLK_DIV 0x1e0
493#define PCIE_GEN3_QHP_COM_CORE_CLK_EN 0x1e8
494#define PCIE_GEN3_QHP_COM_CMN_CONFIG 0x1f0
495#define PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL 0x1fc
496#define PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1 0x21c
497#define PCIE_GEN3_QHP_COM_CMN_MODE 0x224
498#define PCIE_GEN3_QHP_COM_VREGCLK_DIV1 0x228
499#define PCIE_GEN3_QHP_COM_VREGCLK_DIV2 0x22c
500
501/* PCIE GEN3 QHP Lane registers */
502#define PCIE_GEN3_QHP_L0_DRVR_CTRL0 0xc
503#define PCIE_GEN3_QHP_L0_DRVR_CTRL1 0x10
504#define PCIE_GEN3_QHP_L0_DRVR_CTRL2 0x14
505#define PCIE_GEN3_QHP_L0_DRVR_TAP_EN 0x18
506#define PCIE_GEN3_QHP_L0_TX_BAND_MODE 0x60
507#define PCIE_GEN3_QHP_L0_LANE_MODE 0x64
508#define PCIE_GEN3_QHP_L0_PARALLEL_RATE 0x7c
509#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE0 0xc0
510#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE1 0xc4
511#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE2 0xc8
512#define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1 0xd0
513#define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2 0xd4
514#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0 0xd8
515#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1 0xdc
516#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2 0xe0
517#define PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE 0xfc
518#define PCIE_GEN3_QHP_L0_CGA_THRESH_DFE 0x100
519#define PCIE_GEN3_QHP_L0_RXENGINE_EN0 0x108
520#define PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME 0x114
521#define PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME 0x118
522#define PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME 0x11c
523#define PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME 0x120
524#define PCIE_GEN3_QHP_L0_VGA_GAIN 0x124
525#define PCIE_GEN3_QHP_L0_DFE_GAIN 0x128
526#define PCIE_GEN3_QHP_L0_EQ_GAIN 0x130
527#define PCIE_GEN3_QHP_L0_OFFSET_GAIN 0x134
528#define PCIE_GEN3_QHP_L0_PRE_GAIN 0x138
529#define PCIE_GEN3_QHP_L0_VGA_INITVAL 0x13c
530#define PCIE_GEN3_QHP_L0_EQ_INTVAL 0x154
531#define PCIE_GEN3_QHP_L0_EDAC_INITVAL 0x160
532#define PCIE_GEN3_QHP_L0_RXEQ_INITB0 0x168
533#define PCIE_GEN3_QHP_L0_RXEQ_INITB1 0x16c
534#define PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1 0x178
535#define PCIE_GEN3_QHP_L0_RXEQ_CTRL 0x180
536#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0 0x184
537#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1 0x188
538#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2 0x18c
539#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0 0x190
540#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1 0x194
541#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2 0x198
542#define PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG 0x19c
543#define PCIE_GEN3_QHP_L0_RX_BAND 0x1a4
544#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0 0x1c0
545#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1 0x1c4
546#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2 0x1c8
547#define PCIE_GEN3_QHP_L0_SIGDET_ENABLES 0x230
548#define PCIE_GEN3_QHP_L0_SIGDET_CNTRL 0x234
549#define PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL 0x238
550#define PCIE_GEN3_QHP_L0_DCC_GAIN 0x2a4
551#define PCIE_GEN3_QHP_L0_RSM_START 0x2a8
552#define PCIE_GEN3_QHP_L0_RX_EN_SIGNAL 0x2ac
553#define PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL 0x2b0
554#define PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0 0x2b8
555#define PCIE_GEN3_QHP_L0_TS0_TIMER 0x2c0
556#define PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE 0x2c4
557#define PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET 0x2cc
558
559/* PCIE GEN3 PCS registers */
560#define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB 0x2c
561#define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB 0x40
562#define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB 0x54
563#define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB 0x68
564#define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG 0x15c
565#define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5 0x16c
566#define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG 0x174
567
568/* Only for QMP V4 PHY - USB/PCIe PCS registers */
569#define QPHY_V4_PCS_SW_RESET 0x000
570#define QPHY_V4_PCS_REVISION_ID0 0x004
571#define QPHY_V4_PCS_REVISION_ID1 0x008
572#define QPHY_V4_PCS_REVISION_ID2 0x00c
573#define QPHY_V4_PCS_REVISION_ID3 0x010
574#define QPHY_V4_PCS_PCS_STATUS1 0x014
575#define QPHY_V4_PCS_PCS_STATUS2 0x018
576#define QPHY_V4_PCS_PCS_STATUS3 0x01c
577#define QPHY_V4_PCS_PCS_STATUS4 0x020
578#define QPHY_V4_PCS_PCS_STATUS5 0x024
579#define QPHY_V4_PCS_PCS_STATUS6 0x028
580#define QPHY_V4_PCS_PCS_STATUS7 0x02c
581#define QPHY_V4_PCS_DEBUG_BUS_0_STATUS 0x030
582#define QPHY_V4_PCS_DEBUG_BUS_1_STATUS 0x034
583#define QPHY_V4_PCS_DEBUG_BUS_2_STATUS 0x038
584#define QPHY_V4_PCS_DEBUG_BUS_3_STATUS 0x03c
585#define QPHY_V4_PCS_POWER_DOWN_CONTROL 0x040
586#define QPHY_V4_PCS_START_CONTROL 0x044
587#define QPHY_V4_PCS_INSIG_SW_CTRL1 0x048
588#define QPHY_V4_PCS_INSIG_SW_CTRL2 0x04c
589#define QPHY_V4_PCS_INSIG_SW_CTRL3 0x050
590#define QPHY_V4_PCS_INSIG_SW_CTRL4 0x054
591#define QPHY_V4_PCS_INSIG_SW_CTRL5 0x058
592#define QPHY_V4_PCS_INSIG_SW_CTRL6 0x05c
593#define QPHY_V4_PCS_INSIG_SW_CTRL7 0x060
594#define QPHY_V4_PCS_INSIG_SW_CTRL8 0x064
595#define QPHY_V4_PCS_INSIG_MX_CTRL1 0x068
596#define QPHY_V4_PCS_INSIG_MX_CTRL2 0x06c
597#define QPHY_V4_PCS_INSIG_MX_CTRL3 0x070
598#define QPHY_V4_PCS_INSIG_MX_CTRL4 0x074
599#define QPHY_V4_PCS_INSIG_MX_CTRL5 0x078
600#define QPHY_V4_PCS_INSIG_MX_CTRL7 0x07c
601#define QPHY_V4_PCS_INSIG_MX_CTRL8 0x080
602#define QPHY_V4_PCS_OUTSIG_SW_CTRL1 0x084
603#define QPHY_V4_PCS_OUTSIG_MX_CTRL1 0x088
604#define QPHY_V4_PCS_CLAMP_ENABLE 0x08c
605#define QPHY_V4_PCS_POWER_STATE_CONFIG1 0x090
606#define QPHY_V4_PCS_POWER_STATE_CONFIG2 0x094
607#define QPHY_V4_PCS_FLL_CNTRL1 0x098
608#define QPHY_V4_PCS_FLL_CNTRL2 0x09c
609#define QPHY_V4_PCS_FLL_CNT_VAL_L 0x0a0
610#define QPHY_V4_PCS_FLL_CNT_VAL_H_TOL 0x0a4
611#define QPHY_V4_PCS_FLL_MAN_CODE 0x0a8
612#define QPHY_V4_PCS_TEST_CONTROL1 0x0ac
613#define QPHY_V4_PCS_TEST_CONTROL2 0x0b0
614#define QPHY_V4_PCS_TEST_CONTROL3 0x0b4
615#define QPHY_V4_PCS_TEST_CONTROL4 0x0b8
616#define QPHY_V4_PCS_TEST_CONTROL5 0x0bc
617#define QPHY_V4_PCS_TEST_CONTROL6 0x0c0
618#define QPHY_V4_PCS_LOCK_DETECT_CONFIG1 0x0c4
619#define QPHY_V4_PCS_LOCK_DETECT_CONFIG2 0x0c8
620#define QPHY_V4_PCS_LOCK_DETECT_CONFIG3 0x0cc
621#define QPHY_V4_PCS_LOCK_DETECT_CONFIG4 0x0d0
622#define QPHY_V4_PCS_LOCK_DETECT_CONFIG5 0x0d4
623#define QPHY_V4_PCS_LOCK_DETECT_CONFIG6 0x0d8
624#define QPHY_V4_PCS_REFGEN_REQ_CONFIG1 0x0dc
625#define QPHY_V4_PCS_REFGEN_REQ_CONFIG2 0x0e0
626#define QPHY_V4_PCS_REFGEN_REQ_CONFIG3 0x0e4
627#define QPHY_V4_PCS_BIST_CTRL 0x0e8
628#define QPHY_V4_PCS_PRBS_POLY0 0x0ec
629#define QPHY_V4_PCS_PRBS_POLY1 0x0f0
630#define QPHY_V4_PCS_FIXED_PAT0 0x0f4
631#define QPHY_V4_PCS_FIXED_PAT1 0x0f8
632#define QPHY_V4_PCS_FIXED_PAT2 0x0fc
633#define QPHY_V4_PCS_FIXED_PAT3 0x100
634#define QPHY_V4_PCS_FIXED_PAT4 0x104
635#define QPHY_V4_PCS_FIXED_PAT5 0x108
636#define QPHY_V4_PCS_FIXED_PAT6 0x10c
637#define QPHY_V4_PCS_FIXED_PAT7 0x110
638#define QPHY_V4_PCS_FIXED_PAT8 0x114
639#define QPHY_V4_PCS_FIXED_PAT9 0x118
640#define QPHY_V4_PCS_FIXED_PAT10 0x11c
641#define QPHY_V4_PCS_FIXED_PAT11 0x120
642#define QPHY_V4_PCS_FIXED_PAT12 0x124
643#define QPHY_V4_PCS_FIXED_PAT13 0x128
644#define QPHY_V4_PCS_FIXED_PAT14 0x12c
645#define QPHY_V4_PCS_FIXED_PAT15 0x130
646#define QPHY_V4_PCS_TXMGN_CONFIG 0x134
647#define QPHY_V4_PCS_G12S1_TXMGN_V0 0x138
648#define QPHY_V4_PCS_G12S1_TXMGN_V1 0x13c
649#define QPHY_V4_PCS_G12S1_TXMGN_V2 0x140
650#define QPHY_V4_PCS_G12S1_TXMGN_V3 0x144
651#define QPHY_V4_PCS_G12S1_TXMGN_V4 0x148
652#define QPHY_V4_PCS_G12S1_TXMGN_V0_RS 0x14c
653#define QPHY_V4_PCS_G12S1_TXMGN_V1_RS 0x150
654#define QPHY_V4_PCS_G12S1_TXMGN_V2_RS 0x154
655#define QPHY_V4_PCS_G12S1_TXMGN_V3_RS 0x158
656#define QPHY_V4_PCS_G12S1_TXMGN_V4_RS 0x15c
657#define QPHY_V4_PCS_G3S2_TXMGN_MAIN 0x160
658#define QPHY_V4_PCS_G3S2_TXMGN_MAIN_RS 0x164
659#define QPHY_V4_PCS_G12S1_TXDEEMPH_M6DB 0x168
660#define QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB 0x16c
661#define QPHY_V4_PCS_G3S2_PRE_GAIN 0x170
662#define QPHY_V4_PCS_G3S2_POST_GAIN 0x174
663#define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET 0x178
664#define QPHY_V4_PCS_G3S2_PRE_GAIN_RS 0x17c
665#define QPHY_V4_PCS_G3S2_POST_GAIN_RS 0x180
666#define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET_RS 0x184
667#define QPHY_V4_PCS_RX_SIGDET_LVL 0x188
668#define QPHY_V4_PCS_RX_SIGDET_DTCT_CNTRL 0x18c
669#define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L 0x190
670#define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H 0x194
671#define QPHY_V4_PCS_RATE_SLEW_CNTRL1 0x198
672#define QPHY_V4_PCS_RATE_SLEW_CNTRL2 0x19c
673#define QPHY_V4_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1a0
674#define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4
675#define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8
676#define QPHY_V4_PCS_TSYNC_RSYNC_TIME 0x1ac
677#define QPHY_V4_PCS_CDR_RESET_TIME 0x1b0
678#define QPHY_V4_PCS_TSYNC_DLY_TIME 0x1b4
679#define QPHY_V4_PCS_ELECIDLE_DLY_SEL 0x1b8
680#define QPHY_V4_PCS_CMN_ACK_OUT_SEL 0x1bc
681#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG1 0x1c0
682#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG2 0x1c4
683#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG3 0x1c8
684#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG4 0x1cc
685#define QPHY_V4_PCS_PCS_TX_RX_CONFIG 0x1d0
686#define QPHY_V4_PCS_RX_IDLE_DTCT_CNTRL 0x1d4
687#define QPHY_V4_PCS_RX_DCC_CAL_CONFIG 0x1d8
688#define QPHY_V4_PCS_EQ_CONFIG1 0x1dc
689#define QPHY_V4_PCS_EQ_CONFIG2 0x1e0
690#define QPHY_V4_PCS_EQ_CONFIG3 0x1e4
691#define QPHY_V4_PCS_EQ_CONFIG4 0x1e8
692#define QPHY_V4_PCS_EQ_CONFIG5 0x1ec
693#define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1 0x300
694#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x304
695#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x308
696#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x30c
697#define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x310
698#define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x314
699#define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x318
700#define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART 0x31c
701#define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL 0x320
702#define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x324
703#define QPHY_V4_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x328
704#define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x32c
705#define QPHY_V4_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x330
706#define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x334
707#define QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x338
708#define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x33c
709#define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x340
710#define QPHY_V4_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x344
711#define QPHY_V4_PCS_USB3_ARCVR_DTCT_CM_DLY 0x348
712#define QPHY_V4_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x34c
713#define QPHY_V4_PCS_USB3_ALFPS_DEGLITCH_VAL 0x350
714#define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x354
715#define QPHY_V4_PCS_USB3_TEST_CONTROL 0x358
716
717/* Only for QMP V4 PHY - UNI has 0x300 offset for PCS_USB3 regs */
718#define QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL 0x618
719#define QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2 0x638
720
721/* Only for QMP V4 PHY - PCS_MISC registers */
722#define QPHY_V4_PCS_MISC_TYPEC_CTRL 0x00
723#define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL 0x04
724#define QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1 0x08
725#define QPHY_V4_PCS_MISC_CLAMP_ENABLE 0x0c
726#define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10
727#define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14
728
729#endif
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4 */
5
6#ifndef QCOM_PHY_QMP_H_
7#define QCOM_PHY_QMP_H_
8
9#include "phy-qcom-qmp-qserdes-com.h"
10#include "phy-qcom-qmp-qserdes-txrx.h"
11
12#include "phy-qcom-qmp-qserdes-com-v3.h"
13#include "phy-qcom-qmp-qserdes-txrx-v3.h"
14
15#include "phy-qcom-qmp-qserdes-com-v4.h"
16#include "phy-qcom-qmp-qserdes-txrx-v4.h"
17#include "phy-qcom-qmp-qserdes-txrx-v4_20.h"
18
19#include "phy-qcom-qmp-qserdes-com-v5.h"
20#include "phy-qcom-qmp-qserdes-txrx-v5.h"
21#include "phy-qcom-qmp-qserdes-txrx-v5_20.h"
22#include "phy-qcom-qmp-qserdes-txrx-v5_5nm.h"
23
24#include "phy-qcom-qmp-qserdes-com-v6.h"
25#include "phy-qcom-qmp-qserdes-txrx-v6.h"
26#include "phy-qcom-qmp-qserdes-txrx-v6_20.h"
27#include "phy-qcom-qmp-qserdes-txrx-v6_n4.h"
28#include "phy-qcom-qmp-qserdes-ln-shrd-v6.h"
29
30#include "phy-qcom-qmp-qserdes-com-v7.h"
31#include "phy-qcom-qmp-qserdes-txrx-v7.h"
32
33#include "phy-qcom-qmp-qserdes-pll.h"
34
35#include "phy-qcom-qmp-pcs-v2.h"
36
37#include "phy-qcom-qmp-pcs-v3.h"
38
39#include "phy-qcom-qmp-pcs-v4.h"
40
41#include "phy-qcom-qmp-pcs-v4_20.h"
42
43#include "phy-qcom-qmp-pcs-v5.h"
44
45#include "phy-qcom-qmp-pcs-v5_20.h"
46
47#include "phy-qcom-qmp-pcs-v6.h"
48
49#include "phy-qcom-qmp-pcs-v6_20.h"
50
51#include "phy-qcom-qmp-pcs-v7.h"
52
53/* QPHY_SW_RESET bit */
54#define SW_RESET BIT(0)
55/* QPHY_POWER_DOWN_CONTROL */
56#define SW_PWRDN BIT(0)
57#define REFCLK_DRV_DSBL BIT(1) /* PCIe */
58
59/* QPHY_START_CONTROL bits */
60#define SERDES_START BIT(0)
61#define PCS_START BIT(1)
62
63/* QPHY_PCS_STATUS bit */
64#define PHYSTATUS BIT(6)
65#define PHYSTATUS_4_20 BIT(7)
66
67/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
68#define ARCVR_DTCT_EN BIT(0)
69#define ALFPS_DTCT_EN BIT(1)
70#define ARCVR_DTCT_EVENT_SEL BIT(4)
71
72/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
73#define IRQ_CLEAR BIT(0)
74
75/* QPHY_PCS_MISC_CLAMP_ENABLE register bits */
76#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
77
78#endif