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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Cadence Torrent SD0801 PHY driver.
4 *
5 * Copyright 2018 Cadence Design Systems, Inc.
6 *
7 */
8
9#include <dt-bindings/phy/phy.h>
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/err.h>
13#include <linux/io.h>
14#include <linux/iopoll.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19#include <linux/of_device.h>
20#include <linux/phy/phy.h>
21#include <linux/platform_device.h>
22#include <linux/reset.h>
23#include <linux/regmap.h>
24
25#define REF_CLK_19_2MHz 19200000
26#define REF_CLK_25MHz 25000000
27
28#define DEFAULT_NUM_LANES 4
29#define MAX_NUM_LANES 4
30#define DEFAULT_MAX_BIT_RATE 8100 /* in Mbps */
31
32#define POLL_TIMEOUT_US 5000
33
34#define TORRENT_COMMON_CDB_OFFSET 0x0
35
36#define TORRENT_TX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
37 ((0x4000 << (block_offset)) + \
38 (((ln) << 9) << (reg_offset)))
39
40#define TORRENT_RX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
41 ((0x8000 << (block_offset)) + \
42 (((ln) << 9) << (reg_offset)))
43
44#define TORRENT_PHY_PCS_COMMON_OFFSET(block_offset) \
45 (0xC000 << (block_offset))
46
47#define TORRENT_PHY_PMA_COMMON_OFFSET(block_offset) \
48 (0xE000 << (block_offset))
49
50#define TORRENT_DPTX_PHY_OFFSET 0x0
51
52/*
53 * register offsets from DPTX PHY register block base (i.e MHDP
54 * register base + 0x30a00)
55 */
56#define PHY_AUX_CTRL 0x04
57#define PHY_RESET 0x20
58#define PMA_TX_ELEC_IDLE_MASK 0xF0U
59#define PMA_TX_ELEC_IDLE_SHIFT 4
60#define PHY_L00_RESET_N_MASK 0x01U
61#define PHY_PMA_XCVR_PLLCLK_EN 0x24
62#define PHY_PMA_XCVR_PLLCLK_EN_ACK 0x28
63#define PHY_PMA_XCVR_POWER_STATE_REQ 0x2c
64#define PHY_POWER_STATE_LN_0 0x0000
65#define PHY_POWER_STATE_LN_1 0x0008
66#define PHY_POWER_STATE_LN_2 0x0010
67#define PHY_POWER_STATE_LN_3 0x0018
68#define PMA_XCVR_POWER_STATE_REQ_LN_MASK 0x3FU
69#define PHY_PMA_XCVR_POWER_STATE_ACK 0x30
70#define PHY_PMA_CMN_READY 0x34
71
72/*
73 * register offsets from SD0801 PHY register block base (i.e MHDP
74 * register base + 0x500000)
75 */
76#define CMN_SSM_BANDGAP_TMR 0x0021U
77#define CMN_SSM_BIAS_TMR 0x0022U
78#define CMN_PLLSM0_PLLPRE_TMR 0x002AU
79#define CMN_PLLSM0_PLLLOCK_TMR 0x002CU
80#define CMN_PLLSM1_PLLPRE_TMR 0x0032U
81#define CMN_PLLSM1_PLLLOCK_TMR 0x0034U
82#define CMN_BGCAL_INIT_TMR 0x0064U
83#define CMN_BGCAL_ITER_TMR 0x0065U
84#define CMN_IBCAL_INIT_TMR 0x0074U
85#define CMN_PLL0_VCOCAL_TCTRL 0x0082U
86#define CMN_PLL0_VCOCAL_INIT_TMR 0x0084U
87#define CMN_PLL0_VCOCAL_ITER_TMR 0x0085U
88#define CMN_PLL0_VCOCAL_REFTIM_START 0x0086U
89#define CMN_PLL0_VCOCAL_PLLCNT_START 0x0088U
90#define CMN_PLL0_INTDIV_M0 0x0090U
91#define CMN_PLL0_FRACDIVL_M0 0x0091U
92#define CMN_PLL0_FRACDIVH_M0 0x0092U
93#define CMN_PLL0_HIGH_THR_M0 0x0093U
94#define CMN_PLL0_DSM_DIAG_M0 0x0094U
95#define CMN_PLL0_SS_CTRL1_M0 0x0098U
96#define CMN_PLL0_SS_CTRL2_M0 0x0099U
97#define CMN_PLL0_SS_CTRL3_M0 0x009AU
98#define CMN_PLL0_SS_CTRL4_M0 0x009BU
99#define CMN_PLL0_LOCK_REFCNT_START 0x009CU
100#define CMN_PLL0_LOCK_PLLCNT_START 0x009EU
101#define CMN_PLL0_LOCK_PLLCNT_THR 0x009FU
102#define CMN_PLL1_VCOCAL_TCTRL 0x00C2U
103#define CMN_PLL1_VCOCAL_INIT_TMR 0x00C4U
104#define CMN_PLL1_VCOCAL_ITER_TMR 0x00C5U
105#define CMN_PLL1_VCOCAL_REFTIM_START 0x00C6U
106#define CMN_PLL1_VCOCAL_PLLCNT_START 0x00C8U
107#define CMN_PLL1_INTDIV_M0 0x00D0U
108#define CMN_PLL1_FRACDIVL_M0 0x00D1U
109#define CMN_PLL1_FRACDIVH_M0 0x00D2U
110#define CMN_PLL1_HIGH_THR_M0 0x00D3U
111#define CMN_PLL1_DSM_DIAG_M0 0x00D4U
112#define CMN_PLL1_SS_CTRL1_M0 0x00D8U
113#define CMN_PLL1_SS_CTRL2_M0 0x00D9U
114#define CMN_PLL1_SS_CTRL3_M0 0x00DAU
115#define CMN_PLL1_SS_CTRL4_M0 0x00DBU
116#define CMN_PLL1_LOCK_REFCNT_START 0x00DCU
117#define CMN_PLL1_LOCK_PLLCNT_START 0x00DEU
118#define CMN_PLL1_LOCK_PLLCNT_THR 0x00DFU
119#define CMN_TXPUCAL_INIT_TMR 0x0104U
120#define CMN_TXPUCAL_ITER_TMR 0x0105U
121#define CMN_TXPDCAL_INIT_TMR 0x010CU
122#define CMN_TXPDCAL_ITER_TMR 0x010DU
123#define CMN_RXCAL_INIT_TMR 0x0114U
124#define CMN_RXCAL_ITER_TMR 0x0115U
125#define CMN_SD_CAL_INIT_TMR 0x0124U
126#define CMN_SD_CAL_ITER_TMR 0x0125U
127#define CMN_SD_CAL_REFTIM_START 0x0126U
128#define CMN_SD_CAL_PLLCNT_START 0x0128U
129#define CMN_PDIAG_PLL0_CTRL_M0 0x01A0U
130#define CMN_PDIAG_PLL0_CLK_SEL_M0 0x01A1U
131#define CMN_PDIAG_PLL0_CP_PADJ_M0 0x01A4U
132#define CMN_PDIAG_PLL0_CP_IADJ_M0 0x01A5U
133#define CMN_PDIAG_PLL0_FILT_PADJ_M0 0x01A6U
134#define CMN_PDIAG_PLL0_CP_PADJ_M1 0x01B4U
135#define CMN_PDIAG_PLL0_CP_IADJ_M1 0x01B5U
136#define CMN_PDIAG_PLL1_CTRL_M0 0x01C0U
137#define CMN_PDIAG_PLL1_CLK_SEL_M0 0x01C1U
138#define CMN_PDIAG_PLL1_CP_PADJ_M0 0x01C4U
139#define CMN_PDIAG_PLL1_CP_IADJ_M0 0x01C5U
140#define CMN_PDIAG_PLL1_FILT_PADJ_M0 0x01C6U
141
142/* PMA TX Lane registers */
143#define TX_TXCC_CTRL 0x0040U
144#define TX_TXCC_CPOST_MULT_00 0x004CU
145#define TX_TXCC_MGNFS_MULT_000 0x0050U
146#define DRV_DIAG_TX_DRV 0x00C6U
147#define XCVR_DIAG_PLLDRC_CTRL 0x00E5U
148#define XCVR_DIAG_HSCLK_SEL 0x00E6U
149#define XCVR_DIAG_HSCLK_DIV 0x00E7U
150#define XCVR_DIAG_BIDI_CTRL 0x00EAU
151#define TX_PSC_A0 0x0100U
152#define TX_PSC_A2 0x0102U
153#define TX_PSC_A3 0x0103U
154#define TX_RCVDET_ST_TMR 0x0123U
155#define TX_DIAG_ACYA 0x01E7U
156#define TX_DIAG_ACYA_HBDC_MASK 0x0001U
157
158/* PMA RX Lane registers */
159#define RX_PSC_A0 0x0000U
160#define RX_PSC_A2 0x0002U
161#define RX_PSC_A3 0x0003U
162#define RX_PSC_CAL 0x0006U
163#define RX_REE_GCSM1_CTRL 0x0108U
164#define RX_REE_GCSM2_CTRL 0x0110U
165#define RX_REE_PERGCSM_CTRL 0x0118U
166
167/* PHY PCS common registers */
168#define PHY_PLL_CFG 0x000EU
169
170/* PHY PMA common registers */
171#define PHY_PMA_CMN_CTRL2 0x0001U
172#define PHY_PMA_PLL_RAW_CTRL 0x0003U
173
174static const struct reg_field phy_pll_cfg =
175 REG_FIELD(PHY_PLL_CFG, 0, 1);
176
177static const struct reg_field phy_pma_cmn_ctrl_2 =
178 REG_FIELD(PHY_PMA_CMN_CTRL2, 0, 7);
179
180static const struct reg_field phy_pma_pll_raw_ctrl =
181 REG_FIELD(PHY_PMA_PLL_RAW_CTRL, 0, 1);
182
183static const struct reg_field phy_reset_ctrl =
184 REG_FIELD(PHY_RESET, 8, 8);
185
186static const struct of_device_id cdns_torrent_phy_of_match[];
187
188struct cdns_torrent_inst {
189 struct phy *phy;
190 u32 mlane;
191 u32 phy_type;
192 u32 num_lanes;
193 struct reset_control *lnk_rst;
194};
195
196struct cdns_torrent_phy {
197 void __iomem *base; /* DPTX registers base */
198 void __iomem *sd_base; /* SD0801 registers base */
199 u32 max_bit_rate; /* Maximum link bit rate to use (in Mbps) */
200 struct reset_control *phy_rst;
201 struct device *dev;
202 struct clk *clk;
203 unsigned long ref_clk_rate;
204 struct cdns_torrent_inst phys[MAX_NUM_LANES];
205 int nsubnodes;
206 struct regmap *regmap;
207 struct regmap *regmap_common_cdb;
208 struct regmap *regmap_phy_pcs_common_cdb;
209 struct regmap *regmap_phy_pma_common_cdb;
210 struct regmap *regmap_tx_lane_cdb[MAX_NUM_LANES];
211 struct regmap *regmap_rx_lane_cdb[MAX_NUM_LANES];
212 struct regmap *regmap_dptx_phy_reg;
213 struct regmap_field *phy_pll_cfg;
214 struct regmap_field *phy_pma_cmn_ctrl_2;
215 struct regmap_field *phy_pma_pll_raw_ctrl;
216 struct regmap_field *phy_reset_ctrl;
217};
218
219enum phy_powerstate {
220 POWERSTATE_A0 = 0,
221 /* Powerstate A1 is unused */
222 POWERSTATE_A2 = 2,
223 POWERSTATE_A3 = 3,
224};
225
226static int cdns_torrent_dp_init(struct phy *phy);
227static int cdns_torrent_dp_exit(struct phy *phy);
228static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy,
229 u32 num_lanes);
230static
231int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy);
232static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy,
233 struct cdns_torrent_inst *inst);
234static
235void cdns_torrent_dp_pma_cmn_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy);
236static
237void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy,
238 u32 rate, bool ssc);
239static
240void cdns_torrent_dp_pma_cmn_cfg_25mhz(struct cdns_torrent_phy *cdns_phy);
241static
242void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy,
243 u32 rate, bool ssc);
244static void cdns_torrent_dp_pma_lane_cfg(struct cdns_torrent_phy *cdns_phy,
245 unsigned int lane);
246static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy,
247 u32 rate, u32 num_lanes);
248static int cdns_torrent_dp_configure(struct phy *phy,
249 union phy_configure_opts *opts);
250static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy,
251 u32 num_lanes,
252 enum phy_powerstate powerstate);
253static int cdns_torrent_phy_on(struct phy *phy);
254static int cdns_torrent_phy_off(struct phy *phy);
255
256static const struct phy_ops cdns_torrent_phy_ops = {
257 .init = cdns_torrent_dp_init,
258 .exit = cdns_torrent_dp_exit,
259 .configure = cdns_torrent_dp_configure,
260 .power_on = cdns_torrent_phy_on,
261 .power_off = cdns_torrent_phy_off,
262 .owner = THIS_MODULE,
263};
264
265struct cdns_torrent_data {
266 u8 block_offset_shift;
267 u8 reg_offset_shift;
268};
269
270struct cdns_regmap_cdb_context {
271 struct device *dev;
272 void __iomem *base;
273 u8 reg_offset_shift;
274};
275
276static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val)
277{
278 struct cdns_regmap_cdb_context *ctx = context;
279 u32 offset = reg << ctx->reg_offset_shift;
280
281 writew(val, ctx->base + offset);
282
283 return 0;
284}
285
286static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val)
287{
288 struct cdns_regmap_cdb_context *ctx = context;
289 u32 offset = reg << ctx->reg_offset_shift;
290
291 *val = readw(ctx->base + offset);
292 return 0;
293}
294
295static int cdns_regmap_dptx_write(void *context, unsigned int reg,
296 unsigned int val)
297{
298 struct cdns_regmap_cdb_context *ctx = context;
299 u32 offset = reg;
300
301 writel(val, ctx->base + offset);
302
303 return 0;
304}
305
306static int cdns_regmap_dptx_read(void *context, unsigned int reg,
307 unsigned int *val)
308{
309 struct cdns_regmap_cdb_context *ctx = context;
310 u32 offset = reg;
311
312 *val = readl(ctx->base + offset);
313 return 0;
314}
315
316#define TORRENT_TX_LANE_CDB_REGMAP_CONF(n) \
317{ \
318 .name = "torrent_tx_lane" n "_cdb", \
319 .reg_stride = 1, \
320 .fast_io = true, \
321 .reg_write = cdns_regmap_write, \
322 .reg_read = cdns_regmap_read, \
323}
324
325#define TORRENT_RX_LANE_CDB_REGMAP_CONF(n) \
326{ \
327 .name = "torrent_rx_lane" n "_cdb", \
328 .reg_stride = 1, \
329 .fast_io = true, \
330 .reg_write = cdns_regmap_write, \
331 .reg_read = cdns_regmap_read, \
332}
333
334static struct regmap_config cdns_torrent_tx_lane_cdb_config[] = {
335 TORRENT_TX_LANE_CDB_REGMAP_CONF("0"),
336 TORRENT_TX_LANE_CDB_REGMAP_CONF("1"),
337 TORRENT_TX_LANE_CDB_REGMAP_CONF("2"),
338 TORRENT_TX_LANE_CDB_REGMAP_CONF("3"),
339};
340
341static struct regmap_config cdns_torrent_rx_lane_cdb_config[] = {
342 TORRENT_RX_LANE_CDB_REGMAP_CONF("0"),
343 TORRENT_RX_LANE_CDB_REGMAP_CONF("1"),
344 TORRENT_RX_LANE_CDB_REGMAP_CONF("2"),
345 TORRENT_RX_LANE_CDB_REGMAP_CONF("3"),
346};
347
348static struct regmap_config cdns_torrent_common_cdb_config = {
349 .name = "torrent_common_cdb",
350 .reg_stride = 1,
351 .fast_io = true,
352 .reg_write = cdns_regmap_write,
353 .reg_read = cdns_regmap_read,
354};
355
356static struct regmap_config cdns_torrent_phy_pcs_cmn_cdb_config = {
357 .name = "torrent_phy_pcs_cmn_cdb",
358 .reg_stride = 1,
359 .fast_io = true,
360 .reg_write = cdns_regmap_write,
361 .reg_read = cdns_regmap_read,
362};
363
364static struct regmap_config cdns_torrent_phy_pma_cmn_cdb_config = {
365 .name = "torrent_phy_pma_cmn_cdb",
366 .reg_stride = 1,
367 .fast_io = true,
368 .reg_write = cdns_regmap_write,
369 .reg_read = cdns_regmap_read,
370};
371
372static struct regmap_config cdns_torrent_dptx_phy_config = {
373 .name = "torrent_dptx_phy",
374 .reg_stride = 1,
375 .fast_io = true,
376 .reg_write = cdns_regmap_dptx_write,
377 .reg_read = cdns_regmap_dptx_read,
378};
379
380/* PHY mmr access functions */
381
382static void cdns_torrent_phy_write(struct regmap *regmap, u32 offset, u32 val)
383{
384 regmap_write(regmap, offset, val);
385}
386
387static u32 cdns_torrent_phy_read(struct regmap *regmap, u32 offset)
388{
389 unsigned int val;
390
391 regmap_read(regmap, offset, &val);
392 return val;
393}
394
395/* DPTX mmr access functions */
396
397static void cdns_torrent_dp_write(struct regmap *regmap, u32 offset, u32 val)
398{
399 regmap_write(regmap, offset, val);
400}
401
402static u32 cdns_torrent_dp_read(struct regmap *regmap, u32 offset)
403{
404 u32 val;
405
406 regmap_read(regmap, offset, &val);
407 return val;
408}
409
410/*
411 * Structure used to store values of PHY registers for voltage-related
412 * coefficients, for particular voltage swing and pre-emphasis level. Values
413 * are shared across all physical lanes.
414 */
415struct coefficients {
416 /* Value of DRV_DIAG_TX_DRV register to use */
417 u16 diag_tx_drv;
418 /* Value of TX_TXCC_MGNFS_MULT_000 register to use */
419 u16 mgnfs_mult;
420 /* Value of TX_TXCC_CPOST_MULT_00 register to use */
421 u16 cpost_mult;
422};
423
424/*
425 * Array consists of values of voltage-related registers for sd0801 PHY. A value
426 * of 0xFFFF is a placeholder for invalid combination, and will never be used.
427 */
428static const struct coefficients vltg_coeff[4][4] = {
429 /* voltage swing 0, pre-emphasis 0->3 */
430 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x002A,
431 .cpost_mult = 0x0000},
432 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F,
433 .cpost_mult = 0x0014},
434 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0012,
435 .cpost_mult = 0x0020},
436 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
437 .cpost_mult = 0x002A}
438 },
439
440 /* voltage swing 1, pre-emphasis 0->3 */
441 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F,
442 .cpost_mult = 0x0000},
443 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0013,
444 .cpost_mult = 0x0012},
445 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
446 .cpost_mult = 0x001F},
447 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
448 .cpost_mult = 0xFFFF}
449 },
450
451 /* voltage swing 2, pre-emphasis 0->3 */
452 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0013,
453 .cpost_mult = 0x0000},
454 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
455 .cpost_mult = 0x0013},
456 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
457 .cpost_mult = 0xFFFF},
458 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
459 .cpost_mult = 0xFFFF}
460 },
461
462 /* voltage swing 3, pre-emphasis 0->3 */
463 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
464 .cpost_mult = 0x0000},
465 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
466 .cpost_mult = 0xFFFF},
467 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
468 .cpost_mult = 0xFFFF},
469 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
470 .cpost_mult = 0xFFFF}
471 }
472};
473
474/*
475 * Enable or disable PLL for selected lanes.
476 */
477static int cdns_torrent_dp_set_pll_en(struct cdns_torrent_phy *cdns_phy,
478 struct phy_configure_opts_dp *dp,
479 bool enable)
480{
481 u32 rd_val;
482 u32 ret;
483 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
484
485 /*
486 * Used to determine, which bits to check for or enable in
487 * PHY_PMA_XCVR_PLLCLK_EN register.
488 */
489 u32 pll_bits;
490 /* Used to enable or disable lanes. */
491 u32 pll_val;
492
493 /* Select values of registers and mask, depending on enabled lane
494 * count.
495 */
496 switch (dp->lanes) {
497 /* lane 0 */
498 case (1):
499 pll_bits = 0x00000001;
500 break;
501 /* lanes 0-1 */
502 case (2):
503 pll_bits = 0x00000003;
504 break;
505 /* lanes 0-3, all */
506 default:
507 pll_bits = 0x0000000F;
508 break;
509 }
510
511 if (enable)
512 pll_val = pll_bits;
513 else
514 pll_val = 0x00000000;
515
516 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_val);
517
518 /* Wait for acknowledgment from PHY. */
519 ret = regmap_read_poll_timeout(regmap,
520 PHY_PMA_XCVR_PLLCLK_EN_ACK,
521 rd_val,
522 (rd_val & pll_bits) == pll_val,
523 0, POLL_TIMEOUT_US);
524 ndelay(100);
525 return ret;
526}
527
528/*
529 * Perform register operations related to setting link rate, once powerstate is
530 * set and PLL disable request was processed.
531 */
532static int cdns_torrent_dp_configure_rate(struct cdns_torrent_phy *cdns_phy,
533 struct phy_configure_opts_dp *dp)
534{
535 u32 ret;
536 u32 read_val;
537
538 /* Disable the cmn_pll0_en before re-programming the new data rate. */
539 regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, 0x0);
540
541 /*
542 * Wait for PLL ready de-assertion.
543 * For PLL0 - PHY_PMA_CMN_CTRL2[2] == 1
544 */
545 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
546 read_val,
547 ((read_val >> 2) & 0x01) != 0,
548 0, POLL_TIMEOUT_US);
549 if (ret)
550 return ret;
551 ndelay(200);
552
553 /* DP Rate Change - VCO Output settings. */
554 if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz) {
555 /* PMA common configuration 19.2MHz */
556 cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, dp->link_rate,
557 dp->ssc);
558 cdns_torrent_dp_pma_cmn_cfg_19_2mhz(cdns_phy);
559 } else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz) {
560 /* PMA common configuration 25MHz */
561 cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, dp->link_rate,
562 dp->ssc);
563 cdns_torrent_dp_pma_cmn_cfg_25mhz(cdns_phy);
564 }
565 cdns_torrent_dp_pma_cmn_rate(cdns_phy, dp->link_rate, dp->lanes);
566
567 /* Enable the cmn_pll0_en. */
568 regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, 0x3);
569
570 /*
571 * Wait for PLL ready assertion.
572 * For PLL0 - PHY_PMA_CMN_CTRL2[0] == 1
573 */
574 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
575 read_val,
576 (read_val & 0x01) != 0,
577 0, POLL_TIMEOUT_US);
578 return ret;
579}
580
581/*
582 * Verify, that parameters to configure PHY with are correct.
583 */
584static int cdns_torrent_dp_verify_config(struct cdns_torrent_inst *inst,
585 struct phy_configure_opts_dp *dp)
586{
587 u8 i;
588
589 /* If changing link rate was required, verify it's supported. */
590 if (dp->set_rate) {
591 switch (dp->link_rate) {
592 case 1620:
593 case 2160:
594 case 2430:
595 case 2700:
596 case 3240:
597 case 4320:
598 case 5400:
599 case 8100:
600 /* valid bit rate */
601 break;
602 default:
603 return -EINVAL;
604 }
605 }
606
607 /* Verify lane count. */
608 switch (dp->lanes) {
609 case 1:
610 case 2:
611 case 4:
612 /* valid lane count. */
613 break;
614 default:
615 return -EINVAL;
616 }
617
618 /* Check against actual number of PHY's lanes. */
619 if (dp->lanes > inst->num_lanes)
620 return -EINVAL;
621
622 /*
623 * If changing voltages is required, check swing and pre-emphasis
624 * levels, per-lane.
625 */
626 if (dp->set_voltages) {
627 /* Lane count verified previously. */
628 for (i = 0; i < dp->lanes; i++) {
629 if (dp->voltage[i] > 3 || dp->pre[i] > 3)
630 return -EINVAL;
631
632 /* Sum of voltage swing and pre-emphasis levels cannot
633 * exceed 3.
634 */
635 if (dp->voltage[i] + dp->pre[i] > 3)
636 return -EINVAL;
637 }
638 }
639
640 return 0;
641}
642
643/* Set power state A0 and PLL clock enable to 0 on enabled lanes. */
644static void cdns_torrent_dp_set_a0_pll(struct cdns_torrent_phy *cdns_phy,
645 u32 num_lanes)
646{
647 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
648 u32 pwr_state = cdns_torrent_dp_read(regmap,
649 PHY_PMA_XCVR_POWER_STATE_REQ);
650 u32 pll_clk_en = cdns_torrent_dp_read(regmap,
651 PHY_PMA_XCVR_PLLCLK_EN);
652
653 /* Lane 0 is always enabled. */
654 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
655 PHY_POWER_STATE_LN_0);
656 pll_clk_en &= ~0x01U;
657
658 if (num_lanes > 1) {
659 /* lane 1 */
660 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
661 PHY_POWER_STATE_LN_1);
662 pll_clk_en &= ~(0x01U << 1);
663 }
664
665 if (num_lanes > 2) {
666 /* lanes 2 and 3 */
667 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
668 PHY_POWER_STATE_LN_2);
669 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
670 PHY_POWER_STATE_LN_3);
671 pll_clk_en &= ~(0x01U << 2);
672 pll_clk_en &= ~(0x01U << 3);
673 }
674
675 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, pwr_state);
676 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_clk_en);
677}
678
679/* Configure lane count as required. */
680static int cdns_torrent_dp_set_lanes(struct cdns_torrent_phy *cdns_phy,
681 struct phy_configure_opts_dp *dp)
682{
683 u32 value;
684 u32 ret;
685 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
686 u8 lane_mask = (1 << dp->lanes) - 1;
687
688 value = cdns_torrent_dp_read(regmap, PHY_RESET);
689 /* clear pma_tx_elec_idle_ln_* bits. */
690 value &= ~PMA_TX_ELEC_IDLE_MASK;
691 /* Assert pma_tx_elec_idle_ln_* for disabled lanes. */
692 value |= ((~lane_mask) << PMA_TX_ELEC_IDLE_SHIFT) &
693 PMA_TX_ELEC_IDLE_MASK;
694 cdns_torrent_dp_write(regmap, PHY_RESET, value);
695
696 /* reset the link by asserting phy_l00_reset_n low */
697 cdns_torrent_dp_write(regmap, PHY_RESET,
698 value & (~PHY_L00_RESET_N_MASK));
699
700 /*
701 * Assert lane reset on unused lanes and lane 0 so they remain in reset
702 * and powered down when re-enabling the link
703 */
704 value = (value & 0x0000FFF0) | (0x0000000E & lane_mask);
705 cdns_torrent_dp_write(regmap, PHY_RESET, value);
706
707 cdns_torrent_dp_set_a0_pll(cdns_phy, dp->lanes);
708
709 /* release phy_l0*_reset_n based on used laneCount */
710 value = (value & 0x0000FFF0) | (0x0000000F & lane_mask);
711 cdns_torrent_dp_write(regmap, PHY_RESET, value);
712
713 /* Wait, until PHY gets ready after releasing PHY reset signal. */
714 ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy);
715 if (ret)
716 return ret;
717
718 ndelay(100);
719
720 /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
721 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, 0x0001);
722
723 ret = cdns_torrent_dp_run(cdns_phy, dp->lanes);
724
725 return ret;
726}
727
728/* Configure link rate as required. */
729static int cdns_torrent_dp_set_rate(struct cdns_torrent_phy *cdns_phy,
730 struct phy_configure_opts_dp *dp)
731{
732 u32 ret;
733
734 ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes,
735 POWERSTATE_A3);
736 if (ret)
737 return ret;
738 ret = cdns_torrent_dp_set_pll_en(cdns_phy, dp, false);
739 if (ret)
740 return ret;
741 ndelay(200);
742
743 ret = cdns_torrent_dp_configure_rate(cdns_phy, dp);
744 if (ret)
745 return ret;
746 ndelay(200);
747
748 ret = cdns_torrent_dp_set_pll_en(cdns_phy, dp, true);
749 if (ret)
750 return ret;
751 ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes,
752 POWERSTATE_A2);
753 if (ret)
754 return ret;
755 ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes,
756 POWERSTATE_A0);
757 if (ret)
758 return ret;
759 ndelay(900);
760
761 return ret;
762}
763
764/* Configure voltage swing and pre-emphasis for all enabled lanes. */
765static void cdns_torrent_dp_set_voltages(struct cdns_torrent_phy *cdns_phy,
766 struct phy_configure_opts_dp *dp)
767{
768 u8 lane;
769 u16 val;
770
771 for (lane = 0; lane < dp->lanes; lane++) {
772 val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[lane],
773 TX_DIAG_ACYA);
774 /*
775 * Write 1 to register bit TX_DIAG_ACYA[0] to freeze the
776 * current state of the analog TX driver.
777 */
778 val |= TX_DIAG_ACYA_HBDC_MASK;
779 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
780 TX_DIAG_ACYA, val);
781
782 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
783 TX_TXCC_CTRL, 0x08A4);
784 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].diag_tx_drv;
785 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
786 DRV_DIAG_TX_DRV, val);
787 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].mgnfs_mult;
788 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
789 TX_TXCC_MGNFS_MULT_000,
790 val);
791 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].cpost_mult;
792 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
793 TX_TXCC_CPOST_MULT_00,
794 val);
795
796 val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[lane],
797 TX_DIAG_ACYA);
798 /*
799 * Write 0 to register bit TX_DIAG_ACYA[0] to allow the state of
800 * analog TX driver to reflect the new programmed one.
801 */
802 val &= ~TX_DIAG_ACYA_HBDC_MASK;
803 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
804 TX_DIAG_ACYA, val);
805 }
806};
807
808static int cdns_torrent_dp_configure(struct phy *phy,
809 union phy_configure_opts *opts)
810{
811 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
812 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
813 int ret;
814
815 ret = cdns_torrent_dp_verify_config(inst, &opts->dp);
816 if (ret) {
817 dev_err(&phy->dev, "invalid params for phy configure\n");
818 return ret;
819 }
820
821 if (opts->dp.set_lanes) {
822 ret = cdns_torrent_dp_set_lanes(cdns_phy, &opts->dp);
823 if (ret) {
824 dev_err(&phy->dev, "cdns_torrent_dp_set_lanes failed\n");
825 return ret;
826 }
827 }
828
829 if (opts->dp.set_rate) {
830 ret = cdns_torrent_dp_set_rate(cdns_phy, &opts->dp);
831 if (ret) {
832 dev_err(&phy->dev, "cdns_torrent_dp_set_rate failed\n");
833 return ret;
834 }
835 }
836
837 if (opts->dp.set_voltages)
838 cdns_torrent_dp_set_voltages(cdns_phy, &opts->dp);
839
840 return ret;
841}
842
843static int cdns_torrent_dp_init(struct phy *phy)
844{
845 unsigned char lane_bits;
846 int ret;
847 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
848 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
849 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
850
851 ret = clk_prepare_enable(cdns_phy->clk);
852 if (ret) {
853 dev_err(cdns_phy->dev, "Failed to prepare ref clock\n");
854 return ret;
855 }
856
857 cdns_phy->ref_clk_rate = clk_get_rate(cdns_phy->clk);
858 if (!(cdns_phy->ref_clk_rate)) {
859 dev_err(cdns_phy->dev, "Failed to get ref clock rate\n");
860 clk_disable_unprepare(cdns_phy->clk);
861 return -EINVAL;
862 }
863
864 switch (cdns_phy->ref_clk_rate) {
865 case REF_CLK_19_2MHz:
866 case REF_CLK_25MHz:
867 /* Valid Ref Clock Rate */
868 break;
869 default:
870 dev_err(cdns_phy->dev, "Unsupported Ref Clock Rate\n");
871 return -EINVAL;
872 }
873
874 cdns_torrent_dp_write(regmap, PHY_AUX_CTRL, 0x0003); /* enable AUX */
875
876 /* PHY PMA registers configuration function */
877 cdns_torrent_dp_pma_cfg(cdns_phy, inst);
878
879 /*
880 * Set lines power state to A0
881 * Set lines pll clk enable to 0
882 */
883 cdns_torrent_dp_set_a0_pll(cdns_phy, inst->num_lanes);
884
885 /*
886 * release phy_l0*_reset_n and pma_tx_elec_idle_ln_* based on
887 * used lanes
888 */
889 lane_bits = (1 << inst->num_lanes) - 1;
890 cdns_torrent_dp_write(regmap, PHY_RESET,
891 ((0xF & ~lane_bits) << 4) | (0xF & lane_bits));
892
893 /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
894 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, 0x0001);
895
896 /* PHY PMA registers configuration functions */
897 /* Initialize PHY with max supported link rate, without SSC. */
898 if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz)
899 cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy,
900 cdns_phy->max_bit_rate,
901 false);
902 else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz)
903 cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy,
904 cdns_phy->max_bit_rate,
905 false);
906 cdns_torrent_dp_pma_cmn_rate(cdns_phy, cdns_phy->max_bit_rate,
907 inst->num_lanes);
908
909 /* take out of reset */
910 regmap_field_write(cdns_phy->phy_reset_ctrl, 0x1);
911
912 cdns_torrent_phy_on(phy);
913
914 ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy);
915 if (ret)
916 return ret;
917
918 ret = cdns_torrent_dp_run(cdns_phy, inst->num_lanes);
919
920 return ret;
921}
922
923static int cdns_torrent_dp_exit(struct phy *phy)
924{
925 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
926
927 clk_disable_unprepare(cdns_phy->clk);
928 return 0;
929}
930
931static
932int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy)
933{
934 unsigned int reg;
935 int ret;
936 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
937
938 ret = regmap_read_poll_timeout(regmap, PHY_PMA_CMN_READY, reg,
939 reg & 1, 0, POLL_TIMEOUT_US);
940 if (ret == -ETIMEDOUT) {
941 dev_err(cdns_phy->dev,
942 "timeout waiting for PMA common ready\n");
943 return -ETIMEDOUT;
944 }
945
946 return 0;
947}
948
949static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy,
950 struct cdns_torrent_inst *inst)
951{
952 unsigned int i;
953
954 if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz)
955 /* PMA common configuration 19.2MHz */
956 cdns_torrent_dp_pma_cmn_cfg_19_2mhz(cdns_phy);
957 else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz)
958 /* PMA common configuration 25MHz */
959 cdns_torrent_dp_pma_cmn_cfg_25mhz(cdns_phy);
960
961 /* PMA lane configuration to deal with multi-link operation */
962 for (i = 0; i < inst->num_lanes; i++)
963 cdns_torrent_dp_pma_lane_cfg(cdns_phy, i);
964}
965
966static
967void cdns_torrent_dp_pma_cmn_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy)
968{
969 struct regmap *regmap = cdns_phy->regmap_common_cdb;
970
971 /* refclock registers - assumes 19.2 MHz refclock */
972 cdns_torrent_phy_write(regmap, CMN_SSM_BIAS_TMR, 0x0014);
973 cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLPRE_TMR, 0x0027);
974 cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLLOCK_TMR, 0x00A1);
975 cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLPRE_TMR, 0x0027);
976 cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLLOCK_TMR, 0x00A1);
977 cdns_torrent_phy_write(regmap, CMN_BGCAL_INIT_TMR, 0x0060);
978 cdns_torrent_phy_write(regmap, CMN_BGCAL_ITER_TMR, 0x0060);
979 cdns_torrent_phy_write(regmap, CMN_IBCAL_INIT_TMR, 0x0014);
980 cdns_torrent_phy_write(regmap, CMN_TXPUCAL_INIT_TMR, 0x0018);
981 cdns_torrent_phy_write(regmap, CMN_TXPUCAL_ITER_TMR, 0x0005);
982 cdns_torrent_phy_write(regmap, CMN_TXPDCAL_INIT_TMR, 0x0018);
983 cdns_torrent_phy_write(regmap, CMN_TXPDCAL_ITER_TMR, 0x0005);
984 cdns_torrent_phy_write(regmap, CMN_RXCAL_INIT_TMR, 0x0240);
985 cdns_torrent_phy_write(regmap, CMN_RXCAL_ITER_TMR, 0x0005);
986 cdns_torrent_phy_write(regmap, CMN_SD_CAL_INIT_TMR, 0x0002);
987 cdns_torrent_phy_write(regmap, CMN_SD_CAL_ITER_TMR, 0x0002);
988 cdns_torrent_phy_write(regmap, CMN_SD_CAL_REFTIM_START, 0x000B);
989 cdns_torrent_phy_write(regmap, CMN_SD_CAL_PLLCNT_START, 0x0137);
990
991 /* PLL registers */
992 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
993 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
994 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
995 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
996 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
997 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
998 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
999 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
1000 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_INIT_TMR, 0x00C0);
1001 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_ITER_TMR, 0x0004);
1002 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_INIT_TMR, 0x00C0);
1003 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_ITER_TMR, 0x0004);
1004 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_REFTIM_START, 0x0260);
1005 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_TCTRL, 0x0003);
1006 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_REFTIM_START, 0x0260);
1007 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_TCTRL, 0x0003);
1008}
1009
1010/*
1011 * Set registers responsible for enabling and configuring SSC, with second and
1012 * third register values provided by parameters.
1013 */
1014static
1015void cdns_torrent_dp_enable_ssc_19_2mhz(struct cdns_torrent_phy *cdns_phy,
1016 u32 ctrl2_val, u32 ctrl3_val)
1017{
1018 struct regmap *regmap = cdns_phy->regmap_common_cdb;
1019
1020 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001);
1021 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val);
1022 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl3_val);
1023 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003);
1024 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001);
1025 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val);
1026 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl3_val);
1027 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003);
1028}
1029
1030static
1031void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy,
1032 u32 rate, bool ssc)
1033{
1034 struct regmap *regmap = cdns_phy->regmap_common_cdb;
1035
1036 /* Assumes 19.2 MHz refclock */
1037 switch (rate) {
1038 /* Setting VCO for 10.8GHz */
1039 case 2700:
1040 case 5400:
1041 cdns_torrent_phy_write(regmap,
1042 CMN_PLL0_INTDIV_M0, 0x0119);
1043 cdns_torrent_phy_write(regmap,
1044 CMN_PLL0_FRACDIVL_M0, 0x4000);
1045 cdns_torrent_phy_write(regmap,
1046 CMN_PLL0_FRACDIVH_M0, 0x0002);
1047 cdns_torrent_phy_write(regmap,
1048 CMN_PLL0_HIGH_THR_M0, 0x00BC);
1049 cdns_torrent_phy_write(regmap,
1050 CMN_PDIAG_PLL0_CTRL_M0, 0x0012);
1051 cdns_torrent_phy_write(regmap,
1052 CMN_PLL1_INTDIV_M0, 0x0119);
1053 cdns_torrent_phy_write(regmap,
1054 CMN_PLL1_FRACDIVL_M0, 0x4000);
1055 cdns_torrent_phy_write(regmap,
1056 CMN_PLL1_FRACDIVH_M0, 0x0002);
1057 cdns_torrent_phy_write(regmap,
1058 CMN_PLL1_HIGH_THR_M0, 0x00BC);
1059 cdns_torrent_phy_write(regmap,
1060 CMN_PDIAG_PLL1_CTRL_M0, 0x0012);
1061 if (ssc)
1062 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x033A,
1063 0x006A);
1064 break;
1065 /* Setting VCO for 9.72GHz */
1066 case 1620:
1067 case 2430:
1068 case 3240:
1069 cdns_torrent_phy_write(regmap,
1070 CMN_PLL0_INTDIV_M0, 0x01FA);
1071 cdns_torrent_phy_write(regmap,
1072 CMN_PLL0_FRACDIVL_M0, 0x4000);
1073 cdns_torrent_phy_write(regmap,
1074 CMN_PLL0_FRACDIVH_M0, 0x0002);
1075 cdns_torrent_phy_write(regmap,
1076 CMN_PLL0_HIGH_THR_M0, 0x0152);
1077 cdns_torrent_phy_write(regmap,
1078 CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
1079 cdns_torrent_phy_write(regmap,
1080 CMN_PLL1_INTDIV_M0, 0x01FA);
1081 cdns_torrent_phy_write(regmap,
1082 CMN_PLL1_FRACDIVL_M0, 0x4000);
1083 cdns_torrent_phy_write(regmap,
1084 CMN_PLL1_FRACDIVH_M0, 0x0002);
1085 cdns_torrent_phy_write(regmap,
1086 CMN_PLL1_HIGH_THR_M0, 0x0152);
1087 cdns_torrent_phy_write(regmap,
1088 CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
1089 if (ssc)
1090 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x05DD,
1091 0x0069);
1092 break;
1093 /* Setting VCO for 8.64GHz */
1094 case 2160:
1095 case 4320:
1096 cdns_torrent_phy_write(regmap,
1097 CMN_PLL0_INTDIV_M0, 0x01C2);
1098 cdns_torrent_phy_write(regmap,
1099 CMN_PLL0_FRACDIVL_M0, 0x0000);
1100 cdns_torrent_phy_write(regmap,
1101 CMN_PLL0_FRACDIVH_M0, 0x0002);
1102 cdns_torrent_phy_write(regmap,
1103 CMN_PLL0_HIGH_THR_M0, 0x012C);
1104 cdns_torrent_phy_write(regmap,
1105 CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
1106 cdns_torrent_phy_write(regmap,
1107 CMN_PLL1_INTDIV_M0, 0x01C2);
1108 cdns_torrent_phy_write(regmap,
1109 CMN_PLL1_FRACDIVL_M0, 0x0000);
1110 cdns_torrent_phy_write(regmap,
1111 CMN_PLL1_FRACDIVH_M0, 0x0002);
1112 cdns_torrent_phy_write(regmap,
1113 CMN_PLL1_HIGH_THR_M0, 0x012C);
1114 cdns_torrent_phy_write(regmap,
1115 CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
1116 if (ssc)
1117 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x0536,
1118 0x0069);
1119 break;
1120 /* Setting VCO for 8.1GHz */
1121 case 8100:
1122 cdns_torrent_phy_write(regmap,
1123 CMN_PLL0_INTDIV_M0, 0x01A5);
1124 cdns_torrent_phy_write(regmap,
1125 CMN_PLL0_FRACDIVL_M0, 0xE000);
1126 cdns_torrent_phy_write(regmap,
1127 CMN_PLL0_FRACDIVH_M0, 0x0002);
1128 cdns_torrent_phy_write(regmap,
1129 CMN_PLL0_HIGH_THR_M0, 0x011A);
1130 cdns_torrent_phy_write(regmap,
1131 CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
1132 cdns_torrent_phy_write(regmap,
1133 CMN_PLL1_INTDIV_M0, 0x01A5);
1134 cdns_torrent_phy_write(regmap,
1135 CMN_PLL1_FRACDIVL_M0, 0xE000);
1136 cdns_torrent_phy_write(regmap,
1137 CMN_PLL1_FRACDIVH_M0, 0x0002);
1138 cdns_torrent_phy_write(regmap,
1139 CMN_PLL1_HIGH_THR_M0, 0x011A);
1140 cdns_torrent_phy_write(regmap,
1141 CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
1142 if (ssc)
1143 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x04D7,
1144 0x006A);
1145 break;
1146 }
1147
1148 if (ssc) {
1149 cdns_torrent_phy_write(regmap,
1150 CMN_PLL0_VCOCAL_PLLCNT_START, 0x025E);
1151 cdns_torrent_phy_write(regmap,
1152 CMN_PLL0_LOCK_PLLCNT_THR, 0x0005);
1153 cdns_torrent_phy_write(regmap,
1154 CMN_PLL1_VCOCAL_PLLCNT_START, 0x025E);
1155 cdns_torrent_phy_write(regmap,
1156 CMN_PLL1_LOCK_PLLCNT_THR, 0x0005);
1157 } else {
1158 cdns_torrent_phy_write(regmap,
1159 CMN_PLL0_VCOCAL_PLLCNT_START, 0x0260);
1160 cdns_torrent_phy_write(regmap,
1161 CMN_PLL1_VCOCAL_PLLCNT_START, 0x0260);
1162 /* Set reset register values to disable SSC */
1163 cdns_torrent_phy_write(regmap,
1164 CMN_PLL0_SS_CTRL1_M0, 0x0002);
1165 cdns_torrent_phy_write(regmap,
1166 CMN_PLL0_SS_CTRL2_M0, 0x0000);
1167 cdns_torrent_phy_write(regmap,
1168 CMN_PLL0_SS_CTRL3_M0, 0x0000);
1169 cdns_torrent_phy_write(regmap,
1170 CMN_PLL0_SS_CTRL4_M0, 0x0000);
1171 cdns_torrent_phy_write(regmap,
1172 CMN_PLL0_LOCK_PLLCNT_THR, 0x0003);
1173 cdns_torrent_phy_write(regmap,
1174 CMN_PLL1_SS_CTRL1_M0, 0x0002);
1175 cdns_torrent_phy_write(regmap,
1176 CMN_PLL1_SS_CTRL2_M0, 0x0000);
1177 cdns_torrent_phy_write(regmap,
1178 CMN_PLL1_SS_CTRL3_M0, 0x0000);
1179 cdns_torrent_phy_write(regmap,
1180 CMN_PLL1_SS_CTRL4_M0, 0x0000);
1181 cdns_torrent_phy_write(regmap,
1182 CMN_PLL1_LOCK_PLLCNT_THR, 0x0003);
1183 }
1184
1185 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x0099);
1186 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x0099);
1187 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x0099);
1188 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x0099);
1189}
1190
1191static
1192void cdns_torrent_dp_pma_cmn_cfg_25mhz(struct cdns_torrent_phy *cdns_phy)
1193{
1194 struct regmap *regmap = cdns_phy->regmap_common_cdb;
1195
1196 /* refclock registers - assumes 25 MHz refclock */
1197 cdns_torrent_phy_write(regmap, CMN_SSM_BIAS_TMR, 0x0019);
1198 cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLPRE_TMR, 0x0032);
1199 cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLLOCK_TMR, 0x00D1);
1200 cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLPRE_TMR, 0x0032);
1201 cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLLOCK_TMR, 0x00D1);
1202 cdns_torrent_phy_write(regmap, CMN_BGCAL_INIT_TMR, 0x007D);
1203 cdns_torrent_phy_write(regmap, CMN_BGCAL_ITER_TMR, 0x007D);
1204 cdns_torrent_phy_write(regmap, CMN_IBCAL_INIT_TMR, 0x0019);
1205 cdns_torrent_phy_write(regmap, CMN_TXPUCAL_INIT_TMR, 0x001E);
1206 cdns_torrent_phy_write(regmap, CMN_TXPUCAL_ITER_TMR, 0x0006);
1207 cdns_torrent_phy_write(regmap, CMN_TXPDCAL_INIT_TMR, 0x001E);
1208 cdns_torrent_phy_write(regmap, CMN_TXPDCAL_ITER_TMR, 0x0006);
1209 cdns_torrent_phy_write(regmap, CMN_RXCAL_INIT_TMR, 0x02EE);
1210 cdns_torrent_phy_write(regmap, CMN_RXCAL_ITER_TMR, 0x0006);
1211 cdns_torrent_phy_write(regmap, CMN_SD_CAL_INIT_TMR, 0x0002);
1212 cdns_torrent_phy_write(regmap, CMN_SD_CAL_ITER_TMR, 0x0002);
1213 cdns_torrent_phy_write(regmap, CMN_SD_CAL_REFTIM_START, 0x000E);
1214 cdns_torrent_phy_write(regmap, CMN_SD_CAL_PLLCNT_START, 0x012B);
1215
1216 /* PLL registers */
1217 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
1218 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
1219 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
1220 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
1221 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
1222 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
1223 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
1224 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
1225 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_INIT_TMR, 0x00FA);
1226 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_ITER_TMR, 0x0004);
1227 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_INIT_TMR, 0x00FA);
1228 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_ITER_TMR, 0x0004);
1229 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_REFTIM_START, 0x0317);
1230 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_TCTRL, 0x0003);
1231 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_REFTIM_START, 0x0317);
1232 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_TCTRL, 0x0003);
1233}
1234
1235/*
1236 * Set registers responsible for enabling and configuring SSC, with second
1237 * register value provided by a parameter.
1238 */
1239static void cdns_torrent_dp_enable_ssc_25mhz(struct cdns_torrent_phy *cdns_phy,
1240 u32 ctrl2_val)
1241{
1242 struct regmap *regmap = cdns_phy->regmap_common_cdb;
1243
1244 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001);
1245 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val);
1246 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x007F);
1247 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003);
1248 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001);
1249 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val);
1250 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x007F);
1251 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003);
1252}
1253
1254static
1255void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy,
1256 u32 rate, bool ssc)
1257{
1258 struct regmap *regmap = cdns_phy->regmap_common_cdb;
1259
1260 /* Assumes 25 MHz refclock */
1261 switch (rate) {
1262 /* Setting VCO for 10.8GHz */
1263 case 2700:
1264 case 5400:
1265 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01B0);
1266 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000);
1267 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
1268 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0120);
1269 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01B0);
1270 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000);
1271 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
1272 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0120);
1273 if (ssc)
1274 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x0423);
1275 break;
1276 /* Setting VCO for 9.72GHz */
1277 case 1620:
1278 case 2430:
1279 case 3240:
1280 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0184);
1281 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0xCCCD);
1282 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
1283 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0104);
1284 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0184);
1285 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0xCCCD);
1286 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
1287 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0104);
1288 if (ssc)
1289 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x03B9);
1290 break;
1291 /* Setting VCO for 8.64GHz */
1292 case 2160:
1293 case 4320:
1294 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0159);
1295 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x999A);
1296 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
1297 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00E7);
1298 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0159);
1299 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x999A);
1300 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
1301 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00E7);
1302 if (ssc)
1303 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x034F);
1304 break;
1305 /* Setting VCO for 8.1GHz */
1306 case 8100:
1307 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0144);
1308 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000);
1309 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
1310 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00D8);
1311 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0144);
1312 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000);
1313 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
1314 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00D8);
1315 if (ssc)
1316 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x031A);
1317 break;
1318 }
1319
1320 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
1321 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
1322
1323 if (ssc) {
1324 cdns_torrent_phy_write(regmap,
1325 CMN_PLL0_VCOCAL_PLLCNT_START, 0x0315);
1326 cdns_torrent_phy_write(regmap,
1327 CMN_PLL0_LOCK_PLLCNT_THR, 0x0005);
1328 cdns_torrent_phy_write(regmap,
1329 CMN_PLL1_VCOCAL_PLLCNT_START, 0x0315);
1330 cdns_torrent_phy_write(regmap,
1331 CMN_PLL1_LOCK_PLLCNT_THR, 0x0005);
1332 } else {
1333 cdns_torrent_phy_write(regmap,
1334 CMN_PLL0_VCOCAL_PLLCNT_START, 0x0317);
1335 cdns_torrent_phy_write(regmap,
1336 CMN_PLL1_VCOCAL_PLLCNT_START, 0x0317);
1337 /* Set reset register values to disable SSC */
1338 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0002);
1339 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL2_M0, 0x0000);
1340 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL3_M0, 0x0000);
1341 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0000);
1342 cdns_torrent_phy_write(regmap,
1343 CMN_PLL0_LOCK_PLLCNT_THR, 0x0003);
1344 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0002);
1345 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL2_M0, 0x0000);
1346 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL3_M0, 0x0000);
1347 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0000);
1348 cdns_torrent_phy_write(regmap,
1349 CMN_PLL1_LOCK_PLLCNT_THR, 0x0003);
1350 }
1351
1352 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x00C7);
1353 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x00C7);
1354 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x00C7);
1355 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x00C7);
1356}
1357
1358static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy,
1359 u32 rate, u32 num_lanes)
1360{
1361 unsigned int clk_sel_val = 0;
1362 unsigned int hsclk_div_val = 0;
1363 unsigned int i;
1364
1365 /* 16'h0000 for single DP link configuration */
1366 regmap_field_write(cdns_phy->phy_pll_cfg, 0x0);
1367
1368 switch (rate) {
1369 case 1620:
1370 clk_sel_val = 0x0f01;
1371 hsclk_div_val = 2;
1372 break;
1373 case 2160:
1374 case 2430:
1375 case 2700:
1376 clk_sel_val = 0x0701;
1377 hsclk_div_val = 1;
1378 break;
1379 case 3240:
1380 clk_sel_val = 0x0b00;
1381 hsclk_div_val = 2;
1382 break;
1383 case 4320:
1384 case 5400:
1385 clk_sel_val = 0x0301;
1386 hsclk_div_val = 0;
1387 break;
1388 case 8100:
1389 clk_sel_val = 0x0200;
1390 hsclk_div_val = 0;
1391 break;
1392 }
1393
1394 cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,
1395 CMN_PDIAG_PLL0_CLK_SEL_M0, clk_sel_val);
1396 cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,
1397 CMN_PDIAG_PLL1_CLK_SEL_M0, clk_sel_val);
1398
1399 /* PMA lane configuration to deal with multi-link operation */
1400 for (i = 0; i < num_lanes; i++)
1401 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[i],
1402 XCVR_DIAG_HSCLK_DIV, hsclk_div_val);
1403}
1404
1405static void cdns_torrent_dp_pma_lane_cfg(struct cdns_torrent_phy *cdns_phy,
1406 unsigned int lane)
1407{
1408 /* Per lane, refclock-dependent receiver detection setting */
1409 if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz)
1410 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1411 TX_RCVDET_ST_TMR, 0x0780);
1412 else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz)
1413 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1414 TX_RCVDET_ST_TMR, 0x09C4);
1415
1416 /* Writing Tx/Rx Power State Controllers registers */
1417 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1418 TX_PSC_A0, 0x00FB);
1419 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1420 TX_PSC_A2, 0x04AA);
1421 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1422 TX_PSC_A3, 0x04AA);
1423 cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
1424 RX_PSC_A0, 0x0000);
1425 cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
1426 RX_PSC_A2, 0x0000);
1427 cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
1428 RX_PSC_A3, 0x0000);
1429
1430 cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
1431 RX_PSC_CAL, 0x0000);
1432
1433 cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
1434 RX_REE_GCSM1_CTRL, 0x0000);
1435 cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
1436 RX_REE_GCSM2_CTRL, 0x0000);
1437 cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
1438 RX_REE_PERGCSM_CTRL, 0x0000);
1439
1440 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1441 XCVR_DIAG_BIDI_CTRL, 0x000F);
1442 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1443 XCVR_DIAG_PLLDRC_CTRL, 0x0001);
1444 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1445 XCVR_DIAG_HSCLK_SEL, 0x0000);
1446}
1447
1448static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy,
1449 u32 num_lanes,
1450 enum phy_powerstate powerstate)
1451{
1452 /* Register value for power state for a single byte. */
1453 u32 value_part;
1454 u32 value;
1455 u32 mask;
1456 u32 read_val;
1457 u32 ret;
1458 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1459
1460 switch (powerstate) {
1461 case (POWERSTATE_A0):
1462 value_part = 0x01U;
1463 break;
1464 case (POWERSTATE_A2):
1465 value_part = 0x04U;
1466 break;
1467 default:
1468 /* Powerstate A3 */
1469 value_part = 0x08U;
1470 break;
1471 }
1472
1473 /* Select values of registers and mask, depending on enabled
1474 * lane count.
1475 */
1476 switch (num_lanes) {
1477 /* lane 0 */
1478 case (1):
1479 value = value_part;
1480 mask = 0x0000003FU;
1481 break;
1482 /* lanes 0-1 */
1483 case (2):
1484 value = (value_part
1485 | (value_part << 8));
1486 mask = 0x00003F3FU;
1487 break;
1488 /* lanes 0-3, all */
1489 default:
1490 value = (value_part
1491 | (value_part << 8)
1492 | (value_part << 16)
1493 | (value_part << 24));
1494 mask = 0x3F3F3F3FU;
1495 break;
1496 }
1497
1498 /* Set power state A<n>. */
1499 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, value);
1500 /* Wait, until PHY acknowledges power state completion. */
1501 ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_POWER_STATE_ACK,
1502 read_val, (read_val & mask) == value, 0,
1503 POLL_TIMEOUT_US);
1504 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, 0x00000000);
1505 ndelay(100);
1506
1507 return ret;
1508}
1509
1510static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, u32 num_lanes)
1511{
1512 unsigned int read_val;
1513 int ret;
1514 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1515
1516 /*
1517 * waiting for ACK of pma_xcvr_pllclk_en_ln_*, only for the
1518 * master lane
1519 */
1520 ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_PLLCLK_EN_ACK,
1521 read_val, read_val & 1,
1522 0, POLL_TIMEOUT_US);
1523 if (ret == -ETIMEDOUT) {
1524 dev_err(cdns_phy->dev,
1525 "timeout waiting for link PLL clock enable ack\n");
1526 return ret;
1527 }
1528
1529 ndelay(100);
1530
1531 ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes,
1532 POWERSTATE_A2);
1533 if (ret)
1534 return ret;
1535
1536 ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes,
1537 POWERSTATE_A0);
1538
1539 return ret;
1540}
1541
1542static int cdns_torrent_phy_on(struct phy *phy)
1543{
1544 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
1545 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
1546 int ret;
1547
1548 /* Take the PHY out of reset */
1549 ret = reset_control_deassert(cdns_phy->phy_rst);
1550 if (ret)
1551 return ret;
1552
1553 /* Take the PHY lane group out of reset */
1554 return reset_control_deassert(inst->lnk_rst);
1555}
1556
1557static int cdns_torrent_phy_off(struct phy *phy)
1558{
1559 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
1560 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
1561 int ret;
1562
1563 ret = reset_control_assert(cdns_phy->phy_rst);
1564 if (ret)
1565 return ret;
1566
1567 return reset_control_assert(inst->lnk_rst);
1568}
1569
1570static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base,
1571 u32 block_offset,
1572 u8 reg_offset_shift,
1573 const struct regmap_config *config)
1574{
1575 struct cdns_regmap_cdb_context *ctx;
1576
1577 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1578 if (!ctx)
1579 return ERR_PTR(-ENOMEM);
1580
1581 ctx->dev = dev;
1582 ctx->base = base + block_offset;
1583 ctx->reg_offset_shift = reg_offset_shift;
1584
1585 return devm_regmap_init(dev, NULL, ctx, config);
1586}
1587
1588static int cdns_regfield_init(struct cdns_torrent_phy *cdns_phy)
1589{
1590 struct device *dev = cdns_phy->dev;
1591 struct regmap_field *field;
1592 struct regmap *regmap;
1593
1594 regmap = cdns_phy->regmap_phy_pcs_common_cdb;
1595 field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg);
1596 if (IS_ERR(field)) {
1597 dev_err(dev, "PHY_PLL_CFG reg field init failed\n");
1598 return PTR_ERR(field);
1599 }
1600 cdns_phy->phy_pll_cfg = field;
1601
1602 regmap = cdns_phy->regmap_phy_pma_common_cdb;
1603 field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_2);
1604 if (IS_ERR(field)) {
1605 dev_err(dev, "PHY_PMA_CMN_CTRL2 reg field init failed\n");
1606 return PTR_ERR(field);
1607 }
1608 cdns_phy->phy_pma_cmn_ctrl_2 = field;
1609
1610 regmap = cdns_phy->regmap_phy_pma_common_cdb;
1611 field = devm_regmap_field_alloc(dev, regmap, phy_pma_pll_raw_ctrl);
1612 if (IS_ERR(field)) {
1613 dev_err(dev, "PHY_PMA_PLL_RAW_CTRL reg field init failed\n");
1614 return PTR_ERR(field);
1615 }
1616 cdns_phy->phy_pma_pll_raw_ctrl = field;
1617
1618 regmap = cdns_phy->regmap_dptx_phy_reg;
1619 field = devm_regmap_field_alloc(dev, regmap, phy_reset_ctrl);
1620 if (IS_ERR(field)) {
1621 dev_err(dev, "PHY_RESET reg field init failed\n");
1622 return PTR_ERR(field);
1623 }
1624 cdns_phy->phy_reset_ctrl = field;
1625
1626 return 0;
1627}
1628
1629static int cdns_regmap_init_torrent_dp(struct cdns_torrent_phy *cdns_phy,
1630 void __iomem *sd_base,
1631 void __iomem *base,
1632 u8 block_offset_shift,
1633 u8 reg_offset_shift)
1634{
1635 struct device *dev = cdns_phy->dev;
1636 struct regmap *regmap;
1637 u32 block_offset;
1638 int i;
1639
1640 for (i = 0; i < MAX_NUM_LANES; i++) {
1641 block_offset = TORRENT_TX_LANE_CDB_OFFSET(i, block_offset_shift,
1642 reg_offset_shift);
1643 regmap = cdns_regmap_init(dev, sd_base, block_offset,
1644 reg_offset_shift,
1645 &cdns_torrent_tx_lane_cdb_config[i]);
1646 if (IS_ERR(regmap)) {
1647 dev_err(dev, "Failed to init tx lane CDB regmap\n");
1648 return PTR_ERR(regmap);
1649 }
1650 cdns_phy->regmap_tx_lane_cdb[i] = regmap;
1651
1652 block_offset = TORRENT_RX_LANE_CDB_OFFSET(i, block_offset_shift,
1653 reg_offset_shift);
1654 regmap = cdns_regmap_init(dev, sd_base, block_offset,
1655 reg_offset_shift,
1656 &cdns_torrent_rx_lane_cdb_config[i]);
1657 if (IS_ERR(regmap)) {
1658 dev_err(dev, "Failed to init rx lane CDB regmap\n");
1659 return PTR_ERR(regmap);
1660 }
1661 cdns_phy->regmap_rx_lane_cdb[i] = regmap;
1662 }
1663
1664 block_offset = TORRENT_COMMON_CDB_OFFSET;
1665 regmap = cdns_regmap_init(dev, sd_base, block_offset,
1666 reg_offset_shift,
1667 &cdns_torrent_common_cdb_config);
1668 if (IS_ERR(regmap)) {
1669 dev_err(dev, "Failed to init common CDB regmap\n");
1670 return PTR_ERR(regmap);
1671 }
1672 cdns_phy->regmap_common_cdb = regmap;
1673
1674 block_offset = TORRENT_PHY_PCS_COMMON_OFFSET(block_offset_shift);
1675 regmap = cdns_regmap_init(dev, sd_base, block_offset,
1676 reg_offset_shift,
1677 &cdns_torrent_phy_pcs_cmn_cdb_config);
1678 if (IS_ERR(regmap)) {
1679 dev_err(dev, "Failed to init PHY PCS common CDB regmap\n");
1680 return PTR_ERR(regmap);
1681 }
1682 cdns_phy->regmap_phy_pcs_common_cdb = regmap;
1683
1684 block_offset = TORRENT_PHY_PMA_COMMON_OFFSET(block_offset_shift);
1685 regmap = cdns_regmap_init(dev, sd_base, block_offset,
1686 reg_offset_shift,
1687 &cdns_torrent_phy_pma_cmn_cdb_config);
1688 if (IS_ERR(regmap)) {
1689 dev_err(dev, "Failed to init PHY PMA common CDB regmap\n");
1690 return PTR_ERR(regmap);
1691 }
1692 cdns_phy->regmap_phy_pma_common_cdb = regmap;
1693
1694 block_offset = TORRENT_DPTX_PHY_OFFSET;
1695 regmap = cdns_regmap_init(dev, base, block_offset,
1696 reg_offset_shift,
1697 &cdns_torrent_dptx_phy_config);
1698 if (IS_ERR(regmap)) {
1699 dev_err(dev, "Failed to init DPTX PHY regmap\n");
1700 return PTR_ERR(regmap);
1701 }
1702 cdns_phy->regmap_dptx_phy_reg = regmap;
1703
1704 return 0;
1705}
1706
1707static int cdns_torrent_phy_probe(struct platform_device *pdev)
1708{
1709 struct resource *regs;
1710 struct cdns_torrent_phy *cdns_phy;
1711 struct device *dev = &pdev->dev;
1712 struct phy_provider *phy_provider;
1713 const struct of_device_id *match;
1714 struct cdns_torrent_data *data;
1715 struct device_node *child;
1716 int ret, subnodes, node = 0, i;
1717
1718 /* Get init data for this PHY */
1719 match = of_match_device(cdns_torrent_phy_of_match, dev);
1720 if (!match)
1721 return -EINVAL;
1722
1723 data = (struct cdns_torrent_data *)match->data;
1724
1725 cdns_phy = devm_kzalloc(dev, sizeof(*cdns_phy), GFP_KERNEL);
1726 if (!cdns_phy)
1727 return -ENOMEM;
1728
1729 dev_set_drvdata(dev, cdns_phy);
1730 cdns_phy->dev = dev;
1731
1732 cdns_phy->phy_rst = devm_reset_control_get_exclusive_by_index(dev, 0);
1733 if (IS_ERR(cdns_phy->phy_rst)) {
1734 dev_err(dev, "%s: failed to get reset\n",
1735 dev->of_node->full_name);
1736 return PTR_ERR(cdns_phy->phy_rst);
1737 }
1738
1739 cdns_phy->clk = devm_clk_get(dev, "refclk");
1740 if (IS_ERR(cdns_phy->clk)) {
1741 dev_err(dev, "phy ref clock not found\n");
1742 return PTR_ERR(cdns_phy->clk);
1743 }
1744
1745 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1746 cdns_phy->sd_base = devm_ioremap_resource(&pdev->dev, regs);
1747 if (IS_ERR(cdns_phy->sd_base))
1748 return PTR_ERR(cdns_phy->sd_base);
1749
1750 subnodes = of_get_available_child_count(dev->of_node);
1751 if (subnodes == 0) {
1752 dev_err(dev, "No available link subnodes found\n");
1753 return -EINVAL;
1754 } else if (subnodes != 1) {
1755 dev_err(dev, "Driver supports only one link subnode.\n");
1756 return -EINVAL;
1757 }
1758
1759 for_each_available_child_of_node(dev->of_node, child) {
1760 struct phy *gphy;
1761
1762 cdns_phy->phys[node].lnk_rst =
1763 of_reset_control_array_get_exclusive(child);
1764 if (IS_ERR(cdns_phy->phys[node].lnk_rst)) {
1765 dev_err(dev, "%s: failed to get reset\n",
1766 child->full_name);
1767 ret = PTR_ERR(cdns_phy->phys[node].lnk_rst);
1768 goto put_lnk_rst;
1769 }
1770
1771 if (of_property_read_u32(child, "reg",
1772 &cdns_phy->phys[node].mlane)) {
1773 dev_err(dev, "%s: No \"reg\"-property.\n",
1774 child->full_name);
1775 ret = -EINVAL;
1776 goto put_child;
1777 }
1778
1779 if (cdns_phy->phys[node].mlane != 0) {
1780 dev_err(dev,
1781 "%s: Driver supports only lane-0 as master lane.\n",
1782 child->full_name);
1783 ret = -EINVAL;
1784 goto put_child;
1785 }
1786
1787 if (of_property_read_u32(child, "cdns,phy-type",
1788 &cdns_phy->phys[node].phy_type)) {
1789 dev_err(dev, "%s: No \"cdns,phy-type\"-property.\n",
1790 child->full_name);
1791 ret = -EINVAL;
1792 goto put_child;
1793 }
1794
1795 cdns_phy->phys[node].num_lanes = DEFAULT_NUM_LANES;
1796 of_property_read_u32(child, "cdns,num-lanes",
1797 &cdns_phy->phys[node].num_lanes);
1798
1799 if (cdns_phy->phys[node].phy_type == PHY_TYPE_DP) {
1800 switch (cdns_phy->phys[node].num_lanes) {
1801 case 1:
1802 case 2:
1803 case 4:
1804 /* valid number of lanes */
1805 break;
1806 default:
1807 dev_err(dev, "unsupported number of lanes: %d\n",
1808 cdns_phy->phys[node].num_lanes);
1809 ret = -EINVAL;
1810 goto put_child;
1811 }
1812
1813 cdns_phy->max_bit_rate = DEFAULT_MAX_BIT_RATE;
1814 of_property_read_u32(child, "cdns,max-bit-rate",
1815 &cdns_phy->max_bit_rate);
1816
1817 switch (cdns_phy->max_bit_rate) {
1818 case 1620:
1819 case 2160:
1820 case 2430:
1821 case 2700:
1822 case 3240:
1823 case 4320:
1824 case 5400:
1825 case 8100:
1826 /* valid bit rate */
1827 break;
1828 default:
1829 dev_err(dev, "unsupported max bit rate: %dMbps\n",
1830 cdns_phy->max_bit_rate);
1831 ret = -EINVAL;
1832 goto put_child;
1833 }
1834
1835 /* DPTX registers */
1836 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1837 cdns_phy->base = devm_ioremap_resource(&pdev->dev,
1838 regs);
1839 if (IS_ERR(cdns_phy->base)) {
1840 ret = PTR_ERR(cdns_phy->base);
1841 goto put_child;
1842 }
1843
1844 gphy = devm_phy_create(dev, child,
1845 &cdns_torrent_phy_ops);
1846 if (IS_ERR(gphy)) {
1847 ret = PTR_ERR(gphy);
1848 goto put_child;
1849 }
1850
1851 dev_info(dev, "%d lanes, max bit rate %d.%03d Gbps\n",
1852 cdns_phy->phys[node].num_lanes,
1853 cdns_phy->max_bit_rate / 1000,
1854 cdns_phy->max_bit_rate % 1000);
1855 } else {
1856 dev_err(dev, "Driver supports only PHY_TYPE_DP\n");
1857 ret = -ENOTSUPP;
1858 goto put_child;
1859 }
1860 cdns_phy->phys[node].phy = gphy;
1861 phy_set_drvdata(gphy, &cdns_phy->phys[node]);
1862
1863 node++;
1864 }
1865 cdns_phy->nsubnodes = node;
1866
1867 ret = cdns_regmap_init_torrent_dp(cdns_phy, cdns_phy->sd_base,
1868 cdns_phy->base,
1869 data->block_offset_shift,
1870 data->reg_offset_shift);
1871 if (ret)
1872 goto put_lnk_rst;
1873
1874 ret = cdns_regfield_init(cdns_phy);
1875 if (ret)
1876 goto put_lnk_rst;
1877
1878 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1879 if (IS_ERR(phy_provider)) {
1880 ret = PTR_ERR(phy_provider);
1881 goto put_lnk_rst;
1882 }
1883
1884 return 0;
1885
1886put_child:
1887 node++;
1888put_lnk_rst:
1889 for (i = 0; i < node; i++)
1890 reset_control_put(cdns_phy->phys[i].lnk_rst);
1891 of_node_put(child);
1892 return ret;
1893}
1894
1895static int cdns_torrent_phy_remove(struct platform_device *pdev)
1896{
1897 struct cdns_torrent_phy *cdns_phy = platform_get_drvdata(pdev);
1898 int i;
1899
1900 reset_control_assert(cdns_phy->phy_rst);
1901 for (i = 0; i < cdns_phy->nsubnodes; i++) {
1902 reset_control_assert(cdns_phy->phys[i].lnk_rst);
1903 reset_control_put(cdns_phy->phys[i].lnk_rst);
1904 }
1905
1906 return 0;
1907}
1908
1909static const struct cdns_torrent_data cdns_map_torrent = {
1910 .block_offset_shift = 0x2,
1911 .reg_offset_shift = 0x2,
1912};
1913
1914static const struct cdns_torrent_data ti_j721e_map_torrent = {
1915 .block_offset_shift = 0x0,
1916 .reg_offset_shift = 0x1,
1917};
1918
1919static const struct of_device_id cdns_torrent_phy_of_match[] = {
1920 {
1921 .compatible = "cdns,torrent-phy",
1922 .data = &cdns_map_torrent,
1923 },
1924 {
1925 .compatible = "ti,j721e-serdes-10g",
1926 .data = &ti_j721e_map_torrent,
1927 },
1928 {}
1929};
1930MODULE_DEVICE_TABLE(of, cdns_torrent_phy_of_match);
1931
1932static struct platform_driver cdns_torrent_phy_driver = {
1933 .probe = cdns_torrent_phy_probe,
1934 .remove = cdns_torrent_phy_remove,
1935 .driver = {
1936 .name = "cdns-torrent-phy",
1937 .of_match_table = cdns_torrent_phy_of_match,
1938 }
1939};
1940module_platform_driver(cdns_torrent_phy_driver);
1941
1942MODULE_AUTHOR("Cadence Design Systems, Inc.");
1943MODULE_DESCRIPTION("Cadence Torrent PHY driver");
1944MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Cadence Torrent SD0801 PHY driver.
4 *
5 * Copyright 2018 Cadence Design Systems, Inc.
6 *
7 */
8
9#include <dt-bindings/phy/phy.h>
10#include <dt-bindings/phy/phy-cadence.h>
11#include <linux/clk.h>
12#include <linux/clk-provider.h>
13#include <linux/delay.h>
14#include <linux/err.h>
15#include <linux/io.h>
16#include <linux/iopoll.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/phy/phy.h>
21#include <linux/platform_device.h>
22#include <linux/reset.h>
23#include <linux/regmap.h>
24
25#define REF_CLK_19_2MHZ 19200000
26#define REF_CLK_25MHZ 25000000
27#define REF_CLK_100MHZ 100000000
28#define REF_CLK_156_25MHZ 156250000
29
30#define MAX_NUM_LANES 4
31#define DEFAULT_MAX_BIT_RATE 8100 /* in Mbps */
32
33#define POLL_TIMEOUT_US 5000
34#define PLL_LOCK_TIMEOUT 100000
35
36#define DP_PLL0 BIT(0)
37#define DP_PLL1 BIT(1)
38
39#define TORRENT_COMMON_CDB_OFFSET 0x0
40
41#define TORRENT_TX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
42 ((0x4000 << (block_offset)) + \
43 (((ln) << 9) << (reg_offset)))
44
45#define TORRENT_RX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
46 ((0x8000 << (block_offset)) + \
47 (((ln) << 9) << (reg_offset)))
48
49#define TORRENT_PHY_PCS_COMMON_OFFSET(block_offset) \
50 (0xC000 << (block_offset))
51
52#define TORRENT_PHY_PCS_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
53 ((0xD000 << (block_offset)) + \
54 (((ln) << 8) << (reg_offset)))
55
56#define TORRENT_PHY_PMA_COMMON_OFFSET(block_offset) \
57 (0xE000 << (block_offset))
58
59#define TORRENT_DPTX_PHY_OFFSET 0x0
60
61/*
62 * register offsets from DPTX PHY register block base (i.e MHDP
63 * register base + 0x30a00)
64 */
65#define PHY_AUX_CTRL 0x04
66#define PHY_RESET 0x20
67#define PMA_TX_ELEC_IDLE_SHIFT 4
68#define PHY_PMA_XCVR_PLLCLK_EN 0x24
69#define PHY_PMA_XCVR_PLLCLK_EN_ACK 0x28
70#define PHY_PMA_XCVR_POWER_STATE_REQ 0x2c
71#define PHY_POWER_STATE_LN(ln) ((ln) * 8)
72#define PMA_XCVR_POWER_STATE_REQ_LN_MASK 0x3FU
73#define PHY_PMA_XCVR_POWER_STATE_ACK 0x30
74#define PHY_PMA_CMN_READY 0x34
75
76/*
77 * register offsets from SD0801 PHY register block base (i.e MHDP
78 * register base + 0x500000)
79 */
80#define CMN_SSM_BANDGAP_TMR 0x0021U
81#define CMN_SSM_BIAS_TMR 0x0022U
82#define CMN_PLLSM0_PLLPRE_TMR 0x002AU
83#define CMN_PLLSM0_PLLLOCK_TMR 0x002CU
84#define CMN_PLLSM1_PLLPRE_TMR 0x0032U
85#define CMN_PLLSM1_PLLLOCK_TMR 0x0034U
86#define CMN_CDIAG_CDB_PWRI_OVRD 0x0041U
87#define CMN_CDIAG_XCVRC_PWRI_OVRD 0x0047U
88#define CMN_CDIAG_REFCLK_OVRD 0x004CU
89#define CMN_CDIAG_REFCLK_DRV0_CTRL 0x0050U
90#define CMN_BGCAL_INIT_TMR 0x0064U
91#define CMN_BGCAL_ITER_TMR 0x0065U
92#define CMN_IBCAL_INIT_TMR 0x0074U
93#define CMN_PLL0_VCOCAL_TCTRL 0x0082U
94#define CMN_PLL0_VCOCAL_INIT_TMR 0x0084U
95#define CMN_PLL0_VCOCAL_ITER_TMR 0x0085U
96#define CMN_PLL0_VCOCAL_REFTIM_START 0x0086U
97#define CMN_PLL0_VCOCAL_PLLCNT_START 0x0088U
98#define CMN_PLL0_INTDIV_M0 0x0090U
99#define CMN_PLL0_FRACDIVL_M0 0x0091U
100#define CMN_PLL0_FRACDIVH_M0 0x0092U
101#define CMN_PLL0_HIGH_THR_M0 0x0093U
102#define CMN_PLL0_DSM_DIAG_M0 0x0094U
103#define CMN_PLL0_DSM_FBH_OVRD_M0 0x0095U
104#define CMN_PLL0_DSM_FBL_OVRD_M0 0x0096U
105#define CMN_PLL0_SS_CTRL1_M0 0x0098U
106#define CMN_PLL0_SS_CTRL2_M0 0x0099U
107#define CMN_PLL0_SS_CTRL3_M0 0x009AU
108#define CMN_PLL0_SS_CTRL4_M0 0x009BU
109#define CMN_PLL0_LOCK_REFCNT_START 0x009CU
110#define CMN_PLL0_LOCK_PLLCNT_START 0x009EU
111#define CMN_PLL0_LOCK_PLLCNT_THR 0x009FU
112#define CMN_PLL0_INTDIV_M1 0x00A0U
113#define CMN_PLL0_FRACDIVH_M1 0x00A2U
114#define CMN_PLL0_HIGH_THR_M1 0x00A3U
115#define CMN_PLL0_DSM_DIAG_M1 0x00A4U
116#define CMN_PLL0_SS_CTRL1_M1 0x00A8U
117#define CMN_PLL0_SS_CTRL2_M1 0x00A9U
118#define CMN_PLL0_SS_CTRL3_M1 0x00AAU
119#define CMN_PLL0_SS_CTRL4_M1 0x00ABU
120#define CMN_PLL1_VCOCAL_TCTRL 0x00C2U
121#define CMN_PLL1_VCOCAL_INIT_TMR 0x00C4U
122#define CMN_PLL1_VCOCAL_ITER_TMR 0x00C5U
123#define CMN_PLL1_VCOCAL_REFTIM_START 0x00C6U
124#define CMN_PLL1_VCOCAL_PLLCNT_START 0x00C8U
125#define CMN_PLL1_INTDIV_M0 0x00D0U
126#define CMN_PLL1_FRACDIVL_M0 0x00D1U
127#define CMN_PLL1_FRACDIVH_M0 0x00D2U
128#define CMN_PLL1_HIGH_THR_M0 0x00D3U
129#define CMN_PLL1_DSM_DIAG_M0 0x00D4U
130#define CMN_PLL1_DSM_FBH_OVRD_M0 0x00D5U
131#define CMN_PLL1_DSM_FBL_OVRD_M0 0x00D6U
132#define CMN_PLL1_SS_CTRL1_M0 0x00D8U
133#define CMN_PLL1_SS_CTRL2_M0 0x00D9U
134#define CMN_PLL1_SS_CTRL3_M0 0x00DAU
135#define CMN_PLL1_SS_CTRL4_M0 0x00DBU
136#define CMN_PLL1_LOCK_REFCNT_START 0x00DCU
137#define CMN_PLL1_LOCK_PLLCNT_START 0x00DEU
138#define CMN_PLL1_LOCK_PLLCNT_THR 0x00DFU
139#define CMN_TXPUCAL_TUNE 0x0103U
140#define CMN_TXPUCAL_INIT_TMR 0x0104U
141#define CMN_TXPUCAL_ITER_TMR 0x0105U
142#define CMN_TXPDCAL_TUNE 0x010BU
143#define CMN_TXPDCAL_INIT_TMR 0x010CU
144#define CMN_TXPDCAL_ITER_TMR 0x010DU
145#define CMN_RXCAL_INIT_TMR 0x0114U
146#define CMN_RXCAL_ITER_TMR 0x0115U
147#define CMN_SD_CAL_INIT_TMR 0x0124U
148#define CMN_SD_CAL_ITER_TMR 0x0125U
149#define CMN_SD_CAL_REFTIM_START 0x0126U
150#define CMN_SD_CAL_PLLCNT_START 0x0128U
151#define CMN_PDIAG_PLL0_CTRL_M0 0x01A0U
152#define CMN_PDIAG_PLL0_CLK_SEL_M0 0x01A1U
153#define CMN_PDIAG_PLL0_CP_PADJ_M0 0x01A4U
154#define CMN_PDIAG_PLL0_CP_IADJ_M0 0x01A5U
155#define CMN_PDIAG_PLL0_FILT_PADJ_M0 0x01A6U
156#define CMN_PDIAG_PLL0_CTRL_M1 0x01B0U
157#define CMN_PDIAG_PLL0_CLK_SEL_M1 0x01B1U
158#define CMN_PDIAG_PLL0_CP_PADJ_M1 0x01B4U
159#define CMN_PDIAG_PLL0_CP_IADJ_M1 0x01B5U
160#define CMN_PDIAG_PLL0_FILT_PADJ_M1 0x01B6U
161#define CMN_PDIAG_PLL1_CTRL_M0 0x01C0U
162#define CMN_PDIAG_PLL1_CLK_SEL_M0 0x01C1U
163#define CMN_PDIAG_PLL1_CP_PADJ_M0 0x01C4U
164#define CMN_PDIAG_PLL1_CP_IADJ_M0 0x01C5U
165#define CMN_PDIAG_PLL1_FILT_PADJ_M0 0x01C6U
166#define CMN_DIAG_BIAS_OVRD1 0x01E1U
167
168/* PMA TX Lane registers */
169#define TX_TXCC_CTRL 0x0040U
170#define TX_TXCC_CPOST_MULT_00 0x004CU
171#define TX_TXCC_CPOST_MULT_01 0x004DU
172#define TX_TXCC_MGNFS_MULT_000 0x0050U
173#define TX_TXCC_MGNFS_MULT_100 0x0054U
174#define DRV_DIAG_TX_DRV 0x00C6U
175#define XCVR_DIAG_PLLDRC_CTRL 0x00E5U
176#define XCVR_DIAG_HSCLK_SEL 0x00E6U
177#define XCVR_DIAG_HSCLK_DIV 0x00E7U
178#define XCVR_DIAG_RXCLK_CTRL 0x00E9U
179#define XCVR_DIAG_BIDI_CTRL 0x00EAU
180#define XCVR_DIAG_PSC_OVRD 0x00EBU
181#define TX_PSC_A0 0x0100U
182#define TX_PSC_A1 0x0101U
183#define TX_PSC_A2 0x0102U
184#define TX_PSC_A3 0x0103U
185#define TX_RCVDET_ST_TMR 0x0123U
186#define TX_DIAG_ACYA 0x01E7U
187#define TX_DIAG_ACYA_HBDC_MASK 0x0001U
188
189/* PMA RX Lane registers */
190#define RX_PSC_A0 0x0000U
191#define RX_PSC_A1 0x0001U
192#define RX_PSC_A2 0x0002U
193#define RX_PSC_A3 0x0003U
194#define RX_PSC_CAL 0x0006U
195#define RX_SDCAL0_INIT_TMR 0x0044U
196#define RX_SDCAL0_ITER_TMR 0x0045U
197#define RX_SDCAL1_INIT_TMR 0x004CU
198#define RX_SDCAL1_ITER_TMR 0x004DU
199#define RX_CDRLF_CNFG 0x0080U
200#define RX_CDRLF_CNFG3 0x0082U
201#define RX_SIGDET_HL_FILT_TMR 0x0090U
202#define RX_REE_GCSM1_CTRL 0x0108U
203#define RX_REE_GCSM1_EQENM_PH1 0x0109U
204#define RX_REE_GCSM1_EQENM_PH2 0x010AU
205#define RX_REE_GCSM2_CTRL 0x0110U
206#define RX_REE_PERGCSM_CTRL 0x0118U
207#define RX_REE_ATTEN_THR 0x0149U
208#define RX_REE_TAP1_CLIP 0x0171U
209#define RX_REE_TAP2TON_CLIP 0x0172U
210#define RX_REE_SMGM_CTRL1 0x0177U
211#define RX_REE_SMGM_CTRL2 0x0178U
212#define RX_DIAG_DFE_CTRL 0x01E0U
213#define RX_DIAG_DFE_AMP_TUNE_2 0x01E2U
214#define RX_DIAG_DFE_AMP_TUNE_3 0x01E3U
215#define RX_DIAG_NQST_CTRL 0x01E5U
216#define RX_DIAG_SIGDET_TUNE 0x01E8U
217#define RX_DIAG_PI_RATE 0x01F4U
218#define RX_DIAG_PI_CAP 0x01F5U
219#define RX_DIAG_ACYA 0x01FFU
220
221/* PHY PCS common registers */
222#define PHY_PIPE_CMN_CTRL1 0x0000U
223#define PHY_PLL_CFG 0x000EU
224#define PHY_PIPE_USB3_GEN2_PRE_CFG0 0x0020U
225#define PHY_PIPE_USB3_GEN2_POST_CFG0 0x0022U
226#define PHY_PIPE_USB3_GEN2_POST_CFG1 0x0023U
227
228/* PHY PCS lane registers */
229#define PHY_PCS_ISO_LINK_CTRL 0x000BU
230
231/* PHY PMA common registers */
232#define PHY_PMA_CMN_CTRL1 0x0000U
233#define PHY_PMA_CMN_CTRL2 0x0001U
234#define PHY_PMA_PLL_RAW_CTRL 0x0003U
235
236#define CDNS_TORRENT_OUTPUT_CLOCKS 3
237
238static const char * const clk_names[] = {
239 [CDNS_TORRENT_REFCLK_DRIVER] = "refclk-driver",
240 [CDNS_TORRENT_DERIVED_REFCLK] = "refclk-der",
241 [CDNS_TORRENT_RECEIVED_REFCLK] = "refclk-rec",
242};
243
244static const struct reg_field phy_pll_cfg =
245 REG_FIELD(PHY_PLL_CFG, 0, 1);
246
247static const struct reg_field phy_pma_cmn_ctrl_1 =
248 REG_FIELD(PHY_PMA_CMN_CTRL1, 0, 0);
249
250static const struct reg_field phy_pma_cmn_ctrl_2 =
251 REG_FIELD(PHY_PMA_CMN_CTRL2, 0, 7);
252
253static const struct reg_field phy_pma_pll_raw_ctrl =
254 REG_FIELD(PHY_PMA_PLL_RAW_CTRL, 0, 1);
255
256static const struct reg_field phy_reset_ctrl =
257 REG_FIELD(PHY_RESET, 8, 8);
258
259static const struct reg_field phy_pcs_iso_link_ctrl_1 =
260 REG_FIELD(PHY_PCS_ISO_LINK_CTRL, 1, 1);
261
262static const struct reg_field phy_pipe_cmn_ctrl1_0 = REG_FIELD(PHY_PIPE_CMN_CTRL1, 0, 0);
263
264static const struct reg_field cmn_cdiag_refclk_ovrd_4 =
265 REG_FIELD(CMN_CDIAG_REFCLK_OVRD, 4, 4);
266
267#define REFCLK_OUT_NUM_CMN_CONFIG 4
268
269enum cdns_torrent_refclk_out_cmn {
270 CMN_CDIAG_REFCLK_DRV0_CTRL_1,
271 CMN_CDIAG_REFCLK_DRV0_CTRL_4,
272 CMN_CDIAG_REFCLK_DRV0_CTRL_5,
273 CMN_CDIAG_REFCLK_DRV0_CTRL_6,
274};
275
276static const struct reg_field refclk_out_cmn_cfg[] = {
277 [CMN_CDIAG_REFCLK_DRV0_CTRL_1] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 1, 1),
278 [CMN_CDIAG_REFCLK_DRV0_CTRL_4] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 4, 4),
279 [CMN_CDIAG_REFCLK_DRV0_CTRL_5] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 5, 5),
280 [CMN_CDIAG_REFCLK_DRV0_CTRL_6] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 6, 6),
281};
282
283static const int refclk_driver_parent_index[] = {
284 CDNS_TORRENT_DERIVED_REFCLK,
285 CDNS_TORRENT_RECEIVED_REFCLK
286};
287
288static u32 cdns_torrent_refclk_driver_mux_table[] = { 1, 0 };
289
290enum cdns_torrent_phy_type {
291 TYPE_NONE,
292 TYPE_DP,
293 TYPE_PCIE,
294 TYPE_SGMII,
295 TYPE_QSGMII,
296 TYPE_USB,
297 TYPE_USXGMII,
298};
299
300enum cdns_torrent_ref_clk {
301 CLK_19_2_MHZ,
302 CLK_25_MHZ,
303 CLK_100_MHZ,
304 CLK_156_25_MHZ,
305 CLK_ANY,
306};
307
308enum cdns_torrent_ssc_mode {
309 NO_SSC,
310 EXTERNAL_SSC,
311 INTERNAL_SSC,
312 ANY_SSC,
313};
314
315/* Unique key id for vals table entry
316 * REFCLK0_RATE | REFCLK1_RATE | LINK0_TYPE | LINK1_TYPE | SSC_TYPE
317 */
318#define REFCLK0_SHIFT 12
319#define REFCLK0_MASK GENMASK(14, 12)
320#define REFCLK1_SHIFT 9
321#define REFCLK1_MASK GENMASK(11, 9)
322#define LINK0_SHIFT 6
323#define LINK0_MASK GENMASK(8, 6)
324#define LINK1_SHIFT 3
325#define LINK1_MASK GENMASK(5, 3)
326#define SSC_SHIFT 0
327#define SSC_MASK GENMASK(2, 0)
328
329#define CDNS_TORRENT_KEY(refclk0, refclk1, link0, link1, ssc) \
330 ((((refclk0) << REFCLK0_SHIFT) & REFCLK0_MASK) | \
331 (((refclk1) << REFCLK1_SHIFT) & REFCLK1_MASK) | \
332 (((link0) << LINK0_SHIFT) & LINK0_MASK) | \
333 (((link1) << LINK1_SHIFT) & LINK1_MASK) | \
334 (((ssc) << SSC_SHIFT) & SSC_MASK))
335
336#define CDNS_TORRENT_KEY_ANYCLK(link0, link1) \
337 CDNS_TORRENT_KEY(CLK_ANY, CLK_ANY, \
338 (link0), (link1), ANY_SSC)
339
340struct cdns_torrent_inst {
341 struct phy *phy;
342 u32 mlane;
343 enum cdns_torrent_phy_type phy_type;
344 u32 num_lanes;
345 struct reset_control *lnk_rst;
346 enum cdns_torrent_ssc_mode ssc_mode;
347};
348
349struct cdns_torrent_phy {
350 void __iomem *base; /* DPTX registers base */
351 void __iomem *sd_base; /* SD0801 registers base */
352 u32 max_bit_rate; /* Maximum link bit rate to use (in Mbps) */
353 u32 dp_pll;
354 struct reset_control *phy_rst;
355 struct reset_control *apb_rst;
356 struct device *dev;
357 struct clk *clk;
358 struct clk *clk1;
359 enum cdns_torrent_ref_clk ref_clk_rate;
360 enum cdns_torrent_ref_clk ref_clk1_rate;
361 struct cdns_torrent_inst phys[MAX_NUM_LANES];
362 int nsubnodes;
363 const struct cdns_torrent_data *init_data;
364 struct regmap *regmap_common_cdb;
365 struct regmap *regmap_phy_pcs_common_cdb;
366 struct regmap *regmap_phy_pma_common_cdb;
367 struct regmap *regmap_tx_lane_cdb[MAX_NUM_LANES];
368 struct regmap *regmap_rx_lane_cdb[MAX_NUM_LANES];
369 struct regmap *regmap_phy_pcs_lane_cdb[MAX_NUM_LANES];
370 struct regmap *regmap_dptx_phy_reg;
371 struct regmap_field *phy_pll_cfg;
372 struct regmap_field *phy_pipe_cmn_ctrl1_0;
373 struct regmap_field *cmn_cdiag_refclk_ovrd_4;
374 struct regmap_field *phy_pma_cmn_ctrl_1;
375 struct regmap_field *phy_pma_cmn_ctrl_2;
376 struct regmap_field *phy_pma_pll_raw_ctrl;
377 struct regmap_field *phy_reset_ctrl;
378 struct regmap_field *phy_pcs_iso_link_ctrl_1[MAX_NUM_LANES];
379 struct clk_hw_onecell_data *clk_hw_data;
380};
381
382enum phy_powerstate {
383 POWERSTATE_A0 = 0,
384 /* Powerstate A1 is unused */
385 POWERSTATE_A2 = 2,
386 POWERSTATE_A3 = 3,
387};
388
389struct cdns_torrent_refclk_driver {
390 struct clk_hw hw;
391 struct regmap_field *cmn_fields[REFCLK_OUT_NUM_CMN_CONFIG];
392 struct clk_init_data clk_data;
393};
394
395#define to_cdns_torrent_refclk_driver(_hw) \
396 container_of(_hw, struct cdns_torrent_refclk_driver, hw)
397
398struct cdns_torrent_derived_refclk {
399 struct clk_hw hw;
400 struct regmap_field *phy_pipe_cmn_ctrl1_0;
401 struct regmap_field *cmn_cdiag_refclk_ovrd_4;
402 struct clk_init_data clk_data;
403};
404
405#define to_cdns_torrent_derived_refclk(_hw) \
406 container_of(_hw, struct cdns_torrent_derived_refclk, hw)
407
408struct cdns_torrent_received_refclk {
409 struct clk_hw hw;
410 struct regmap_field *phy_pipe_cmn_ctrl1_0;
411 struct regmap_field *cmn_cdiag_refclk_ovrd_4;
412 struct clk_init_data clk_data;
413};
414
415#define to_cdns_torrent_received_refclk(_hw) \
416 container_of(_hw, struct cdns_torrent_received_refclk, hw)
417
418struct cdns_reg_pairs {
419 u32 val;
420 u32 off;
421};
422
423struct cdns_torrent_vals {
424 struct cdns_reg_pairs *reg_pairs;
425 u32 num_regs;
426};
427
428struct cdns_torrent_vals_entry {
429 u32 key;
430 struct cdns_torrent_vals *vals;
431};
432
433struct cdns_torrent_vals_table {
434 struct cdns_torrent_vals_entry *entries;
435 u32 num_entries;
436};
437
438struct cdns_torrent_data {
439 u8 block_offset_shift;
440 u8 reg_offset_shift;
441 struct cdns_torrent_vals_table link_cmn_vals_tbl;
442 struct cdns_torrent_vals_table xcvr_diag_vals_tbl;
443 struct cdns_torrent_vals_table pcs_cmn_vals_tbl;
444 struct cdns_torrent_vals_table phy_pma_cmn_vals_tbl;
445 struct cdns_torrent_vals_table cmn_vals_tbl;
446 struct cdns_torrent_vals_table tx_ln_vals_tbl;
447 struct cdns_torrent_vals_table rx_ln_vals_tbl;
448};
449
450struct cdns_regmap_cdb_context {
451 struct device *dev;
452 void __iomem *base;
453 u8 reg_offset_shift;
454};
455
456static struct cdns_torrent_vals *cdns_torrent_get_tbl_vals(const struct cdns_torrent_vals_table *tbl,
457 enum cdns_torrent_ref_clk refclk0,
458 enum cdns_torrent_ref_clk refclk1,
459 enum cdns_torrent_phy_type link0,
460 enum cdns_torrent_phy_type link1,
461 enum cdns_torrent_ssc_mode ssc)
462{
463 int i;
464 u32 key = CDNS_TORRENT_KEY(refclk0, refclk1, link0, link1, ssc);
465
466 for (i = 0; i < tbl->num_entries; i++) {
467 if (tbl->entries[i].key == key)
468 return tbl->entries[i].vals;
469 }
470
471 return NULL;
472}
473
474static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val)
475{
476 struct cdns_regmap_cdb_context *ctx = context;
477 u32 offset = reg << ctx->reg_offset_shift;
478
479 writew(val, ctx->base + offset);
480
481 return 0;
482}
483
484static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val)
485{
486 struct cdns_regmap_cdb_context *ctx = context;
487 u32 offset = reg << ctx->reg_offset_shift;
488
489 *val = readw(ctx->base + offset);
490 return 0;
491}
492
493static int cdns_regmap_dptx_write(void *context, unsigned int reg,
494 unsigned int val)
495{
496 struct cdns_regmap_cdb_context *ctx = context;
497 u32 offset = reg;
498
499 writel(val, ctx->base + offset);
500
501 return 0;
502}
503
504static int cdns_regmap_dptx_read(void *context, unsigned int reg,
505 unsigned int *val)
506{
507 struct cdns_regmap_cdb_context *ctx = context;
508 u32 offset = reg;
509
510 *val = readl(ctx->base + offset);
511 return 0;
512}
513
514#define TORRENT_TX_LANE_CDB_REGMAP_CONF(n) \
515{ \
516 .name = "torrent_tx_lane" n "_cdb", \
517 .reg_stride = 1, \
518 .fast_io = true, \
519 .reg_write = cdns_regmap_write, \
520 .reg_read = cdns_regmap_read, \
521}
522
523#define TORRENT_RX_LANE_CDB_REGMAP_CONF(n) \
524{ \
525 .name = "torrent_rx_lane" n "_cdb", \
526 .reg_stride = 1, \
527 .fast_io = true, \
528 .reg_write = cdns_regmap_write, \
529 .reg_read = cdns_regmap_read, \
530}
531
532static const struct regmap_config cdns_torrent_tx_lane_cdb_config[] = {
533 TORRENT_TX_LANE_CDB_REGMAP_CONF("0"),
534 TORRENT_TX_LANE_CDB_REGMAP_CONF("1"),
535 TORRENT_TX_LANE_CDB_REGMAP_CONF("2"),
536 TORRENT_TX_LANE_CDB_REGMAP_CONF("3"),
537};
538
539static const struct regmap_config cdns_torrent_rx_lane_cdb_config[] = {
540 TORRENT_RX_LANE_CDB_REGMAP_CONF("0"),
541 TORRENT_RX_LANE_CDB_REGMAP_CONF("1"),
542 TORRENT_RX_LANE_CDB_REGMAP_CONF("2"),
543 TORRENT_RX_LANE_CDB_REGMAP_CONF("3"),
544};
545
546static const struct regmap_config cdns_torrent_common_cdb_config = {
547 .name = "torrent_common_cdb",
548 .reg_stride = 1,
549 .fast_io = true,
550 .reg_write = cdns_regmap_write,
551 .reg_read = cdns_regmap_read,
552};
553
554#define TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF(n) \
555{ \
556 .name = "torrent_phy_pcs_lane" n "_cdb", \
557 .reg_stride = 1, \
558 .fast_io = true, \
559 .reg_write = cdns_regmap_write, \
560 .reg_read = cdns_regmap_read, \
561}
562
563static const struct regmap_config cdns_torrent_phy_pcs_lane_cdb_config[] = {
564 TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("0"),
565 TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("1"),
566 TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("2"),
567 TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("3"),
568};
569
570static const struct regmap_config cdns_torrent_phy_pcs_cmn_cdb_config = {
571 .name = "torrent_phy_pcs_cmn_cdb",
572 .reg_stride = 1,
573 .fast_io = true,
574 .reg_write = cdns_regmap_write,
575 .reg_read = cdns_regmap_read,
576};
577
578static const struct regmap_config cdns_torrent_phy_pma_cmn_cdb_config = {
579 .name = "torrent_phy_pma_cmn_cdb",
580 .reg_stride = 1,
581 .fast_io = true,
582 .reg_write = cdns_regmap_write,
583 .reg_read = cdns_regmap_read,
584};
585
586static const struct regmap_config cdns_torrent_dptx_phy_config = {
587 .name = "torrent_dptx_phy",
588 .reg_stride = 1,
589 .fast_io = true,
590 .reg_write = cdns_regmap_dptx_write,
591 .reg_read = cdns_regmap_dptx_read,
592};
593
594/* PHY mmr access functions */
595
596static void cdns_torrent_phy_write(struct regmap *regmap, u32 offset, u32 val)
597{
598 regmap_write(regmap, offset, val);
599}
600
601static u32 cdns_torrent_phy_read(struct regmap *regmap, u32 offset)
602{
603 unsigned int val;
604
605 regmap_read(regmap, offset, &val);
606 return val;
607}
608
609/* DPTX mmr access functions */
610
611static void cdns_torrent_dp_write(struct regmap *regmap, u32 offset, u32 val)
612{
613 regmap_write(regmap, offset, val);
614}
615
616static u32 cdns_torrent_dp_read(struct regmap *regmap, u32 offset)
617{
618 u32 val;
619
620 regmap_read(regmap, offset, &val);
621 return val;
622}
623
624/*
625 * Structure used to store values of PHY registers for voltage-related
626 * coefficients, for particular voltage swing and pre-emphasis level. Values
627 * are shared across all physical lanes.
628 */
629struct coefficients {
630 /* Value of DRV_DIAG_TX_DRV register to use */
631 u16 diag_tx_drv;
632 /* Value of TX_TXCC_MGNFS_MULT_000 register to use */
633 u16 mgnfs_mult;
634 /* Value of TX_TXCC_CPOST_MULT_00 register to use */
635 u16 cpost_mult;
636};
637
638/*
639 * Array consists of values of voltage-related registers for sd0801 PHY. A value
640 * of 0xFFFF is a placeholder for invalid combination, and will never be used.
641 */
642static const struct coefficients vltg_coeff[4][4] = {
643 /* voltage swing 0, pre-emphasis 0->3 */
644 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x002A,
645 .cpost_mult = 0x0000},
646 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F,
647 .cpost_mult = 0x0014},
648 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0012,
649 .cpost_mult = 0x0020},
650 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
651 .cpost_mult = 0x002A}
652 },
653
654 /* voltage swing 1, pre-emphasis 0->3 */
655 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F,
656 .cpost_mult = 0x0000},
657 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0013,
658 .cpost_mult = 0x0012},
659 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
660 .cpost_mult = 0x001F},
661 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
662 .cpost_mult = 0xFFFF}
663 },
664
665 /* voltage swing 2, pre-emphasis 0->3 */
666 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0013,
667 .cpost_mult = 0x0000},
668 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
669 .cpost_mult = 0x0013},
670 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
671 .cpost_mult = 0xFFFF},
672 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
673 .cpost_mult = 0xFFFF}
674 },
675
676 /* voltage swing 3, pre-emphasis 0->3 */
677 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
678 .cpost_mult = 0x0000},
679 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
680 .cpost_mult = 0xFFFF},
681 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
682 .cpost_mult = 0xFFFF},
683 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
684 .cpost_mult = 0xFFFF}
685 }
686};
687
688static const char *cdns_torrent_get_phy_type(enum cdns_torrent_phy_type phy_type)
689{
690 switch (phy_type) {
691 case TYPE_DP:
692 return "DisplayPort";
693 case TYPE_PCIE:
694 return "PCIe";
695 case TYPE_SGMII:
696 return "SGMII";
697 case TYPE_QSGMII:
698 return "QSGMII";
699 case TYPE_USB:
700 return "USB";
701 case TYPE_USXGMII:
702 return "USXGMII";
703 default:
704 return "None";
705 }
706}
707
708/*
709 * Set registers responsible for enabling and configuring SSC, with second and
710 * third register values provided by parameters.
711 */
712static
713void cdns_torrent_dp_enable_ssc_19_2mhz(struct cdns_torrent_phy *cdns_phy,
714 u32 ctrl2_val, u32 ctrl3_val)
715{
716 struct regmap *regmap = cdns_phy->regmap_common_cdb;
717
718 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001);
719 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val);
720 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl3_val);
721 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003);
722 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001);
723 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val);
724 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl3_val);
725 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003);
726}
727
728static
729void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy,
730 u32 rate, bool ssc)
731{
732 struct regmap *regmap = cdns_phy->regmap_common_cdb;
733
734 /* Assumes 19.2 MHz refclock */
735 switch (rate) {
736 /* Setting VCO for 10.8GHz */
737 case 2700:
738 case 5400:
739 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0119);
740 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x4000);
741 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
742 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00BC);
743 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0012);
744 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0119);
745 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x4000);
746 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
747 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00BC);
748 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0012);
749 if (ssc)
750 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x033A, 0x006A);
751 break;
752 /* Setting VCO for 9.72GHz */
753 case 1620:
754 case 2430:
755 case 3240:
756 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01FA);
757 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x4000);
758 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
759 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0152);
760 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
761 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01FA);
762 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x4000);
763 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
764 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0152);
765 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
766 if (ssc)
767 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x05DD, 0x0069);
768 break;
769 /* Setting VCO for 8.64GHz */
770 case 2160:
771 case 4320:
772 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01C2);
773 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000);
774 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
775 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x012C);
776 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
777 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01C2);
778 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000);
779 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
780 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x012C);
781 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
782 if (ssc)
783 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x0536, 0x0069);
784 break;
785 /* Setting VCO for 8.1GHz */
786 case 8100:
787 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01A5);
788 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0xE000);
789 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
790 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x011A);
791 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
792 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01A5);
793 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0xE000);
794 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
795 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x011A);
796 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
797 if (ssc)
798 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x04D7, 0x006A);
799 break;
800 }
801
802 if (ssc) {
803 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_PLLCNT_START, 0x025E);
804 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_THR, 0x0005);
805 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_PLLCNT_START, 0x025E);
806 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_THR, 0x0005);
807 } else {
808 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_PLLCNT_START, 0x0260);
809 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_PLLCNT_START, 0x0260);
810 /* Set reset register values to disable SSC */
811 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0002);
812 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL2_M0, 0x0000);
813 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL3_M0, 0x0000);
814 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0000);
815 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_THR, 0x0003);
816 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0002);
817 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL2_M0, 0x0000);
818 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL3_M0, 0x0000);
819 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0000);
820 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_THR, 0x0003);
821 }
822
823 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x0099);
824 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x0099);
825 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x0099);
826 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x0099);
827}
828
829/*
830 * Set registers responsible for enabling and configuring SSC, with second
831 * register value provided by a parameter.
832 */
833static void cdns_torrent_dp_enable_ssc_25mhz(struct cdns_torrent_phy *cdns_phy,
834 u32 ctrl2_val)
835{
836 struct regmap *regmap = cdns_phy->regmap_common_cdb;
837
838 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001);
839 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val);
840 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x007F);
841 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003);
842 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001);
843 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val);
844 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x007F);
845 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003);
846}
847
848static
849void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy,
850 u32 rate, bool ssc)
851{
852 struct regmap *regmap = cdns_phy->regmap_common_cdb;
853
854 /* Assumes 25 MHz refclock */
855 switch (rate) {
856 /* Setting VCO for 10.8GHz */
857 case 2700:
858 case 5400:
859 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01B0);
860 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000);
861 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
862 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0120);
863 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01B0);
864 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000);
865 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
866 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0120);
867 if (ssc)
868 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x0423);
869 break;
870 /* Setting VCO for 9.72GHz */
871 case 1620:
872 case 2430:
873 case 3240:
874 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0184);
875 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0xCCCD);
876 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
877 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0104);
878 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0184);
879 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0xCCCD);
880 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
881 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0104);
882 if (ssc)
883 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x03B9);
884 break;
885 /* Setting VCO for 8.64GHz */
886 case 2160:
887 case 4320:
888 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0159);
889 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x999A);
890 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
891 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00E7);
892 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0159);
893 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x999A);
894 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
895 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00E7);
896 if (ssc)
897 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x034F);
898 break;
899 /* Setting VCO for 8.1GHz */
900 case 8100:
901 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0144);
902 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000);
903 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
904 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00D8);
905 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0144);
906 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000);
907 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
908 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00D8);
909 if (ssc)
910 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x031A);
911 break;
912 }
913
914 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
915 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
916
917 if (ssc) {
918 cdns_torrent_phy_write(regmap,
919 CMN_PLL0_VCOCAL_PLLCNT_START, 0x0315);
920 cdns_torrent_phy_write(regmap,
921 CMN_PLL0_LOCK_PLLCNT_THR, 0x0005);
922 cdns_torrent_phy_write(regmap,
923 CMN_PLL1_VCOCAL_PLLCNT_START, 0x0315);
924 cdns_torrent_phy_write(regmap,
925 CMN_PLL1_LOCK_PLLCNT_THR, 0x0005);
926 } else {
927 cdns_torrent_phy_write(regmap,
928 CMN_PLL0_VCOCAL_PLLCNT_START, 0x0317);
929 cdns_torrent_phy_write(regmap,
930 CMN_PLL1_VCOCAL_PLLCNT_START, 0x0317);
931 /* Set reset register values to disable SSC */
932 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0002);
933 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL2_M0, 0x0000);
934 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL3_M0, 0x0000);
935 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0000);
936 cdns_torrent_phy_write(regmap,
937 CMN_PLL0_LOCK_PLLCNT_THR, 0x0003);
938 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0002);
939 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL2_M0, 0x0000);
940 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL3_M0, 0x0000);
941 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0000);
942 cdns_torrent_phy_write(regmap,
943 CMN_PLL1_LOCK_PLLCNT_THR, 0x0003);
944 }
945
946 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x00C7);
947 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x00C7);
948 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x00C7);
949 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x00C7);
950}
951
952static
953void cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(struct cdns_torrent_phy *cdns_phy,
954 u32 rate, bool ssc)
955{
956 struct regmap *regmap = cdns_phy->regmap_common_cdb;
957
958 /* Assumes 100 MHz refclock */
959 switch (rate) {
960 /* Setting VCO for 10.8GHz */
961 case 2700:
962 case 5400:
963 if (cdns_phy->dp_pll & DP_PLL0)
964 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_FBH_OVRD_M0, 0x0022);
965
966 if (cdns_phy->dp_pll & DP_PLL1) {
967 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0028);
968 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_FBH_OVRD_M0, 0x0022);
969 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_FBL_OVRD_M0, 0x000C);
970 }
971 break;
972 /* Setting VCO for 9.72GHz */
973 case 1620:
974 case 2430:
975 case 3240:
976 if (cdns_phy->dp_pll & DP_PLL0) {
977 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
978 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
979 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
980 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
981 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0061);
982 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x3333);
983 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
984 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0042);
985 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
986 }
987 if (cdns_phy->dp_pll & DP_PLL1) {
988 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
989 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
990 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
991 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
992 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0061);
993 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x3333);
994 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
995 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0042);
996 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
997 }
998 break;
999 /* Setting VCO for 8.64GHz */
1000 case 2160:
1001 case 4320:
1002 if (cdns_phy->dp_pll & DP_PLL0) {
1003 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
1004 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
1005 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
1006 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
1007 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0056);
1008 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x6666);
1009 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
1010 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x003A);
1011 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
1012 }
1013 if (cdns_phy->dp_pll & DP_PLL1) {
1014 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
1015 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
1016 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
1017 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
1018 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0056);
1019 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x6666);
1020 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
1021 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x003A);
1022 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
1023 }
1024 break;
1025 /* Setting VCO for 8.1GHz */
1026 case 8100:
1027 if (cdns_phy->dp_pll & DP_PLL0) {
1028 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
1029 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
1030 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
1031 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
1032 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0051);
1033 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
1034 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0036);
1035 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
1036 }
1037 if (cdns_phy->dp_pll & DP_PLL1) {
1038 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
1039 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
1040 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
1041 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
1042 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0051);
1043 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
1044 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0036);
1045 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
1046 }
1047 break;
1048 }
1049}
1050
1051/* Set PLL used for DP configuration */
1052static int cdns_torrent_dp_get_pll(struct cdns_torrent_phy *cdns_phy,
1053 enum cdns_torrent_phy_type phy_t2)
1054{
1055 switch (phy_t2) {
1056 case TYPE_PCIE:
1057 case TYPE_USB:
1058 cdns_phy->dp_pll = DP_PLL1;
1059 break;
1060 case TYPE_SGMII:
1061 case TYPE_QSGMII:
1062 cdns_phy->dp_pll = DP_PLL0;
1063 break;
1064 case TYPE_NONE:
1065 cdns_phy->dp_pll = DP_PLL0 | DP_PLL1;
1066 break;
1067 default:
1068 dev_err(cdns_phy->dev, "Unsupported PHY configuration\n");
1069 return -EINVAL;
1070 }
1071
1072 return 0;
1073}
1074
1075/*
1076 * Enable or disable PLL for selected lanes.
1077 */
1078static int cdns_torrent_dp_set_pll_en(struct cdns_torrent_phy *cdns_phy,
1079 struct cdns_torrent_inst *inst,
1080 struct phy_configure_opts_dp *dp,
1081 bool enable)
1082{
1083 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1084 u32 rd_val, pll_ack_val;
1085 int ret;
1086
1087 /*
1088 * Used to determine, which bits to check for or enable in
1089 * PHY_PMA_XCVR_PLLCLK_EN register.
1090 */
1091 u32 pll_bits;
1092 /* Used to enable or disable lanes. */
1093 u32 pll_val;
1094
1095 /* Select values of registers and mask, depending on enabled lane count. */
1096 pll_val = cdns_torrent_dp_read(regmap, PHY_PMA_XCVR_PLLCLK_EN);
1097
1098 if (enable) {
1099 pll_bits = ((1 << dp->lanes) - 1);
1100 pll_val |= pll_bits;
1101 pll_ack_val = pll_bits;
1102 } else {
1103 pll_bits = ((1 << inst->num_lanes) - 1);
1104 pll_val &= (~pll_bits);
1105 pll_ack_val = 0;
1106 }
1107
1108 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_val);
1109
1110 /* Wait for acknowledgment from PHY. */
1111 ret = regmap_read_poll_timeout(regmap,
1112 PHY_PMA_XCVR_PLLCLK_EN_ACK,
1113 rd_val,
1114 (rd_val & pll_bits) == pll_ack_val,
1115 0, POLL_TIMEOUT_US);
1116 ndelay(100);
1117 return ret;
1118}
1119
1120static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy,
1121 struct cdns_torrent_inst *inst,
1122 u32 num_lanes,
1123 enum phy_powerstate powerstate)
1124{
1125 /* Register value for power state for a single byte. */
1126 u32 value_part, i;
1127 u32 value = 0;
1128 u32 mask = 0;
1129 u32 read_val;
1130 int ret;
1131 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1132
1133 switch (powerstate) {
1134 case (POWERSTATE_A0):
1135 value_part = 0x01U;
1136 break;
1137 case (POWERSTATE_A2):
1138 value_part = 0x04U;
1139 break;
1140 default:
1141 /* Powerstate A3 */
1142 value_part = 0x08U;
1143 break;
1144 }
1145
1146 /* Select values of registers and mask, depending on enabled lane count. */
1147
1148 for (i = 0; i < num_lanes; i++) {
1149 value |= (value_part << PHY_POWER_STATE_LN(i));
1150 mask |= (PMA_XCVR_POWER_STATE_REQ_LN_MASK << PHY_POWER_STATE_LN(i));
1151 }
1152
1153 /* Set power state A<n>. */
1154 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, value);
1155 /* Wait, until PHY acknowledges power state completion. */
1156 ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_POWER_STATE_ACK,
1157 read_val, (read_val & mask) == value, 0,
1158 POLL_TIMEOUT_US);
1159 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, 0x00000000);
1160 ndelay(100);
1161
1162 return ret;
1163}
1164
1165static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy,
1166 struct cdns_torrent_inst *inst, u32 num_lanes)
1167{
1168 unsigned int read_val;
1169 int ret;
1170 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1171
1172 /*
1173 * waiting for ACK of pma_xcvr_pllclk_en_ln_*, only for the
1174 * master lane
1175 */
1176 ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_PLLCLK_EN_ACK,
1177 read_val, read_val & 1,
1178 0, POLL_TIMEOUT_US);
1179 if (ret == -ETIMEDOUT) {
1180 dev_err(cdns_phy->dev,
1181 "timeout waiting for link PLL clock enable ack\n");
1182 return ret;
1183 }
1184
1185 ndelay(100);
1186
1187 ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, num_lanes,
1188 POWERSTATE_A2);
1189 if (ret)
1190 return ret;
1191
1192 ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, num_lanes,
1193 POWERSTATE_A0);
1194
1195 return ret;
1196}
1197
1198static int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy)
1199{
1200 unsigned int reg;
1201 int ret;
1202 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1203
1204 ret = regmap_read_poll_timeout(regmap, PHY_PMA_CMN_READY, reg,
1205 reg & 1, 0, POLL_TIMEOUT_US);
1206 if (ret == -ETIMEDOUT) {
1207 dev_err(cdns_phy->dev,
1208 "timeout waiting for PMA common ready\n");
1209 return -ETIMEDOUT;
1210 }
1211
1212 return 0;
1213}
1214
1215static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy,
1216 struct cdns_torrent_inst *inst,
1217 u32 rate, u32 num_lanes)
1218{
1219 unsigned int clk_sel_val = 0;
1220 unsigned int hsclk_div_val = 0;
1221 unsigned int i;
1222
1223 switch (rate) {
1224 case 1620:
1225 clk_sel_val = 0x0f01;
1226 hsclk_div_val = 2;
1227 break;
1228 case 2160:
1229 case 2430:
1230 case 2700:
1231 clk_sel_val = 0x0701;
1232 hsclk_div_val = 1;
1233 break;
1234 case 3240:
1235 clk_sel_val = 0x0b00;
1236 hsclk_div_val = 2;
1237 break;
1238 case 4320:
1239 case 5400:
1240 clk_sel_val = 0x0301;
1241 hsclk_div_val = 0;
1242 break;
1243 case 8100:
1244 clk_sel_val = 0x0200;
1245 hsclk_div_val = 0;
1246 break;
1247 }
1248
1249 if (cdns_phy->dp_pll & DP_PLL0)
1250 cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,
1251 CMN_PDIAG_PLL0_CLK_SEL_M0, clk_sel_val);
1252
1253 if (cdns_phy->dp_pll & DP_PLL1)
1254 cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,
1255 CMN_PDIAG_PLL1_CLK_SEL_M0, clk_sel_val);
1256
1257 /* PMA lane configuration to deal with multi-link operation */
1258 for (i = 0; i < num_lanes; i++)
1259 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + i],
1260 XCVR_DIAG_HSCLK_DIV, hsclk_div_val);
1261}
1262
1263/*
1264 * Perform register operations related to setting link rate, once powerstate is
1265 * set and PLL disable request was processed.
1266 */
1267static int cdns_torrent_dp_configure_rate(struct cdns_torrent_phy *cdns_phy,
1268 struct cdns_torrent_inst *inst,
1269 struct phy_configure_opts_dp *dp)
1270{
1271 u32 read_val, field_val;
1272 int ret;
1273
1274 /*
1275 * Disable the associated PLL (cmn_pll0_en or cmn_pll1_en) before
1276 * re-programming the new data rate.
1277 */
1278 ret = regmap_field_read(cdns_phy->phy_pma_pll_raw_ctrl, &field_val);
1279 if (ret)
1280 return ret;
1281 field_val &= ~(cdns_phy->dp_pll);
1282 regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, field_val);
1283
1284 /*
1285 * Wait for PLL ready de-assertion.
1286 * For PLL0 - PHY_PMA_CMN_CTRL2[2] == 1
1287 * For PLL1 - PHY_PMA_CMN_CTRL2[3] == 1
1288 */
1289 if (cdns_phy->dp_pll & DP_PLL0) {
1290 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
1291 read_val,
1292 ((read_val >> 2) & 0x01) != 0,
1293 0, POLL_TIMEOUT_US);
1294 if (ret)
1295 return ret;
1296 }
1297
1298 if ((cdns_phy->dp_pll & DP_PLL1) && cdns_phy->nsubnodes != 1) {
1299 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
1300 read_val,
1301 ((read_val >> 3) & 0x01) != 0,
1302 0, POLL_TIMEOUT_US);
1303 if (ret)
1304 return ret;
1305 }
1306 ndelay(200);
1307
1308 /* DP Rate Change - VCO Output settings. */
1309 if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ)
1310 /* PMA common configuration 19.2MHz */
1311 cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, dp->link_rate, dp->ssc);
1312 else if (cdns_phy->ref_clk_rate == CLK_25_MHZ)
1313 /* PMA common configuration 25MHz */
1314 cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, dp->link_rate, dp->ssc);
1315 else if (cdns_phy->ref_clk_rate == CLK_100_MHZ)
1316 /* PMA common configuration 100MHz */
1317 cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(cdns_phy, dp->link_rate, dp->ssc);
1318
1319 cdns_torrent_dp_pma_cmn_rate(cdns_phy, inst, dp->link_rate, dp->lanes);
1320
1321 /* Enable the associated PLL (cmn_pll0_en or cmn_pll1_en) */
1322 ret = regmap_field_read(cdns_phy->phy_pma_pll_raw_ctrl, &field_val);
1323 if (ret)
1324 return ret;
1325 field_val |= cdns_phy->dp_pll;
1326 regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, field_val);
1327
1328 /*
1329 * Wait for PLL ready assertion.
1330 * For PLL0 - PHY_PMA_CMN_CTRL2[0] == 1
1331 * For PLL1 - PHY_PMA_CMN_CTRL2[1] == 1
1332 */
1333 if (cdns_phy->dp_pll & DP_PLL0) {
1334 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
1335 read_val,
1336 (read_val & 0x01) != 0,
1337 0, POLL_TIMEOUT_US);
1338 if (ret)
1339 return ret;
1340 }
1341
1342 if ((cdns_phy->dp_pll & DP_PLL1) && cdns_phy->nsubnodes != 1)
1343 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
1344 read_val,
1345 ((read_val >> 1) & 0x01) != 0,
1346 0, POLL_TIMEOUT_US);
1347
1348 return ret;
1349}
1350
1351/*
1352 * Verify, that parameters to configure PHY with are correct.
1353 */
1354static int cdns_torrent_dp_verify_config(struct cdns_torrent_inst *inst,
1355 struct phy_configure_opts_dp *dp)
1356{
1357 u8 i;
1358
1359 /* If changing link rate was required, verify it's supported. */
1360 if (dp->set_rate) {
1361 switch (dp->link_rate) {
1362 case 1620:
1363 case 2160:
1364 case 2430:
1365 case 2700:
1366 case 3240:
1367 case 4320:
1368 case 5400:
1369 case 8100:
1370 /* valid bit rate */
1371 break;
1372 default:
1373 return -EINVAL;
1374 }
1375 }
1376
1377 /* Verify lane count. */
1378 switch (dp->lanes) {
1379 case 1:
1380 case 2:
1381 case 4:
1382 /* valid lane count. */
1383 break;
1384 default:
1385 return -EINVAL;
1386 }
1387
1388 /* Check against actual number of PHY's lanes. */
1389 if (dp->lanes > inst->num_lanes)
1390 return -EINVAL;
1391
1392 /*
1393 * If changing voltages is required, check swing and pre-emphasis
1394 * levels, per-lane.
1395 */
1396 if (dp->set_voltages) {
1397 /* Lane count verified previously. */
1398 for (i = 0; i < dp->lanes; i++) {
1399 if (dp->voltage[i] > 3 || dp->pre[i] > 3)
1400 return -EINVAL;
1401
1402 /* Sum of voltage swing and pre-emphasis levels cannot
1403 * exceed 3.
1404 */
1405 if (dp->voltage[i] + dp->pre[i] > 3)
1406 return -EINVAL;
1407 }
1408 }
1409
1410 return 0;
1411}
1412
1413/* Set power state A0 and PLL clock enable to 0 on enabled lanes. */
1414static void cdns_torrent_dp_set_a0_pll(struct cdns_torrent_phy *cdns_phy,
1415 struct cdns_torrent_inst *inst,
1416 u32 num_lanes)
1417{
1418 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1419 u32 pwr_state = cdns_torrent_dp_read(regmap,
1420 PHY_PMA_XCVR_POWER_STATE_REQ);
1421 u32 pll_clk_en = cdns_torrent_dp_read(regmap,
1422 PHY_PMA_XCVR_PLLCLK_EN);
1423 u32 i;
1424
1425 for (i = 0; i < num_lanes; i++) {
1426 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK
1427 << PHY_POWER_STATE_LN(inst->mlane + i));
1428
1429 pll_clk_en &= ~(0x01U << (inst->mlane + i));
1430 }
1431
1432 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, pwr_state);
1433 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_clk_en);
1434}
1435
1436/* Configure lane count as required. */
1437static int cdns_torrent_dp_set_lanes(struct cdns_torrent_phy *cdns_phy,
1438 struct cdns_torrent_inst *inst,
1439 struct phy_configure_opts_dp *dp)
1440{
1441 u32 value, i;
1442 int ret;
1443 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1444 u8 lane_mask = (1 << dp->lanes) - 1;
1445 u8 pma_tx_elec_idle_mask = 0;
1446 u32 clane = inst->mlane;
1447
1448 lane_mask <<= clane;
1449
1450 value = cdns_torrent_dp_read(regmap, PHY_RESET);
1451 /* clear pma_tx_elec_idle_ln_* bits. */
1452 pma_tx_elec_idle_mask = ((1 << inst->num_lanes) - 1) << clane;
1453
1454 pma_tx_elec_idle_mask <<= PMA_TX_ELEC_IDLE_SHIFT;
1455
1456 value &= ~pma_tx_elec_idle_mask;
1457
1458 /* Assert pma_tx_elec_idle_ln_* for disabled lanes. */
1459 value |= ((~lane_mask) << PMA_TX_ELEC_IDLE_SHIFT) &
1460 pma_tx_elec_idle_mask;
1461
1462 cdns_torrent_dp_write(regmap, PHY_RESET, value);
1463
1464 /* reset the link by asserting master lane phy_l0*_reset_n low */
1465 cdns_torrent_dp_write(regmap, PHY_RESET,
1466 value & (~(1 << clane)));
1467
1468 /*
1469 * Assert lane reset on unused lanes and master lane so they remain in reset
1470 * and powered down when re-enabling the link
1471 */
1472 for (i = 0; i < inst->num_lanes; i++)
1473 value &= (~(1 << (clane + i)));
1474
1475 for (i = 1; i < inst->num_lanes; i++)
1476 value |= ((1 << (clane + i)) & lane_mask);
1477
1478 cdns_torrent_dp_write(regmap, PHY_RESET, value);
1479
1480 cdns_torrent_dp_set_a0_pll(cdns_phy, inst, dp->lanes);
1481
1482 /* release phy_l0*_reset_n based on used laneCount */
1483 for (i = 0; i < inst->num_lanes; i++)
1484 value &= (~(1 << (clane + i)));
1485
1486 for (i = 0; i < inst->num_lanes; i++)
1487 value |= ((1 << (clane + i)) & lane_mask);
1488
1489 cdns_torrent_dp_write(regmap, PHY_RESET, value);
1490
1491 /* Wait, until PHY gets ready after releasing PHY reset signal. */
1492 ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy);
1493 if (ret)
1494 return ret;
1495
1496 ndelay(100);
1497
1498 /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
1499 value = cdns_torrent_dp_read(regmap, PHY_PMA_XCVR_PLLCLK_EN);
1500 value |= (1 << clane);
1501 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, value);
1502
1503 ret = cdns_torrent_dp_run(cdns_phy, inst, dp->lanes);
1504
1505 return ret;
1506}
1507
1508/* Configure link rate as required. */
1509static int cdns_torrent_dp_set_rate(struct cdns_torrent_phy *cdns_phy,
1510 struct cdns_torrent_inst *inst,
1511 struct phy_configure_opts_dp *dp)
1512{
1513 int ret;
1514
1515 ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, dp->lanes,
1516 POWERSTATE_A3);
1517 if (ret)
1518 return ret;
1519 ret = cdns_torrent_dp_set_pll_en(cdns_phy, inst, dp, false);
1520 if (ret)
1521 return ret;
1522 ndelay(200);
1523
1524 ret = cdns_torrent_dp_configure_rate(cdns_phy, inst, dp);
1525 if (ret)
1526 return ret;
1527 ndelay(200);
1528
1529 ret = cdns_torrent_dp_set_pll_en(cdns_phy, inst, dp, true);
1530 if (ret)
1531 return ret;
1532 ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, dp->lanes,
1533 POWERSTATE_A2);
1534 if (ret)
1535 return ret;
1536 ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, dp->lanes,
1537 POWERSTATE_A0);
1538 if (ret)
1539 return ret;
1540 ndelay(900);
1541
1542 return ret;
1543}
1544
1545/* Configure voltage swing and pre-emphasis for all enabled lanes. */
1546static void cdns_torrent_dp_set_voltages(struct cdns_torrent_phy *cdns_phy,
1547 struct cdns_torrent_inst *inst,
1548 struct phy_configure_opts_dp *dp)
1549{
1550 u8 lane;
1551 u16 val;
1552
1553 for (lane = 0; lane < dp->lanes; lane++) {
1554 val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
1555 TX_DIAG_ACYA);
1556 /*
1557 * Write 1 to register bit TX_DIAG_ACYA[0] to freeze the
1558 * current state of the analog TX driver.
1559 */
1560 val |= TX_DIAG_ACYA_HBDC_MASK;
1561 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
1562 TX_DIAG_ACYA, val);
1563
1564 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
1565 TX_TXCC_CTRL, 0x08A4);
1566 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].diag_tx_drv;
1567 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
1568 DRV_DIAG_TX_DRV, val);
1569 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].mgnfs_mult;
1570 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
1571 TX_TXCC_MGNFS_MULT_000,
1572 val);
1573 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].cpost_mult;
1574 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
1575 TX_TXCC_CPOST_MULT_00,
1576 val);
1577
1578 val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
1579 TX_DIAG_ACYA);
1580 /*
1581 * Write 0 to register bit TX_DIAG_ACYA[0] to allow the state of
1582 * analog TX driver to reflect the new programmed one.
1583 */
1584 val &= ~TX_DIAG_ACYA_HBDC_MASK;
1585 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
1586 TX_DIAG_ACYA, val);
1587 }
1588};
1589
1590static int cdns_torrent_dp_configure(struct phy *phy,
1591 union phy_configure_opts *opts)
1592{
1593 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
1594 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
1595 int ret;
1596
1597 ret = cdns_torrent_dp_verify_config(inst, &opts->dp);
1598 if (ret) {
1599 dev_err(&phy->dev, "invalid params for phy configure\n");
1600 return ret;
1601 }
1602
1603 if (opts->dp.set_lanes) {
1604 ret = cdns_torrent_dp_set_lanes(cdns_phy, inst, &opts->dp);
1605 if (ret) {
1606 dev_err(&phy->dev, "cdns_torrent_dp_set_lanes failed\n");
1607 return ret;
1608 }
1609 }
1610
1611 if (opts->dp.set_rate) {
1612 ret = cdns_torrent_dp_set_rate(cdns_phy, inst, &opts->dp);
1613 if (ret) {
1614 dev_err(&phy->dev, "cdns_torrent_dp_set_rate failed\n");
1615 return ret;
1616 }
1617 }
1618
1619 if (opts->dp.set_voltages)
1620 cdns_torrent_dp_set_voltages(cdns_phy, inst, &opts->dp);
1621
1622 return ret;
1623}
1624
1625static int cdns_torrent_phy_on(struct phy *phy)
1626{
1627 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
1628 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
1629 u32 read_val;
1630 int ret;
1631
1632 if (cdns_phy->nsubnodes == 1) {
1633 /* Take the PHY lane group out of reset */
1634 reset_control_deassert(inst->lnk_rst);
1635
1636 /* Take the PHY out of reset */
1637 ret = reset_control_deassert(cdns_phy->phy_rst);
1638 if (ret)
1639 return ret;
1640 }
1641
1642 /*
1643 * Wait for cmn_ready assertion
1644 * PHY_PMA_CMN_CTRL1[0] == 1
1645 */
1646 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_1,
1647 read_val, read_val, 1000,
1648 PLL_LOCK_TIMEOUT);
1649 if (ret) {
1650 dev_err(cdns_phy->dev, "Timeout waiting for CMN ready\n");
1651 return ret;
1652 }
1653
1654 if (inst->phy_type == TYPE_PCIE || inst->phy_type == TYPE_USB) {
1655 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pcs_iso_link_ctrl_1[inst->mlane],
1656 read_val, !read_val, 1000,
1657 PLL_LOCK_TIMEOUT);
1658 if (ret == -ETIMEDOUT) {
1659 dev_err(cdns_phy->dev, "Timeout waiting for PHY status ready\n");
1660 return ret;
1661 }
1662 }
1663
1664 return 0;
1665}
1666
1667static int cdns_torrent_phy_off(struct phy *phy)
1668{
1669 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
1670 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
1671 int ret;
1672
1673 if (cdns_phy->nsubnodes != 1)
1674 return 0;
1675
1676 ret = reset_control_assert(cdns_phy->phy_rst);
1677 if (ret)
1678 return ret;
1679
1680 return reset_control_assert(inst->lnk_rst);
1681}
1682
1683static void cdns_torrent_dp_common_init(struct cdns_torrent_phy *cdns_phy,
1684 struct cdns_torrent_inst *inst)
1685{
1686 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1687 unsigned char lane_bits;
1688 u32 val;
1689
1690 cdns_torrent_dp_write(regmap, PHY_AUX_CTRL, 0x0003); /* enable AUX */
1691
1692 /*
1693 * Set lines power state to A0
1694 * Set lines pll clk enable to 0
1695 */
1696 cdns_torrent_dp_set_a0_pll(cdns_phy, inst, inst->num_lanes);
1697
1698 /*
1699 * release phy_l0*_reset_n and pma_tx_elec_idle_ln_* based on
1700 * used lanes
1701 */
1702 lane_bits = (1 << inst->num_lanes) - 1;
1703
1704 val = cdns_torrent_dp_read(regmap, PHY_RESET);
1705 val |= (0xF & lane_bits);
1706 val &= ~(lane_bits << 4);
1707 cdns_torrent_dp_write(regmap, PHY_RESET, val);
1708
1709 /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
1710 val = cdns_torrent_dp_read(regmap, PHY_PMA_XCVR_PLLCLK_EN);
1711 val |= 1;
1712 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, val);
1713
1714 /*
1715 * PHY PMA registers configuration functions
1716 * Initialize PHY with max supported link rate, without SSC.
1717 */
1718 if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ)
1719 cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy,
1720 cdns_phy->max_bit_rate,
1721 false);
1722 else if (cdns_phy->ref_clk_rate == CLK_25_MHZ)
1723 cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy,
1724 cdns_phy->max_bit_rate,
1725 false);
1726 else if (cdns_phy->ref_clk_rate == CLK_100_MHZ)
1727 cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(cdns_phy,
1728 cdns_phy->max_bit_rate,
1729 false);
1730
1731 cdns_torrent_dp_pma_cmn_rate(cdns_phy, inst, cdns_phy->max_bit_rate,
1732 inst->num_lanes);
1733
1734 /* take out of reset */
1735 regmap_field_write(cdns_phy->phy_reset_ctrl, 0x1);
1736}
1737
1738static int cdns_torrent_dp_start(struct cdns_torrent_phy *cdns_phy,
1739 struct cdns_torrent_inst *inst,
1740 struct phy *phy)
1741{
1742 int ret;
1743
1744 ret = cdns_torrent_phy_on(phy);
1745 if (ret)
1746 return ret;
1747
1748 ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy);
1749 if (ret)
1750 return ret;
1751
1752 ret = cdns_torrent_dp_run(cdns_phy, inst, inst->num_lanes);
1753
1754 return ret;
1755}
1756
1757static int cdns_torrent_dp_init(struct phy *phy)
1758{
1759 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
1760 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
1761 int ret;
1762
1763 switch (cdns_phy->ref_clk_rate) {
1764 case CLK_19_2_MHZ:
1765 case CLK_25_MHZ:
1766 case CLK_100_MHZ:
1767 /* Valid Ref Clock Rate */
1768 break;
1769 default:
1770 dev_err(cdns_phy->dev, "Unsupported Ref Clock Rate\n");
1771 return -EINVAL;
1772 }
1773
1774 ret = cdns_torrent_dp_get_pll(cdns_phy, TYPE_NONE);
1775 if (ret)
1776 return ret;
1777
1778 cdns_torrent_dp_common_init(cdns_phy, inst);
1779
1780 return cdns_torrent_dp_start(cdns_phy, inst, phy);
1781}
1782
1783static int cdns_torrent_dp_multilink_init(struct cdns_torrent_phy *cdns_phy,
1784 struct cdns_torrent_inst *inst,
1785 struct phy *phy)
1786{
1787 if (cdns_phy->ref_clk_rate != CLK_100_MHZ) {
1788 dev_err(cdns_phy->dev, "Unsupported Ref Clock Rate\n");
1789 return -EINVAL;
1790 }
1791
1792 cdns_torrent_dp_common_init(cdns_phy, inst);
1793
1794 return cdns_torrent_dp_start(cdns_phy, inst, phy);
1795}
1796
1797static int cdns_torrent_derived_refclk_enable(struct clk_hw *hw)
1798{
1799 struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw);
1800
1801 regmap_field_write(derived_refclk->cmn_cdiag_refclk_ovrd_4, 1);
1802 regmap_field_write(derived_refclk->phy_pipe_cmn_ctrl1_0, 1);
1803
1804 return 0;
1805}
1806
1807static void cdns_torrent_derived_refclk_disable(struct clk_hw *hw)
1808{
1809 struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw);
1810
1811 regmap_field_write(derived_refclk->phy_pipe_cmn_ctrl1_0, 0);
1812 regmap_field_write(derived_refclk->cmn_cdiag_refclk_ovrd_4, 0);
1813}
1814
1815static int cdns_torrent_derived_refclk_is_enabled(struct clk_hw *hw)
1816{
1817 struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw);
1818 int val;
1819
1820 regmap_field_read(derived_refclk->cmn_cdiag_refclk_ovrd_4, &val);
1821
1822 return !!val;
1823}
1824
1825static const struct clk_ops cdns_torrent_derived_refclk_ops = {
1826 .enable = cdns_torrent_derived_refclk_enable,
1827 .disable = cdns_torrent_derived_refclk_disable,
1828 .is_enabled = cdns_torrent_derived_refclk_is_enabled,
1829};
1830
1831static int cdns_torrent_derived_refclk_register(struct cdns_torrent_phy *cdns_phy)
1832{
1833 struct cdns_torrent_derived_refclk *derived_refclk;
1834 struct device *dev = cdns_phy->dev;
1835 struct clk_init_data *init;
1836 const char *parent_name;
1837 char clk_name[100];
1838 struct clk_hw *hw;
1839 struct clk *clk;
1840 int ret;
1841
1842 derived_refclk = devm_kzalloc(dev, sizeof(*derived_refclk), GFP_KERNEL);
1843 if (!derived_refclk)
1844 return -ENOMEM;
1845
1846 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
1847 clk_names[CDNS_TORRENT_DERIVED_REFCLK]);
1848
1849 clk = devm_clk_get_optional(dev, "phy_en_refclk");
1850 if (IS_ERR(clk)) {
1851 dev_err(dev, "No parent clock for derived_refclk\n");
1852 return PTR_ERR(clk);
1853 }
1854
1855 init = &derived_refclk->clk_data;
1856
1857 if (clk) {
1858 parent_name = __clk_get_name(clk);
1859 init->parent_names = &parent_name;
1860 init->num_parents = 1;
1861 }
1862 init->ops = &cdns_torrent_derived_refclk_ops;
1863 init->flags = 0;
1864 init->name = clk_name;
1865
1866 derived_refclk->phy_pipe_cmn_ctrl1_0 = cdns_phy->phy_pipe_cmn_ctrl1_0;
1867 derived_refclk->cmn_cdiag_refclk_ovrd_4 = cdns_phy->cmn_cdiag_refclk_ovrd_4;
1868
1869 derived_refclk->hw.init = init;
1870
1871 hw = &derived_refclk->hw;
1872 ret = devm_clk_hw_register(dev, hw);
1873 if (ret)
1874 return ret;
1875
1876 cdns_phy->clk_hw_data->hws[CDNS_TORRENT_DERIVED_REFCLK] = hw;
1877
1878 return 0;
1879}
1880
1881static int cdns_torrent_received_refclk_enable(struct clk_hw *hw)
1882{
1883 struct cdns_torrent_received_refclk *received_refclk = to_cdns_torrent_received_refclk(hw);
1884
1885 regmap_field_write(received_refclk->phy_pipe_cmn_ctrl1_0, 1);
1886
1887 return 0;
1888}
1889
1890static void cdns_torrent_received_refclk_disable(struct clk_hw *hw)
1891{
1892 struct cdns_torrent_received_refclk *received_refclk = to_cdns_torrent_received_refclk(hw);
1893
1894 regmap_field_write(received_refclk->phy_pipe_cmn_ctrl1_0, 0);
1895}
1896
1897static int cdns_torrent_received_refclk_is_enabled(struct clk_hw *hw)
1898{
1899 struct cdns_torrent_received_refclk *received_refclk = to_cdns_torrent_received_refclk(hw);
1900 int val, cmn_val;
1901
1902 regmap_field_read(received_refclk->phy_pipe_cmn_ctrl1_0, &val);
1903 regmap_field_read(received_refclk->cmn_cdiag_refclk_ovrd_4, &cmn_val);
1904
1905 return val && !cmn_val;
1906}
1907
1908static const struct clk_ops cdns_torrent_received_refclk_ops = {
1909 .enable = cdns_torrent_received_refclk_enable,
1910 .disable = cdns_torrent_received_refclk_disable,
1911 .is_enabled = cdns_torrent_received_refclk_is_enabled,
1912};
1913
1914static int cdns_torrent_received_refclk_register(struct cdns_torrent_phy *cdns_phy)
1915{
1916 struct cdns_torrent_received_refclk *received_refclk;
1917 struct device *dev = cdns_phy->dev;
1918 struct clk_init_data *init;
1919 const char *parent_name;
1920 char clk_name[100];
1921 struct clk_hw *hw;
1922 struct clk *clk;
1923 int ret;
1924
1925 received_refclk = devm_kzalloc(dev, sizeof(*received_refclk), GFP_KERNEL);
1926 if (!received_refclk)
1927 return -ENOMEM;
1928
1929 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
1930 clk_names[CDNS_TORRENT_RECEIVED_REFCLK]);
1931
1932 clk = devm_clk_get_optional(dev, "phy_en_refclk");
1933 if (IS_ERR(clk)) {
1934 dev_err(dev, "No parent clock for received_refclk\n");
1935 return PTR_ERR(clk);
1936 }
1937
1938 init = &received_refclk->clk_data;
1939
1940 if (clk) {
1941 parent_name = __clk_get_name(clk);
1942 init->parent_names = &parent_name;
1943 init->num_parents = 1;
1944 }
1945 init->ops = &cdns_torrent_received_refclk_ops;
1946 init->flags = 0;
1947 init->name = clk_name;
1948
1949 received_refclk->phy_pipe_cmn_ctrl1_0 = cdns_phy->phy_pipe_cmn_ctrl1_0;
1950 received_refclk->cmn_cdiag_refclk_ovrd_4 = cdns_phy->cmn_cdiag_refclk_ovrd_4;
1951
1952 received_refclk->hw.init = init;
1953
1954 hw = &received_refclk->hw;
1955 ret = devm_clk_hw_register(dev, hw);
1956 if (ret)
1957 return ret;
1958
1959 cdns_phy->clk_hw_data->hws[CDNS_TORRENT_RECEIVED_REFCLK] = hw;
1960
1961 return 0;
1962}
1963
1964static int cdns_torrent_refclk_driver_enable(struct clk_hw *hw)
1965{
1966 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw);
1967
1968 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_6], 0);
1969 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_5], 1);
1970 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], 0);
1971
1972 return 0;
1973}
1974
1975static void cdns_torrent_refclk_driver_disable(struct clk_hw *hw)
1976{
1977 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw);
1978
1979 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], 1);
1980}
1981
1982static int cdns_torrent_refclk_driver_is_enabled(struct clk_hw *hw)
1983{
1984 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw);
1985 int val;
1986
1987 regmap_field_read(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], &val);
1988
1989 return !val;
1990}
1991
1992static u8 cdns_torrent_refclk_driver_get_parent(struct clk_hw *hw)
1993{
1994 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw);
1995 unsigned int val;
1996
1997 regmap_field_read(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], &val);
1998 return clk_mux_val_to_index(hw, cdns_torrent_refclk_driver_mux_table, 0, val);
1999}
2000
2001static int cdns_torrent_refclk_driver_set_parent(struct clk_hw *hw, u8 index)
2002{
2003 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw);
2004 unsigned int val;
2005
2006 val = cdns_torrent_refclk_driver_mux_table[index];
2007 return regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], val);
2008}
2009
2010static const struct clk_ops cdns_torrent_refclk_driver_ops = {
2011 .enable = cdns_torrent_refclk_driver_enable,
2012 .disable = cdns_torrent_refclk_driver_disable,
2013 .is_enabled = cdns_torrent_refclk_driver_is_enabled,
2014 .determine_rate = __clk_mux_determine_rate,
2015 .set_parent = cdns_torrent_refclk_driver_set_parent,
2016 .get_parent = cdns_torrent_refclk_driver_get_parent,
2017};
2018
2019static int cdns_torrent_refclk_driver_register(struct cdns_torrent_phy *cdns_phy)
2020{
2021 struct cdns_torrent_refclk_driver *refclk_driver;
2022 struct device *dev = cdns_phy->dev;
2023 struct regmap_field *field;
2024 struct clk_init_data *init;
2025 const char **parent_names;
2026 unsigned int num_parents;
2027 struct regmap *regmap;
2028 char clk_name[100];
2029 struct clk_hw *hw;
2030 int i, ret;
2031
2032 refclk_driver = devm_kzalloc(dev, sizeof(*refclk_driver), GFP_KERNEL);
2033 if (!refclk_driver)
2034 return -ENOMEM;
2035
2036 num_parents = ARRAY_SIZE(refclk_driver_parent_index);
2037 parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents), GFP_KERNEL);
2038 if (!parent_names)
2039 return -ENOMEM;
2040
2041 for (i = 0; i < num_parents; i++) {
2042 hw = cdns_phy->clk_hw_data->hws[refclk_driver_parent_index[i]];
2043 if (IS_ERR_OR_NULL(hw)) {
2044 dev_err(dev, "No parent clock for refclk driver clock\n");
2045 return IS_ERR(hw) ? PTR_ERR(hw) : -ENOENT;
2046 }
2047 parent_names[i] = clk_hw_get_name(hw);
2048 }
2049
2050 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
2051 clk_names[CDNS_TORRENT_REFCLK_DRIVER]);
2052
2053 init = &refclk_driver->clk_data;
2054
2055 init->ops = &cdns_torrent_refclk_driver_ops;
2056 init->flags = CLK_SET_RATE_NO_REPARENT;
2057 init->parent_names = parent_names;
2058 init->num_parents = num_parents;
2059 init->name = clk_name;
2060
2061 regmap = cdns_phy->regmap_common_cdb;
2062
2063 for (i = 0; i < REFCLK_OUT_NUM_CMN_CONFIG; i++) {
2064 field = devm_regmap_field_alloc(dev, regmap, refclk_out_cmn_cfg[i]);
2065 if (IS_ERR(field)) {
2066 dev_err(dev, "Refclk driver CMN reg field init failed\n");
2067 return PTR_ERR(field);
2068 }
2069 refclk_driver->cmn_fields[i] = field;
2070 }
2071
2072 /* Enable Derived reference clock as default */
2073 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], 1);
2074
2075 refclk_driver->hw.init = init;
2076
2077 hw = &refclk_driver->hw;
2078 ret = devm_clk_hw_register(dev, hw);
2079 if (ret)
2080 return ret;
2081
2082 cdns_phy->clk_hw_data->hws[CDNS_TORRENT_REFCLK_DRIVER] = hw;
2083
2084 return 0;
2085}
2086
2087static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base,
2088 u32 block_offset,
2089 u8 reg_offset_shift,
2090 const struct regmap_config *config)
2091{
2092 struct cdns_regmap_cdb_context *ctx;
2093
2094 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
2095 if (!ctx)
2096 return ERR_PTR(-ENOMEM);
2097
2098 ctx->dev = dev;
2099 ctx->base = base + block_offset;
2100 ctx->reg_offset_shift = reg_offset_shift;
2101
2102 return devm_regmap_init(dev, NULL, ctx, config);
2103}
2104
2105static int cdns_torrent_dp_regfield_init(struct cdns_torrent_phy *cdns_phy)
2106{
2107 struct device *dev = cdns_phy->dev;
2108 struct regmap_field *field;
2109 struct regmap *regmap;
2110
2111 regmap = cdns_phy->regmap_dptx_phy_reg;
2112 field = devm_regmap_field_alloc(dev, regmap, phy_reset_ctrl);
2113 if (IS_ERR(field)) {
2114 dev_err(dev, "PHY_RESET reg field init failed\n");
2115 return PTR_ERR(field);
2116 }
2117 cdns_phy->phy_reset_ctrl = field;
2118
2119 return 0;
2120}
2121
2122static int cdns_torrent_regfield_init(struct cdns_torrent_phy *cdns_phy)
2123{
2124 struct device *dev = cdns_phy->dev;
2125 struct regmap_field *field;
2126 struct regmap *regmap;
2127 int i;
2128
2129 regmap = cdns_phy->regmap_phy_pcs_common_cdb;
2130 field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg);
2131 if (IS_ERR(field)) {
2132 dev_err(dev, "PHY_PLL_CFG reg field init failed\n");
2133 return PTR_ERR(field);
2134 }
2135 cdns_phy->phy_pll_cfg = field;
2136
2137 regmap = cdns_phy->regmap_phy_pcs_common_cdb;
2138 field = devm_regmap_field_alloc(dev, regmap, phy_pipe_cmn_ctrl1_0);
2139 if (IS_ERR(field)) {
2140 dev_err(dev, "phy_pipe_cmn_ctrl1_0 reg field init failed\n");
2141 return PTR_ERR(field);
2142 }
2143 cdns_phy->phy_pipe_cmn_ctrl1_0 = field;
2144
2145 regmap = cdns_phy->regmap_common_cdb;
2146 field = devm_regmap_field_alloc(dev, regmap, cmn_cdiag_refclk_ovrd_4);
2147 if (IS_ERR(field)) {
2148 dev_err(dev, "cmn_cdiag_refclk_ovrd_4 reg field init failed\n");
2149 return PTR_ERR(field);
2150 }
2151 cdns_phy->cmn_cdiag_refclk_ovrd_4 = field;
2152
2153 regmap = cdns_phy->regmap_phy_pma_common_cdb;
2154 field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_1);
2155 if (IS_ERR(field)) {
2156 dev_err(dev, "PHY_PMA_CMN_CTRL1 reg field init failed\n");
2157 return PTR_ERR(field);
2158 }
2159 cdns_phy->phy_pma_cmn_ctrl_1 = field;
2160
2161 regmap = cdns_phy->regmap_phy_pma_common_cdb;
2162 field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_2);
2163 if (IS_ERR(field)) {
2164 dev_err(dev, "PHY_PMA_CMN_CTRL2 reg field init failed\n");
2165 return PTR_ERR(field);
2166 }
2167 cdns_phy->phy_pma_cmn_ctrl_2 = field;
2168
2169 regmap = cdns_phy->regmap_phy_pma_common_cdb;
2170 field = devm_regmap_field_alloc(dev, regmap, phy_pma_pll_raw_ctrl);
2171 if (IS_ERR(field)) {
2172 dev_err(dev, "PHY_PMA_PLL_RAW_CTRL reg field init failed\n");
2173 return PTR_ERR(field);
2174 }
2175 cdns_phy->phy_pma_pll_raw_ctrl = field;
2176
2177 for (i = 0; i < MAX_NUM_LANES; i++) {
2178 regmap = cdns_phy->regmap_phy_pcs_lane_cdb[i];
2179 field = devm_regmap_field_alloc(dev, regmap, phy_pcs_iso_link_ctrl_1);
2180 if (IS_ERR(field)) {
2181 dev_err(dev, "PHY_PCS_ISO_LINK_CTRL reg field init for ln %d failed\n", i);
2182 return PTR_ERR(field);
2183 }
2184 cdns_phy->phy_pcs_iso_link_ctrl_1[i] = field;
2185 }
2186
2187 return 0;
2188}
2189
2190static int cdns_torrent_dp_regmap_init(struct cdns_torrent_phy *cdns_phy)
2191{
2192 void __iomem *base = cdns_phy->base;
2193 struct device *dev = cdns_phy->dev;
2194 struct regmap *regmap;
2195 u8 reg_offset_shift;
2196 u32 block_offset;
2197
2198 reg_offset_shift = cdns_phy->init_data->reg_offset_shift;
2199
2200 block_offset = TORRENT_DPTX_PHY_OFFSET;
2201 regmap = cdns_regmap_init(dev, base, block_offset,
2202 reg_offset_shift,
2203 &cdns_torrent_dptx_phy_config);
2204 if (IS_ERR(regmap)) {
2205 dev_err(dev, "Failed to init DPTX PHY regmap\n");
2206 return PTR_ERR(regmap);
2207 }
2208 cdns_phy->regmap_dptx_phy_reg = regmap;
2209
2210 return 0;
2211}
2212
2213static int cdns_torrent_regmap_init(struct cdns_torrent_phy *cdns_phy)
2214{
2215 void __iomem *sd_base = cdns_phy->sd_base;
2216 u8 block_offset_shift, reg_offset_shift;
2217 struct device *dev = cdns_phy->dev;
2218 struct regmap *regmap;
2219 u32 block_offset;
2220 int i;
2221
2222 block_offset_shift = cdns_phy->init_data->block_offset_shift;
2223 reg_offset_shift = cdns_phy->init_data->reg_offset_shift;
2224
2225 for (i = 0; i < MAX_NUM_LANES; i++) {
2226 block_offset = TORRENT_TX_LANE_CDB_OFFSET(i, block_offset_shift,
2227 reg_offset_shift);
2228 regmap = cdns_regmap_init(dev, sd_base, block_offset,
2229 reg_offset_shift,
2230 &cdns_torrent_tx_lane_cdb_config[i]);
2231 if (IS_ERR(regmap)) {
2232 dev_err(dev, "Failed to init tx lane CDB regmap\n");
2233 return PTR_ERR(regmap);
2234 }
2235 cdns_phy->regmap_tx_lane_cdb[i] = regmap;
2236
2237 block_offset = TORRENT_RX_LANE_CDB_OFFSET(i, block_offset_shift,
2238 reg_offset_shift);
2239 regmap = cdns_regmap_init(dev, sd_base, block_offset,
2240 reg_offset_shift,
2241 &cdns_torrent_rx_lane_cdb_config[i]);
2242 if (IS_ERR(regmap)) {
2243 dev_err(dev, "Failed to init rx lane CDB regmap\n");
2244 return PTR_ERR(regmap);
2245 }
2246 cdns_phy->regmap_rx_lane_cdb[i] = regmap;
2247
2248 block_offset = TORRENT_PHY_PCS_LANE_CDB_OFFSET(i, block_offset_shift,
2249 reg_offset_shift);
2250 regmap = cdns_regmap_init(dev, sd_base, block_offset,
2251 reg_offset_shift,
2252 &cdns_torrent_phy_pcs_lane_cdb_config[i]);
2253 if (IS_ERR(regmap)) {
2254 dev_err(dev, "Failed to init PHY PCS lane CDB regmap\n");
2255 return PTR_ERR(regmap);
2256 }
2257 cdns_phy->regmap_phy_pcs_lane_cdb[i] = regmap;
2258 }
2259
2260 block_offset = TORRENT_COMMON_CDB_OFFSET;
2261 regmap = cdns_regmap_init(dev, sd_base, block_offset,
2262 reg_offset_shift,
2263 &cdns_torrent_common_cdb_config);
2264 if (IS_ERR(regmap)) {
2265 dev_err(dev, "Failed to init common CDB regmap\n");
2266 return PTR_ERR(regmap);
2267 }
2268 cdns_phy->regmap_common_cdb = regmap;
2269
2270 block_offset = TORRENT_PHY_PCS_COMMON_OFFSET(block_offset_shift);
2271 regmap = cdns_regmap_init(dev, sd_base, block_offset,
2272 reg_offset_shift,
2273 &cdns_torrent_phy_pcs_cmn_cdb_config);
2274 if (IS_ERR(regmap)) {
2275 dev_err(dev, "Failed to init PHY PCS common CDB regmap\n");
2276 return PTR_ERR(regmap);
2277 }
2278 cdns_phy->regmap_phy_pcs_common_cdb = regmap;
2279
2280 block_offset = TORRENT_PHY_PMA_COMMON_OFFSET(block_offset_shift);
2281 regmap = cdns_regmap_init(dev, sd_base, block_offset,
2282 reg_offset_shift,
2283 &cdns_torrent_phy_pma_cmn_cdb_config);
2284 if (IS_ERR(regmap)) {
2285 dev_err(dev, "Failed to init PHY PMA common CDB regmap\n");
2286 return PTR_ERR(regmap);
2287 }
2288 cdns_phy->regmap_phy_pma_common_cdb = regmap;
2289
2290 return 0;
2291}
2292
2293static int cdns_torrent_phy_init(struct phy *phy)
2294{
2295 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
2296 const struct cdns_torrent_data *init_data = cdns_phy->init_data;
2297 struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals;
2298 enum cdns_torrent_ref_clk ref_clk = cdns_phy->ref_clk_rate;
2299 struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals;
2300 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
2301 enum cdns_torrent_phy_type phy_type = inst->phy_type;
2302 enum cdns_torrent_ssc_mode ssc = inst->ssc_mode;
2303 struct cdns_torrent_vals *phy_pma_cmn_vals;
2304 struct cdns_torrent_vals *pcs_cmn_vals;
2305 struct cdns_reg_pairs *reg_pairs;
2306 struct regmap *regmap;
2307 u32 num_regs;
2308 int i, j;
2309
2310 if (cdns_phy->nsubnodes > 1) {
2311 if (phy_type == TYPE_DP)
2312 return cdns_torrent_dp_multilink_init(cdns_phy, inst, phy);
2313 return 0;
2314 }
2315
2316 /**
2317 * Spread spectrum generation is not required or supported
2318 * for SGMII/QSGMII/USXGMII
2319 */
2320 if (phy_type == TYPE_SGMII || phy_type == TYPE_QSGMII || phy_type == TYPE_USXGMII)
2321 ssc = NO_SSC;
2322
2323 /* PHY configuration specific registers for single link */
2324 link_cmn_vals = cdns_torrent_get_tbl_vals(&init_data->link_cmn_vals_tbl,
2325 CLK_ANY, CLK_ANY,
2326 phy_type, TYPE_NONE,
2327 ANY_SSC);
2328 if (link_cmn_vals) {
2329 reg_pairs = link_cmn_vals->reg_pairs;
2330 num_regs = link_cmn_vals->num_regs;
2331 regmap = cdns_phy->regmap_common_cdb;
2332
2333 /**
2334 * First array value in link_cmn_vals must be of
2335 * PHY_PLL_CFG register
2336 */
2337 regmap_field_write(cdns_phy->phy_pll_cfg, reg_pairs[0].val);
2338
2339 for (i = 1; i < num_regs; i++)
2340 regmap_write(regmap, reg_pairs[i].off,
2341 reg_pairs[i].val);
2342 }
2343
2344 xcvr_diag_vals = cdns_torrent_get_tbl_vals(&init_data->xcvr_diag_vals_tbl,
2345 CLK_ANY, CLK_ANY,
2346 phy_type, TYPE_NONE,
2347 ANY_SSC);
2348 if (xcvr_diag_vals) {
2349 reg_pairs = xcvr_diag_vals->reg_pairs;
2350 num_regs = xcvr_diag_vals->num_regs;
2351 for (i = 0; i < inst->num_lanes; i++) {
2352 regmap = cdns_phy->regmap_tx_lane_cdb[i + inst->mlane];
2353 for (j = 0; j < num_regs; j++)
2354 regmap_write(regmap, reg_pairs[j].off,
2355 reg_pairs[j].val);
2356 }
2357 }
2358
2359 /* PHY PCS common registers configurations */
2360 pcs_cmn_vals = cdns_torrent_get_tbl_vals(&init_data->pcs_cmn_vals_tbl,
2361 CLK_ANY, CLK_ANY,
2362 phy_type, TYPE_NONE,
2363 ANY_SSC);
2364 if (pcs_cmn_vals) {
2365 reg_pairs = pcs_cmn_vals->reg_pairs;
2366 num_regs = pcs_cmn_vals->num_regs;
2367 regmap = cdns_phy->regmap_phy_pcs_common_cdb;
2368 for (i = 0; i < num_regs; i++)
2369 regmap_write(regmap, reg_pairs[i].off,
2370 reg_pairs[i].val);
2371 }
2372
2373 /* PHY PMA common registers configurations */
2374 phy_pma_cmn_vals = cdns_torrent_get_tbl_vals(&init_data->phy_pma_cmn_vals_tbl,
2375 CLK_ANY, CLK_ANY,
2376 phy_type, TYPE_NONE,
2377 ANY_SSC);
2378 if (phy_pma_cmn_vals) {
2379 reg_pairs = phy_pma_cmn_vals->reg_pairs;
2380 num_regs = phy_pma_cmn_vals->num_regs;
2381 regmap = cdns_phy->regmap_phy_pma_common_cdb;
2382 for (i = 0; i < num_regs; i++)
2383 regmap_write(regmap, reg_pairs[i].off,
2384 reg_pairs[i].val);
2385 }
2386
2387 /* PMA common registers configurations */
2388 cmn_vals = cdns_torrent_get_tbl_vals(&init_data->cmn_vals_tbl,
2389 ref_clk, ref_clk,
2390 phy_type, TYPE_NONE,
2391 ssc);
2392 if (cmn_vals) {
2393 reg_pairs = cmn_vals->reg_pairs;
2394 num_regs = cmn_vals->num_regs;
2395 regmap = cdns_phy->regmap_common_cdb;
2396 for (i = 0; i < num_regs; i++)
2397 regmap_write(regmap, reg_pairs[i].off,
2398 reg_pairs[i].val);
2399 }
2400
2401 /* PMA TX lane registers configurations */
2402 tx_ln_vals = cdns_torrent_get_tbl_vals(&init_data->tx_ln_vals_tbl,
2403 ref_clk, ref_clk,
2404 phy_type, TYPE_NONE,
2405 ssc);
2406 if (tx_ln_vals) {
2407 reg_pairs = tx_ln_vals->reg_pairs;
2408 num_regs = tx_ln_vals->num_regs;
2409 for (i = 0; i < inst->num_lanes; i++) {
2410 regmap = cdns_phy->regmap_tx_lane_cdb[i + inst->mlane];
2411 for (j = 0; j < num_regs; j++)
2412 regmap_write(regmap, reg_pairs[j].off,
2413 reg_pairs[j].val);
2414 }
2415 }
2416
2417 /* PMA RX lane registers configurations */
2418 rx_ln_vals = cdns_torrent_get_tbl_vals(&init_data->rx_ln_vals_tbl,
2419 ref_clk, ref_clk,
2420 phy_type, TYPE_NONE,
2421 ssc);
2422 if (rx_ln_vals) {
2423 reg_pairs = rx_ln_vals->reg_pairs;
2424 num_regs = rx_ln_vals->num_regs;
2425 for (i = 0; i < inst->num_lanes; i++) {
2426 regmap = cdns_phy->regmap_rx_lane_cdb[i + inst->mlane];
2427 for (j = 0; j < num_regs; j++)
2428 regmap_write(regmap, reg_pairs[j].off,
2429 reg_pairs[j].val);
2430 }
2431 }
2432
2433 if (phy_type == TYPE_DP)
2434 return cdns_torrent_dp_init(phy);
2435
2436 return 0;
2437}
2438
2439static const struct phy_ops cdns_torrent_phy_ops = {
2440 .init = cdns_torrent_phy_init,
2441 .configure = cdns_torrent_dp_configure,
2442 .power_on = cdns_torrent_phy_on,
2443 .power_off = cdns_torrent_phy_off,
2444 .owner = THIS_MODULE,
2445};
2446
2447static int cdns_torrent_noop_phy_on(struct phy *phy)
2448{
2449 /* Give 5ms to 10ms delay for the PIPE clock to be stable */
2450 usleep_range(5000, 10000);
2451
2452 return 0;
2453}
2454
2455static const struct phy_ops noop_ops = {
2456 .power_on = cdns_torrent_noop_phy_on,
2457 .owner = THIS_MODULE,
2458};
2459
2460static
2461int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy)
2462{
2463 const struct cdns_torrent_data *init_data = cdns_phy->init_data;
2464 struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals;
2465 enum cdns_torrent_ref_clk ref_clk1 = cdns_phy->ref_clk1_rate;
2466 enum cdns_torrent_ref_clk ref_clk = cdns_phy->ref_clk_rate;
2467 struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals;
2468 enum cdns_torrent_phy_type phy_t1, phy_t2;
2469 struct cdns_torrent_vals *phy_pma_cmn_vals;
2470 struct cdns_torrent_vals *pcs_cmn_vals;
2471 int i, j, node, mlane, num_lanes, ret;
2472 struct cdns_reg_pairs *reg_pairs;
2473 enum cdns_torrent_ssc_mode ssc;
2474 struct regmap *regmap;
2475 u32 num_regs;
2476
2477 /* Maximum 2 links (subnodes) are supported */
2478 if (cdns_phy->nsubnodes != 2)
2479 return -EINVAL;
2480
2481 phy_t1 = cdns_phy->phys[0].phy_type;
2482 phy_t2 = cdns_phy->phys[1].phy_type;
2483
2484 /**
2485 * First configure the PHY for first link with phy_t1. Get the array
2486 * values as [phy_t1][phy_t2][ssc].
2487 */
2488 for (node = 0; node < cdns_phy->nsubnodes; node++) {
2489 if (node == 1) {
2490 /**
2491 * If first link with phy_t1 is configured, then
2492 * configure the PHY for second link with phy_t2.
2493 * Get the array values as [phy_t2][phy_t1][ssc].
2494 */
2495 swap(phy_t1, phy_t2);
2496 swap(ref_clk, ref_clk1);
2497 }
2498
2499 mlane = cdns_phy->phys[node].mlane;
2500 ssc = cdns_phy->phys[node].ssc_mode;
2501 num_lanes = cdns_phy->phys[node].num_lanes;
2502
2503 /**
2504 * PHY configuration specific registers:
2505 * link_cmn_vals depend on combination of PHY types being
2506 * configured and are common for both PHY types, so array
2507 * values should be same for [phy_t1][phy_t2][ssc] and
2508 * [phy_t2][phy_t1][ssc].
2509 * xcvr_diag_vals also depend on combination of PHY types
2510 * being configured, but these can be different for particular
2511 * PHY type and are per lane.
2512 */
2513 link_cmn_vals = cdns_torrent_get_tbl_vals(&init_data->link_cmn_vals_tbl,
2514 CLK_ANY, CLK_ANY,
2515 phy_t1, phy_t2, ANY_SSC);
2516 if (link_cmn_vals) {
2517 reg_pairs = link_cmn_vals->reg_pairs;
2518 num_regs = link_cmn_vals->num_regs;
2519 regmap = cdns_phy->regmap_common_cdb;
2520
2521 /**
2522 * First array value in link_cmn_vals must be of
2523 * PHY_PLL_CFG register
2524 */
2525 regmap_field_write(cdns_phy->phy_pll_cfg,
2526 reg_pairs[0].val);
2527
2528 for (i = 1; i < num_regs; i++)
2529 regmap_write(regmap, reg_pairs[i].off,
2530 reg_pairs[i].val);
2531 }
2532
2533 xcvr_diag_vals = cdns_torrent_get_tbl_vals(&init_data->xcvr_diag_vals_tbl,
2534 CLK_ANY, CLK_ANY,
2535 phy_t1, phy_t2, ANY_SSC);
2536 if (xcvr_diag_vals) {
2537 reg_pairs = xcvr_diag_vals->reg_pairs;
2538 num_regs = xcvr_diag_vals->num_regs;
2539 for (i = 0; i < num_lanes; i++) {
2540 regmap = cdns_phy->regmap_tx_lane_cdb[i + mlane];
2541 for (j = 0; j < num_regs; j++)
2542 regmap_write(regmap, reg_pairs[j].off,
2543 reg_pairs[j].val);
2544 }
2545 }
2546
2547 /* PHY PCS common registers configurations */
2548 pcs_cmn_vals = cdns_torrent_get_tbl_vals(&init_data->pcs_cmn_vals_tbl,
2549 CLK_ANY, CLK_ANY,
2550 phy_t1, phy_t2, ANY_SSC);
2551 if (pcs_cmn_vals) {
2552 reg_pairs = pcs_cmn_vals->reg_pairs;
2553 num_regs = pcs_cmn_vals->num_regs;
2554 regmap = cdns_phy->regmap_phy_pcs_common_cdb;
2555 for (i = 0; i < num_regs; i++)
2556 regmap_write(regmap, reg_pairs[i].off,
2557 reg_pairs[i].val);
2558 }
2559
2560 /* PHY PMA common registers configurations */
2561 phy_pma_cmn_vals = cdns_torrent_get_tbl_vals(&init_data->phy_pma_cmn_vals_tbl,
2562 CLK_ANY, CLK_ANY,
2563 phy_t1, phy_t2, ANY_SSC);
2564 if (phy_pma_cmn_vals) {
2565 reg_pairs = phy_pma_cmn_vals->reg_pairs;
2566 num_regs = phy_pma_cmn_vals->num_regs;
2567 regmap = cdns_phy->regmap_phy_pma_common_cdb;
2568 for (i = 0; i < num_regs; i++)
2569 regmap_write(regmap, reg_pairs[i].off,
2570 reg_pairs[i].val);
2571 }
2572
2573 /* PMA common registers configurations */
2574 cmn_vals = cdns_torrent_get_tbl_vals(&init_data->cmn_vals_tbl,
2575 ref_clk, ref_clk1,
2576 phy_t1, phy_t2, ssc);
2577 if (cmn_vals) {
2578 reg_pairs = cmn_vals->reg_pairs;
2579 num_regs = cmn_vals->num_regs;
2580 regmap = cdns_phy->regmap_common_cdb;
2581 for (i = 0; i < num_regs; i++)
2582 regmap_write(regmap, reg_pairs[i].off,
2583 reg_pairs[i].val);
2584 }
2585
2586 /* PMA TX lane registers configurations */
2587 tx_ln_vals = cdns_torrent_get_tbl_vals(&init_data->tx_ln_vals_tbl,
2588 ref_clk, ref_clk1,
2589 phy_t1, phy_t2, ssc);
2590 if (tx_ln_vals) {
2591 reg_pairs = tx_ln_vals->reg_pairs;
2592 num_regs = tx_ln_vals->num_regs;
2593 for (i = 0; i < num_lanes; i++) {
2594 regmap = cdns_phy->regmap_tx_lane_cdb[i + mlane];
2595 for (j = 0; j < num_regs; j++)
2596 regmap_write(regmap, reg_pairs[j].off,
2597 reg_pairs[j].val);
2598 }
2599 }
2600
2601 /* PMA RX lane registers configurations */
2602 rx_ln_vals = cdns_torrent_get_tbl_vals(&init_data->rx_ln_vals_tbl,
2603 ref_clk, ref_clk1,
2604 phy_t1, phy_t2, ssc);
2605 if (rx_ln_vals) {
2606 reg_pairs = rx_ln_vals->reg_pairs;
2607 num_regs = rx_ln_vals->num_regs;
2608 for (i = 0; i < num_lanes; i++) {
2609 regmap = cdns_phy->regmap_rx_lane_cdb[i + mlane];
2610 for (j = 0; j < num_regs; j++)
2611 regmap_write(regmap, reg_pairs[j].off,
2612 reg_pairs[j].val);
2613 }
2614 }
2615
2616 if (phy_t1 == TYPE_DP) {
2617 ret = cdns_torrent_dp_get_pll(cdns_phy, phy_t2);
2618 if (ret)
2619 return ret;
2620 }
2621
2622 reset_control_deassert(cdns_phy->phys[node].lnk_rst);
2623 }
2624
2625 /* Take the PHY out of reset */
2626 ret = reset_control_deassert(cdns_phy->phy_rst);
2627 if (ret)
2628 return ret;
2629
2630 return 0;
2631}
2632
2633static void cdns_torrent_clk_cleanup(struct cdns_torrent_phy *cdns_phy)
2634{
2635 struct device *dev = cdns_phy->dev;
2636
2637 of_clk_del_provider(dev->of_node);
2638}
2639
2640static int cdns_torrent_clk_register(struct cdns_torrent_phy *cdns_phy)
2641{
2642 struct device *dev = cdns_phy->dev;
2643 struct device_node *node = dev->of_node;
2644 struct clk_hw_onecell_data *data;
2645 int ret;
2646
2647 data = devm_kzalloc(dev, struct_size(data, hws, CDNS_TORRENT_OUTPUT_CLOCKS), GFP_KERNEL);
2648 if (!data)
2649 return -ENOMEM;
2650
2651 data->num = CDNS_TORRENT_OUTPUT_CLOCKS;
2652 cdns_phy->clk_hw_data = data;
2653
2654 ret = cdns_torrent_derived_refclk_register(cdns_phy);
2655 if (ret) {
2656 dev_err(dev, "failed to register derived refclk\n");
2657 return ret;
2658 }
2659
2660 ret = cdns_torrent_received_refclk_register(cdns_phy);
2661 if (ret) {
2662 dev_err(dev, "failed to register received refclk\n");
2663 return ret;
2664 }
2665
2666 ret = cdns_torrent_refclk_driver_register(cdns_phy);
2667 if (ret) {
2668 dev_err(dev, "failed to register refclk driver\n");
2669 return ret;
2670 }
2671
2672 ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, data);
2673 if (ret) {
2674 dev_err(dev, "Failed to add clock provider: %s\n", node->name);
2675 return ret;
2676 }
2677
2678 return 0;
2679}
2680
2681static int cdns_torrent_reset(struct cdns_torrent_phy *cdns_phy)
2682{
2683 struct device *dev = cdns_phy->dev;
2684
2685 cdns_phy->phy_rst = devm_reset_control_get_exclusive_by_index(dev, 0);
2686 if (IS_ERR(cdns_phy->phy_rst)) {
2687 dev_err(dev, "%s: failed to get reset\n",
2688 dev->of_node->full_name);
2689 return PTR_ERR(cdns_phy->phy_rst);
2690 }
2691
2692 cdns_phy->apb_rst = devm_reset_control_get_optional_exclusive(dev, "torrent_apb");
2693 if (IS_ERR(cdns_phy->apb_rst)) {
2694 dev_err(dev, "%s: failed to get apb reset\n",
2695 dev->of_node->full_name);
2696 return PTR_ERR(cdns_phy->apb_rst);
2697 }
2698
2699 return 0;
2700}
2701
2702static int cdns_torrent_clk(struct cdns_torrent_phy *cdns_phy)
2703{
2704 struct device *dev = cdns_phy->dev;
2705 unsigned long ref_clk1_rate;
2706 unsigned long ref_clk_rate;
2707 int ret;
2708
2709 /* refclk: Input reference clock for PLL0 */
2710 cdns_phy->clk = devm_clk_get(dev, "refclk");
2711 if (IS_ERR(cdns_phy->clk)) {
2712 dev_err(dev, "phy ref clock not found\n");
2713 return PTR_ERR(cdns_phy->clk);
2714 }
2715
2716 ret = clk_prepare_enable(cdns_phy->clk);
2717 if (ret) {
2718 dev_err(cdns_phy->dev, "Failed to prepare ref clock: %d\n", ret);
2719 return ret;
2720 }
2721
2722 ref_clk_rate = clk_get_rate(cdns_phy->clk);
2723 if (!ref_clk_rate) {
2724 dev_err(cdns_phy->dev, "Failed to get ref clock rate\n");
2725 ret = -EINVAL;
2726 goto disable_clk;
2727 }
2728
2729 switch (ref_clk_rate) {
2730 case REF_CLK_19_2MHZ:
2731 cdns_phy->ref_clk_rate = CLK_19_2_MHZ;
2732 break;
2733 case REF_CLK_25MHZ:
2734 cdns_phy->ref_clk_rate = CLK_25_MHZ;
2735 break;
2736 case REF_CLK_100MHZ:
2737 cdns_phy->ref_clk_rate = CLK_100_MHZ;
2738 break;
2739 case REF_CLK_156_25MHZ:
2740 cdns_phy->ref_clk_rate = CLK_156_25_MHZ;
2741 break;
2742 default:
2743 dev_err(cdns_phy->dev, "Invalid ref clock rate\n");
2744 ret = -EINVAL;
2745 goto disable_clk;
2746 }
2747
2748 /* refclk1: Input reference clock for PLL1 */
2749 cdns_phy->clk1 = devm_clk_get_optional(dev, "pll1_refclk");
2750 if (IS_ERR(cdns_phy->clk1)) {
2751 dev_err(dev, "phy PLL1 ref clock not found\n");
2752 ret = PTR_ERR(cdns_phy->clk1);
2753 goto disable_clk;
2754 }
2755
2756 if (cdns_phy->clk1) {
2757 ret = clk_prepare_enable(cdns_phy->clk1);
2758 if (ret) {
2759 dev_err(cdns_phy->dev, "Failed to prepare PLL1 ref clock: %d\n", ret);
2760 goto disable_clk;
2761 }
2762
2763 ref_clk1_rate = clk_get_rate(cdns_phy->clk1);
2764 if (!ref_clk1_rate) {
2765 dev_err(cdns_phy->dev, "Failed to get PLL1 ref clock rate\n");
2766 ret = -EINVAL;
2767 goto disable_clk1;
2768 }
2769
2770 switch (ref_clk1_rate) {
2771 case REF_CLK_19_2MHZ:
2772 cdns_phy->ref_clk1_rate = CLK_19_2_MHZ;
2773 break;
2774 case REF_CLK_25MHZ:
2775 cdns_phy->ref_clk1_rate = CLK_25_MHZ;
2776 break;
2777 case REF_CLK_100MHZ:
2778 cdns_phy->ref_clk1_rate = CLK_100_MHZ;
2779 break;
2780 case REF_CLK_156_25MHZ:
2781 cdns_phy->ref_clk1_rate = CLK_156_25_MHZ;
2782 break;
2783 default:
2784 dev_err(cdns_phy->dev, "Invalid PLL1 ref clock rate\n");
2785 ret = -EINVAL;
2786 goto disable_clk1;
2787 }
2788 } else {
2789 cdns_phy->ref_clk1_rate = cdns_phy->ref_clk_rate;
2790 }
2791
2792 return 0;
2793
2794disable_clk1:
2795 clk_disable_unprepare(cdns_phy->clk1);
2796disable_clk:
2797 clk_disable_unprepare(cdns_phy->clk);
2798 return ret;
2799}
2800
2801static int cdns_torrent_phy_probe(struct platform_device *pdev)
2802{
2803 struct cdns_torrent_phy *cdns_phy;
2804 struct device *dev = &pdev->dev;
2805 struct phy_provider *phy_provider;
2806 const struct cdns_torrent_data *data;
2807 struct device_node *child;
2808 int ret, subnodes, node = 0, i;
2809 u32 total_num_lanes = 0;
2810 int already_configured;
2811 u8 init_dp_regmap = 0;
2812 u32 phy_type;
2813
2814 /* Get init data for this PHY */
2815 data = of_device_get_match_data(dev);
2816 if (!data)
2817 return -EINVAL;
2818
2819 cdns_phy = devm_kzalloc(dev, sizeof(*cdns_phy), GFP_KERNEL);
2820 if (!cdns_phy)
2821 return -ENOMEM;
2822
2823 dev_set_drvdata(dev, cdns_phy);
2824 cdns_phy->dev = dev;
2825 cdns_phy->init_data = data;
2826
2827 cdns_phy->sd_base = devm_platform_ioremap_resource(pdev, 0);
2828 if (IS_ERR(cdns_phy->sd_base))
2829 return PTR_ERR(cdns_phy->sd_base);
2830
2831 subnodes = of_get_available_child_count(dev->of_node);
2832 if (subnodes == 0) {
2833 dev_err(dev, "No available link subnodes found\n");
2834 return -EINVAL;
2835 }
2836
2837 ret = cdns_torrent_regmap_init(cdns_phy);
2838 if (ret)
2839 return ret;
2840
2841 ret = cdns_torrent_regfield_init(cdns_phy);
2842 if (ret)
2843 return ret;
2844
2845 ret = cdns_torrent_clk_register(cdns_phy);
2846 if (ret)
2847 return ret;
2848
2849 regmap_field_read(cdns_phy->phy_pma_cmn_ctrl_1, &already_configured);
2850
2851 if (!already_configured) {
2852 ret = cdns_torrent_reset(cdns_phy);
2853 if (ret)
2854 goto clk_cleanup;
2855
2856 ret = cdns_torrent_clk(cdns_phy);
2857 if (ret)
2858 goto clk_cleanup;
2859
2860 /* Enable APB */
2861 reset_control_deassert(cdns_phy->apb_rst);
2862 }
2863
2864 for_each_available_child_of_node(dev->of_node, child) {
2865 struct phy *gphy;
2866
2867 /* PHY subnode name must be 'phy'. */
2868 if (!(of_node_name_eq(child, "phy")))
2869 continue;
2870
2871 cdns_phy->phys[node].lnk_rst =
2872 of_reset_control_array_get_exclusive(child);
2873 if (IS_ERR(cdns_phy->phys[node].lnk_rst)) {
2874 dev_err(dev, "%s: failed to get reset\n",
2875 child->full_name);
2876 ret = PTR_ERR(cdns_phy->phys[node].lnk_rst);
2877 goto put_lnk_rst;
2878 }
2879
2880 if (of_property_read_u32(child, "reg",
2881 &cdns_phy->phys[node].mlane)) {
2882 dev_err(dev, "%s: No \"reg\"-property.\n",
2883 child->full_name);
2884 ret = -EINVAL;
2885 goto put_child;
2886 }
2887
2888 if (of_property_read_u32(child, "cdns,phy-type", &phy_type)) {
2889 dev_err(dev, "%s: No \"cdns,phy-type\"-property.\n",
2890 child->full_name);
2891 ret = -EINVAL;
2892 goto put_child;
2893 }
2894
2895 switch (phy_type) {
2896 case PHY_TYPE_PCIE:
2897 cdns_phy->phys[node].phy_type = TYPE_PCIE;
2898 break;
2899 case PHY_TYPE_DP:
2900 cdns_phy->phys[node].phy_type = TYPE_DP;
2901 break;
2902 case PHY_TYPE_SGMII:
2903 cdns_phy->phys[node].phy_type = TYPE_SGMII;
2904 break;
2905 case PHY_TYPE_QSGMII:
2906 cdns_phy->phys[node].phy_type = TYPE_QSGMII;
2907 break;
2908 case PHY_TYPE_USB3:
2909 cdns_phy->phys[node].phy_type = TYPE_USB;
2910 break;
2911 case PHY_TYPE_USXGMII:
2912 cdns_phy->phys[node].phy_type = TYPE_USXGMII;
2913 break;
2914 default:
2915 dev_err(dev, "Unsupported protocol\n");
2916 ret = -EINVAL;
2917 goto put_child;
2918 }
2919
2920 if (of_property_read_u32(child, "cdns,num-lanes",
2921 &cdns_phy->phys[node].num_lanes)) {
2922 dev_err(dev, "%s: No \"cdns,num-lanes\"-property.\n",
2923 child->full_name);
2924 ret = -EINVAL;
2925 goto put_child;
2926 }
2927
2928 total_num_lanes += cdns_phy->phys[node].num_lanes;
2929
2930 /* Get SSC mode */
2931 cdns_phy->phys[node].ssc_mode = NO_SSC;
2932 of_property_read_u32(child, "cdns,ssc-mode",
2933 &cdns_phy->phys[node].ssc_mode);
2934
2935 if (!already_configured)
2936 gphy = devm_phy_create(dev, child, &cdns_torrent_phy_ops);
2937 else
2938 gphy = devm_phy_create(dev, child, &noop_ops);
2939 if (IS_ERR(gphy)) {
2940 ret = PTR_ERR(gphy);
2941 goto put_child;
2942 }
2943
2944 if (cdns_phy->phys[node].phy_type == TYPE_DP) {
2945 switch (cdns_phy->phys[node].num_lanes) {
2946 case 1:
2947 case 2:
2948 case 4:
2949 /* valid number of lanes */
2950 break;
2951 default:
2952 dev_err(dev, "unsupported number of lanes: %d\n",
2953 cdns_phy->phys[node].num_lanes);
2954 ret = -EINVAL;
2955 goto put_child;
2956 }
2957
2958 cdns_phy->max_bit_rate = DEFAULT_MAX_BIT_RATE;
2959 of_property_read_u32(child, "cdns,max-bit-rate",
2960 &cdns_phy->max_bit_rate);
2961
2962 switch (cdns_phy->max_bit_rate) {
2963 case 1620:
2964 case 2160:
2965 case 2430:
2966 case 2700:
2967 case 3240:
2968 case 4320:
2969 case 5400:
2970 case 8100:
2971 /* valid bit rate */
2972 break;
2973 default:
2974 dev_err(dev, "unsupported max bit rate: %dMbps\n",
2975 cdns_phy->max_bit_rate);
2976 ret = -EINVAL;
2977 goto put_child;
2978 }
2979
2980 /* DPTX registers */
2981 cdns_phy->base = devm_platform_ioremap_resource(pdev, 1);
2982 if (IS_ERR(cdns_phy->base)) {
2983 ret = PTR_ERR(cdns_phy->base);
2984 goto put_child;
2985 }
2986
2987 if (!init_dp_regmap) {
2988 ret = cdns_torrent_dp_regmap_init(cdns_phy);
2989 if (ret)
2990 goto put_child;
2991
2992 ret = cdns_torrent_dp_regfield_init(cdns_phy);
2993 if (ret)
2994 goto put_child;
2995
2996 init_dp_regmap++;
2997 }
2998
2999 dev_dbg(dev, "DP max bit rate %d.%03d Gbps\n",
3000 cdns_phy->max_bit_rate / 1000,
3001 cdns_phy->max_bit_rate % 1000);
3002
3003 gphy->attrs.bus_width = cdns_phy->phys[node].num_lanes;
3004 gphy->attrs.max_link_rate = cdns_phy->max_bit_rate;
3005 gphy->attrs.mode = PHY_MODE_DP;
3006 }
3007
3008 cdns_phy->phys[node].phy = gphy;
3009 phy_set_drvdata(gphy, &cdns_phy->phys[node]);
3010
3011 node++;
3012 }
3013 cdns_phy->nsubnodes = node;
3014
3015 if (total_num_lanes > MAX_NUM_LANES) {
3016 dev_err(dev, "Invalid lane configuration\n");
3017 ret = -EINVAL;
3018 goto put_lnk_rst;
3019 }
3020
3021 if (cdns_phy->nsubnodes > 1 && !already_configured) {
3022 ret = cdns_torrent_phy_configure_multilink(cdns_phy);
3023 if (ret)
3024 goto put_lnk_rst;
3025 }
3026
3027 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
3028 if (IS_ERR(phy_provider)) {
3029 ret = PTR_ERR(phy_provider);
3030 goto put_lnk_rst;
3031 }
3032
3033 if (cdns_phy->nsubnodes > 1)
3034 dev_dbg(dev, "Multi-link: %s (%d lanes) & %s (%d lanes)",
3035 cdns_torrent_get_phy_type(cdns_phy->phys[0].phy_type),
3036 cdns_phy->phys[0].num_lanes,
3037 cdns_torrent_get_phy_type(cdns_phy->phys[1].phy_type),
3038 cdns_phy->phys[1].num_lanes);
3039 else
3040 dev_dbg(dev, "Single link: %s (%d lanes)",
3041 cdns_torrent_get_phy_type(cdns_phy->phys[0].phy_type),
3042 cdns_phy->phys[0].num_lanes);
3043
3044 return 0;
3045
3046put_child:
3047 node++;
3048put_lnk_rst:
3049 for (i = 0; i < node; i++)
3050 reset_control_put(cdns_phy->phys[i].lnk_rst);
3051 of_node_put(child);
3052 reset_control_assert(cdns_phy->apb_rst);
3053 clk_disable_unprepare(cdns_phy->clk1);
3054 clk_disable_unprepare(cdns_phy->clk);
3055clk_cleanup:
3056 cdns_torrent_clk_cleanup(cdns_phy);
3057 return ret;
3058}
3059
3060static void cdns_torrent_phy_remove(struct platform_device *pdev)
3061{
3062 struct cdns_torrent_phy *cdns_phy = platform_get_drvdata(pdev);
3063 int i;
3064
3065 reset_control_assert(cdns_phy->phy_rst);
3066 reset_control_assert(cdns_phy->apb_rst);
3067 for (i = 0; i < cdns_phy->nsubnodes; i++) {
3068 reset_control_assert(cdns_phy->phys[i].lnk_rst);
3069 reset_control_put(cdns_phy->phys[i].lnk_rst);
3070 }
3071
3072 clk_disable_unprepare(cdns_phy->clk1);
3073 clk_disable_unprepare(cdns_phy->clk);
3074 cdns_torrent_clk_cleanup(cdns_phy);
3075}
3076
3077/* USB and DP link configuration */
3078static struct cdns_reg_pairs usb_dp_link_cmn_regs[] = {
3079 {0x0002, PHY_PLL_CFG},
3080 {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0}
3081};
3082
3083static struct cdns_reg_pairs usb_dp_xcvr_diag_ln_regs[] = {
3084 {0x0000, XCVR_DIAG_HSCLK_SEL},
3085 {0x0001, XCVR_DIAG_HSCLK_DIV},
3086 {0x0041, XCVR_DIAG_PLLDRC_CTRL}
3087};
3088
3089static struct cdns_reg_pairs dp_usb_xcvr_diag_ln_regs[] = {
3090 {0x0001, XCVR_DIAG_HSCLK_SEL},
3091 {0x0009, XCVR_DIAG_PLLDRC_CTRL}
3092};
3093
3094static struct cdns_torrent_vals usb_dp_link_cmn_vals = {
3095 .reg_pairs = usb_dp_link_cmn_regs,
3096 .num_regs = ARRAY_SIZE(usb_dp_link_cmn_regs),
3097};
3098
3099static struct cdns_torrent_vals usb_dp_xcvr_diag_ln_vals = {
3100 .reg_pairs = usb_dp_xcvr_diag_ln_regs,
3101 .num_regs = ARRAY_SIZE(usb_dp_xcvr_diag_ln_regs),
3102};
3103
3104static struct cdns_torrent_vals dp_usb_xcvr_diag_ln_vals = {
3105 .reg_pairs = dp_usb_xcvr_diag_ln_regs,
3106 .num_regs = ARRAY_SIZE(dp_usb_xcvr_diag_ln_regs),
3107};
3108
3109/* USXGMII and SGMII/QSGMII link configuration */
3110static struct cdns_reg_pairs usxgmii_sgmii_link_cmn_regs[] = {
3111 {0x0002, PHY_PLL_CFG},
3112 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M0},
3113 {0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0}
3114};
3115
3116static struct cdns_reg_pairs usxgmii_sgmii_xcvr_diag_ln_regs[] = {
3117 {0x0000, XCVR_DIAG_HSCLK_SEL},
3118 {0x0001, XCVR_DIAG_HSCLK_DIV},
3119 {0x0001, XCVR_DIAG_PLLDRC_CTRL}
3120};
3121
3122static struct cdns_reg_pairs sgmii_usxgmii_xcvr_diag_ln_regs[] = {
3123 {0x0111, XCVR_DIAG_HSCLK_SEL},
3124 {0x0103, XCVR_DIAG_HSCLK_DIV},
3125 {0x0A9B, XCVR_DIAG_PLLDRC_CTRL}
3126};
3127
3128static struct cdns_torrent_vals usxgmii_sgmii_link_cmn_vals = {
3129 .reg_pairs = usxgmii_sgmii_link_cmn_regs,
3130 .num_regs = ARRAY_SIZE(usxgmii_sgmii_link_cmn_regs),
3131};
3132
3133static struct cdns_torrent_vals usxgmii_sgmii_xcvr_diag_ln_vals = {
3134 .reg_pairs = usxgmii_sgmii_xcvr_diag_ln_regs,
3135 .num_regs = ARRAY_SIZE(usxgmii_sgmii_xcvr_diag_ln_regs),
3136};
3137
3138static struct cdns_torrent_vals sgmii_usxgmii_xcvr_diag_ln_vals = {
3139 .reg_pairs = sgmii_usxgmii_xcvr_diag_ln_regs,
3140 .num_regs = ARRAY_SIZE(sgmii_usxgmii_xcvr_diag_ln_regs),
3141};
3142
3143/* Multilink USXGMII, using PLL0, 156.25 MHz Ref clk, no SSC */
3144static struct cdns_reg_pairs ml_usxgmii_pll0_156_25_no_ssc_cmn_regs[] = {
3145 {0x0014, CMN_PLL0_DSM_FBH_OVRD_M0},
3146 {0x0005, CMN_PLL0_DSM_FBL_OVRD_M0},
3147 {0x061B, CMN_PLL0_VCOCAL_INIT_TMR},
3148 {0x0019, CMN_PLL0_VCOCAL_ITER_TMR},
3149 {0x1354, CMN_PLL0_VCOCAL_REFTIM_START},
3150 {0x1354, CMN_PLL0_VCOCAL_PLLCNT_START},
3151 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
3152 {0x0138, CMN_PLL0_LOCK_REFCNT_START},
3153 {0x0138, CMN_PLL0_LOCK_PLLCNT_START}
3154};
3155
3156static struct cdns_torrent_vals ml_usxgmii_pll0_156_25_no_ssc_cmn_vals = {
3157 .reg_pairs = ml_usxgmii_pll0_156_25_no_ssc_cmn_regs,
3158 .num_regs = ARRAY_SIZE(ml_usxgmii_pll0_156_25_no_ssc_cmn_regs),
3159};
3160
3161/* Multilink SGMII/QSGMII, using PLL1, 100 MHz Ref clk, no SSC */
3162static struct cdns_reg_pairs ml_sgmii_pll1_100_no_ssc_cmn_regs[] = {
3163 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
3164 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},
3165 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0},
3166 {0x0003, CMN_PLL1_VCOCAL_TCTRL},
3167 {0x007F, CMN_TXPUCAL_TUNE},
3168 {0x007F, CMN_TXPDCAL_TUNE}
3169};
3170
3171static struct cdns_torrent_vals ml_sgmii_pll1_100_no_ssc_cmn_vals = {
3172 .reg_pairs = ml_sgmii_pll1_100_no_ssc_cmn_regs,
3173 .num_regs = ARRAY_SIZE(ml_sgmii_pll1_100_no_ssc_cmn_regs),
3174};
3175
3176/* TI J7200, Multilink USXGMII, using PLL0, 156.25 MHz Ref clk, no SSC */
3177static struct cdns_reg_pairs j7200_ml_usxgmii_pll0_156_25_no_ssc_cmn_regs[] = {
3178 {0x0014, CMN_SSM_BIAS_TMR},
3179 {0x0028, CMN_PLLSM0_PLLPRE_TMR},
3180 {0x00A4, CMN_PLLSM0_PLLLOCK_TMR},
3181 {0x0062, CMN_BGCAL_INIT_TMR},
3182 {0x0062, CMN_BGCAL_ITER_TMR},
3183 {0x0014, CMN_IBCAL_INIT_TMR},
3184 {0x0018, CMN_TXPUCAL_INIT_TMR},
3185 {0x0005, CMN_TXPUCAL_ITER_TMR},
3186 {0x0018, CMN_TXPDCAL_INIT_TMR},
3187 {0x0005, CMN_TXPDCAL_ITER_TMR},
3188 {0x024A, CMN_RXCAL_INIT_TMR},
3189 {0x0005, CMN_RXCAL_ITER_TMR},
3190 {0x000B, CMN_SD_CAL_REFTIM_START},
3191 {0x0132, CMN_SD_CAL_PLLCNT_START},
3192 {0x0014, CMN_PLL0_DSM_FBH_OVRD_M0},
3193 {0x0005, CMN_PLL0_DSM_FBL_OVRD_M0},
3194 {0x061B, CMN_PLL0_VCOCAL_INIT_TMR},
3195 {0x0019, CMN_PLL0_VCOCAL_ITER_TMR},
3196 {0x1354, CMN_PLL0_VCOCAL_REFTIM_START},
3197 {0x1354, CMN_PLL0_VCOCAL_PLLCNT_START},
3198 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
3199 {0x0138, CMN_PLL0_LOCK_REFCNT_START},
3200 {0x0138, CMN_PLL0_LOCK_PLLCNT_START}
3201};
3202
3203static struct cdns_torrent_vals j7200_ml_usxgmii_pll0_156_25_no_ssc_cmn_vals = {
3204 .reg_pairs = j7200_ml_usxgmii_pll0_156_25_no_ssc_cmn_regs,
3205 .num_regs = ARRAY_SIZE(j7200_ml_usxgmii_pll0_156_25_no_ssc_cmn_regs),
3206};
3207
3208/* TI J7200, Multilink SGMII/QSGMII, using PLL1, 100 MHz Ref clk, no SSC */
3209static struct cdns_reg_pairs j7200_ml_sgmii_pll1_100_no_ssc_cmn_regs[] = {
3210 {0x0028, CMN_PLLSM1_PLLPRE_TMR},
3211 {0x00A4, CMN_PLLSM1_PLLLOCK_TMR},
3212 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
3213 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},
3214 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0},
3215 {0x0003, CMN_PLL1_VCOCAL_TCTRL},
3216 {0x007F, CMN_TXPUCAL_TUNE},
3217 {0x007F, CMN_TXPDCAL_TUNE}
3218};
3219
3220static struct cdns_torrent_vals j7200_ml_sgmii_pll1_100_no_ssc_cmn_vals = {
3221 .reg_pairs = j7200_ml_sgmii_pll1_100_no_ssc_cmn_regs,
3222 .num_regs = ARRAY_SIZE(j7200_ml_sgmii_pll1_100_no_ssc_cmn_regs),
3223};
3224
3225/* PCIe and USXGMII link configuration */
3226static struct cdns_reg_pairs pcie_usxgmii_link_cmn_regs[] = {
3227 {0x0003, PHY_PLL_CFG},
3228 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0},
3229 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1},
3230 {0x0400, CMN_PDIAG_PLL1_CLK_SEL_M0}
3231};
3232
3233static struct cdns_reg_pairs pcie_usxgmii_xcvr_diag_ln_regs[] = {
3234 {0x0000, XCVR_DIAG_HSCLK_SEL},
3235 {0x0001, XCVR_DIAG_HSCLK_DIV},
3236 {0x0012, XCVR_DIAG_PLLDRC_CTRL}
3237};
3238
3239static struct cdns_reg_pairs usxgmii_pcie_xcvr_diag_ln_regs[] = {
3240 {0x0011, XCVR_DIAG_HSCLK_SEL},
3241 {0x0001, XCVR_DIAG_HSCLK_DIV},
3242 {0x0089, XCVR_DIAG_PLLDRC_CTRL}
3243};
3244
3245static struct cdns_torrent_vals pcie_usxgmii_link_cmn_vals = {
3246 .reg_pairs = pcie_usxgmii_link_cmn_regs,
3247 .num_regs = ARRAY_SIZE(pcie_usxgmii_link_cmn_regs),
3248};
3249
3250static struct cdns_torrent_vals pcie_usxgmii_xcvr_diag_ln_vals = {
3251 .reg_pairs = pcie_usxgmii_xcvr_diag_ln_regs,
3252 .num_regs = ARRAY_SIZE(pcie_usxgmii_xcvr_diag_ln_regs),
3253};
3254
3255static struct cdns_torrent_vals usxgmii_pcie_xcvr_diag_ln_vals = {
3256 .reg_pairs = usxgmii_pcie_xcvr_diag_ln_regs,
3257 .num_regs = ARRAY_SIZE(usxgmii_pcie_xcvr_diag_ln_regs),
3258};
3259
3260/*
3261 * Multilink USXGMII, using PLL1, 156.25 MHz Ref clk, no SSC
3262 */
3263static struct cdns_reg_pairs ml_usxgmii_pll1_156_25_no_ssc_cmn_regs[] = {
3264 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
3265 {0x0014, CMN_PLL1_DSM_FBH_OVRD_M0},
3266 {0x0005, CMN_PLL1_DSM_FBL_OVRD_M0},
3267 {0x061B, CMN_PLL1_VCOCAL_INIT_TMR},
3268 {0x0019, CMN_PLL1_VCOCAL_ITER_TMR},
3269 {0x1354, CMN_PLL1_VCOCAL_REFTIM_START},
3270 {0x1354, CMN_PLL1_VCOCAL_PLLCNT_START},
3271 {0x0003, CMN_PLL1_VCOCAL_TCTRL},
3272 {0x0138, CMN_PLL1_LOCK_REFCNT_START},
3273 {0x0138, CMN_PLL1_LOCK_PLLCNT_START},
3274 {0x007F, CMN_TXPUCAL_TUNE},
3275 {0x007F, CMN_TXPDCAL_TUNE}
3276};
3277
3278static struct cdns_reg_pairs ml_usxgmii_156_25_no_ssc_tx_ln_regs[] = {
3279 {0x00F3, TX_PSC_A0},
3280 {0x04A2, TX_PSC_A2},
3281 {0x04A2, TX_PSC_A3 },
3282 {0x0000, TX_TXCC_CPOST_MULT_00},
3283 {0x0000, XCVR_DIAG_PSC_OVRD}
3284};
3285
3286static struct cdns_reg_pairs ml_usxgmii_156_25_no_ssc_rx_ln_regs[] = {
3287 {0x091D, RX_PSC_A0},
3288 {0x0900, RX_PSC_A2},
3289 {0x0100, RX_PSC_A3},
3290 {0x0030, RX_REE_SMGM_CTRL1},
3291 {0x03C7, RX_REE_GCSM1_EQENM_PH1},
3292 {0x01C7, RX_REE_GCSM1_EQENM_PH2},
3293 {0x0000, RX_DIAG_DFE_CTRL},
3294 {0x0019, RX_REE_TAP1_CLIP},
3295 {0x0019, RX_REE_TAP2TON_CLIP},
3296 {0x00B9, RX_DIAG_NQST_CTRL},
3297 {0x0C21, RX_DIAG_DFE_AMP_TUNE_2},
3298 {0x0002, RX_DIAG_DFE_AMP_TUNE_3},
3299 {0x0033, RX_DIAG_PI_RATE},
3300 {0x0001, RX_DIAG_ACYA},
3301 {0x018C, RX_CDRLF_CNFG}
3302};
3303
3304static struct cdns_torrent_vals ml_usxgmii_pll1_156_25_no_ssc_cmn_vals = {
3305 .reg_pairs = ml_usxgmii_pll1_156_25_no_ssc_cmn_regs,
3306 .num_regs = ARRAY_SIZE(ml_usxgmii_pll1_156_25_no_ssc_cmn_regs),
3307};
3308
3309static struct cdns_torrent_vals ml_usxgmii_156_25_no_ssc_tx_ln_vals = {
3310 .reg_pairs = ml_usxgmii_156_25_no_ssc_tx_ln_regs,
3311 .num_regs = ARRAY_SIZE(ml_usxgmii_156_25_no_ssc_tx_ln_regs),
3312};
3313
3314static struct cdns_torrent_vals ml_usxgmii_156_25_no_ssc_rx_ln_vals = {
3315 .reg_pairs = ml_usxgmii_156_25_no_ssc_rx_ln_regs,
3316 .num_regs = ARRAY_SIZE(ml_usxgmii_156_25_no_ssc_rx_ln_regs),
3317};
3318
3319/* TI USXGMII configuration: Enable cmn_refclk_rcv_out_en */
3320static struct cdns_reg_pairs ti_usxgmii_phy_pma_cmn_regs[] = {
3321 {0x0040, PHY_PMA_CMN_CTRL1},
3322};
3323
3324static struct cdns_torrent_vals ti_usxgmii_phy_pma_cmn_vals = {
3325 .reg_pairs = ti_usxgmii_phy_pma_cmn_regs,
3326 .num_regs = ARRAY_SIZE(ti_usxgmii_phy_pma_cmn_regs),
3327};
3328
3329/* Single USXGMII link configuration */
3330static struct cdns_reg_pairs sl_usxgmii_link_cmn_regs[] = {
3331 {0x0000, PHY_PLL_CFG},
3332 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M0}
3333};
3334
3335static struct cdns_reg_pairs sl_usxgmii_xcvr_diag_ln_regs[] = {
3336 {0x0000, XCVR_DIAG_HSCLK_SEL},
3337 {0x0001, XCVR_DIAG_HSCLK_DIV},
3338 {0x0001, XCVR_DIAG_PLLDRC_CTRL}
3339};
3340
3341static struct cdns_torrent_vals sl_usxgmii_link_cmn_vals = {
3342 .reg_pairs = sl_usxgmii_link_cmn_regs,
3343 .num_regs = ARRAY_SIZE(sl_usxgmii_link_cmn_regs),
3344};
3345
3346static struct cdns_torrent_vals sl_usxgmii_xcvr_diag_ln_vals = {
3347 .reg_pairs = sl_usxgmii_xcvr_diag_ln_regs,
3348 .num_regs = ARRAY_SIZE(sl_usxgmii_xcvr_diag_ln_regs),
3349};
3350
3351/* Single link USXGMII, 156.25 MHz Ref clk, no SSC */
3352static struct cdns_reg_pairs sl_usxgmii_156_25_no_ssc_cmn_regs[] = {
3353 {0x0014, CMN_SSM_BIAS_TMR},
3354 {0x0028, CMN_PLLSM0_PLLPRE_TMR},
3355 {0x00A4, CMN_PLLSM0_PLLLOCK_TMR},
3356 {0x0028, CMN_PLLSM1_PLLPRE_TMR},
3357 {0x00A4, CMN_PLLSM1_PLLLOCK_TMR},
3358 {0x0062, CMN_BGCAL_INIT_TMR},
3359 {0x0062, CMN_BGCAL_ITER_TMR},
3360 {0x0014, CMN_IBCAL_INIT_TMR},
3361 {0x0018, CMN_TXPUCAL_INIT_TMR},
3362 {0x0005, CMN_TXPUCAL_ITER_TMR},
3363 {0x0018, CMN_TXPDCAL_INIT_TMR},
3364 {0x0005, CMN_TXPDCAL_ITER_TMR},
3365 {0x024A, CMN_RXCAL_INIT_TMR},
3366 {0x0005, CMN_RXCAL_ITER_TMR},
3367 {0x000B, CMN_SD_CAL_REFTIM_START},
3368 {0x0132, CMN_SD_CAL_PLLCNT_START},
3369 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
3370 {0x0014, CMN_PLL0_DSM_FBH_OVRD_M0},
3371 {0x0014, CMN_PLL1_DSM_FBH_OVRD_M0},
3372 {0x0005, CMN_PLL0_DSM_FBL_OVRD_M0},
3373 {0x0005, CMN_PLL1_DSM_FBL_OVRD_M0},
3374 {0x061B, CMN_PLL0_VCOCAL_INIT_TMR},
3375 {0x061B, CMN_PLL1_VCOCAL_INIT_TMR},
3376 {0x0019, CMN_PLL0_VCOCAL_ITER_TMR},
3377 {0x0019, CMN_PLL1_VCOCAL_ITER_TMR},
3378 {0x1354, CMN_PLL0_VCOCAL_REFTIM_START},
3379 {0x1354, CMN_PLL1_VCOCAL_REFTIM_START},
3380 {0x1354, CMN_PLL0_VCOCAL_PLLCNT_START},
3381 {0x1354, CMN_PLL1_VCOCAL_PLLCNT_START},
3382 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
3383 {0x0003, CMN_PLL1_VCOCAL_TCTRL},
3384 {0x0138, CMN_PLL0_LOCK_REFCNT_START},
3385 {0x0138, CMN_PLL1_LOCK_REFCNT_START},
3386 {0x0138, CMN_PLL0_LOCK_PLLCNT_START},
3387 {0x0138, CMN_PLL1_LOCK_PLLCNT_START}
3388};
3389
3390static struct cdns_reg_pairs usxgmii_156_25_no_ssc_tx_ln_regs[] = {
3391 {0x07A2, TX_RCVDET_ST_TMR},
3392 {0x00F3, TX_PSC_A0},
3393 {0x04A2, TX_PSC_A2},
3394 {0x04A2, TX_PSC_A3},
3395 {0x0000, TX_TXCC_CPOST_MULT_00},
3396 {0x0000, XCVR_DIAG_PSC_OVRD}
3397};
3398
3399static struct cdns_reg_pairs usxgmii_156_25_no_ssc_rx_ln_regs[] = {
3400 {0x0014, RX_SDCAL0_INIT_TMR},
3401 {0x0062, RX_SDCAL0_ITER_TMR},
3402 {0x0014, RX_SDCAL1_INIT_TMR},
3403 {0x0062, RX_SDCAL1_ITER_TMR},
3404 {0x091D, RX_PSC_A0},
3405 {0x0900, RX_PSC_A2},
3406 {0x0100, RX_PSC_A3},
3407 {0x0030, RX_REE_SMGM_CTRL1},
3408 {0x03C7, RX_REE_GCSM1_EQENM_PH1},
3409 {0x01C7, RX_REE_GCSM1_EQENM_PH2},
3410 {0x0000, RX_DIAG_DFE_CTRL},
3411 {0x0019, RX_REE_TAP1_CLIP},
3412 {0x0019, RX_REE_TAP2TON_CLIP},
3413 {0x00B9, RX_DIAG_NQST_CTRL},
3414 {0x0C21, RX_DIAG_DFE_AMP_TUNE_2},
3415 {0x0002, RX_DIAG_DFE_AMP_TUNE_3},
3416 {0x0033, RX_DIAG_PI_RATE},
3417 {0x0001, RX_DIAG_ACYA},
3418 {0x018C, RX_CDRLF_CNFG}
3419};
3420
3421static struct cdns_torrent_vals sl_usxgmii_156_25_no_ssc_cmn_vals = {
3422 .reg_pairs = sl_usxgmii_156_25_no_ssc_cmn_regs,
3423 .num_regs = ARRAY_SIZE(sl_usxgmii_156_25_no_ssc_cmn_regs),
3424};
3425
3426static struct cdns_torrent_vals usxgmii_156_25_no_ssc_tx_ln_vals = {
3427 .reg_pairs = usxgmii_156_25_no_ssc_tx_ln_regs,
3428 .num_regs = ARRAY_SIZE(usxgmii_156_25_no_ssc_tx_ln_regs),
3429};
3430
3431static struct cdns_torrent_vals usxgmii_156_25_no_ssc_rx_ln_vals = {
3432 .reg_pairs = usxgmii_156_25_no_ssc_rx_ln_regs,
3433 .num_regs = ARRAY_SIZE(usxgmii_156_25_no_ssc_rx_ln_regs),
3434};
3435
3436/* PCIe and DP link configuration */
3437static struct cdns_reg_pairs pcie_dp_link_cmn_regs[] = {
3438 {0x0003, PHY_PLL_CFG},
3439 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0},
3440 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1}
3441};
3442
3443static struct cdns_reg_pairs pcie_dp_xcvr_diag_ln_regs[] = {
3444 {0x0000, XCVR_DIAG_HSCLK_SEL},
3445 {0x0001, XCVR_DIAG_HSCLK_DIV},
3446 {0x0012, XCVR_DIAG_PLLDRC_CTRL}
3447};
3448
3449static struct cdns_reg_pairs dp_pcie_xcvr_diag_ln_regs[] = {
3450 {0x0001, XCVR_DIAG_HSCLK_SEL},
3451 {0x0009, XCVR_DIAG_PLLDRC_CTRL}
3452};
3453
3454static struct cdns_torrent_vals pcie_dp_link_cmn_vals = {
3455 .reg_pairs = pcie_dp_link_cmn_regs,
3456 .num_regs = ARRAY_SIZE(pcie_dp_link_cmn_regs),
3457};
3458
3459static struct cdns_torrent_vals pcie_dp_xcvr_diag_ln_vals = {
3460 .reg_pairs = pcie_dp_xcvr_diag_ln_regs,
3461 .num_regs = ARRAY_SIZE(pcie_dp_xcvr_diag_ln_regs),
3462};
3463
3464static struct cdns_torrent_vals dp_pcie_xcvr_diag_ln_vals = {
3465 .reg_pairs = dp_pcie_xcvr_diag_ln_regs,
3466 .num_regs = ARRAY_SIZE(dp_pcie_xcvr_diag_ln_regs),
3467};
3468
3469/* DP Multilink, 100 MHz Ref clk, no SSC */
3470static struct cdns_reg_pairs dp_100_no_ssc_cmn_regs[] = {
3471 {0x007F, CMN_TXPUCAL_TUNE},
3472 {0x007F, CMN_TXPDCAL_TUNE}
3473};
3474
3475static struct cdns_reg_pairs dp_100_no_ssc_tx_ln_regs[] = {
3476 {0x00FB, TX_PSC_A0},
3477 {0x04AA, TX_PSC_A2},
3478 {0x04AA, TX_PSC_A3},
3479 {0x000F, XCVR_DIAG_BIDI_CTRL}
3480};
3481
3482static struct cdns_reg_pairs dp_100_no_ssc_rx_ln_regs[] = {
3483 {0x0000, RX_PSC_A0},
3484 {0x0000, RX_PSC_A2},
3485 {0x0000, RX_PSC_A3},
3486 {0x0000, RX_PSC_CAL},
3487 {0x0000, RX_REE_GCSM1_CTRL},
3488 {0x0000, RX_REE_GCSM2_CTRL},
3489 {0x0000, RX_REE_PERGCSM_CTRL}
3490};
3491
3492static struct cdns_torrent_vals dp_100_no_ssc_cmn_vals = {
3493 .reg_pairs = dp_100_no_ssc_cmn_regs,
3494 .num_regs = ARRAY_SIZE(dp_100_no_ssc_cmn_regs),
3495};
3496
3497static struct cdns_torrent_vals dp_100_no_ssc_tx_ln_vals = {
3498 .reg_pairs = dp_100_no_ssc_tx_ln_regs,
3499 .num_regs = ARRAY_SIZE(dp_100_no_ssc_tx_ln_regs),
3500};
3501
3502static struct cdns_torrent_vals dp_100_no_ssc_rx_ln_vals = {
3503 .reg_pairs = dp_100_no_ssc_rx_ln_regs,
3504 .num_regs = ARRAY_SIZE(dp_100_no_ssc_rx_ln_regs),
3505};
3506
3507/* Single DisplayPort(DP) link configuration */
3508static struct cdns_reg_pairs sl_dp_link_cmn_regs[] = {
3509 {0x0000, PHY_PLL_CFG},
3510};
3511
3512static struct cdns_reg_pairs sl_dp_xcvr_diag_ln_regs[] = {
3513 {0x0000, XCVR_DIAG_HSCLK_SEL},
3514 {0x0001, XCVR_DIAG_PLLDRC_CTRL}
3515};
3516
3517static struct cdns_torrent_vals sl_dp_link_cmn_vals = {
3518 .reg_pairs = sl_dp_link_cmn_regs,
3519 .num_regs = ARRAY_SIZE(sl_dp_link_cmn_regs),
3520};
3521
3522static struct cdns_torrent_vals sl_dp_xcvr_diag_ln_vals = {
3523 .reg_pairs = sl_dp_xcvr_diag_ln_regs,
3524 .num_regs = ARRAY_SIZE(sl_dp_xcvr_diag_ln_regs),
3525};
3526
3527/* Single DP, 19.2 MHz Ref clk, no SSC */
3528static struct cdns_reg_pairs sl_dp_19_2_no_ssc_cmn_regs[] = {
3529 {0x0014, CMN_SSM_BIAS_TMR},
3530 {0x0027, CMN_PLLSM0_PLLPRE_TMR},
3531 {0x00A1, CMN_PLLSM0_PLLLOCK_TMR},
3532 {0x0027, CMN_PLLSM1_PLLPRE_TMR},
3533 {0x00A1, CMN_PLLSM1_PLLLOCK_TMR},
3534 {0x0060, CMN_BGCAL_INIT_TMR},
3535 {0x0060, CMN_BGCAL_ITER_TMR},
3536 {0x0014, CMN_IBCAL_INIT_TMR},
3537 {0x0018, CMN_TXPUCAL_INIT_TMR},
3538 {0x0005, CMN_TXPUCAL_ITER_TMR},
3539 {0x0018, CMN_TXPDCAL_INIT_TMR},
3540 {0x0005, CMN_TXPDCAL_ITER_TMR},
3541 {0x0240, CMN_RXCAL_INIT_TMR},
3542 {0x0005, CMN_RXCAL_ITER_TMR},
3543 {0x0002, CMN_SD_CAL_INIT_TMR},
3544 {0x0002, CMN_SD_CAL_ITER_TMR},
3545 {0x000B, CMN_SD_CAL_REFTIM_START},
3546 {0x0137, CMN_SD_CAL_PLLCNT_START},
3547 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3548 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3549 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3550 {0x0004, CMN_PLL0_DSM_DIAG_M0},
3551 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3552 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3553 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3554 {0x0004, CMN_PLL1_DSM_DIAG_M0},
3555 {0x00C0, CMN_PLL0_VCOCAL_INIT_TMR},
3556 {0x0004, CMN_PLL0_VCOCAL_ITER_TMR},
3557 {0x00C0, CMN_PLL1_VCOCAL_INIT_TMR},
3558 {0x0004, CMN_PLL1_VCOCAL_ITER_TMR},
3559 {0x0260, CMN_PLL0_VCOCAL_REFTIM_START},
3560 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
3561 {0x0260, CMN_PLL1_VCOCAL_REFTIM_START},
3562 {0x0003, CMN_PLL1_VCOCAL_TCTRL}
3563};
3564
3565static struct cdns_reg_pairs sl_dp_19_2_no_ssc_tx_ln_regs[] = {
3566 {0x0780, TX_RCVDET_ST_TMR},
3567 {0x00FB, TX_PSC_A0},
3568 {0x04AA, TX_PSC_A2},
3569 {0x04AA, TX_PSC_A3},
3570 {0x000F, XCVR_DIAG_BIDI_CTRL}
3571};
3572
3573static struct cdns_reg_pairs sl_dp_19_2_no_ssc_rx_ln_regs[] = {
3574 {0x0000, RX_PSC_A0},
3575 {0x0000, RX_PSC_A2},
3576 {0x0000, RX_PSC_A3},
3577 {0x0000, RX_PSC_CAL},
3578 {0x0000, RX_REE_GCSM1_CTRL},
3579 {0x0000, RX_REE_GCSM2_CTRL},
3580 {0x0000, RX_REE_PERGCSM_CTRL}
3581};
3582
3583static struct cdns_torrent_vals sl_dp_19_2_no_ssc_cmn_vals = {
3584 .reg_pairs = sl_dp_19_2_no_ssc_cmn_regs,
3585 .num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_cmn_regs),
3586};
3587
3588static struct cdns_torrent_vals sl_dp_19_2_no_ssc_tx_ln_vals = {
3589 .reg_pairs = sl_dp_19_2_no_ssc_tx_ln_regs,
3590 .num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_tx_ln_regs),
3591};
3592
3593static struct cdns_torrent_vals sl_dp_19_2_no_ssc_rx_ln_vals = {
3594 .reg_pairs = sl_dp_19_2_no_ssc_rx_ln_regs,
3595 .num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_rx_ln_regs),
3596};
3597
3598/* Single DP, 25 MHz Ref clk, no SSC */
3599static struct cdns_reg_pairs sl_dp_25_no_ssc_cmn_regs[] = {
3600 {0x0019, CMN_SSM_BIAS_TMR},
3601 {0x0032, CMN_PLLSM0_PLLPRE_TMR},
3602 {0x00D1, CMN_PLLSM0_PLLLOCK_TMR},
3603 {0x0032, CMN_PLLSM1_PLLPRE_TMR},
3604 {0x00D1, CMN_PLLSM1_PLLLOCK_TMR},
3605 {0x007D, CMN_BGCAL_INIT_TMR},
3606 {0x007D, CMN_BGCAL_ITER_TMR},
3607 {0x0019, CMN_IBCAL_INIT_TMR},
3608 {0x001E, CMN_TXPUCAL_INIT_TMR},
3609 {0x0006, CMN_TXPUCAL_ITER_TMR},
3610 {0x001E, CMN_TXPDCAL_INIT_TMR},
3611 {0x0006, CMN_TXPDCAL_ITER_TMR},
3612 {0x02EE, CMN_RXCAL_INIT_TMR},
3613 {0x0006, CMN_RXCAL_ITER_TMR},
3614 {0x0002, CMN_SD_CAL_INIT_TMR},
3615 {0x0002, CMN_SD_CAL_ITER_TMR},
3616 {0x000E, CMN_SD_CAL_REFTIM_START},
3617 {0x012B, CMN_SD_CAL_PLLCNT_START},
3618 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3619 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3620 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3621 {0x0004, CMN_PLL0_DSM_DIAG_M0},
3622 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3623 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3624 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3625 {0x0004, CMN_PLL1_DSM_DIAG_M0},
3626 {0x00FA, CMN_PLL0_VCOCAL_INIT_TMR},
3627 {0x0004, CMN_PLL0_VCOCAL_ITER_TMR},
3628 {0x00FA, CMN_PLL1_VCOCAL_INIT_TMR},
3629 {0x0004, CMN_PLL1_VCOCAL_ITER_TMR},
3630 {0x0317, CMN_PLL0_VCOCAL_REFTIM_START},
3631 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
3632 {0x0317, CMN_PLL1_VCOCAL_REFTIM_START},
3633 {0x0003, CMN_PLL1_VCOCAL_TCTRL}
3634};
3635
3636static struct cdns_reg_pairs sl_dp_25_no_ssc_tx_ln_regs[] = {
3637 {0x09C4, TX_RCVDET_ST_TMR},
3638 {0x00FB, TX_PSC_A0},
3639 {0x04AA, TX_PSC_A2},
3640 {0x04AA, TX_PSC_A3},
3641 {0x000F, XCVR_DIAG_BIDI_CTRL}
3642};
3643
3644static struct cdns_reg_pairs sl_dp_25_no_ssc_rx_ln_regs[] = {
3645 {0x0000, RX_PSC_A0},
3646 {0x0000, RX_PSC_A2},
3647 {0x0000, RX_PSC_A3},
3648 {0x0000, RX_PSC_CAL},
3649 {0x0000, RX_REE_GCSM1_CTRL},
3650 {0x0000, RX_REE_GCSM2_CTRL},
3651 {0x0000, RX_REE_PERGCSM_CTRL}
3652};
3653
3654static struct cdns_torrent_vals sl_dp_25_no_ssc_cmn_vals = {
3655 .reg_pairs = sl_dp_25_no_ssc_cmn_regs,
3656 .num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_cmn_regs),
3657};
3658
3659static struct cdns_torrent_vals sl_dp_25_no_ssc_tx_ln_vals = {
3660 .reg_pairs = sl_dp_25_no_ssc_tx_ln_regs,
3661 .num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_tx_ln_regs),
3662};
3663
3664static struct cdns_torrent_vals sl_dp_25_no_ssc_rx_ln_vals = {
3665 .reg_pairs = sl_dp_25_no_ssc_rx_ln_regs,
3666 .num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_rx_ln_regs),
3667};
3668
3669/* Single DP, 100 MHz Ref clk, no SSC */
3670static struct cdns_reg_pairs sl_dp_100_no_ssc_cmn_regs[] = {
3671 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
3672 {0x0003, CMN_PLL1_VCOCAL_TCTRL}
3673};
3674
3675static struct cdns_reg_pairs sl_dp_100_no_ssc_tx_ln_regs[] = {
3676 {0x00FB, TX_PSC_A0},
3677 {0x04AA, TX_PSC_A2},
3678 {0x04AA, TX_PSC_A3},
3679 {0x000F, XCVR_DIAG_BIDI_CTRL}
3680};
3681
3682static struct cdns_reg_pairs sl_dp_100_no_ssc_rx_ln_regs[] = {
3683 {0x0000, RX_PSC_A0},
3684 {0x0000, RX_PSC_A2},
3685 {0x0000, RX_PSC_A3},
3686 {0x0000, RX_PSC_CAL},
3687 {0x0000, RX_REE_GCSM1_CTRL},
3688 {0x0000, RX_REE_GCSM2_CTRL},
3689 {0x0000, RX_REE_PERGCSM_CTRL}
3690};
3691
3692static struct cdns_torrent_vals sl_dp_100_no_ssc_cmn_vals = {
3693 .reg_pairs = sl_dp_100_no_ssc_cmn_regs,
3694 .num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_cmn_regs),
3695};
3696
3697static struct cdns_torrent_vals sl_dp_100_no_ssc_tx_ln_vals = {
3698 .reg_pairs = sl_dp_100_no_ssc_tx_ln_regs,
3699 .num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_tx_ln_regs),
3700};
3701
3702static struct cdns_torrent_vals sl_dp_100_no_ssc_rx_ln_vals = {
3703 .reg_pairs = sl_dp_100_no_ssc_rx_ln_regs,
3704 .num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_rx_ln_regs),
3705};
3706
3707/* USB and SGMII/QSGMII link configuration */
3708static struct cdns_reg_pairs usb_sgmii_link_cmn_regs[] = {
3709 {0x0002, PHY_PLL_CFG},
3710 {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0},
3711 {0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0}
3712};
3713
3714static struct cdns_reg_pairs usb_sgmii_xcvr_diag_ln_regs[] = {
3715 {0x0000, XCVR_DIAG_HSCLK_SEL},
3716 {0x0001, XCVR_DIAG_HSCLK_DIV},
3717 {0x0041, XCVR_DIAG_PLLDRC_CTRL}
3718};
3719
3720static struct cdns_reg_pairs sgmii_usb_xcvr_diag_ln_regs[] = {
3721 {0x0011, XCVR_DIAG_HSCLK_SEL},
3722 {0x0003, XCVR_DIAG_HSCLK_DIV},
3723 {0x009B, XCVR_DIAG_PLLDRC_CTRL}
3724};
3725
3726static struct cdns_torrent_vals usb_sgmii_link_cmn_vals = {
3727 .reg_pairs = usb_sgmii_link_cmn_regs,
3728 .num_regs = ARRAY_SIZE(usb_sgmii_link_cmn_regs),
3729};
3730
3731static struct cdns_torrent_vals usb_sgmii_xcvr_diag_ln_vals = {
3732 .reg_pairs = usb_sgmii_xcvr_diag_ln_regs,
3733 .num_regs = ARRAY_SIZE(usb_sgmii_xcvr_diag_ln_regs),
3734};
3735
3736static struct cdns_torrent_vals sgmii_usb_xcvr_diag_ln_vals = {
3737 .reg_pairs = sgmii_usb_xcvr_diag_ln_regs,
3738 .num_regs = ARRAY_SIZE(sgmii_usb_xcvr_diag_ln_regs),
3739};
3740
3741/* PCIe and USB Unique SSC link configuration */
3742static struct cdns_reg_pairs pcie_usb_link_cmn_regs[] = {
3743 {0x0003, PHY_PLL_CFG},
3744 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0},
3745 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1},
3746 {0x8600, CMN_PDIAG_PLL1_CLK_SEL_M0}
3747};
3748
3749static struct cdns_reg_pairs pcie_usb_xcvr_diag_ln_regs[] = {
3750 {0x0000, XCVR_DIAG_HSCLK_SEL},
3751 {0x0001, XCVR_DIAG_HSCLK_DIV},
3752 {0x0012, XCVR_DIAG_PLLDRC_CTRL}
3753};
3754
3755static struct cdns_reg_pairs usb_pcie_xcvr_diag_ln_regs[] = {
3756 {0x0011, XCVR_DIAG_HSCLK_SEL},
3757 {0x0001, XCVR_DIAG_HSCLK_DIV},
3758 {0x00C9, XCVR_DIAG_PLLDRC_CTRL}
3759};
3760
3761static struct cdns_torrent_vals pcie_usb_link_cmn_vals = {
3762 .reg_pairs = pcie_usb_link_cmn_regs,
3763 .num_regs = ARRAY_SIZE(pcie_usb_link_cmn_regs),
3764};
3765
3766static struct cdns_torrent_vals pcie_usb_xcvr_diag_ln_vals = {
3767 .reg_pairs = pcie_usb_xcvr_diag_ln_regs,
3768 .num_regs = ARRAY_SIZE(pcie_usb_xcvr_diag_ln_regs),
3769};
3770
3771static struct cdns_torrent_vals usb_pcie_xcvr_diag_ln_vals = {
3772 .reg_pairs = usb_pcie_xcvr_diag_ln_regs,
3773 .num_regs = ARRAY_SIZE(usb_pcie_xcvr_diag_ln_regs),
3774};
3775
3776/* USB 100 MHz Ref clk, internal SSC */
3777static struct cdns_reg_pairs usb_100_int_ssc_cmn_regs[] = {
3778 {0x0004, CMN_PLL0_DSM_DIAG_M0},
3779 {0x0004, CMN_PLL0_DSM_DIAG_M1},
3780 {0x0004, CMN_PLL1_DSM_DIAG_M0},
3781 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3782 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
3783 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3784 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3785 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
3786 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3787 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3788 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
3789 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3790 {0x0064, CMN_PLL0_INTDIV_M0},
3791 {0x0050, CMN_PLL0_INTDIV_M1},
3792 {0x0064, CMN_PLL1_INTDIV_M0},
3793 {0x0002, CMN_PLL0_FRACDIVH_M0},
3794 {0x0002, CMN_PLL0_FRACDIVH_M1},
3795 {0x0002, CMN_PLL1_FRACDIVH_M0},
3796 {0x0044, CMN_PLL0_HIGH_THR_M0},
3797 {0x0036, CMN_PLL0_HIGH_THR_M1},
3798 {0x0044, CMN_PLL1_HIGH_THR_M0},
3799 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
3800 {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
3801 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
3802 {0x0001, CMN_PLL0_SS_CTRL1_M0},
3803 {0x0001, CMN_PLL0_SS_CTRL1_M1},
3804 {0x0001, CMN_PLL1_SS_CTRL1_M0},
3805 {0x011B, CMN_PLL0_SS_CTRL2_M0},
3806 {0x011B, CMN_PLL0_SS_CTRL2_M1},
3807 {0x011B, CMN_PLL1_SS_CTRL2_M0},
3808 {0x006E, CMN_PLL0_SS_CTRL3_M0},
3809 {0x0058, CMN_PLL0_SS_CTRL3_M1},
3810 {0x006E, CMN_PLL1_SS_CTRL3_M0},
3811 {0x000E, CMN_PLL0_SS_CTRL4_M0},
3812 {0x0012, CMN_PLL0_SS_CTRL4_M1},
3813 {0x000E, CMN_PLL1_SS_CTRL4_M0},
3814 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
3815 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
3816 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
3817 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
3818 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
3819 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
3820 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
3821 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
3822 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
3823 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
3824 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
3825 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD},
3826 {0x007F, CMN_TXPUCAL_TUNE},
3827 {0x007F, CMN_TXPDCAL_TUNE}
3828};
3829
3830static struct cdns_torrent_vals usb_100_int_ssc_cmn_vals = {
3831 .reg_pairs = usb_100_int_ssc_cmn_regs,
3832 .num_regs = ARRAY_SIZE(usb_100_int_ssc_cmn_regs),
3833};
3834
3835/* Single USB link configuration */
3836static struct cdns_reg_pairs sl_usb_link_cmn_regs[] = {
3837 {0x0000, PHY_PLL_CFG},
3838 {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0}
3839};
3840
3841static struct cdns_reg_pairs sl_usb_xcvr_diag_ln_regs[] = {
3842 {0x0000, XCVR_DIAG_HSCLK_SEL},
3843 {0x0001, XCVR_DIAG_HSCLK_DIV},
3844 {0x0041, XCVR_DIAG_PLLDRC_CTRL}
3845};
3846
3847static struct cdns_torrent_vals sl_usb_link_cmn_vals = {
3848 .reg_pairs = sl_usb_link_cmn_regs,
3849 .num_regs = ARRAY_SIZE(sl_usb_link_cmn_regs),
3850};
3851
3852static struct cdns_torrent_vals sl_usb_xcvr_diag_ln_vals = {
3853 .reg_pairs = sl_usb_xcvr_diag_ln_regs,
3854 .num_regs = ARRAY_SIZE(sl_usb_xcvr_diag_ln_regs),
3855};
3856
3857/* USB PHY PCS common configuration */
3858static struct cdns_reg_pairs usb_phy_pcs_cmn_regs[] = {
3859 {0x0A0A, PHY_PIPE_USB3_GEN2_PRE_CFG0},
3860 {0x1000, PHY_PIPE_USB3_GEN2_POST_CFG0},
3861 {0x0010, PHY_PIPE_USB3_GEN2_POST_CFG1}
3862};
3863
3864static struct cdns_torrent_vals usb_phy_pcs_cmn_vals = {
3865 .reg_pairs = usb_phy_pcs_cmn_regs,
3866 .num_regs = ARRAY_SIZE(usb_phy_pcs_cmn_regs),
3867};
3868
3869/* USB 100 MHz Ref clk, no SSC */
3870static struct cdns_reg_pairs sl_usb_100_no_ssc_cmn_regs[] = {
3871 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
3872 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},
3873 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0},
3874 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
3875 {0x0003, CMN_PLL1_VCOCAL_TCTRL},
3876 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
3877 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}
3878};
3879
3880static struct cdns_torrent_vals sl_usb_100_no_ssc_cmn_vals = {
3881 .reg_pairs = sl_usb_100_no_ssc_cmn_regs,
3882 .num_regs = ARRAY_SIZE(sl_usb_100_no_ssc_cmn_regs),
3883};
3884
3885static struct cdns_reg_pairs usb_100_no_ssc_cmn_regs[] = {
3886 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
3887 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD},
3888 {0x007F, CMN_TXPUCAL_TUNE},
3889 {0x007F, CMN_TXPDCAL_TUNE}
3890};
3891
3892static struct cdns_reg_pairs usb_100_no_ssc_tx_ln_regs[] = {
3893 {0x02FF, TX_PSC_A0},
3894 {0x06AF, TX_PSC_A1},
3895 {0x06AE, TX_PSC_A2},
3896 {0x06AE, TX_PSC_A3},
3897 {0x2A82, TX_TXCC_CTRL},
3898 {0x0014, TX_TXCC_CPOST_MULT_01},
3899 {0x0003, XCVR_DIAG_PSC_OVRD}
3900};
3901
3902static struct cdns_reg_pairs usb_100_no_ssc_rx_ln_regs[] = {
3903 {0x0D1D, RX_PSC_A0},
3904 {0x0D1D, RX_PSC_A1},
3905 {0x0D00, RX_PSC_A2},
3906 {0x0500, RX_PSC_A3},
3907 {0x0013, RX_SIGDET_HL_FILT_TMR},
3908 {0x0000, RX_REE_GCSM1_CTRL},
3909 {0x0C02, RX_REE_ATTEN_THR},
3910 {0x0330, RX_REE_SMGM_CTRL1},
3911 {0x0300, RX_REE_SMGM_CTRL2},
3912 {0x0019, RX_REE_TAP1_CLIP},
3913 {0x0019, RX_REE_TAP2TON_CLIP},
3914 {0x1004, RX_DIAG_SIGDET_TUNE},
3915 {0x00F9, RX_DIAG_NQST_CTRL},
3916 {0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
3917 {0x0002, RX_DIAG_DFE_AMP_TUNE_3},
3918 {0x0000, RX_DIAG_PI_CAP},
3919 {0x0031, RX_DIAG_PI_RATE},
3920 {0x0001, RX_DIAG_ACYA},
3921 {0x018C, RX_CDRLF_CNFG},
3922 {0x0003, RX_CDRLF_CNFG3}
3923};
3924
3925static struct cdns_torrent_vals usb_100_no_ssc_cmn_vals = {
3926 .reg_pairs = usb_100_no_ssc_cmn_regs,
3927 .num_regs = ARRAY_SIZE(usb_100_no_ssc_cmn_regs),
3928};
3929
3930static struct cdns_torrent_vals usb_100_no_ssc_tx_ln_vals = {
3931 .reg_pairs = usb_100_no_ssc_tx_ln_regs,
3932 .num_regs = ARRAY_SIZE(usb_100_no_ssc_tx_ln_regs),
3933};
3934
3935static struct cdns_torrent_vals usb_100_no_ssc_rx_ln_vals = {
3936 .reg_pairs = usb_100_no_ssc_rx_ln_regs,
3937 .num_regs = ARRAY_SIZE(usb_100_no_ssc_rx_ln_regs),
3938};
3939
3940/* Single link USB, 100 MHz Ref clk, internal SSC */
3941static struct cdns_reg_pairs sl_usb_100_int_ssc_cmn_regs[] = {
3942 {0x0004, CMN_PLL0_DSM_DIAG_M0},
3943 {0x0004, CMN_PLL1_DSM_DIAG_M0},
3944 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3945 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3946 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3947 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3948 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3949 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3950 {0x0064, CMN_PLL0_INTDIV_M0},
3951 {0x0064, CMN_PLL1_INTDIV_M0},
3952 {0x0002, CMN_PLL0_FRACDIVH_M0},
3953 {0x0002, CMN_PLL1_FRACDIVH_M0},
3954 {0x0044, CMN_PLL0_HIGH_THR_M0},
3955 {0x0044, CMN_PLL1_HIGH_THR_M0},
3956 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
3957 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
3958 {0x0001, CMN_PLL0_SS_CTRL1_M0},
3959 {0x0001, CMN_PLL1_SS_CTRL1_M0},
3960 {0x011B, CMN_PLL0_SS_CTRL2_M0},
3961 {0x011B, CMN_PLL1_SS_CTRL2_M0},
3962 {0x006E, CMN_PLL0_SS_CTRL3_M0},
3963 {0x006E, CMN_PLL1_SS_CTRL3_M0},
3964 {0x000E, CMN_PLL0_SS_CTRL4_M0},
3965 {0x000E, CMN_PLL1_SS_CTRL4_M0},
3966 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
3967 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
3968 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
3969 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
3970 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
3971 {0x0003, CMN_PLL1_VCOCAL_TCTRL},
3972 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
3973 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
3974 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
3975 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
3976 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
3977 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
3978 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
3979 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}
3980};
3981
3982static struct cdns_torrent_vals sl_usb_100_int_ssc_cmn_vals = {
3983 .reg_pairs = sl_usb_100_int_ssc_cmn_regs,
3984 .num_regs = ARRAY_SIZE(sl_usb_100_int_ssc_cmn_regs),
3985};
3986
3987/* PCIe and SGMII/QSGMII Unique SSC link configuration */
3988static struct cdns_reg_pairs pcie_sgmii_link_cmn_regs[] = {
3989 {0x0003, PHY_PLL_CFG},
3990 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0},
3991 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1},
3992 {0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0}
3993};
3994
3995static struct cdns_reg_pairs pcie_sgmii_xcvr_diag_ln_regs[] = {
3996 {0x0000, XCVR_DIAG_HSCLK_SEL},
3997 {0x0001, XCVR_DIAG_HSCLK_DIV},
3998 {0x0012, XCVR_DIAG_PLLDRC_CTRL}
3999};
4000
4001static struct cdns_reg_pairs sgmii_pcie_xcvr_diag_ln_regs[] = {
4002 {0x0011, XCVR_DIAG_HSCLK_SEL},
4003 {0x0003, XCVR_DIAG_HSCLK_DIV},
4004 {0x009B, XCVR_DIAG_PLLDRC_CTRL}
4005};
4006
4007static struct cdns_torrent_vals pcie_sgmii_link_cmn_vals = {
4008 .reg_pairs = pcie_sgmii_link_cmn_regs,
4009 .num_regs = ARRAY_SIZE(pcie_sgmii_link_cmn_regs),
4010};
4011
4012static struct cdns_torrent_vals pcie_sgmii_xcvr_diag_ln_vals = {
4013 .reg_pairs = pcie_sgmii_xcvr_diag_ln_regs,
4014 .num_regs = ARRAY_SIZE(pcie_sgmii_xcvr_diag_ln_regs),
4015};
4016
4017static struct cdns_torrent_vals sgmii_pcie_xcvr_diag_ln_vals = {
4018 .reg_pairs = sgmii_pcie_xcvr_diag_ln_regs,
4019 .num_regs = ARRAY_SIZE(sgmii_pcie_xcvr_diag_ln_regs),
4020};
4021
4022/* SGMII 100 MHz Ref clk, no SSC */
4023static struct cdns_reg_pairs sl_sgmii_100_no_ssc_cmn_regs[] = {
4024 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
4025 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},
4026 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0},
4027 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
4028 {0x0003, CMN_PLL1_VCOCAL_TCTRL}
4029};
4030
4031static struct cdns_torrent_vals sl_sgmii_100_no_ssc_cmn_vals = {
4032 .reg_pairs = sl_sgmii_100_no_ssc_cmn_regs,
4033 .num_regs = ARRAY_SIZE(sl_sgmii_100_no_ssc_cmn_regs),
4034};
4035
4036static struct cdns_reg_pairs sgmii_100_no_ssc_cmn_regs[] = {
4037 {0x007F, CMN_TXPUCAL_TUNE},
4038 {0x007F, CMN_TXPDCAL_TUNE}
4039};
4040
4041static struct cdns_reg_pairs sgmii_100_no_ssc_tx_ln_regs[] = {
4042 {0x00F3, TX_PSC_A0},
4043 {0x04A2, TX_PSC_A2},
4044 {0x04A2, TX_PSC_A3},
4045 {0x0000, TX_TXCC_CPOST_MULT_00},
4046 {0x00B3, DRV_DIAG_TX_DRV}
4047};
4048
4049static struct cdns_reg_pairs ti_sgmii_100_no_ssc_tx_ln_regs[] = {
4050 {0x00F3, TX_PSC_A0},
4051 {0x04A2, TX_PSC_A2},
4052 {0x04A2, TX_PSC_A3},
4053 {0x0000, TX_TXCC_CPOST_MULT_00},
4054 {0x00B3, DRV_DIAG_TX_DRV},
4055 {0x4000, XCVR_DIAG_RXCLK_CTRL},
4056};
4057
4058static struct cdns_reg_pairs sgmii_100_no_ssc_rx_ln_regs[] = {
4059 {0x091D, RX_PSC_A0},
4060 {0x0900, RX_PSC_A2},
4061 {0x0100, RX_PSC_A3},
4062 {0x03C7, RX_REE_GCSM1_EQENM_PH1},
4063 {0x01C7, RX_REE_GCSM1_EQENM_PH2},
4064 {0x0000, RX_DIAG_DFE_CTRL},
4065 {0x0019, RX_REE_TAP1_CLIP},
4066 {0x0019, RX_REE_TAP2TON_CLIP},
4067 {0x0098, RX_DIAG_NQST_CTRL},
4068 {0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
4069 {0x0000, RX_DIAG_DFE_AMP_TUNE_3},
4070 {0x0000, RX_DIAG_PI_CAP},
4071 {0x0010, RX_DIAG_PI_RATE},
4072 {0x0001, RX_DIAG_ACYA},
4073 {0x018C, RX_CDRLF_CNFG},
4074};
4075
4076static struct cdns_torrent_vals sgmii_100_no_ssc_cmn_vals = {
4077 .reg_pairs = sgmii_100_no_ssc_cmn_regs,
4078 .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_cmn_regs),
4079};
4080
4081static struct cdns_torrent_vals sgmii_100_no_ssc_tx_ln_vals = {
4082 .reg_pairs = sgmii_100_no_ssc_tx_ln_regs,
4083 .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_tx_ln_regs),
4084};
4085
4086static struct cdns_torrent_vals ti_sgmii_100_no_ssc_tx_ln_vals = {
4087 .reg_pairs = ti_sgmii_100_no_ssc_tx_ln_regs,
4088 .num_regs = ARRAY_SIZE(ti_sgmii_100_no_ssc_tx_ln_regs),
4089};
4090
4091static struct cdns_torrent_vals sgmii_100_no_ssc_rx_ln_vals = {
4092 .reg_pairs = sgmii_100_no_ssc_rx_ln_regs,
4093 .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_rx_ln_regs),
4094};
4095
4096/* TI J7200, multilink SGMII */
4097static struct cdns_reg_pairs j7200_sgmii_100_no_ssc_tx_ln_regs[] = {
4098 {0x07A2, TX_RCVDET_ST_TMR},
4099 {0x00F3, TX_PSC_A0},
4100 {0x04A2, TX_PSC_A2},
4101 {0x04A2, TX_PSC_A3 },
4102 {0x0000, TX_TXCC_CPOST_MULT_00},
4103 {0x00B3, DRV_DIAG_TX_DRV},
4104 {0x0002, XCVR_DIAG_PSC_OVRD},
4105 {0x4000, XCVR_DIAG_RXCLK_CTRL}
4106};
4107
4108static struct cdns_torrent_vals j7200_sgmii_100_no_ssc_tx_ln_vals = {
4109 .reg_pairs = j7200_sgmii_100_no_ssc_tx_ln_regs,
4110 .num_regs = ARRAY_SIZE(j7200_sgmii_100_no_ssc_tx_ln_regs),
4111};
4112
4113static struct cdns_reg_pairs j7200_sgmii_100_no_ssc_rx_ln_regs[] = {
4114 {0x0014, RX_SDCAL0_INIT_TMR},
4115 {0x0062, RX_SDCAL0_ITER_TMR},
4116 {0x0014, RX_SDCAL1_INIT_TMR},
4117 {0x0062, RX_SDCAL1_ITER_TMR},
4118 {0x091D, RX_PSC_A0},
4119 {0x0900, RX_PSC_A2},
4120 {0x0100, RX_PSC_A3},
4121 {0x03C7, RX_REE_GCSM1_EQENM_PH1},
4122 {0x01C7, RX_REE_GCSM1_EQENM_PH2},
4123 {0x0000, RX_DIAG_DFE_CTRL},
4124 {0x0019, RX_REE_TAP1_CLIP},
4125 {0x0019, RX_REE_TAP2TON_CLIP},
4126 {0x0098, RX_DIAG_NQST_CTRL},
4127 {0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
4128 {0x0000, RX_DIAG_DFE_AMP_TUNE_3},
4129 {0x0000, RX_DIAG_PI_CAP},
4130 {0x0010, RX_DIAG_PI_RATE},
4131 {0x0001, RX_DIAG_ACYA},
4132 {0x018C, RX_CDRLF_CNFG}
4133};
4134
4135static struct cdns_torrent_vals j7200_sgmii_100_no_ssc_rx_ln_vals = {
4136 .reg_pairs = j7200_sgmii_100_no_ssc_rx_ln_regs,
4137 .num_regs = ARRAY_SIZE(j7200_sgmii_100_no_ssc_rx_ln_regs),
4138};
4139
4140/* SGMII 100 MHz Ref clk, internal SSC */
4141static struct cdns_reg_pairs sgmii_100_int_ssc_cmn_regs[] = {
4142 {0x0004, CMN_PLL0_DSM_DIAG_M0},
4143 {0x0004, CMN_PLL0_DSM_DIAG_M1},
4144 {0x0004, CMN_PLL1_DSM_DIAG_M0},
4145 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
4146 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
4147 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
4148 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
4149 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
4150 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
4151 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
4152 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
4153 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
4154 {0x0064, CMN_PLL0_INTDIV_M0},
4155 {0x0050, CMN_PLL0_INTDIV_M1},
4156 {0x0064, CMN_PLL1_INTDIV_M0},
4157 {0x0002, CMN_PLL0_FRACDIVH_M0},
4158 {0x0002, CMN_PLL0_FRACDIVH_M1},
4159 {0x0002, CMN_PLL1_FRACDIVH_M0},
4160 {0x0044, CMN_PLL0_HIGH_THR_M0},
4161 {0x0036, CMN_PLL0_HIGH_THR_M1},
4162 {0x0044, CMN_PLL1_HIGH_THR_M0},
4163 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
4164 {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
4165 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
4166 {0x0001, CMN_PLL0_SS_CTRL1_M0},
4167 {0x0001, CMN_PLL0_SS_CTRL1_M1},
4168 {0x0001, CMN_PLL1_SS_CTRL1_M0},
4169 {0x011B, CMN_PLL0_SS_CTRL2_M0},
4170 {0x011B, CMN_PLL0_SS_CTRL2_M1},
4171 {0x011B, CMN_PLL1_SS_CTRL2_M0},
4172 {0x006E, CMN_PLL0_SS_CTRL3_M0},
4173 {0x0058, CMN_PLL0_SS_CTRL3_M1},
4174 {0x006E, CMN_PLL1_SS_CTRL3_M0},
4175 {0x000E, CMN_PLL0_SS_CTRL4_M0},
4176 {0x0012, CMN_PLL0_SS_CTRL4_M1},
4177 {0x000E, CMN_PLL1_SS_CTRL4_M0},
4178 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
4179 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
4180 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
4181 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
4182 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
4183 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
4184 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
4185 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
4186 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
4187 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
4188 {0x007F, CMN_TXPUCAL_TUNE},
4189 {0x007F, CMN_TXPDCAL_TUNE}
4190};
4191
4192static struct cdns_torrent_vals sgmii_100_int_ssc_cmn_vals = {
4193 .reg_pairs = sgmii_100_int_ssc_cmn_regs,
4194 .num_regs = ARRAY_SIZE(sgmii_100_int_ssc_cmn_regs),
4195};
4196
4197/* QSGMII 100 MHz Ref clk, no SSC */
4198static struct cdns_reg_pairs sl_qsgmii_100_no_ssc_cmn_regs[] = {
4199 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
4200 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},
4201 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0},
4202 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
4203 {0x0003, CMN_PLL1_VCOCAL_TCTRL}
4204};
4205
4206static struct cdns_torrent_vals sl_qsgmii_100_no_ssc_cmn_vals = {
4207 .reg_pairs = sl_qsgmii_100_no_ssc_cmn_regs,
4208 .num_regs = ARRAY_SIZE(sl_qsgmii_100_no_ssc_cmn_regs),
4209};
4210
4211static struct cdns_reg_pairs qsgmii_100_no_ssc_cmn_regs[] = {
4212 {0x007F, CMN_TXPUCAL_TUNE},
4213 {0x007F, CMN_TXPDCAL_TUNE}
4214};
4215
4216static struct cdns_reg_pairs qsgmii_100_no_ssc_tx_ln_regs[] = {
4217 {0x00F3, TX_PSC_A0},
4218 {0x04A2, TX_PSC_A2},
4219 {0x04A2, TX_PSC_A3},
4220 {0x0000, TX_TXCC_CPOST_MULT_00},
4221 {0x0011, TX_TXCC_MGNFS_MULT_100},
4222 {0x0003, DRV_DIAG_TX_DRV}
4223};
4224
4225static struct cdns_reg_pairs ti_qsgmii_100_no_ssc_tx_ln_regs[] = {
4226 {0x00F3, TX_PSC_A0},
4227 {0x04A2, TX_PSC_A2},
4228 {0x04A2, TX_PSC_A3},
4229 {0x0000, TX_TXCC_CPOST_MULT_00},
4230 {0x0011, TX_TXCC_MGNFS_MULT_100},
4231 {0x0003, DRV_DIAG_TX_DRV},
4232 {0x4000, XCVR_DIAG_RXCLK_CTRL},
4233};
4234
4235static struct cdns_reg_pairs qsgmii_100_no_ssc_rx_ln_regs[] = {
4236 {0x091D, RX_PSC_A0},
4237 {0x0900, RX_PSC_A2},
4238 {0x0100, RX_PSC_A3},
4239 {0x03C7, RX_REE_GCSM1_EQENM_PH1},
4240 {0x01C7, RX_REE_GCSM1_EQENM_PH2},
4241 {0x0000, RX_DIAG_DFE_CTRL},
4242 {0x0019, RX_REE_TAP1_CLIP},
4243 {0x0019, RX_REE_TAP2TON_CLIP},
4244 {0x0098, RX_DIAG_NQST_CTRL},
4245 {0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
4246 {0x0000, RX_DIAG_DFE_AMP_TUNE_3},
4247 {0x0000, RX_DIAG_PI_CAP},
4248 {0x0010, RX_DIAG_PI_RATE},
4249 {0x0001, RX_DIAG_ACYA},
4250 {0x018C, RX_CDRLF_CNFG},
4251};
4252
4253static struct cdns_torrent_vals qsgmii_100_no_ssc_cmn_vals = {
4254 .reg_pairs = qsgmii_100_no_ssc_cmn_regs,
4255 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_cmn_regs),
4256};
4257
4258static struct cdns_torrent_vals qsgmii_100_no_ssc_tx_ln_vals = {
4259 .reg_pairs = qsgmii_100_no_ssc_tx_ln_regs,
4260 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_tx_ln_regs),
4261};
4262
4263static struct cdns_torrent_vals ti_qsgmii_100_no_ssc_tx_ln_vals = {
4264 .reg_pairs = ti_qsgmii_100_no_ssc_tx_ln_regs,
4265 .num_regs = ARRAY_SIZE(ti_qsgmii_100_no_ssc_tx_ln_regs),
4266};
4267
4268static struct cdns_torrent_vals qsgmii_100_no_ssc_rx_ln_vals = {
4269 .reg_pairs = qsgmii_100_no_ssc_rx_ln_regs,
4270 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_rx_ln_regs),
4271};
4272
4273/* TI J7200, multilink QSGMII */
4274static struct cdns_reg_pairs j7200_qsgmii_100_no_ssc_tx_ln_regs[] = {
4275 {0x07A2, TX_RCVDET_ST_TMR},
4276 {0x00F3, TX_PSC_A0},
4277 {0x04A2, TX_PSC_A2},
4278 {0x04A2, TX_PSC_A3 },
4279 {0x0000, TX_TXCC_CPOST_MULT_00},
4280 {0x0011, TX_TXCC_MGNFS_MULT_100},
4281 {0x0003, DRV_DIAG_TX_DRV},
4282 {0x0002, XCVR_DIAG_PSC_OVRD},
4283 {0x4000, XCVR_DIAG_RXCLK_CTRL}
4284};
4285
4286static struct cdns_torrent_vals j7200_qsgmii_100_no_ssc_tx_ln_vals = {
4287 .reg_pairs = j7200_qsgmii_100_no_ssc_tx_ln_regs,
4288 .num_regs = ARRAY_SIZE(j7200_qsgmii_100_no_ssc_tx_ln_regs),
4289};
4290
4291static struct cdns_reg_pairs j7200_qsgmii_100_no_ssc_rx_ln_regs[] = {
4292 {0x0014, RX_SDCAL0_INIT_TMR},
4293 {0x0062, RX_SDCAL0_ITER_TMR},
4294 {0x0014, RX_SDCAL1_INIT_TMR},
4295 {0x0062, RX_SDCAL1_ITER_TMR},
4296 {0x091D, RX_PSC_A0},
4297 {0x0900, RX_PSC_A2},
4298 {0x0100, RX_PSC_A3},
4299 {0x03C7, RX_REE_GCSM1_EQENM_PH1},
4300 {0x01C7, RX_REE_GCSM1_EQENM_PH2},
4301 {0x0000, RX_DIAG_DFE_CTRL},
4302 {0x0019, RX_REE_TAP1_CLIP},
4303 {0x0019, RX_REE_TAP2TON_CLIP},
4304 {0x0098, RX_DIAG_NQST_CTRL},
4305 {0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
4306 {0x0000, RX_DIAG_DFE_AMP_TUNE_3},
4307 {0x0000, RX_DIAG_PI_CAP},
4308 {0x0010, RX_DIAG_PI_RATE},
4309 {0x0001, RX_DIAG_ACYA},
4310 {0x018C, RX_CDRLF_CNFG}
4311};
4312
4313static struct cdns_torrent_vals j7200_qsgmii_100_no_ssc_rx_ln_vals = {
4314 .reg_pairs = j7200_qsgmii_100_no_ssc_rx_ln_regs,
4315 .num_regs = ARRAY_SIZE(j7200_qsgmii_100_no_ssc_rx_ln_regs),
4316};
4317
4318/* QSGMII 100 MHz Ref clk, internal SSC */
4319static struct cdns_reg_pairs qsgmii_100_int_ssc_cmn_regs[] = {
4320 {0x0004, CMN_PLL0_DSM_DIAG_M0},
4321 {0x0004, CMN_PLL0_DSM_DIAG_M1},
4322 {0x0004, CMN_PLL1_DSM_DIAG_M0},
4323 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
4324 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
4325 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
4326 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
4327 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
4328 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
4329 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
4330 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
4331 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
4332 {0x0064, CMN_PLL0_INTDIV_M0},
4333 {0x0050, CMN_PLL0_INTDIV_M1},
4334 {0x0064, CMN_PLL1_INTDIV_M0},
4335 {0x0002, CMN_PLL0_FRACDIVH_M0},
4336 {0x0002, CMN_PLL0_FRACDIVH_M1},
4337 {0x0002, CMN_PLL1_FRACDIVH_M0},
4338 {0x0044, CMN_PLL0_HIGH_THR_M0},
4339 {0x0036, CMN_PLL0_HIGH_THR_M1},
4340 {0x0044, CMN_PLL1_HIGH_THR_M0},
4341 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
4342 {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
4343 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
4344 {0x0001, CMN_PLL0_SS_CTRL1_M0},
4345 {0x0001, CMN_PLL0_SS_CTRL1_M1},
4346 {0x0001, CMN_PLL1_SS_CTRL1_M0},
4347 {0x011B, CMN_PLL0_SS_CTRL2_M0},
4348 {0x011B, CMN_PLL0_SS_CTRL2_M1},
4349 {0x011B, CMN_PLL1_SS_CTRL2_M0},
4350 {0x006E, CMN_PLL0_SS_CTRL3_M0},
4351 {0x0058, CMN_PLL0_SS_CTRL3_M1},
4352 {0x006E, CMN_PLL1_SS_CTRL3_M0},
4353 {0x000E, CMN_PLL0_SS_CTRL4_M0},
4354 {0x0012, CMN_PLL0_SS_CTRL4_M1},
4355 {0x000E, CMN_PLL1_SS_CTRL4_M0},
4356 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
4357 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
4358 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
4359 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
4360 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
4361 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
4362 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
4363 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
4364 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
4365 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
4366 {0x007F, CMN_TXPUCAL_TUNE},
4367 {0x007F, CMN_TXPDCAL_TUNE}
4368};
4369
4370static struct cdns_torrent_vals qsgmii_100_int_ssc_cmn_vals = {
4371 .reg_pairs = qsgmii_100_int_ssc_cmn_regs,
4372 .num_regs = ARRAY_SIZE(qsgmii_100_int_ssc_cmn_regs),
4373};
4374
4375/* Single SGMII/QSGMII link configuration */
4376static struct cdns_reg_pairs sl_sgmii_link_cmn_regs[] = {
4377 {0x0000, PHY_PLL_CFG},
4378 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}
4379};
4380
4381static struct cdns_reg_pairs sl_sgmii_xcvr_diag_ln_regs[] = {
4382 {0x0000, XCVR_DIAG_HSCLK_SEL},
4383 {0x0003, XCVR_DIAG_HSCLK_DIV},
4384 {0x0013, XCVR_DIAG_PLLDRC_CTRL}
4385};
4386
4387static struct cdns_torrent_vals sl_sgmii_link_cmn_vals = {
4388 .reg_pairs = sl_sgmii_link_cmn_regs,
4389 .num_regs = ARRAY_SIZE(sl_sgmii_link_cmn_regs),
4390};
4391
4392static struct cdns_torrent_vals sl_sgmii_xcvr_diag_ln_vals = {
4393 .reg_pairs = sl_sgmii_xcvr_diag_ln_regs,
4394 .num_regs = ARRAY_SIZE(sl_sgmii_xcvr_diag_ln_regs),
4395};
4396
4397/* Multi link PCIe, 100 MHz Ref clk, internal SSC */
4398static struct cdns_reg_pairs pcie_100_int_ssc_cmn_regs[] = {
4399 {0x0004, CMN_PLL0_DSM_DIAG_M0},
4400 {0x0004, CMN_PLL0_DSM_DIAG_M1},
4401 {0x0004, CMN_PLL1_DSM_DIAG_M0},
4402 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
4403 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
4404 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
4405 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
4406 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
4407 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
4408 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
4409 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
4410 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
4411 {0x0064, CMN_PLL0_INTDIV_M0},
4412 {0x0050, CMN_PLL0_INTDIV_M1},
4413 {0x0064, CMN_PLL1_INTDIV_M0},
4414 {0x0002, CMN_PLL0_FRACDIVH_M0},
4415 {0x0002, CMN_PLL0_FRACDIVH_M1},
4416 {0x0002, CMN_PLL1_FRACDIVH_M0},
4417 {0x0044, CMN_PLL0_HIGH_THR_M0},
4418 {0x0036, CMN_PLL0_HIGH_THR_M1},
4419 {0x0044, CMN_PLL1_HIGH_THR_M0},
4420 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
4421 {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
4422 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
4423 {0x0001, CMN_PLL0_SS_CTRL1_M0},
4424 {0x0001, CMN_PLL0_SS_CTRL1_M1},
4425 {0x0001, CMN_PLL1_SS_CTRL1_M0},
4426 {0x011B, CMN_PLL0_SS_CTRL2_M0},
4427 {0x011B, CMN_PLL0_SS_CTRL2_M1},
4428 {0x011B, CMN_PLL1_SS_CTRL2_M0},
4429 {0x006E, CMN_PLL0_SS_CTRL3_M0},
4430 {0x0058, CMN_PLL0_SS_CTRL3_M1},
4431 {0x006E, CMN_PLL1_SS_CTRL3_M0},
4432 {0x000E, CMN_PLL0_SS_CTRL4_M0},
4433 {0x0012, CMN_PLL0_SS_CTRL4_M1},
4434 {0x000E, CMN_PLL1_SS_CTRL4_M0},
4435 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
4436 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
4437 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
4438 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
4439 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
4440 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
4441 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
4442 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
4443 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
4444 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}
4445};
4446
4447static struct cdns_torrent_vals pcie_100_int_ssc_cmn_vals = {
4448 .reg_pairs = pcie_100_int_ssc_cmn_regs,
4449 .num_regs = ARRAY_SIZE(pcie_100_int_ssc_cmn_regs),
4450};
4451
4452/* Single link PCIe, 100 MHz Ref clk, internal SSC */
4453static struct cdns_reg_pairs sl_pcie_100_int_ssc_cmn_regs[] = {
4454 {0x0004, CMN_PLL0_DSM_DIAG_M0},
4455 {0x0004, CMN_PLL0_DSM_DIAG_M1},
4456 {0x0004, CMN_PLL1_DSM_DIAG_M0},
4457 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
4458 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
4459 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
4460 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
4461 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
4462 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
4463 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
4464 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
4465 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
4466 {0x0064, CMN_PLL0_INTDIV_M0},
4467 {0x0050, CMN_PLL0_INTDIV_M1},
4468 {0x0050, CMN_PLL1_INTDIV_M0},
4469 {0x0002, CMN_PLL0_FRACDIVH_M0},
4470 {0x0002, CMN_PLL0_FRACDIVH_M1},
4471 {0x0002, CMN_PLL1_FRACDIVH_M0},
4472 {0x0044, CMN_PLL0_HIGH_THR_M0},
4473 {0x0036, CMN_PLL0_HIGH_THR_M1},
4474 {0x0036, CMN_PLL1_HIGH_THR_M0},
4475 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
4476 {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
4477 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
4478 {0x0001, CMN_PLL0_SS_CTRL1_M0},
4479 {0x0001, CMN_PLL0_SS_CTRL1_M1},
4480 {0x0001, CMN_PLL1_SS_CTRL1_M0},
4481 {0x011B, CMN_PLL0_SS_CTRL2_M0},
4482 {0x011B, CMN_PLL0_SS_CTRL2_M1},
4483 {0x011B, CMN_PLL1_SS_CTRL2_M0},
4484 {0x006E, CMN_PLL0_SS_CTRL3_M0},
4485 {0x0058, CMN_PLL0_SS_CTRL3_M1},
4486 {0x0058, CMN_PLL1_SS_CTRL3_M0},
4487 {0x000E, CMN_PLL0_SS_CTRL4_M0},
4488 {0x0012, CMN_PLL0_SS_CTRL4_M1},
4489 {0x0012, CMN_PLL1_SS_CTRL4_M0},
4490 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
4491 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
4492 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
4493 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
4494 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
4495 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
4496 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
4497 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
4498 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
4499 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}
4500};
4501
4502static struct cdns_torrent_vals sl_pcie_100_int_ssc_cmn_vals = {
4503 .reg_pairs = sl_pcie_100_int_ssc_cmn_regs,
4504 .num_regs = ARRAY_SIZE(sl_pcie_100_int_ssc_cmn_regs),
4505};
4506
4507/* PCIe, 100 MHz Ref clk, no SSC & external SSC */
4508static struct cdns_reg_pairs pcie_100_ext_no_ssc_cmn_regs[] = {
4509 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
4510 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},
4511 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0}
4512};
4513
4514static struct cdns_reg_pairs pcie_100_ext_no_ssc_rx_ln_regs[] = {
4515 {0x0019, RX_REE_TAP1_CLIP},
4516 {0x0019, RX_REE_TAP2TON_CLIP},
4517 {0x0001, RX_DIAG_ACYA}
4518};
4519
4520static struct cdns_torrent_vals pcie_100_no_ssc_cmn_vals = {
4521 .reg_pairs = pcie_100_ext_no_ssc_cmn_regs,
4522 .num_regs = ARRAY_SIZE(pcie_100_ext_no_ssc_cmn_regs),
4523};
4524
4525static struct cdns_torrent_vals pcie_100_no_ssc_rx_ln_vals = {
4526 .reg_pairs = pcie_100_ext_no_ssc_rx_ln_regs,
4527 .num_regs = ARRAY_SIZE(pcie_100_ext_no_ssc_rx_ln_regs),
4528};
4529
4530static struct cdns_torrent_vals_entry link_cmn_vals_entries[] = {
4531 {CDNS_TORRENT_KEY_ANYCLK(TYPE_DP, TYPE_NONE), &sl_dp_link_cmn_vals},
4532 {CDNS_TORRENT_KEY_ANYCLK(TYPE_DP, TYPE_PCIE), &pcie_dp_link_cmn_vals},
4533 {CDNS_TORRENT_KEY_ANYCLK(TYPE_DP, TYPE_USB), &usb_dp_link_cmn_vals},
4534
4535 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_NONE), NULL},
4536 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_SGMII), &pcie_sgmii_link_cmn_vals},
4537 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_QSGMII), &pcie_sgmii_link_cmn_vals},
4538 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USB), &pcie_usb_link_cmn_vals},
4539 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_DP), &pcie_dp_link_cmn_vals},
4540 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USXGMII), &pcie_usxgmii_link_cmn_vals},
4541
4542 {CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_NONE), &sl_sgmii_link_cmn_vals},
4543 {CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_PCIE), &pcie_sgmii_link_cmn_vals},
4544 {CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_USB), &usb_sgmii_link_cmn_vals},
4545 {CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_USXGMII), &usxgmii_sgmii_link_cmn_vals},
4546
4547 {CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_NONE), &sl_sgmii_link_cmn_vals},
4548 {CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_PCIE), &pcie_sgmii_link_cmn_vals},
4549 {CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_USB), &usb_sgmii_link_cmn_vals},
4550 {CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_USXGMII), &usxgmii_sgmii_link_cmn_vals},
4551
4552 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_NONE), &sl_usb_link_cmn_vals},
4553 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_PCIE), &pcie_usb_link_cmn_vals},
4554 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_SGMII), &usb_sgmii_link_cmn_vals},
4555 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_QSGMII), &usb_sgmii_link_cmn_vals},
4556 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_DP), &usb_dp_link_cmn_vals},
4557
4558 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_NONE), &sl_usxgmii_link_cmn_vals},
4559 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_PCIE), &pcie_usxgmii_link_cmn_vals},
4560 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_SGMII), &usxgmii_sgmii_link_cmn_vals},
4561 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_QSGMII), &usxgmii_sgmii_link_cmn_vals},
4562};
4563
4564static struct cdns_torrent_vals_entry xcvr_diag_vals_entries[] = {
4565 {CDNS_TORRENT_KEY_ANYCLK(TYPE_DP, TYPE_NONE), &sl_dp_xcvr_diag_ln_vals},
4566 {CDNS_TORRENT_KEY_ANYCLK(TYPE_DP, TYPE_PCIE), &dp_pcie_xcvr_diag_ln_vals},
4567 {CDNS_TORRENT_KEY_ANYCLK(TYPE_DP, TYPE_USB), &dp_usb_xcvr_diag_ln_vals},
4568
4569 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_NONE), NULL},
4570 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_SGMII), &pcie_sgmii_xcvr_diag_ln_vals},
4571 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_QSGMII), &pcie_sgmii_xcvr_diag_ln_vals},
4572 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USB), &pcie_usb_xcvr_diag_ln_vals},
4573 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_DP), &pcie_dp_xcvr_diag_ln_vals},
4574 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USXGMII), &pcie_usxgmii_xcvr_diag_ln_vals},
4575
4576 {CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_NONE), &sl_sgmii_xcvr_diag_ln_vals},
4577 {CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_PCIE), &sgmii_pcie_xcvr_diag_ln_vals},
4578 {CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_USB), &sgmii_usb_xcvr_diag_ln_vals},
4579 {CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_USXGMII), &sgmii_usxgmii_xcvr_diag_ln_vals},
4580
4581 {CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_NONE), &sl_sgmii_xcvr_diag_ln_vals},
4582 {CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_PCIE), &sgmii_pcie_xcvr_diag_ln_vals},
4583 {CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_USB), &sgmii_usb_xcvr_diag_ln_vals},
4584 {CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_USXGMII), &sgmii_usxgmii_xcvr_diag_ln_vals},
4585
4586 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_NONE), &sl_usb_xcvr_diag_ln_vals},
4587 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_PCIE), &usb_pcie_xcvr_diag_ln_vals},
4588 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_SGMII), &usb_sgmii_xcvr_diag_ln_vals},
4589 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_QSGMII), &usb_sgmii_xcvr_diag_ln_vals},
4590 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_DP), &usb_dp_xcvr_diag_ln_vals},
4591
4592 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_NONE), &sl_usxgmii_xcvr_diag_ln_vals},
4593 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_PCIE), &usxgmii_pcie_xcvr_diag_ln_vals},
4594 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_SGMII), &usxgmii_sgmii_xcvr_diag_ln_vals},
4595 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_QSGMII), &usxgmii_sgmii_xcvr_diag_ln_vals},
4596};
4597
4598static struct cdns_torrent_vals_entry pcs_cmn_vals_entries[] = {
4599 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_NONE), &usb_phy_pcs_cmn_vals},
4600 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_PCIE), &usb_phy_pcs_cmn_vals},
4601 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_SGMII), &usb_phy_pcs_cmn_vals},
4602 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_QSGMII), &usb_phy_pcs_cmn_vals},
4603 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_DP), &usb_phy_pcs_cmn_vals},
4604};
4605
4606static struct cdns_torrent_vals_entry cmn_vals_entries[] = {
4607 {CDNS_TORRENT_KEY(CLK_19_2_MHZ, CLK_19_2_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_19_2_no_ssc_cmn_vals},
4608 {CDNS_TORRENT_KEY(CLK_25_MHZ, CLK_25_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_25_no_ssc_cmn_vals},
4609
4610 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_100_no_ssc_cmn_vals},
4611 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_PCIE, NO_SSC), &dp_100_no_ssc_cmn_vals},
4612 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_USB, NO_SSC), &sl_dp_100_no_ssc_cmn_vals},
4613
4614 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, NO_SSC), NULL},
4615 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL},
4616 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), &sl_pcie_100_int_ssc_cmn_vals},
4617
4618 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), &pcie_100_no_ssc_cmn_vals},
4619 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), &pcie_100_no_ssc_cmn_vals},
4620 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), &pcie_100_int_ssc_cmn_vals},
4621
4622 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, NO_SSC), &pcie_100_no_ssc_cmn_vals},
4623 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, EXTERNAL_SSC), &pcie_100_no_ssc_cmn_vals},
4624 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, INTERNAL_SSC), &pcie_100_int_ssc_cmn_vals},
4625
4626 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, NO_SSC), &pcie_100_no_ssc_cmn_vals},
4627 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, EXTERNAL_SSC), &pcie_100_no_ssc_cmn_vals},
4628 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, INTERNAL_SSC), &pcie_100_int_ssc_cmn_vals},
4629
4630 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), NULL},
4631
4632 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &sl_sgmii_100_no_ssc_cmn_vals},
4633
4634 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, NO_SSC), &sgmii_100_no_ssc_cmn_vals},
4635 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, EXTERNAL_SSC), &sgmii_100_no_ssc_cmn_vals},
4636 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, INTERNAL_SSC), &sgmii_100_int_ssc_cmn_vals},
4637
4638 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, NO_SSC), &sgmii_100_no_ssc_cmn_vals},
4639 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, EXTERNAL_SSC), &sgmii_100_no_ssc_cmn_vals},
4640 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, INTERNAL_SSC), &sgmii_100_no_ssc_cmn_vals},
4641
4642 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_NONE, NO_SSC), &sl_qsgmii_100_no_ssc_cmn_vals},
4643
4644 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, NO_SSC), &qsgmii_100_no_ssc_cmn_vals},
4645 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, EXTERNAL_SSC), &qsgmii_100_no_ssc_cmn_vals},
4646 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, INTERNAL_SSC), &qsgmii_100_int_ssc_cmn_vals},
4647
4648 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, NO_SSC), &qsgmii_100_no_ssc_cmn_vals},
4649 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, EXTERNAL_SSC), &qsgmii_100_no_ssc_cmn_vals},
4650 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, INTERNAL_SSC), &qsgmii_100_no_ssc_cmn_vals},
4651
4652 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, NO_SSC), &sl_usb_100_no_ssc_cmn_vals},
4653 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, EXTERNAL_SSC), &sl_usb_100_no_ssc_cmn_vals},
4654 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, INTERNAL_SSC), &sl_usb_100_int_ssc_cmn_vals},
4655
4656 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, NO_SSC), &usb_100_no_ssc_cmn_vals},
4657 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_cmn_vals},
4658 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_int_ssc_cmn_vals},
4659
4660 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &sl_usb_100_no_ssc_cmn_vals},
4661 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &sl_usb_100_no_ssc_cmn_vals},
4662 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, INTERNAL_SSC), &sl_usb_100_int_ssc_cmn_vals},
4663
4664 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, NO_SSC), &sl_usb_100_no_ssc_cmn_vals},
4665 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, EXTERNAL_SSC), &sl_usb_100_no_ssc_cmn_vals},
4666 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, INTERNAL_SSC), &sl_usb_100_int_ssc_cmn_vals},
4667
4668 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_cmn_vals},
4669
4670 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &sl_usxgmii_156_25_no_ssc_cmn_vals},
4671
4672 /* Dual refclk */
4673 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_PCIE, TYPE_USXGMII, NO_SSC), NULL},
4674
4675 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_SGMII, TYPE_USXGMII, NO_SSC), &ml_sgmii_pll1_100_no_ssc_cmn_vals},
4676
4677 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_QSGMII, TYPE_USXGMII, NO_SSC), &ml_sgmii_pll1_100_no_ssc_cmn_vals},
4678
4679 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_PCIE, NO_SSC), &ml_usxgmii_pll1_156_25_no_ssc_cmn_vals},
4680 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_SGMII, NO_SSC), &ml_usxgmii_pll0_156_25_no_ssc_cmn_vals},
4681 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_QSGMII, NO_SSC), &ml_usxgmii_pll0_156_25_no_ssc_cmn_vals},
4682};
4683
4684static struct cdns_torrent_vals_entry cdns_tx_ln_vals_entries[] = {
4685 {CDNS_TORRENT_KEY(CLK_19_2_MHZ, CLK_19_2_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_19_2_no_ssc_tx_ln_vals},
4686 {CDNS_TORRENT_KEY(CLK_25_MHZ, CLK_25_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_25_no_ssc_tx_ln_vals},
4687
4688 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_100_no_ssc_tx_ln_vals},
4689 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_PCIE, NO_SSC), &dp_100_no_ssc_tx_ln_vals},
4690 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_USB, NO_SSC), &dp_100_no_ssc_tx_ln_vals},
4691
4692 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, NO_SSC), NULL},
4693 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL},
4694 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), NULL},
4695
4696 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), NULL},
4697 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), NULL},
4698 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), NULL},
4699
4700 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, NO_SSC), NULL},
4701 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, EXTERNAL_SSC), NULL},
4702 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, INTERNAL_SSC), NULL},
4703
4704 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, NO_SSC), NULL},
4705 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, EXTERNAL_SSC), NULL},
4706 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, INTERNAL_SSC), NULL},
4707
4708 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), NULL},
4709
4710 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &sgmii_100_no_ssc_tx_ln_vals},
4711
4712 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, NO_SSC), &sgmii_100_no_ssc_tx_ln_vals},
4713 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, EXTERNAL_SSC), &sgmii_100_no_ssc_tx_ln_vals},
4714 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, INTERNAL_SSC), &sgmii_100_no_ssc_tx_ln_vals},
4715
4716 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, NO_SSC), &sgmii_100_no_ssc_tx_ln_vals},
4717 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, EXTERNAL_SSC), &sgmii_100_no_ssc_tx_ln_vals},
4718 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, INTERNAL_SSC), &sgmii_100_no_ssc_tx_ln_vals},
4719
4720 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_NONE, NO_SSC), &qsgmii_100_no_ssc_tx_ln_vals},
4721
4722 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, NO_SSC), &qsgmii_100_no_ssc_tx_ln_vals},
4723 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, EXTERNAL_SSC), &qsgmii_100_no_ssc_tx_ln_vals},
4724 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, INTERNAL_SSC), &qsgmii_100_no_ssc_tx_ln_vals},
4725
4726 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, NO_SSC), &qsgmii_100_no_ssc_tx_ln_vals},
4727 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, EXTERNAL_SSC), &qsgmii_100_no_ssc_tx_ln_vals},
4728 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, INTERNAL_SSC), &qsgmii_100_no_ssc_tx_ln_vals},
4729
4730 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
4731 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4732 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4733
4734 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
4735 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4736 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4737
4738 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
4739 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4740 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4741
4742 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
4743 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4744 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4745
4746 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
4747
4748 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &usxgmii_156_25_no_ssc_tx_ln_vals},
4749
4750 /* Dual refclk */
4751 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_PCIE, TYPE_USXGMII, NO_SSC), NULL},
4752
4753 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_SGMII, TYPE_USXGMII, NO_SSC), &sgmii_100_no_ssc_tx_ln_vals},
4754
4755 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_QSGMII, TYPE_USXGMII, NO_SSC), &qsgmii_100_no_ssc_tx_ln_vals},
4756
4757 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_PCIE, NO_SSC), &ml_usxgmii_156_25_no_ssc_tx_ln_vals},
4758 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_SGMII, NO_SSC), &ml_usxgmii_156_25_no_ssc_tx_ln_vals},
4759 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_QSGMII, NO_SSC), &ml_usxgmii_156_25_no_ssc_tx_ln_vals},
4760};
4761
4762static struct cdns_torrent_vals_entry cdns_rx_ln_vals_entries[] = {
4763 {CDNS_TORRENT_KEY(CLK_19_2_MHZ, CLK_19_2_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_19_2_no_ssc_rx_ln_vals},
4764 {CDNS_TORRENT_KEY(CLK_25_MHZ, CLK_25_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_25_no_ssc_rx_ln_vals},
4765
4766 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_100_no_ssc_rx_ln_vals},
4767 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_PCIE, NO_SSC), &dp_100_no_ssc_rx_ln_vals},
4768 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_USB, NO_SSC), &dp_100_no_ssc_rx_ln_vals},
4769
4770 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
4771 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
4772 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
4773
4774 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
4775 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
4776 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
4777
4778 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
4779 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
4780 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
4781
4782 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
4783 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
4784 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
4785
4786 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
4787
4788 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals},
4789
4790 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals},
4791 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, EXTERNAL_SSC), &sgmii_100_no_ssc_rx_ln_vals},
4792 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, INTERNAL_SSC), &sgmii_100_no_ssc_rx_ln_vals},
4793
4794 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals},
4795 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, EXTERNAL_SSC), &sgmii_100_no_ssc_rx_ln_vals},
4796 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, INTERNAL_SSC), &sgmii_100_no_ssc_rx_ln_vals},
4797
4798 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_NONE, NO_SSC), &qsgmii_100_no_ssc_rx_ln_vals},
4799
4800 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, NO_SSC), &qsgmii_100_no_ssc_rx_ln_vals},
4801 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, EXTERNAL_SSC), &qsgmii_100_no_ssc_rx_ln_vals},
4802 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, INTERNAL_SSC), &qsgmii_100_no_ssc_rx_ln_vals},
4803
4804 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, NO_SSC), &qsgmii_100_no_ssc_rx_ln_vals},
4805 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, EXTERNAL_SSC), &qsgmii_100_no_ssc_rx_ln_vals},
4806 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, INTERNAL_SSC), &qsgmii_100_no_ssc_rx_ln_vals},
4807
4808 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, NO_SSC), &usb_100_no_ssc_rx_ln_vals},
4809 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
4810 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
4811
4812 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, NO_SSC), &usb_100_no_ssc_rx_ln_vals},
4813 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
4814 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
4815
4816 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &usb_100_no_ssc_rx_ln_vals},
4817 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
4818 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
4819
4820 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, NO_SSC), &usb_100_no_ssc_rx_ln_vals},
4821 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
4822 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
4823
4824 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_rx_ln_vals},
4825
4826 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &usxgmii_156_25_no_ssc_rx_ln_vals},
4827
4828 /* Dual refclk */
4829 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_PCIE, TYPE_USXGMII, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
4830
4831 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_SGMII, TYPE_USXGMII, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals},
4832
4833 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_QSGMII, TYPE_USXGMII, NO_SSC), &qsgmii_100_no_ssc_rx_ln_vals},
4834
4835 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_PCIE, NO_SSC), &ml_usxgmii_156_25_no_ssc_rx_ln_vals},
4836 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_SGMII, NO_SSC), &ml_usxgmii_156_25_no_ssc_rx_ln_vals},
4837 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_QSGMII, NO_SSC), &ml_usxgmii_156_25_no_ssc_rx_ln_vals},
4838};
4839
4840static const struct cdns_torrent_data cdns_map_torrent = {
4841 .block_offset_shift = 0x2,
4842 .reg_offset_shift = 0x2,
4843 .link_cmn_vals_tbl = {
4844 .entries = link_cmn_vals_entries,
4845 .num_entries = ARRAY_SIZE(link_cmn_vals_entries),
4846 },
4847 .xcvr_diag_vals_tbl = {
4848 .entries = xcvr_diag_vals_entries,
4849 .num_entries = ARRAY_SIZE(xcvr_diag_vals_entries),
4850 },
4851 .pcs_cmn_vals_tbl = {
4852 .entries = pcs_cmn_vals_entries,
4853 .num_entries = ARRAY_SIZE(pcs_cmn_vals_entries),
4854 },
4855 .cmn_vals_tbl = {
4856 .entries = cmn_vals_entries,
4857 .num_entries = ARRAY_SIZE(cmn_vals_entries),
4858 },
4859 .tx_ln_vals_tbl = {
4860 .entries = cdns_tx_ln_vals_entries,
4861 .num_entries = ARRAY_SIZE(cdns_tx_ln_vals_entries),
4862 },
4863 .rx_ln_vals_tbl = {
4864 .entries = cdns_rx_ln_vals_entries,
4865 .num_entries = ARRAY_SIZE(cdns_rx_ln_vals_entries),
4866 },
4867};
4868
4869static struct cdns_torrent_vals_entry j721e_phy_pma_cmn_vals_entries[] = {
4870 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_NONE), &ti_usxgmii_phy_pma_cmn_vals},
4871 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_PCIE), &ti_usxgmii_phy_pma_cmn_vals},
4872 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_SGMII), &ti_usxgmii_phy_pma_cmn_vals},
4873 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_QSGMII), &ti_usxgmii_phy_pma_cmn_vals},
4874};
4875
4876static struct cdns_torrent_vals_entry ti_tx_ln_vals_entries[] = {
4877 {CDNS_TORRENT_KEY(CLK_19_2_MHZ, CLK_19_2_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_19_2_no_ssc_tx_ln_vals},
4878 {CDNS_TORRENT_KEY(CLK_25_MHZ, CLK_25_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_25_no_ssc_tx_ln_vals},
4879
4880 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_100_no_ssc_tx_ln_vals},
4881 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_PCIE, NO_SSC), &dp_100_no_ssc_tx_ln_vals},
4882 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_USB, NO_SSC), &dp_100_no_ssc_tx_ln_vals},
4883
4884 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, NO_SSC), NULL},
4885 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL},
4886 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), NULL},
4887
4888 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), NULL},
4889 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), NULL},
4890 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), NULL},
4891
4892 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, NO_SSC), NULL},
4893 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, EXTERNAL_SSC), NULL},
4894 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, INTERNAL_SSC), NULL},
4895
4896 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, NO_SSC), NULL},
4897 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, EXTERNAL_SSC), NULL},
4898 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, INTERNAL_SSC), NULL},
4899
4900 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), NULL},
4901
4902 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},
4903
4904 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},
4905 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, EXTERNAL_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},
4906 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, INTERNAL_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},
4907
4908 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},
4909 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, EXTERNAL_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},
4910 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, INTERNAL_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},
4911
4912 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_NONE, NO_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},
4913
4914 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, NO_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},
4915 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, EXTERNAL_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},
4916 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, INTERNAL_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},
4917
4918 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, NO_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},
4919 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, EXTERNAL_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},
4920 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, INTERNAL_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},
4921
4922 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
4923 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4924 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4925
4926 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
4927 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4928 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4929
4930 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
4931 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4932 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4933
4934 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
4935 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4936 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4937
4938 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
4939
4940 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &usxgmii_156_25_no_ssc_tx_ln_vals},
4941
4942 /* Dual refclk */
4943 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_PCIE, TYPE_USXGMII, NO_SSC), NULL},
4944
4945 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_SGMII, TYPE_USXGMII, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},
4946
4947 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_QSGMII, TYPE_USXGMII, NO_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},
4948
4949 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_PCIE, NO_SSC), &ml_usxgmii_156_25_no_ssc_tx_ln_vals},
4950 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_SGMII, NO_SSC), &ml_usxgmii_156_25_no_ssc_tx_ln_vals},
4951 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_QSGMII, NO_SSC), &ml_usxgmii_156_25_no_ssc_tx_ln_vals},
4952};
4953
4954static const struct cdns_torrent_data ti_j721e_map_torrent = {
4955 .block_offset_shift = 0x0,
4956 .reg_offset_shift = 0x1,
4957 .link_cmn_vals_tbl = {
4958 .entries = link_cmn_vals_entries,
4959 .num_entries = ARRAY_SIZE(link_cmn_vals_entries),
4960 },
4961 .xcvr_diag_vals_tbl = {
4962 .entries = xcvr_diag_vals_entries,
4963 .num_entries = ARRAY_SIZE(xcvr_diag_vals_entries),
4964 },
4965 .pcs_cmn_vals_tbl = {
4966 .entries = pcs_cmn_vals_entries,
4967 .num_entries = ARRAY_SIZE(pcs_cmn_vals_entries),
4968 },
4969 .phy_pma_cmn_vals_tbl = {
4970 .entries = j721e_phy_pma_cmn_vals_entries,
4971 .num_entries = ARRAY_SIZE(j721e_phy_pma_cmn_vals_entries),
4972 },
4973 .cmn_vals_tbl = {
4974 .entries = cmn_vals_entries,
4975 .num_entries = ARRAY_SIZE(cmn_vals_entries),
4976 },
4977 .tx_ln_vals_tbl = {
4978 .entries = ti_tx_ln_vals_entries,
4979 .num_entries = ARRAY_SIZE(ti_tx_ln_vals_entries),
4980 },
4981 .rx_ln_vals_tbl = {
4982 .entries = cdns_rx_ln_vals_entries,
4983 .num_entries = ARRAY_SIZE(cdns_rx_ln_vals_entries),
4984 },
4985};
4986
4987/* TI J7200 (Torrent SD0805) */
4988static struct cdns_torrent_vals_entry ti_j7200_cmn_vals_entries[] = {
4989 {CDNS_TORRENT_KEY(CLK_19_2_MHZ, CLK_19_2_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_19_2_no_ssc_cmn_vals},
4990 {CDNS_TORRENT_KEY(CLK_25_MHZ, CLK_25_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_25_no_ssc_cmn_vals},
4991
4992 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_100_no_ssc_cmn_vals},
4993 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_PCIE, NO_SSC), &dp_100_no_ssc_cmn_vals},
4994 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_USB, NO_SSC), &sl_dp_100_no_ssc_cmn_vals},
4995
4996 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, NO_SSC), NULL},
4997 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL},
4998 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), &sl_pcie_100_int_ssc_cmn_vals},
4999
5000 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), &pcie_100_no_ssc_cmn_vals},
5001 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), &pcie_100_no_ssc_cmn_vals},
5002 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), &pcie_100_int_ssc_cmn_vals},
5003
5004 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, NO_SSC), &pcie_100_no_ssc_cmn_vals},
5005 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, EXTERNAL_SSC), &pcie_100_no_ssc_cmn_vals},
5006 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, INTERNAL_SSC), &pcie_100_int_ssc_cmn_vals},
5007
5008 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, NO_SSC), &pcie_100_no_ssc_cmn_vals},
5009 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, EXTERNAL_SSC), &pcie_100_no_ssc_cmn_vals},
5010 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, INTERNAL_SSC), &pcie_100_int_ssc_cmn_vals},
5011
5012 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), NULL},
5013
5014 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &sl_sgmii_100_no_ssc_cmn_vals},
5015
5016 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, NO_SSC), &sgmii_100_no_ssc_cmn_vals},
5017 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, EXTERNAL_SSC), &sgmii_100_no_ssc_cmn_vals},
5018 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, INTERNAL_SSC), &sgmii_100_int_ssc_cmn_vals},
5019
5020 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, NO_SSC), &sgmii_100_no_ssc_cmn_vals},
5021 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, EXTERNAL_SSC), &sgmii_100_no_ssc_cmn_vals},
5022 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, INTERNAL_SSC), &sgmii_100_no_ssc_cmn_vals},
5023
5024 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_NONE, NO_SSC), &sl_qsgmii_100_no_ssc_cmn_vals},
5025
5026 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, NO_SSC), &qsgmii_100_no_ssc_cmn_vals},
5027 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, EXTERNAL_SSC), &qsgmii_100_no_ssc_cmn_vals},
5028 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, INTERNAL_SSC), &qsgmii_100_int_ssc_cmn_vals},
5029
5030 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, NO_SSC), &qsgmii_100_no_ssc_cmn_vals},
5031 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, EXTERNAL_SSC), &qsgmii_100_no_ssc_cmn_vals},
5032 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, INTERNAL_SSC), &qsgmii_100_no_ssc_cmn_vals},
5033
5034 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, NO_SSC), &sl_usb_100_no_ssc_cmn_vals},
5035 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, EXTERNAL_SSC), &sl_usb_100_no_ssc_cmn_vals},
5036 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, INTERNAL_SSC), &sl_usb_100_int_ssc_cmn_vals},
5037
5038 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, NO_SSC), &usb_100_no_ssc_cmn_vals},
5039 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_cmn_vals},
5040 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_int_ssc_cmn_vals},
5041
5042 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &sl_usb_100_no_ssc_cmn_vals},
5043 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &sl_usb_100_no_ssc_cmn_vals},
5044 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, INTERNAL_SSC), &sl_usb_100_int_ssc_cmn_vals},
5045
5046 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, NO_SSC), &sl_usb_100_no_ssc_cmn_vals},
5047 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, EXTERNAL_SSC), &sl_usb_100_no_ssc_cmn_vals},
5048 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, INTERNAL_SSC), &sl_usb_100_int_ssc_cmn_vals},
5049
5050 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_cmn_vals},
5051
5052 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &sl_usxgmii_156_25_no_ssc_cmn_vals},
5053
5054 /* Dual refclk */
5055 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_PCIE, TYPE_USXGMII, NO_SSC), NULL},
5056
5057 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_SGMII, TYPE_USXGMII, NO_SSC), &j7200_ml_sgmii_pll1_100_no_ssc_cmn_vals},
5058
5059 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_QSGMII, TYPE_USXGMII, NO_SSC), &j7200_ml_sgmii_pll1_100_no_ssc_cmn_vals},
5060
5061 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_PCIE, NO_SSC), &ml_usxgmii_pll1_156_25_no_ssc_cmn_vals},
5062 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_SGMII, NO_SSC), &j7200_ml_usxgmii_pll0_156_25_no_ssc_cmn_vals},
5063 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_QSGMII, NO_SSC), &j7200_ml_usxgmii_pll0_156_25_no_ssc_cmn_vals},
5064};
5065
5066static struct cdns_torrent_vals_entry ti_j7200_tx_ln_vals_entries[] = {
5067 {CDNS_TORRENT_KEY(CLK_19_2_MHZ, CLK_19_2_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_19_2_no_ssc_tx_ln_vals},
5068 {CDNS_TORRENT_KEY(CLK_25_MHZ, CLK_25_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_25_no_ssc_tx_ln_vals},
5069
5070 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_100_no_ssc_tx_ln_vals},
5071 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_PCIE, NO_SSC), &dp_100_no_ssc_tx_ln_vals},
5072 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_USB, NO_SSC), &dp_100_no_ssc_tx_ln_vals},
5073
5074 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, NO_SSC), NULL},
5075 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL},
5076 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), NULL},
5077
5078 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), NULL},
5079 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), NULL},
5080 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), NULL},
5081
5082 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, NO_SSC), NULL},
5083 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, EXTERNAL_SSC), NULL},
5084 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, INTERNAL_SSC), NULL},
5085
5086 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, NO_SSC), NULL},
5087 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, EXTERNAL_SSC), NULL},
5088 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, INTERNAL_SSC), NULL},
5089
5090 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), NULL},
5091
5092 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},
5093
5094 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},
5095 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, EXTERNAL_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},
5096 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, INTERNAL_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},
5097
5098 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},
5099 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, EXTERNAL_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},
5100 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, INTERNAL_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},
5101
5102 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_NONE, NO_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},
5103
5104 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, NO_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},
5105 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, EXTERNAL_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},
5106 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, INTERNAL_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},
5107
5108 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, NO_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},
5109 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, EXTERNAL_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},
5110 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, INTERNAL_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},
5111
5112 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
5113 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
5114 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
5115
5116 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
5117 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
5118 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
5119
5120 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
5121 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
5122 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
5123
5124 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
5125 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
5126 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
5127
5128 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
5129
5130 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &usxgmii_156_25_no_ssc_tx_ln_vals},
5131
5132 /* Dual refclk */
5133 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_PCIE, TYPE_USXGMII, NO_SSC), NULL},
5134
5135 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_SGMII, TYPE_USXGMII, NO_SSC), &j7200_sgmii_100_no_ssc_tx_ln_vals},
5136
5137 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_QSGMII, TYPE_USXGMII, NO_SSC), &j7200_qsgmii_100_no_ssc_tx_ln_vals},
5138
5139 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_PCIE, NO_SSC), &ml_usxgmii_156_25_no_ssc_tx_ln_vals},
5140 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_SGMII, NO_SSC), &usxgmii_156_25_no_ssc_tx_ln_vals},
5141 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_QSGMII, NO_SSC), &usxgmii_156_25_no_ssc_tx_ln_vals},
5142};
5143
5144static struct cdns_torrent_vals_entry ti_j7200_rx_ln_vals_entries[] = {
5145 {CDNS_TORRENT_KEY(CLK_19_2_MHZ, CLK_19_2_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_19_2_no_ssc_rx_ln_vals},
5146 {CDNS_TORRENT_KEY(CLK_25_MHZ, CLK_25_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_25_no_ssc_rx_ln_vals},
5147
5148 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_100_no_ssc_rx_ln_vals},
5149 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_PCIE, NO_SSC), &dp_100_no_ssc_rx_ln_vals},
5150 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_USB, NO_SSC), &dp_100_no_ssc_rx_ln_vals},
5151
5152 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
5153 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
5154 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
5155
5156 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
5157 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
5158 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
5159
5160 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
5161 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
5162 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
5163
5164 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
5165 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
5166 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
5167
5168 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
5169
5170 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals},
5171
5172 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals},
5173 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, EXTERNAL_SSC), &sgmii_100_no_ssc_rx_ln_vals},
5174 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, INTERNAL_SSC), &sgmii_100_no_ssc_rx_ln_vals},
5175
5176 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals},
5177 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, EXTERNAL_SSC), &sgmii_100_no_ssc_rx_ln_vals},
5178 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, INTERNAL_SSC), &sgmii_100_no_ssc_rx_ln_vals},
5179
5180 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_NONE, NO_SSC), &qsgmii_100_no_ssc_rx_ln_vals},
5181
5182 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, NO_SSC), &qsgmii_100_no_ssc_rx_ln_vals},
5183 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, EXTERNAL_SSC), &qsgmii_100_no_ssc_rx_ln_vals},
5184 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, INTERNAL_SSC), &qsgmii_100_no_ssc_rx_ln_vals},
5185
5186 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, NO_SSC), &qsgmii_100_no_ssc_rx_ln_vals},
5187 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, EXTERNAL_SSC), &qsgmii_100_no_ssc_rx_ln_vals},
5188 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, INTERNAL_SSC), &qsgmii_100_no_ssc_rx_ln_vals},
5189
5190 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, NO_SSC), &usb_100_no_ssc_rx_ln_vals},
5191 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
5192 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
5193
5194 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, NO_SSC), &usb_100_no_ssc_rx_ln_vals},
5195 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
5196 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
5197
5198 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &usb_100_no_ssc_rx_ln_vals},
5199 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
5200 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
5201
5202 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, NO_SSC), &usb_100_no_ssc_rx_ln_vals},
5203 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
5204 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
5205
5206 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_rx_ln_vals},
5207
5208 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &usxgmii_156_25_no_ssc_rx_ln_vals},
5209
5210 /* Dual refclk */
5211 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_PCIE, TYPE_USXGMII, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
5212
5213 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_SGMII, TYPE_USXGMII, NO_SSC), &j7200_sgmii_100_no_ssc_rx_ln_vals},
5214
5215 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_QSGMII, TYPE_USXGMII, NO_SSC), &j7200_qsgmii_100_no_ssc_rx_ln_vals},
5216
5217 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_PCIE, NO_SSC), &ml_usxgmii_156_25_no_ssc_rx_ln_vals},
5218 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_SGMII, NO_SSC), &usxgmii_156_25_no_ssc_rx_ln_vals},
5219 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_QSGMII, NO_SSC), &usxgmii_156_25_no_ssc_rx_ln_vals},
5220};
5221
5222static const struct cdns_torrent_data ti_j7200_map_torrent = {
5223 .block_offset_shift = 0x0,
5224 .reg_offset_shift = 0x1,
5225 .link_cmn_vals_tbl = {
5226 .entries = link_cmn_vals_entries,
5227 .num_entries = ARRAY_SIZE(link_cmn_vals_entries),
5228 },
5229 .xcvr_diag_vals_tbl = {
5230 .entries = xcvr_diag_vals_entries,
5231 .num_entries = ARRAY_SIZE(xcvr_diag_vals_entries),
5232 },
5233 .pcs_cmn_vals_tbl = {
5234 .entries = pcs_cmn_vals_entries,
5235 .num_entries = ARRAY_SIZE(pcs_cmn_vals_entries),
5236 },
5237 .phy_pma_cmn_vals_tbl = {
5238 .entries = j721e_phy_pma_cmn_vals_entries,
5239 .num_entries = ARRAY_SIZE(j721e_phy_pma_cmn_vals_entries),
5240 },
5241 .cmn_vals_tbl = {
5242 .entries = ti_j7200_cmn_vals_entries,
5243 .num_entries = ARRAY_SIZE(ti_j7200_cmn_vals_entries),
5244 },
5245 .tx_ln_vals_tbl = {
5246 .entries = ti_j7200_tx_ln_vals_entries,
5247 .num_entries = ARRAY_SIZE(ti_j7200_tx_ln_vals_entries),
5248 },
5249 .rx_ln_vals_tbl = {
5250 .entries = ti_j7200_rx_ln_vals_entries,
5251 .num_entries = ARRAY_SIZE(ti_j7200_rx_ln_vals_entries),
5252 },
5253};
5254
5255static const struct of_device_id cdns_torrent_phy_of_match[] = {
5256 {
5257 .compatible = "cdns,torrent-phy",
5258 .data = &cdns_map_torrent,
5259 },
5260 {
5261 .compatible = "ti,j721e-serdes-10g",
5262 .data = &ti_j721e_map_torrent,
5263 },
5264 {
5265 .compatible = "ti,j7200-serdes-10g",
5266 .data = &ti_j7200_map_torrent,
5267 },
5268 {}
5269};
5270MODULE_DEVICE_TABLE(of, cdns_torrent_phy_of_match);
5271
5272static struct platform_driver cdns_torrent_phy_driver = {
5273 .probe = cdns_torrent_phy_probe,
5274 .remove_new = cdns_torrent_phy_remove,
5275 .driver = {
5276 .name = "cdns-torrent-phy",
5277 .of_match_table = cdns_torrent_phy_of_match,
5278 }
5279};
5280module_platform_driver(cdns_torrent_phy_driver);
5281
5282MODULE_AUTHOR("Cadence Design Systems, Inc.");
5283MODULE_DESCRIPTION("Cadence Torrent PHY driver");
5284MODULE_LICENSE("GPL v2");