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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * tc358767 eDP bridge driver
4 *
5 * Copyright (C) 2016 CogentEmbedded Inc
6 * Author: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
7 *
8 * Copyright (C) 2016 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de>
9 *
10 * Copyright (C) 2016 Zodiac Inflight Innovations
11 *
12 * Initially based on: drivers/gpu/drm/i2c/tda998x_drv.c
13 *
14 * Copyright (C) 2012 Texas Instruments
15 * Author: Rob Clark <robdclark@gmail.com>
16 */
17
18#include <linux/bitfield.h>
19#include <linux/clk.h>
20#include <linux/device.h>
21#include <linux/gpio/consumer.h>
22#include <linux/i2c.h>
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/regmap.h>
26#include <linux/slab.h>
27
28#include <drm/drm_atomic_helper.h>
29#include <drm/drm_bridge.h>
30#include <drm/drm_dp_helper.h>
31#include <drm/drm_edid.h>
32#include <drm/drm_of.h>
33#include <drm/drm_panel.h>
34#include <drm/drm_print.h>
35#include <drm/drm_probe_helper.h>
36
37/* Registers */
38
39/* Display Parallel Interface */
40#define DPIPXLFMT 0x0440
41#define VS_POL_ACTIVE_LOW (1 << 10)
42#define HS_POL_ACTIVE_LOW (1 << 9)
43#define DE_POL_ACTIVE_HIGH (0 << 8)
44#define SUB_CFG_TYPE_CONFIG1 (0 << 2) /* LSB aligned */
45#define SUB_CFG_TYPE_CONFIG2 (1 << 2) /* Loosely Packed */
46#define SUB_CFG_TYPE_CONFIG3 (2 << 2) /* LSB aligned 8-bit */
47#define DPI_BPP_RGB888 (0 << 0)
48#define DPI_BPP_RGB666 (1 << 0)
49#define DPI_BPP_RGB565 (2 << 0)
50
51/* Video Path */
52#define VPCTRL0 0x0450
53#define VSDELAY GENMASK(31, 20)
54#define OPXLFMT_RGB666 (0 << 8)
55#define OPXLFMT_RGB888 (1 << 8)
56#define FRMSYNC_DISABLED (0 << 4) /* Video Timing Gen Disabled */
57#define FRMSYNC_ENABLED (1 << 4) /* Video Timing Gen Enabled */
58#define MSF_DISABLED (0 << 0) /* Magic Square FRC disabled */
59#define MSF_ENABLED (1 << 0) /* Magic Square FRC enabled */
60#define HTIM01 0x0454
61#define HPW GENMASK(8, 0)
62#define HBPR GENMASK(24, 16)
63#define HTIM02 0x0458
64#define HDISPR GENMASK(10, 0)
65#define HFPR GENMASK(24, 16)
66#define VTIM01 0x045c
67#define VSPR GENMASK(7, 0)
68#define VBPR GENMASK(23, 16)
69#define VTIM02 0x0460
70#define VFPR GENMASK(23, 16)
71#define VDISPR GENMASK(10, 0)
72#define VFUEN0 0x0464
73#define VFUEN BIT(0) /* Video Frame Timing Upload */
74
75/* System */
76#define TC_IDREG 0x0500
77#define SYSSTAT 0x0508
78#define SYSCTRL 0x0510
79#define DP0_AUDSRC_NO_INPUT (0 << 3)
80#define DP0_AUDSRC_I2S_RX (1 << 3)
81#define DP0_VIDSRC_NO_INPUT (0 << 0)
82#define DP0_VIDSRC_DSI_RX (1 << 0)
83#define DP0_VIDSRC_DPI_RX (2 << 0)
84#define DP0_VIDSRC_COLOR_BAR (3 << 0)
85#define SYSRSTENB 0x050c
86#define ENBI2C (1 << 0)
87#define ENBLCD0 (1 << 2)
88#define ENBBM (1 << 3)
89#define ENBDSIRX (1 << 4)
90#define ENBREG (1 << 5)
91#define ENBHDCP (1 << 8)
92#define GPIOM 0x0540
93#define GPIOC 0x0544
94#define GPIOO 0x0548
95#define GPIOI 0x054c
96#define INTCTL_G 0x0560
97#define INTSTS_G 0x0564
98
99#define INT_SYSERR BIT(16)
100#define INT_GPIO_H(x) (1 << (x == 0 ? 2 : 10))
101#define INT_GPIO_LC(x) (1 << (x == 0 ? 3 : 11))
102
103#define INT_GP0_LCNT 0x0584
104#define INT_GP1_LCNT 0x0588
105
106/* Control */
107#define DP0CTL 0x0600
108#define VID_MN_GEN BIT(6) /* Auto-generate M/N values */
109#define EF_EN BIT(5) /* Enable Enhanced Framing */
110#define VID_EN BIT(1) /* Video transmission enable */
111#define DP_EN BIT(0) /* Enable DPTX function */
112
113/* Clocks */
114#define DP0_VIDMNGEN0 0x0610
115#define DP0_VIDMNGEN1 0x0614
116#define DP0_VMNGENSTATUS 0x0618
117
118/* Main Channel */
119#define DP0_SECSAMPLE 0x0640
120#define DP0_VIDSYNCDELAY 0x0644
121#define VID_SYNC_DLY GENMASK(15, 0)
122#define THRESH_DLY GENMASK(31, 16)
123
124#define DP0_TOTALVAL 0x0648
125#define H_TOTAL GENMASK(15, 0)
126#define V_TOTAL GENMASK(31, 16)
127#define DP0_STARTVAL 0x064c
128#define H_START GENMASK(15, 0)
129#define V_START GENMASK(31, 16)
130#define DP0_ACTIVEVAL 0x0650
131#define H_ACT GENMASK(15, 0)
132#define V_ACT GENMASK(31, 16)
133
134#define DP0_SYNCVAL 0x0654
135#define VS_WIDTH GENMASK(30, 16)
136#define HS_WIDTH GENMASK(14, 0)
137#define SYNCVAL_HS_POL_ACTIVE_LOW (1 << 15)
138#define SYNCVAL_VS_POL_ACTIVE_LOW (1 << 31)
139#define DP0_MISC 0x0658
140#define TU_SIZE_RECOMMENDED (63) /* LSCLK cycles per TU */
141#define MAX_TU_SYMBOL GENMASK(28, 23)
142#define TU_SIZE GENMASK(21, 16)
143#define BPC_6 (0 << 5)
144#define BPC_8 (1 << 5)
145
146/* AUX channel */
147#define DP0_AUXCFG0 0x0660
148#define DP0_AUXCFG0_BSIZE GENMASK(11, 8)
149#define DP0_AUXCFG0_ADDR_ONLY BIT(4)
150#define DP0_AUXCFG1 0x0664
151#define AUX_RX_FILTER_EN BIT(16)
152
153#define DP0_AUXADDR 0x0668
154#define DP0_AUXWDATA(i) (0x066c + (i) * 4)
155#define DP0_AUXRDATA(i) (0x067c + (i) * 4)
156#define DP0_AUXSTATUS 0x068c
157#define AUX_BYTES GENMASK(15, 8)
158#define AUX_STATUS GENMASK(7, 4)
159#define AUX_TIMEOUT BIT(1)
160#define AUX_BUSY BIT(0)
161#define DP0_AUXI2CADR 0x0698
162
163/* Link Training */
164#define DP0_SRCCTRL 0x06a0
165#define DP0_SRCCTRL_SCRMBLDIS BIT(13)
166#define DP0_SRCCTRL_EN810B BIT(12)
167#define DP0_SRCCTRL_NOTP (0 << 8)
168#define DP0_SRCCTRL_TP1 (1 << 8)
169#define DP0_SRCCTRL_TP2 (2 << 8)
170#define DP0_SRCCTRL_LANESKEW BIT(7)
171#define DP0_SRCCTRL_SSCG BIT(3)
172#define DP0_SRCCTRL_LANES_1 (0 << 2)
173#define DP0_SRCCTRL_LANES_2 (1 << 2)
174#define DP0_SRCCTRL_BW27 (1 << 1)
175#define DP0_SRCCTRL_BW162 (0 << 1)
176#define DP0_SRCCTRL_AUTOCORRECT BIT(0)
177#define DP0_LTSTAT 0x06d0
178#define LT_LOOPDONE BIT(13)
179#define LT_STATUS_MASK (0x1f << 8)
180#define LT_CHANNEL1_EQ_BITS (DP_CHANNEL_EQ_BITS << 4)
181#define LT_INTERLANE_ALIGN_DONE BIT(3)
182#define LT_CHANNEL0_EQ_BITS (DP_CHANNEL_EQ_BITS)
183#define DP0_SNKLTCHGREQ 0x06d4
184#define DP0_LTLOOPCTRL 0x06d8
185#define DP0_SNKLTCTRL 0x06e4
186
187#define DP1_SRCCTRL 0x07a0
188
189/* PHY */
190#define DP_PHY_CTRL 0x0800
191#define DP_PHY_RST BIT(28) /* DP PHY Global Soft Reset */
192#define BGREN BIT(25) /* AUX PHY BGR Enable */
193#define PWR_SW_EN BIT(24) /* PHY Power Switch Enable */
194#define PHY_M1_RST BIT(12) /* Reset PHY1 Main Channel */
195#define PHY_RDY BIT(16) /* PHY Main Channels Ready */
196#define PHY_M0_RST BIT(8) /* Reset PHY0 Main Channel */
197#define PHY_2LANE BIT(2) /* PHY Enable 2 lanes */
198#define PHY_A0_EN BIT(1) /* PHY Aux Channel0 Enable */
199#define PHY_M0_EN BIT(0) /* PHY Main Channel0 Enable */
200
201/* PLL */
202#define DP0_PLLCTRL 0x0900
203#define DP1_PLLCTRL 0x0904 /* not defined in DS */
204#define PXL_PLLCTRL 0x0908
205#define PLLUPDATE BIT(2)
206#define PLLBYP BIT(1)
207#define PLLEN BIT(0)
208#define PXL_PLLPARAM 0x0914
209#define IN_SEL_REFCLK (0 << 14)
210#define SYS_PLLPARAM 0x0918
211#define REF_FREQ_38M4 (0 << 8) /* 38.4 MHz */
212#define REF_FREQ_19M2 (1 << 8) /* 19.2 MHz */
213#define REF_FREQ_26M (2 << 8) /* 26 MHz */
214#define REF_FREQ_13M (3 << 8) /* 13 MHz */
215#define SYSCLK_SEL_LSCLK (0 << 4)
216#define LSCLK_DIV_1 (0 << 0)
217#define LSCLK_DIV_2 (1 << 0)
218
219/* Test & Debug */
220#define TSTCTL 0x0a00
221#define COLOR_R GENMASK(31, 24)
222#define COLOR_G GENMASK(23, 16)
223#define COLOR_B GENMASK(15, 8)
224#define ENI2CFILTER BIT(4)
225#define COLOR_BAR_MODE GENMASK(1, 0)
226#define COLOR_BAR_MODE_BARS 2
227#define PLL_DBG 0x0a04
228
229static bool tc_test_pattern;
230module_param_named(test, tc_test_pattern, bool, 0644);
231
232struct tc_edp_link {
233 u8 dpcd[DP_RECEIVER_CAP_SIZE];
234 unsigned int rate;
235 u8 num_lanes;
236 u8 assr;
237 bool scrambler_dis;
238 bool spread;
239};
240
241struct tc_data {
242 struct device *dev;
243 struct regmap *regmap;
244 struct drm_dp_aux aux;
245
246 struct drm_bridge bridge;
247 struct drm_connector connector;
248 struct drm_panel *panel;
249
250 /* link settings */
251 struct tc_edp_link link;
252
253 /* display edid */
254 struct edid *edid;
255 /* current mode */
256 struct drm_display_mode mode;
257
258 u32 rev;
259 u8 assr;
260
261 struct gpio_desc *sd_gpio;
262 struct gpio_desc *reset_gpio;
263 struct clk *refclk;
264
265 /* do we have IRQ */
266 bool have_irq;
267
268 /* HPD pin number (0 or 1) or -ENODEV */
269 int hpd_pin;
270};
271
272static inline struct tc_data *aux_to_tc(struct drm_dp_aux *a)
273{
274 return container_of(a, struct tc_data, aux);
275}
276
277static inline struct tc_data *bridge_to_tc(struct drm_bridge *b)
278{
279 return container_of(b, struct tc_data, bridge);
280}
281
282static inline struct tc_data *connector_to_tc(struct drm_connector *c)
283{
284 return container_of(c, struct tc_data, connector);
285}
286
287static inline int tc_poll_timeout(struct tc_data *tc, unsigned int addr,
288 unsigned int cond_mask,
289 unsigned int cond_value,
290 unsigned long sleep_us, u64 timeout_us)
291{
292 unsigned int val;
293
294 return regmap_read_poll_timeout(tc->regmap, addr, val,
295 (val & cond_mask) == cond_value,
296 sleep_us, timeout_us);
297}
298
299static int tc_aux_wait_busy(struct tc_data *tc)
300{
301 return tc_poll_timeout(tc, DP0_AUXSTATUS, AUX_BUSY, 0, 100, 100000);
302}
303
304static int tc_aux_write_data(struct tc_data *tc, const void *data,
305 size_t size)
306{
307 u32 auxwdata[DP_AUX_MAX_PAYLOAD_BYTES / sizeof(u32)] = { 0 };
308 int ret, count = ALIGN(size, sizeof(u32));
309
310 memcpy(auxwdata, data, size);
311
312 ret = regmap_raw_write(tc->regmap, DP0_AUXWDATA(0), auxwdata, count);
313 if (ret)
314 return ret;
315
316 return size;
317}
318
319static int tc_aux_read_data(struct tc_data *tc, void *data, size_t size)
320{
321 u32 auxrdata[DP_AUX_MAX_PAYLOAD_BYTES / sizeof(u32)];
322 int ret, count = ALIGN(size, sizeof(u32));
323
324 ret = regmap_raw_read(tc->regmap, DP0_AUXRDATA(0), auxrdata, count);
325 if (ret)
326 return ret;
327
328 memcpy(data, auxrdata, size);
329
330 return size;
331}
332
333static u32 tc_auxcfg0(struct drm_dp_aux_msg *msg, size_t size)
334{
335 u32 auxcfg0 = msg->request;
336
337 if (size)
338 auxcfg0 |= FIELD_PREP(DP0_AUXCFG0_BSIZE, size - 1);
339 else
340 auxcfg0 |= DP0_AUXCFG0_ADDR_ONLY;
341
342 return auxcfg0;
343}
344
345static ssize_t tc_aux_transfer(struct drm_dp_aux *aux,
346 struct drm_dp_aux_msg *msg)
347{
348 struct tc_data *tc = aux_to_tc(aux);
349 size_t size = min_t(size_t, DP_AUX_MAX_PAYLOAD_BYTES - 1, msg->size);
350 u8 request = msg->request & ~DP_AUX_I2C_MOT;
351 u32 auxstatus;
352 int ret;
353
354 ret = tc_aux_wait_busy(tc);
355 if (ret)
356 return ret;
357
358 switch (request) {
359 case DP_AUX_NATIVE_READ:
360 case DP_AUX_I2C_READ:
361 break;
362 case DP_AUX_NATIVE_WRITE:
363 case DP_AUX_I2C_WRITE:
364 if (size) {
365 ret = tc_aux_write_data(tc, msg->buffer, size);
366 if (ret < 0)
367 return ret;
368 }
369 break;
370 default:
371 return -EINVAL;
372 }
373
374 /* Store address */
375 ret = regmap_write(tc->regmap, DP0_AUXADDR, msg->address);
376 if (ret)
377 return ret;
378 /* Start transfer */
379 ret = regmap_write(tc->regmap, DP0_AUXCFG0, tc_auxcfg0(msg, size));
380 if (ret)
381 return ret;
382
383 ret = tc_aux_wait_busy(tc);
384 if (ret)
385 return ret;
386
387 ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &auxstatus);
388 if (ret)
389 return ret;
390
391 if (auxstatus & AUX_TIMEOUT)
392 return -ETIMEDOUT;
393 /*
394 * For some reason address-only DP_AUX_I2C_WRITE (MOT), still
395 * reports 1 byte transferred in its status. To deal we that
396 * we ignore aux_bytes field if we know that this was an
397 * address-only transfer
398 */
399 if (size)
400 size = FIELD_GET(AUX_BYTES, auxstatus);
401 msg->reply = FIELD_GET(AUX_STATUS, auxstatus);
402
403 switch (request) {
404 case DP_AUX_NATIVE_READ:
405 case DP_AUX_I2C_READ:
406 if (size)
407 return tc_aux_read_data(tc, msg->buffer, size);
408 break;
409 }
410
411 return size;
412}
413
414static const char * const training_pattern1_errors[] = {
415 "No errors",
416 "Aux write error",
417 "Aux read error",
418 "Max voltage reached error",
419 "Loop counter expired error",
420 "res", "res", "res"
421};
422
423static const char * const training_pattern2_errors[] = {
424 "No errors",
425 "Aux write error",
426 "Aux read error",
427 "Clock recovery failed error",
428 "Loop counter expired error",
429 "res", "res", "res"
430};
431
432static u32 tc_srcctrl(struct tc_data *tc)
433{
434 /*
435 * No training pattern, skew lane 1 data by two LSCLK cycles with
436 * respect to lane 0 data, AutoCorrect Mode = 0
437 */
438 u32 reg = DP0_SRCCTRL_NOTP | DP0_SRCCTRL_LANESKEW | DP0_SRCCTRL_EN810B;
439
440 if (tc->link.scrambler_dis)
441 reg |= DP0_SRCCTRL_SCRMBLDIS; /* Scrambler Disabled */
442 if (tc->link.spread)
443 reg |= DP0_SRCCTRL_SSCG; /* Spread Spectrum Enable */
444 if (tc->link.num_lanes == 2)
445 reg |= DP0_SRCCTRL_LANES_2; /* Two Main Channel Lanes */
446 if (tc->link.rate != 162000)
447 reg |= DP0_SRCCTRL_BW27; /* 2.7 Gbps link */
448 return reg;
449}
450
451static int tc_pllupdate(struct tc_data *tc, unsigned int pllctrl)
452{
453 int ret;
454
455 ret = regmap_write(tc->regmap, pllctrl, PLLUPDATE | PLLEN);
456 if (ret)
457 return ret;
458
459 /* Wait for PLL to lock: up to 2.09 ms, depending on refclk */
460 usleep_range(3000, 6000);
461
462 return 0;
463}
464
465static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
466{
467 int ret;
468 int i_pre, best_pre = 1;
469 int i_post, best_post = 1;
470 int div, best_div = 1;
471 int mul, best_mul = 1;
472 int delta, best_delta;
473 int ext_div[] = {1, 2, 3, 5, 7};
474 int best_pixelclock = 0;
475 int vco_hi = 0;
476 u32 pxl_pllparam;
477
478 dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock,
479 refclk);
480 best_delta = pixelclock;
481 /* Loop over all possible ext_divs, skipping invalid configurations */
482 for (i_pre = 0; i_pre < ARRAY_SIZE(ext_div); i_pre++) {
483 /*
484 * refclk / ext_pre_div should be in the 1 to 200 MHz range.
485 * We don't allow any refclk > 200 MHz, only check lower bounds.
486 */
487 if (refclk / ext_div[i_pre] < 1000000)
488 continue;
489 for (i_post = 0; i_post < ARRAY_SIZE(ext_div); i_post++) {
490 for (div = 1; div <= 16; div++) {
491 u32 clk;
492 u64 tmp;
493
494 tmp = pixelclock * ext_div[i_pre] *
495 ext_div[i_post] * div;
496 do_div(tmp, refclk);
497 mul = tmp;
498
499 /* Check limits */
500 if ((mul < 1) || (mul > 128))
501 continue;
502
503 clk = (refclk / ext_div[i_pre] / div) * mul;
504 /*
505 * refclk * mul / (ext_pre_div * pre_div)
506 * should be in the 150 to 650 MHz range
507 */
508 if ((clk > 650000000) || (clk < 150000000))
509 continue;
510
511 clk = clk / ext_div[i_post];
512 delta = clk - pixelclock;
513
514 if (abs(delta) < abs(best_delta)) {
515 best_pre = i_pre;
516 best_post = i_post;
517 best_div = div;
518 best_mul = mul;
519 best_delta = delta;
520 best_pixelclock = clk;
521 }
522 }
523 }
524 }
525 if (best_pixelclock == 0) {
526 dev_err(tc->dev, "Failed to calc clock for %d pixelclock\n",
527 pixelclock);
528 return -EINVAL;
529 }
530
531 dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock,
532 best_delta);
533 dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk,
534 ext_div[best_pre], best_div, best_mul, ext_div[best_post]);
535
536 /* if VCO >= 300 MHz */
537 if (refclk / ext_div[best_pre] / best_div * best_mul >= 300000000)
538 vco_hi = 1;
539 /* see DS */
540 if (best_div == 16)
541 best_div = 0;
542 if (best_mul == 128)
543 best_mul = 0;
544
545 /* Power up PLL and switch to bypass */
546 ret = regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP | PLLEN);
547 if (ret)
548 return ret;
549
550 pxl_pllparam = vco_hi << 24; /* For PLL VCO >= 300 MHz = 1 */
551 pxl_pllparam |= ext_div[best_pre] << 20; /* External Pre-divider */
552 pxl_pllparam |= ext_div[best_post] << 16; /* External Post-divider */
553 pxl_pllparam |= IN_SEL_REFCLK; /* Use RefClk as PLL input */
554 pxl_pllparam |= best_div << 8; /* Divider for PLL RefClk */
555 pxl_pllparam |= best_mul; /* Multiplier for PLL */
556
557 ret = regmap_write(tc->regmap, PXL_PLLPARAM, pxl_pllparam);
558 if (ret)
559 return ret;
560
561 /* Force PLL parameter update and disable bypass */
562 return tc_pllupdate(tc, PXL_PLLCTRL);
563}
564
565static int tc_pxl_pll_dis(struct tc_data *tc)
566{
567 /* Enable PLL bypass, power down PLL */
568 return regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP);
569}
570
571static int tc_stream_clock_calc(struct tc_data *tc)
572{
573 /*
574 * If the Stream clock and Link Symbol clock are
575 * asynchronous with each other, the value of M changes over
576 * time. This way of generating link clock and stream
577 * clock is called Asynchronous Clock mode. The value M
578 * must change while the value N stays constant. The
579 * value of N in this Asynchronous Clock mode must be set
580 * to 2^15 or 32,768.
581 *
582 * LSCLK = 1/10 of high speed link clock
583 *
584 * f_STRMCLK = M/N * f_LSCLK
585 * M/N = f_STRMCLK / f_LSCLK
586 *
587 */
588 return regmap_write(tc->regmap, DP0_VIDMNGEN1, 32768);
589}
590
591static int tc_set_syspllparam(struct tc_data *tc)
592{
593 unsigned long rate;
594 u32 pllparam = SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
595
596 rate = clk_get_rate(tc->refclk);
597 switch (rate) {
598 case 38400000:
599 pllparam |= REF_FREQ_38M4;
600 break;
601 case 26000000:
602 pllparam |= REF_FREQ_26M;
603 break;
604 case 19200000:
605 pllparam |= REF_FREQ_19M2;
606 break;
607 case 13000000:
608 pllparam |= REF_FREQ_13M;
609 break;
610 default:
611 dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate);
612 return -EINVAL;
613 }
614
615 return regmap_write(tc->regmap, SYS_PLLPARAM, pllparam);
616}
617
618static int tc_aux_link_setup(struct tc_data *tc)
619{
620 int ret;
621 u32 dp0_auxcfg1;
622
623 /* Setup DP-PHY / PLL */
624 ret = tc_set_syspllparam(tc);
625 if (ret)
626 goto err;
627
628 ret = regmap_write(tc->regmap, DP_PHY_CTRL,
629 BGREN | PWR_SW_EN | PHY_A0_EN);
630 if (ret)
631 goto err;
632 /*
633 * Initially PLLs are in bypass. Force PLL parameter update,
634 * disable PLL bypass, enable PLL
635 */
636 ret = tc_pllupdate(tc, DP0_PLLCTRL);
637 if (ret)
638 goto err;
639
640 ret = tc_pllupdate(tc, DP1_PLLCTRL);
641 if (ret)
642 goto err;
643
644 ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 100, 100000);
645 if (ret == -ETIMEDOUT) {
646 dev_err(tc->dev, "Timeout waiting for PHY to become ready");
647 return ret;
648 } else if (ret) {
649 goto err;
650 }
651
652 /* Setup AUX link */
653 dp0_auxcfg1 = AUX_RX_FILTER_EN;
654 dp0_auxcfg1 |= 0x06 << 8; /* Aux Bit Period Calculator Threshold */
655 dp0_auxcfg1 |= 0x3f << 0; /* Aux Response Timeout Timer */
656
657 ret = regmap_write(tc->regmap, DP0_AUXCFG1, dp0_auxcfg1);
658 if (ret)
659 goto err;
660
661 return 0;
662err:
663 dev_err(tc->dev, "tc_aux_link_setup failed: %d\n", ret);
664 return ret;
665}
666
667static int tc_get_display_props(struct tc_data *tc)
668{
669 u8 revision, num_lanes;
670 unsigned int rate;
671 int ret;
672 u8 reg;
673
674 /* Read DP Rx Link Capability */
675 ret = drm_dp_dpcd_read(&tc->aux, DP_DPCD_REV, tc->link.dpcd,
676 DP_RECEIVER_CAP_SIZE);
677 if (ret < 0)
678 goto err_dpcd_read;
679
680 revision = tc->link.dpcd[DP_DPCD_REV];
681 rate = drm_dp_max_link_rate(tc->link.dpcd);
682 num_lanes = drm_dp_max_lane_count(tc->link.dpcd);
683
684 if (rate != 162000 && rate != 270000) {
685 dev_dbg(tc->dev, "Falling to 2.7 Gbps rate\n");
686 rate = 270000;
687 }
688
689 tc->link.rate = rate;
690
691 if (num_lanes > 2) {
692 dev_dbg(tc->dev, "Falling to 2 lanes\n");
693 num_lanes = 2;
694 }
695
696 tc->link.num_lanes = num_lanes;
697
698 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, ®);
699 if (ret < 0)
700 goto err_dpcd_read;
701 tc->link.spread = reg & DP_MAX_DOWNSPREAD_0_5;
702
703 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, ®);
704 if (ret < 0)
705 goto err_dpcd_read;
706
707 tc->link.scrambler_dis = false;
708 /* read assr */
709 ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, ®);
710 if (ret < 0)
711 goto err_dpcd_read;
712 tc->link.assr = reg & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;
713
714 dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n",
715 revision >> 4, revision & 0x0f,
716 (tc->link.rate == 162000) ? "1.62Gbps" : "2.7Gbps",
717 tc->link.num_lanes,
718 drm_dp_enhanced_frame_cap(tc->link.dpcd) ?
719 "enhanced" : "default");
720 dev_dbg(tc->dev, "Downspread: %s, scrambler: %s\n",
721 tc->link.spread ? "0.5%" : "0.0%",
722 tc->link.scrambler_dis ? "disabled" : "enabled");
723 dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n",
724 tc->link.assr, tc->assr);
725
726 return 0;
727
728err_dpcd_read:
729 dev_err(tc->dev, "failed to read DPCD: %d\n", ret);
730 return ret;
731}
732
733static int tc_set_video_mode(struct tc_data *tc,
734 const struct drm_display_mode *mode)
735{
736 int ret;
737 int vid_sync_dly;
738 int max_tu_symbol;
739
740 int left_margin = mode->htotal - mode->hsync_end;
741 int right_margin = mode->hsync_start - mode->hdisplay;
742 int hsync_len = mode->hsync_end - mode->hsync_start;
743 int upper_margin = mode->vtotal - mode->vsync_end;
744 int lower_margin = mode->vsync_start - mode->vdisplay;
745 int vsync_len = mode->vsync_end - mode->vsync_start;
746 u32 dp0_syncval;
747 u32 bits_per_pixel = 24;
748 u32 in_bw, out_bw;
749
750 /*
751 * Recommended maximum number of symbols transferred in a transfer unit:
752 * DIV_ROUND_UP((input active video bandwidth in bytes) * tu_size,
753 * (output active video bandwidth in bytes))
754 * Must be less than tu_size.
755 */
756
757 in_bw = mode->clock * bits_per_pixel / 8;
758 out_bw = tc->link.num_lanes * tc->link.rate;
759 max_tu_symbol = DIV_ROUND_UP(in_bw * TU_SIZE_RECOMMENDED, out_bw);
760
761 dev_dbg(tc->dev, "set mode %dx%d\n",
762 mode->hdisplay, mode->vdisplay);
763 dev_dbg(tc->dev, "H margin %d,%d sync %d\n",
764 left_margin, right_margin, hsync_len);
765 dev_dbg(tc->dev, "V margin %d,%d sync %d\n",
766 upper_margin, lower_margin, vsync_len);
767 dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal);
768
769
770 /*
771 * LCD Ctl Frame Size
772 * datasheet is not clear of vsdelay in case of DPI
773 * assume we do not need any delay when DPI is a source of
774 * sync signals
775 */
776 ret = regmap_write(tc->regmap, VPCTRL0,
777 FIELD_PREP(VSDELAY, 0) |
778 OPXLFMT_RGB888 | FRMSYNC_DISABLED | MSF_DISABLED);
779 if (ret)
780 return ret;
781
782 ret = regmap_write(tc->regmap, HTIM01,
783 FIELD_PREP(HBPR, ALIGN(left_margin, 2)) |
784 FIELD_PREP(HPW, ALIGN(hsync_len, 2)));
785 if (ret)
786 return ret;
787
788 ret = regmap_write(tc->regmap, HTIM02,
789 FIELD_PREP(HDISPR, ALIGN(mode->hdisplay, 2)) |
790 FIELD_PREP(HFPR, ALIGN(right_margin, 2)));
791 if (ret)
792 return ret;
793
794 ret = regmap_write(tc->regmap, VTIM01,
795 FIELD_PREP(VBPR, upper_margin) |
796 FIELD_PREP(VSPR, vsync_len));
797 if (ret)
798 return ret;
799
800 ret = regmap_write(tc->regmap, VTIM02,
801 FIELD_PREP(VFPR, lower_margin) |
802 FIELD_PREP(VDISPR, mode->vdisplay));
803 if (ret)
804 return ret;
805
806 ret = regmap_write(tc->regmap, VFUEN0, VFUEN); /* update settings */
807 if (ret)
808 return ret;
809
810 /* Test pattern settings */
811 ret = regmap_write(tc->regmap, TSTCTL,
812 FIELD_PREP(COLOR_R, 120) |
813 FIELD_PREP(COLOR_G, 20) |
814 FIELD_PREP(COLOR_B, 99) |
815 ENI2CFILTER |
816 FIELD_PREP(COLOR_BAR_MODE, COLOR_BAR_MODE_BARS));
817 if (ret)
818 return ret;
819
820 /* DP Main Stream Attributes */
821 vid_sync_dly = hsync_len + left_margin + mode->hdisplay;
822 ret = regmap_write(tc->regmap, DP0_VIDSYNCDELAY,
823 FIELD_PREP(THRESH_DLY, max_tu_symbol) |
824 FIELD_PREP(VID_SYNC_DLY, vid_sync_dly));
825
826 ret = regmap_write(tc->regmap, DP0_TOTALVAL,
827 FIELD_PREP(H_TOTAL, mode->htotal) |
828 FIELD_PREP(V_TOTAL, mode->vtotal));
829 if (ret)
830 return ret;
831
832 ret = regmap_write(tc->regmap, DP0_STARTVAL,
833 FIELD_PREP(H_START, left_margin + hsync_len) |
834 FIELD_PREP(V_START, upper_margin + vsync_len));
835 if (ret)
836 return ret;
837
838 ret = regmap_write(tc->regmap, DP0_ACTIVEVAL,
839 FIELD_PREP(V_ACT, mode->vdisplay) |
840 FIELD_PREP(H_ACT, mode->hdisplay));
841 if (ret)
842 return ret;
843
844 dp0_syncval = FIELD_PREP(VS_WIDTH, vsync_len) |
845 FIELD_PREP(HS_WIDTH, hsync_len);
846
847 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
848 dp0_syncval |= SYNCVAL_VS_POL_ACTIVE_LOW;
849
850 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
851 dp0_syncval |= SYNCVAL_HS_POL_ACTIVE_LOW;
852
853 ret = regmap_write(tc->regmap, DP0_SYNCVAL, dp0_syncval);
854 if (ret)
855 return ret;
856
857 ret = regmap_write(tc->regmap, DPIPXLFMT,
858 VS_POL_ACTIVE_LOW | HS_POL_ACTIVE_LOW |
859 DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 |
860 DPI_BPP_RGB888);
861 if (ret)
862 return ret;
863
864 ret = regmap_write(tc->regmap, DP0_MISC,
865 FIELD_PREP(MAX_TU_SYMBOL, max_tu_symbol) |
866 FIELD_PREP(TU_SIZE, TU_SIZE_RECOMMENDED) |
867 BPC_8);
868 if (ret)
869 return ret;
870
871 return 0;
872}
873
874static int tc_wait_link_training(struct tc_data *tc)
875{
876 u32 value;
877 int ret;
878
879 ret = tc_poll_timeout(tc, DP0_LTSTAT, LT_LOOPDONE,
880 LT_LOOPDONE, 500, 100000);
881 if (ret) {
882 dev_err(tc->dev, "Link training timeout waiting for LT_LOOPDONE!\n");
883 return ret;
884 }
885
886 ret = regmap_read(tc->regmap, DP0_LTSTAT, &value);
887 if (ret)
888 return ret;
889
890 return (value >> 8) & 0x7;
891}
892
893static int tc_main_link_enable(struct tc_data *tc)
894{
895 struct drm_dp_aux *aux = &tc->aux;
896 struct device *dev = tc->dev;
897 u32 dp_phy_ctrl;
898 u32 value;
899 int ret;
900 u8 tmp[DP_LINK_STATUS_SIZE];
901
902 dev_dbg(tc->dev, "link enable\n");
903
904 ret = regmap_read(tc->regmap, DP0CTL, &value);
905 if (ret)
906 return ret;
907
908 if (WARN_ON(value & DP_EN)) {
909 ret = regmap_write(tc->regmap, DP0CTL, 0);
910 if (ret)
911 return ret;
912 }
913
914 ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc));
915 if (ret)
916 return ret;
917 /* SSCG and BW27 on DP1 must be set to the same as on DP0 */
918 ret = regmap_write(tc->regmap, DP1_SRCCTRL,
919 (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) |
920 ((tc->link.rate != 162000) ? DP0_SRCCTRL_BW27 : 0));
921 if (ret)
922 return ret;
923
924 ret = tc_set_syspllparam(tc);
925 if (ret)
926 return ret;
927
928 /* Setup Main Link */
929 dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN | PHY_M0_EN;
930 if (tc->link.num_lanes == 2)
931 dp_phy_ctrl |= PHY_2LANE;
932
933 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
934 if (ret)
935 return ret;
936
937 /* PLL setup */
938 ret = tc_pllupdate(tc, DP0_PLLCTRL);
939 if (ret)
940 return ret;
941
942 ret = tc_pllupdate(tc, DP1_PLLCTRL);
943 if (ret)
944 return ret;
945
946 /* Reset/Enable Main Links */
947 dp_phy_ctrl |= DP_PHY_RST | PHY_M1_RST | PHY_M0_RST;
948 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
949 usleep_range(100, 200);
950 dp_phy_ctrl &= ~(DP_PHY_RST | PHY_M1_RST | PHY_M0_RST);
951 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
952
953 ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 500, 100000);
954 if (ret) {
955 dev_err(dev, "timeout waiting for phy become ready");
956 return ret;
957 }
958
959 /* Set misc: 8 bits per color */
960 ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8);
961 if (ret)
962 return ret;
963
964 /*
965 * ASSR mode
966 * on TC358767 side ASSR configured through strap pin
967 * seems there is no way to change this setting from SW
968 *
969 * check is tc configured for same mode
970 */
971 if (tc->assr != tc->link.assr) {
972 dev_dbg(dev, "Trying to set display to ASSR: %d\n",
973 tc->assr);
974 /* try to set ASSR on display side */
975 tmp[0] = tc->assr;
976 ret = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, tmp[0]);
977 if (ret < 0)
978 goto err_dpcd_read;
979 /* read back */
980 ret = drm_dp_dpcd_readb(aux, DP_EDP_CONFIGURATION_SET, tmp);
981 if (ret < 0)
982 goto err_dpcd_read;
983
984 if (tmp[0] != tc->assr) {
985 dev_dbg(dev, "Failed to switch display ASSR to %d, falling back to unscrambled mode\n",
986 tc->assr);
987 /* trying with disabled scrambler */
988 tc->link.scrambler_dis = true;
989 }
990 }
991
992 /* Setup Link & DPRx Config for Training */
993 tmp[0] = drm_dp_link_rate_to_bw_code(tc->link.rate);
994 tmp[1] = tc->link.num_lanes;
995
996 if (drm_dp_enhanced_frame_cap(tc->link.dpcd))
997 tmp[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
998
999 ret = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, tmp, 2);
1000 if (ret < 0)
1001 goto err_dpcd_write;
1002
1003 /* DOWNSPREAD_CTRL */
1004 tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00;
1005 /* MAIN_LINK_CHANNEL_CODING_SET */
1006 tmp[1] = DP_SET_ANSI_8B10B;
1007 ret = drm_dp_dpcd_write(aux, DP_DOWNSPREAD_CTRL, tmp, 2);
1008 if (ret < 0)
1009 goto err_dpcd_write;
1010
1011 /* Reset voltage-swing & pre-emphasis */
1012 tmp[0] = tmp[1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 |
1013 DP_TRAIN_PRE_EMPH_LEVEL_0;
1014 ret = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, tmp, 2);
1015 if (ret < 0)
1016 goto err_dpcd_write;
1017
1018 /* Clock-Recovery */
1019
1020 /* Set DPCD 0x102 for Training Pattern 1 */
1021 ret = regmap_write(tc->regmap, DP0_SNKLTCTRL,
1022 DP_LINK_SCRAMBLING_DISABLE |
1023 DP_TRAINING_PATTERN_1);
1024 if (ret)
1025 return ret;
1026
1027 ret = regmap_write(tc->regmap, DP0_LTLOOPCTRL,
1028 (15 << 28) | /* Defer Iteration Count */
1029 (15 << 24) | /* Loop Iteration Count */
1030 (0xd << 0)); /* Loop Timer Delay */
1031 if (ret)
1032 return ret;
1033
1034 ret = regmap_write(tc->regmap, DP0_SRCCTRL,
1035 tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS |
1036 DP0_SRCCTRL_AUTOCORRECT |
1037 DP0_SRCCTRL_TP1);
1038 if (ret)
1039 return ret;
1040
1041 /* Enable DP0 to start Link Training */
1042 ret = regmap_write(tc->regmap, DP0CTL,
1043 (drm_dp_enhanced_frame_cap(tc->link.dpcd) ?
1044 EF_EN : 0) | DP_EN);
1045 if (ret)
1046 return ret;
1047
1048 /* wait */
1049
1050 ret = tc_wait_link_training(tc);
1051 if (ret < 0)
1052 return ret;
1053
1054 if (ret) {
1055 dev_err(tc->dev, "Link training phase 1 failed: %s\n",
1056 training_pattern1_errors[ret]);
1057 return -ENODEV;
1058 }
1059
1060 /* Channel Equalization */
1061
1062 /* Set DPCD 0x102 for Training Pattern 2 */
1063 ret = regmap_write(tc->regmap, DP0_SNKLTCTRL,
1064 DP_LINK_SCRAMBLING_DISABLE |
1065 DP_TRAINING_PATTERN_2);
1066 if (ret)
1067 return ret;
1068
1069 ret = regmap_write(tc->regmap, DP0_SRCCTRL,
1070 tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS |
1071 DP0_SRCCTRL_AUTOCORRECT |
1072 DP0_SRCCTRL_TP2);
1073 if (ret)
1074 return ret;
1075
1076 /* wait */
1077 ret = tc_wait_link_training(tc);
1078 if (ret < 0)
1079 return ret;
1080
1081 if (ret) {
1082 dev_err(tc->dev, "Link training phase 2 failed: %s\n",
1083 training_pattern2_errors[ret]);
1084 return -ENODEV;
1085 }
1086
1087 /*
1088 * Toshiba's documentation suggests to first clear DPCD 0x102, then
1089 * clear the training pattern bit in DP0_SRCCTRL. Testing shows
1090 * that the link sometimes drops if those steps are done in that order,
1091 * but if the steps are done in reverse order, the link stays up.
1092 *
1093 * So we do the steps differently than documented here.
1094 */
1095
1096 /* Clear Training Pattern, set AutoCorrect Mode = 1 */
1097 ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc) |
1098 DP0_SRCCTRL_AUTOCORRECT);
1099 if (ret)
1100 return ret;
1101
1102 /* Clear DPCD 0x102 */
1103 /* Note: Can Not use DP0_SNKLTCTRL (0x06E4) short cut */
1104 tmp[0] = tc->link.scrambler_dis ? DP_LINK_SCRAMBLING_DISABLE : 0x00;
1105 ret = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, tmp[0]);
1106 if (ret < 0)
1107 goto err_dpcd_write;
1108
1109 /* Check link status */
1110 ret = drm_dp_dpcd_read_link_status(aux, tmp);
1111 if (ret < 0)
1112 goto err_dpcd_read;
1113
1114 ret = 0;
1115
1116 value = tmp[0] & DP_CHANNEL_EQ_BITS;
1117
1118 if (value != DP_CHANNEL_EQ_BITS) {
1119 dev_err(tc->dev, "Lane 0 failed: %x\n", value);
1120 ret = -ENODEV;
1121 }
1122
1123 if (tc->link.num_lanes == 2) {
1124 value = (tmp[0] >> 4) & DP_CHANNEL_EQ_BITS;
1125
1126 if (value != DP_CHANNEL_EQ_BITS) {
1127 dev_err(tc->dev, "Lane 1 failed: %x\n", value);
1128 ret = -ENODEV;
1129 }
1130
1131 if (!(tmp[2] & DP_INTERLANE_ALIGN_DONE)) {
1132 dev_err(tc->dev, "Interlane align failed\n");
1133 ret = -ENODEV;
1134 }
1135 }
1136
1137 if (ret) {
1138 dev_err(dev, "0x0202 LANE0_1_STATUS: 0x%02x\n", tmp[0]);
1139 dev_err(dev, "0x0203 LANE2_3_STATUS 0x%02x\n", tmp[1]);
1140 dev_err(dev, "0x0204 LANE_ALIGN_STATUS_UPDATED: 0x%02x\n", tmp[2]);
1141 dev_err(dev, "0x0205 SINK_STATUS: 0x%02x\n", tmp[3]);
1142 dev_err(dev, "0x0206 ADJUST_REQUEST_LANE0_1: 0x%02x\n", tmp[4]);
1143 dev_err(dev, "0x0207 ADJUST_REQUEST_LANE2_3: 0x%02x\n", tmp[5]);
1144 return ret;
1145 }
1146
1147 return 0;
1148err_dpcd_read:
1149 dev_err(tc->dev, "Failed to read DPCD: %d\n", ret);
1150 return ret;
1151err_dpcd_write:
1152 dev_err(tc->dev, "Failed to write DPCD: %d\n", ret);
1153 return ret;
1154}
1155
1156static int tc_main_link_disable(struct tc_data *tc)
1157{
1158 int ret;
1159
1160 dev_dbg(tc->dev, "link disable\n");
1161
1162 ret = regmap_write(tc->regmap, DP0_SRCCTRL, 0);
1163 if (ret)
1164 return ret;
1165
1166 return regmap_write(tc->regmap, DP0CTL, 0);
1167}
1168
1169static int tc_stream_enable(struct tc_data *tc)
1170{
1171 int ret;
1172 u32 value;
1173
1174 dev_dbg(tc->dev, "enable video stream\n");
1175
1176 /* PXL PLL setup */
1177 if (tc_test_pattern) {
1178 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk),
1179 1000 * tc->mode.clock);
1180 if (ret)
1181 return ret;
1182 }
1183
1184 ret = tc_set_video_mode(tc, &tc->mode);
1185 if (ret)
1186 return ret;
1187
1188 /* Set M/N */
1189 ret = tc_stream_clock_calc(tc);
1190 if (ret)
1191 return ret;
1192
1193 value = VID_MN_GEN | DP_EN;
1194 if (drm_dp_enhanced_frame_cap(tc->link.dpcd))
1195 value |= EF_EN;
1196 ret = regmap_write(tc->regmap, DP0CTL, value);
1197 if (ret)
1198 return ret;
1199 /*
1200 * VID_EN assertion should be delayed by at least N * LSCLK
1201 * cycles from the time VID_MN_GEN is enabled in order to
1202 * generate stable values for VID_M. LSCLK is 270 MHz or
1203 * 162 MHz, VID_N is set to 32768 in tc_stream_clock_calc(),
1204 * so a delay of at least 203 us should suffice.
1205 */
1206 usleep_range(500, 1000);
1207 value |= VID_EN;
1208 ret = regmap_write(tc->regmap, DP0CTL, value);
1209 if (ret)
1210 return ret;
1211 /* Set input interface */
1212 value = DP0_AUDSRC_NO_INPUT;
1213 if (tc_test_pattern)
1214 value |= DP0_VIDSRC_COLOR_BAR;
1215 else
1216 value |= DP0_VIDSRC_DPI_RX;
1217 ret = regmap_write(tc->regmap, SYSCTRL, value);
1218 if (ret)
1219 return ret;
1220
1221 return 0;
1222}
1223
1224static int tc_stream_disable(struct tc_data *tc)
1225{
1226 int ret;
1227
1228 dev_dbg(tc->dev, "disable video stream\n");
1229
1230 ret = regmap_update_bits(tc->regmap, DP0CTL, VID_EN, 0);
1231 if (ret)
1232 return ret;
1233
1234 tc_pxl_pll_dis(tc);
1235
1236 return 0;
1237}
1238
1239static void tc_bridge_pre_enable(struct drm_bridge *bridge)
1240{
1241 struct tc_data *tc = bridge_to_tc(bridge);
1242
1243 drm_panel_prepare(tc->panel);
1244}
1245
1246static void tc_bridge_enable(struct drm_bridge *bridge)
1247{
1248 struct tc_data *tc = bridge_to_tc(bridge);
1249 int ret;
1250
1251 ret = tc_get_display_props(tc);
1252 if (ret < 0) {
1253 dev_err(tc->dev, "failed to read display props: %d\n", ret);
1254 return;
1255 }
1256
1257 ret = tc_main_link_enable(tc);
1258 if (ret < 0) {
1259 dev_err(tc->dev, "main link enable error: %d\n", ret);
1260 return;
1261 }
1262
1263 ret = tc_stream_enable(tc);
1264 if (ret < 0) {
1265 dev_err(tc->dev, "main link stream start error: %d\n", ret);
1266 tc_main_link_disable(tc);
1267 return;
1268 }
1269
1270 drm_panel_enable(tc->panel);
1271}
1272
1273static void tc_bridge_disable(struct drm_bridge *bridge)
1274{
1275 struct tc_data *tc = bridge_to_tc(bridge);
1276 int ret;
1277
1278 drm_panel_disable(tc->panel);
1279
1280 ret = tc_stream_disable(tc);
1281 if (ret < 0)
1282 dev_err(tc->dev, "main link stream stop error: %d\n", ret);
1283
1284 ret = tc_main_link_disable(tc);
1285 if (ret < 0)
1286 dev_err(tc->dev, "main link disable error: %d\n", ret);
1287}
1288
1289static void tc_bridge_post_disable(struct drm_bridge *bridge)
1290{
1291 struct tc_data *tc = bridge_to_tc(bridge);
1292
1293 drm_panel_unprepare(tc->panel);
1294}
1295
1296static bool tc_bridge_mode_fixup(struct drm_bridge *bridge,
1297 const struct drm_display_mode *mode,
1298 struct drm_display_mode *adj)
1299{
1300 /* Fixup sync polarities, both hsync and vsync are active low */
1301 adj->flags = mode->flags;
1302 adj->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
1303 adj->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
1304
1305 return true;
1306}
1307
1308static enum drm_mode_status tc_mode_valid(struct drm_bridge *bridge,
1309 const struct drm_display_info *info,
1310 const struct drm_display_mode *mode)
1311{
1312 struct tc_data *tc = bridge_to_tc(bridge);
1313 u32 req, avail;
1314 u32 bits_per_pixel = 24;
1315
1316 /* DPI interface clock limitation: upto 154 MHz */
1317 if (mode->clock > 154000)
1318 return MODE_CLOCK_HIGH;
1319
1320 req = mode->clock * bits_per_pixel / 8;
1321 avail = tc->link.num_lanes * tc->link.rate;
1322
1323 if (req > avail)
1324 return MODE_BAD;
1325
1326 return MODE_OK;
1327}
1328
1329static void tc_bridge_mode_set(struct drm_bridge *bridge,
1330 const struct drm_display_mode *mode,
1331 const struct drm_display_mode *adj)
1332{
1333 struct tc_data *tc = bridge_to_tc(bridge);
1334
1335 tc->mode = *mode;
1336}
1337
1338static int tc_connector_get_modes(struct drm_connector *connector)
1339{
1340 struct tc_data *tc = connector_to_tc(connector);
1341 struct edid *edid;
1342 int count;
1343 int ret;
1344
1345 ret = tc_get_display_props(tc);
1346 if (ret < 0) {
1347 dev_err(tc->dev, "failed to read display props: %d\n", ret);
1348 return 0;
1349 }
1350
1351 count = drm_panel_get_modes(tc->panel, connector);
1352 if (count > 0)
1353 return count;
1354
1355 edid = drm_get_edid(connector, &tc->aux.ddc);
1356
1357 kfree(tc->edid);
1358 tc->edid = edid;
1359 if (!edid)
1360 return 0;
1361
1362 drm_connector_update_edid_property(connector, edid);
1363 count = drm_add_edid_modes(connector, edid);
1364
1365 return count;
1366}
1367
1368static const struct drm_connector_helper_funcs tc_connector_helper_funcs = {
1369 .get_modes = tc_connector_get_modes,
1370};
1371
1372static enum drm_connector_status tc_connector_detect(struct drm_connector *connector,
1373 bool force)
1374{
1375 struct tc_data *tc = connector_to_tc(connector);
1376 bool conn;
1377 u32 val;
1378 int ret;
1379
1380 if (tc->hpd_pin < 0) {
1381 if (tc->panel)
1382 return connector_status_connected;
1383 else
1384 return connector_status_unknown;
1385 }
1386
1387 ret = regmap_read(tc->regmap, GPIOI, &val);
1388 if (ret)
1389 return connector_status_unknown;
1390
1391 conn = val & BIT(tc->hpd_pin);
1392
1393 if (conn)
1394 return connector_status_connected;
1395 else
1396 return connector_status_disconnected;
1397}
1398
1399static const struct drm_connector_funcs tc_connector_funcs = {
1400 .detect = tc_connector_detect,
1401 .fill_modes = drm_helper_probe_single_connector_modes,
1402 .destroy = drm_connector_cleanup,
1403 .reset = drm_atomic_helper_connector_reset,
1404 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1405 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1406};
1407
1408static int tc_bridge_attach(struct drm_bridge *bridge,
1409 enum drm_bridge_attach_flags flags)
1410{
1411 u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1412 struct tc_data *tc = bridge_to_tc(bridge);
1413 struct drm_device *drm = bridge->dev;
1414 int ret;
1415
1416 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) {
1417 DRM_ERROR("Fix bridge driver to make connector optional!");
1418 return -EINVAL;
1419 }
1420
1421 /* Create DP/eDP connector */
1422 drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs);
1423 ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs,
1424 tc->panel ? DRM_MODE_CONNECTOR_eDP :
1425 DRM_MODE_CONNECTOR_DisplayPort);
1426 if (ret)
1427 return ret;
1428
1429 /* Don't poll if don't have HPD connected */
1430 if (tc->hpd_pin >= 0) {
1431 if (tc->have_irq)
1432 tc->connector.polled = DRM_CONNECTOR_POLL_HPD;
1433 else
1434 tc->connector.polled = DRM_CONNECTOR_POLL_CONNECT |
1435 DRM_CONNECTOR_POLL_DISCONNECT;
1436 }
1437
1438 if (tc->panel)
1439 drm_panel_attach(tc->panel, &tc->connector);
1440
1441 drm_display_info_set_bus_formats(&tc->connector.display_info,
1442 &bus_format, 1);
1443 tc->connector.display_info.bus_flags =
1444 DRM_BUS_FLAG_DE_HIGH |
1445 DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE |
1446 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE;
1447 drm_connector_attach_encoder(&tc->connector, tc->bridge.encoder);
1448
1449 return 0;
1450}
1451
1452static const struct drm_bridge_funcs tc_bridge_funcs = {
1453 .attach = tc_bridge_attach,
1454 .mode_valid = tc_mode_valid,
1455 .mode_set = tc_bridge_mode_set,
1456 .pre_enable = tc_bridge_pre_enable,
1457 .enable = tc_bridge_enable,
1458 .disable = tc_bridge_disable,
1459 .post_disable = tc_bridge_post_disable,
1460 .mode_fixup = tc_bridge_mode_fixup,
1461};
1462
1463static bool tc_readable_reg(struct device *dev, unsigned int reg)
1464{
1465 return reg != SYSCTRL;
1466}
1467
1468static const struct regmap_range tc_volatile_ranges[] = {
1469 regmap_reg_range(DP0_AUXWDATA(0), DP0_AUXSTATUS),
1470 regmap_reg_range(DP0_LTSTAT, DP0_SNKLTCHGREQ),
1471 regmap_reg_range(DP_PHY_CTRL, DP_PHY_CTRL),
1472 regmap_reg_range(DP0_PLLCTRL, PXL_PLLCTRL),
1473 regmap_reg_range(VFUEN0, VFUEN0),
1474 regmap_reg_range(INTSTS_G, INTSTS_G),
1475 regmap_reg_range(GPIOI, GPIOI),
1476};
1477
1478static const struct regmap_access_table tc_volatile_table = {
1479 .yes_ranges = tc_volatile_ranges,
1480 .n_yes_ranges = ARRAY_SIZE(tc_volatile_ranges),
1481};
1482
1483static bool tc_writeable_reg(struct device *dev, unsigned int reg)
1484{
1485 return (reg != TC_IDREG) &&
1486 (reg != DP0_LTSTAT) &&
1487 (reg != DP0_SNKLTCHGREQ);
1488}
1489
1490static const struct regmap_config tc_regmap_config = {
1491 .name = "tc358767",
1492 .reg_bits = 16,
1493 .val_bits = 32,
1494 .reg_stride = 4,
1495 .max_register = PLL_DBG,
1496 .cache_type = REGCACHE_RBTREE,
1497 .readable_reg = tc_readable_reg,
1498 .volatile_table = &tc_volatile_table,
1499 .writeable_reg = tc_writeable_reg,
1500 .reg_format_endian = REGMAP_ENDIAN_BIG,
1501 .val_format_endian = REGMAP_ENDIAN_LITTLE,
1502};
1503
1504static irqreturn_t tc_irq_handler(int irq, void *arg)
1505{
1506 struct tc_data *tc = arg;
1507 u32 val;
1508 int r;
1509
1510 r = regmap_read(tc->regmap, INTSTS_G, &val);
1511 if (r)
1512 return IRQ_NONE;
1513
1514 if (!val)
1515 return IRQ_NONE;
1516
1517 if (val & INT_SYSERR) {
1518 u32 stat = 0;
1519
1520 regmap_read(tc->regmap, SYSSTAT, &stat);
1521
1522 dev_err(tc->dev, "syserr %x\n", stat);
1523 }
1524
1525 if (tc->hpd_pin >= 0 && tc->bridge.dev) {
1526 /*
1527 * H is triggered when the GPIO goes high.
1528 *
1529 * LC is triggered when the GPIO goes low and stays low for
1530 * the duration of LCNT
1531 */
1532 bool h = val & INT_GPIO_H(tc->hpd_pin);
1533 bool lc = val & INT_GPIO_LC(tc->hpd_pin);
1534
1535 dev_dbg(tc->dev, "GPIO%d: %s %s\n", tc->hpd_pin,
1536 h ? "H" : "", lc ? "LC" : "");
1537
1538 if (h || lc)
1539 drm_kms_helper_hotplug_event(tc->bridge.dev);
1540 }
1541
1542 regmap_write(tc->regmap, INTSTS_G, val);
1543
1544 return IRQ_HANDLED;
1545}
1546
1547static int tc_probe(struct i2c_client *client, const struct i2c_device_id *id)
1548{
1549 struct device *dev = &client->dev;
1550 struct tc_data *tc;
1551 int ret;
1552
1553 tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL);
1554 if (!tc)
1555 return -ENOMEM;
1556
1557 tc->dev = dev;
1558
1559 /* port@2 is the output port */
1560 ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &tc->panel, NULL);
1561 if (ret && ret != -ENODEV)
1562 return ret;
1563
1564 /* Shut down GPIO is optional */
1565 tc->sd_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH);
1566 if (IS_ERR(tc->sd_gpio))
1567 return PTR_ERR(tc->sd_gpio);
1568
1569 if (tc->sd_gpio) {
1570 gpiod_set_value_cansleep(tc->sd_gpio, 0);
1571 usleep_range(5000, 10000);
1572 }
1573
1574 /* Reset GPIO is optional */
1575 tc->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
1576 if (IS_ERR(tc->reset_gpio))
1577 return PTR_ERR(tc->reset_gpio);
1578
1579 if (tc->reset_gpio) {
1580 gpiod_set_value_cansleep(tc->reset_gpio, 1);
1581 usleep_range(5000, 10000);
1582 }
1583
1584 tc->refclk = devm_clk_get(dev, "ref");
1585 if (IS_ERR(tc->refclk)) {
1586 ret = PTR_ERR(tc->refclk);
1587 dev_err(dev, "Failed to get refclk: %d\n", ret);
1588 return ret;
1589 }
1590
1591 tc->regmap = devm_regmap_init_i2c(client, &tc_regmap_config);
1592 if (IS_ERR(tc->regmap)) {
1593 ret = PTR_ERR(tc->regmap);
1594 dev_err(dev, "Failed to initialize regmap: %d\n", ret);
1595 return ret;
1596 }
1597
1598 ret = of_property_read_u32(dev->of_node, "toshiba,hpd-pin",
1599 &tc->hpd_pin);
1600 if (ret) {
1601 tc->hpd_pin = -ENODEV;
1602 } else {
1603 if (tc->hpd_pin < 0 || tc->hpd_pin > 1) {
1604 dev_err(dev, "failed to parse HPD number\n");
1605 return ret;
1606 }
1607 }
1608
1609 if (client->irq > 0) {
1610 /* enable SysErr */
1611 regmap_write(tc->regmap, INTCTL_G, INT_SYSERR);
1612
1613 ret = devm_request_threaded_irq(dev, client->irq,
1614 NULL, tc_irq_handler,
1615 IRQF_ONESHOT,
1616 "tc358767-irq", tc);
1617 if (ret) {
1618 dev_err(dev, "failed to register dp interrupt\n");
1619 return ret;
1620 }
1621
1622 tc->have_irq = true;
1623 }
1624
1625 ret = regmap_read(tc->regmap, TC_IDREG, &tc->rev);
1626 if (ret) {
1627 dev_err(tc->dev, "can not read device ID: %d\n", ret);
1628 return ret;
1629 }
1630
1631 if ((tc->rev != 0x6601) && (tc->rev != 0x6603)) {
1632 dev_err(tc->dev, "invalid device ID: 0x%08x\n", tc->rev);
1633 return -EINVAL;
1634 }
1635
1636 tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */
1637
1638 if (!tc->reset_gpio) {
1639 /*
1640 * If the reset pin isn't present, do a software reset. It isn't
1641 * as thorough as the hardware reset, as we can't reset the I2C
1642 * communication block for obvious reasons, but it's getting the
1643 * chip into a defined state.
1644 */
1645 regmap_update_bits(tc->regmap, SYSRSTENB,
1646 ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP,
1647 0);
1648 regmap_update_bits(tc->regmap, SYSRSTENB,
1649 ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP,
1650 ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP);
1651 usleep_range(5000, 10000);
1652 }
1653
1654 if (tc->hpd_pin >= 0) {
1655 u32 lcnt_reg = tc->hpd_pin == 0 ? INT_GP0_LCNT : INT_GP1_LCNT;
1656 u32 h_lc = INT_GPIO_H(tc->hpd_pin) | INT_GPIO_LC(tc->hpd_pin);
1657
1658 /* Set LCNT to 2ms */
1659 regmap_write(tc->regmap, lcnt_reg,
1660 clk_get_rate(tc->refclk) * 2 / 1000);
1661 /* We need the "alternate" mode for HPD */
1662 regmap_write(tc->regmap, GPIOM, BIT(tc->hpd_pin));
1663
1664 if (tc->have_irq) {
1665 /* enable H & LC */
1666 regmap_update_bits(tc->regmap, INTCTL_G, h_lc, h_lc);
1667 }
1668 }
1669
1670 ret = tc_aux_link_setup(tc);
1671 if (ret)
1672 return ret;
1673
1674 /* Register DP AUX channel */
1675 tc->aux.name = "TC358767 AUX i2c adapter";
1676 tc->aux.dev = tc->dev;
1677 tc->aux.transfer = tc_aux_transfer;
1678 ret = drm_dp_aux_register(&tc->aux);
1679 if (ret)
1680 return ret;
1681
1682 tc->bridge.funcs = &tc_bridge_funcs;
1683 tc->bridge.of_node = dev->of_node;
1684 drm_bridge_add(&tc->bridge);
1685
1686 i2c_set_clientdata(client, tc);
1687
1688 return 0;
1689}
1690
1691static int tc_remove(struct i2c_client *client)
1692{
1693 struct tc_data *tc = i2c_get_clientdata(client);
1694
1695 drm_bridge_remove(&tc->bridge);
1696 drm_dp_aux_unregister(&tc->aux);
1697
1698 return 0;
1699}
1700
1701static const struct i2c_device_id tc358767_i2c_ids[] = {
1702 { "tc358767", 0 },
1703 { }
1704};
1705MODULE_DEVICE_TABLE(i2c, tc358767_i2c_ids);
1706
1707static const struct of_device_id tc358767_of_ids[] = {
1708 { .compatible = "toshiba,tc358767", },
1709 { }
1710};
1711MODULE_DEVICE_TABLE(of, tc358767_of_ids);
1712
1713static struct i2c_driver tc358767_driver = {
1714 .driver = {
1715 .name = "tc358767",
1716 .of_match_table = tc358767_of_ids,
1717 },
1718 .id_table = tc358767_i2c_ids,
1719 .probe = tc_probe,
1720 .remove = tc_remove,
1721};
1722module_i2c_driver(tc358767_driver);
1723
1724MODULE_AUTHOR("Andrey Gusakov <andrey.gusakov@cogentembedded.com>");
1725MODULE_DESCRIPTION("tc358767 eDP encoder driver");
1726MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * TC358767/TC358867/TC9595 DSI/DPI-to-DPI/(e)DP bridge driver
4 *
5 * The TC358767/TC358867/TC9595 can operate in multiple modes.
6 * All modes are supported -- DPI->(e)DP / DSI->DPI / DSI->(e)DP .
7 *
8 * Copyright (C) 2016 CogentEmbedded Inc
9 * Author: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
10 *
11 * Copyright (C) 2016 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de>
12 *
13 * Copyright (C) 2016 Zodiac Inflight Innovations
14 *
15 * Initially based on: drivers/gpu/drm/i2c/tda998x_drv.c
16 *
17 * Copyright (C) 2012 Texas Instruments
18 * Author: Rob Clark <robdclark@gmail.com>
19 */
20
21#include <linux/bitfield.h>
22#include <linux/clk.h>
23#include <linux/device.h>
24#include <linux/gpio/consumer.h>
25#include <linux/i2c.h>
26#include <linux/kernel.h>
27#include <linux/media-bus-format.h>
28#include <linux/module.h>
29#include <linux/regmap.h>
30#include <linux/slab.h>
31
32#include <drm/display/drm_dp_helper.h>
33#include <drm/drm_atomic_helper.h>
34#include <drm/drm_bridge.h>
35#include <drm/drm_edid.h>
36#include <drm/drm_mipi_dsi.h>
37#include <drm/drm_of.h>
38#include <drm/drm_panel.h>
39#include <drm/drm_print.h>
40#include <drm/drm_probe_helper.h>
41
42/* Registers */
43
44/* DSI D-PHY Layer registers */
45#define D0W_DPHYCONTTX 0x0004
46#define CLW_DPHYCONTTX 0x0020
47#define D0W_DPHYCONTRX 0x0024
48#define D1W_DPHYCONTRX 0x0028
49#define D2W_DPHYCONTRX 0x002c
50#define D3W_DPHYCONTRX 0x0030
51#define COM_DPHYCONTRX 0x0038
52#define CLW_CNTRL 0x0040
53#define D0W_CNTRL 0x0044
54#define D1W_CNTRL 0x0048
55#define D2W_CNTRL 0x004c
56#define D3W_CNTRL 0x0050
57#define TESTMODE_CNTRL 0x0054
58
59/* PPI layer registers */
60#define PPI_STARTPPI 0x0104 /* START control bit */
61#define PPI_BUSYPPI 0x0108 /* PPI busy status */
62#define PPI_LPTXTIMECNT 0x0114 /* LPTX timing signal */
63#define LPX_PERIOD 3
64#define PPI_LANEENABLE 0x0134
65#define PPI_TX_RX_TA 0x013c
66#define TTA_GET 0x40000
67#define TTA_SURE 6
68#define PPI_D0S_ATMR 0x0144
69#define PPI_D1S_ATMR 0x0148
70#define PPI_D0S_CLRSIPOCOUNT 0x0164 /* Assertion timer for Lane 0 */
71#define PPI_D1S_CLRSIPOCOUNT 0x0168 /* Assertion timer for Lane 1 */
72#define PPI_D2S_CLRSIPOCOUNT 0x016c /* Assertion timer for Lane 2 */
73#define PPI_D3S_CLRSIPOCOUNT 0x0170 /* Assertion timer for Lane 3 */
74#define PPI_START_FUNCTION BIT(0)
75
76/* DSI layer registers */
77#define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
78#define DSI_BUSYDSI 0x0208 /* DSI busy status */
79#define DSI_LANEENABLE 0x0210 /* Enables each lane */
80#define DSI_RX_START BIT(0)
81
82/* Lane enable PPI and DSI register bits */
83#define LANEENABLE_CLEN BIT(0)
84#define LANEENABLE_L0EN BIT(1)
85#define LANEENABLE_L1EN BIT(2)
86#define LANEENABLE_L2EN BIT(1)
87#define LANEENABLE_L3EN BIT(2)
88
89#define DSI_LANESTATUS0 0x0214 /* DSI lane status 0 */
90#define DSI_LANESTATUS1 0x0218 /* DSI lane status 1 */
91#define DSI_INTSTATUS 0x0220 /* Interrupt Status */
92#define DSI_INTMASK 0x0224 /* Interrupt Mask */
93#define DSI_INTCLR 0x0228 /* Interrupt Clear */
94#define DSI_LPTXTO 0x0230 /* LPTX Time Out Counter */
95
96/* DSI General Registers */
97#define DSIERRCNT 0x0300 /* DSI Error Count Register */
98
99/* DSI Application Layer Registers */
100#define APLCTRL 0x0400 /* Application layer Control Register */
101#define RDPKTLN 0x0404 /* DSI Read packet Length Register */
102
103/* Display Parallel Input Interface */
104#define DPIPXLFMT 0x0440
105#define VS_POL_ACTIVE_LOW (1 << 10)
106#define HS_POL_ACTIVE_LOW (1 << 9)
107#define DE_POL_ACTIVE_HIGH (0 << 8)
108#define SUB_CFG_TYPE_CONFIG1 (0 << 2) /* LSB aligned */
109#define SUB_CFG_TYPE_CONFIG2 (1 << 2) /* Loosely Packed */
110#define SUB_CFG_TYPE_CONFIG3 (2 << 2) /* LSB aligned 8-bit */
111#define DPI_BPP_RGB888 (0 << 0)
112#define DPI_BPP_RGB666 (1 << 0)
113#define DPI_BPP_RGB565 (2 << 0)
114
115/* Display Parallel Output Interface */
116#define POCTRL 0x0448
117#define POCTRL_S2P BIT(7)
118#define POCTRL_PCLK_POL BIT(3)
119#define POCTRL_VS_POL BIT(2)
120#define POCTRL_HS_POL BIT(1)
121#define POCTRL_DE_POL BIT(0)
122
123/* Video Path */
124#define VPCTRL0 0x0450
125#define VSDELAY GENMASK(31, 20)
126#define OPXLFMT_RGB666 (0 << 8)
127#define OPXLFMT_RGB888 (1 << 8)
128#define FRMSYNC_DISABLED (0 << 4) /* Video Timing Gen Disabled */
129#define FRMSYNC_ENABLED (1 << 4) /* Video Timing Gen Enabled */
130#define MSF_DISABLED (0 << 0) /* Magic Square FRC disabled */
131#define MSF_ENABLED (1 << 0) /* Magic Square FRC enabled */
132#define HTIM01 0x0454
133#define HPW GENMASK(8, 0)
134#define HBPR GENMASK(24, 16)
135#define HTIM02 0x0458
136#define HDISPR GENMASK(10, 0)
137#define HFPR GENMASK(24, 16)
138#define VTIM01 0x045c
139#define VSPR GENMASK(7, 0)
140#define VBPR GENMASK(23, 16)
141#define VTIM02 0x0460
142#define VFPR GENMASK(23, 16)
143#define VDISPR GENMASK(10, 0)
144#define VFUEN0 0x0464
145#define VFUEN BIT(0) /* Video Frame Timing Upload */
146
147/* System */
148#define TC_IDREG 0x0500 /* Chip ID and Revision ID */
149#define SYSBOOT 0x0504 /* System BootStrap Status Register */
150#define SYSSTAT 0x0508 /* System Status Register */
151#define SYSRSTENB 0x050c /* System Reset/Enable Register */
152#define ENBI2C (1 << 0)
153#define ENBLCD0 (1 << 2)
154#define ENBBM (1 << 3)
155#define ENBDSIRX (1 << 4)
156#define ENBREG (1 << 5)
157#define ENBHDCP (1 << 8)
158#define SYSCTRL 0x0510 /* System Control Register */
159#define DP0_AUDSRC_NO_INPUT (0 << 3)
160#define DP0_AUDSRC_I2S_RX (1 << 3)
161#define DP0_VIDSRC_NO_INPUT (0 << 0)
162#define DP0_VIDSRC_DSI_RX (1 << 0)
163#define DP0_VIDSRC_DPI_RX (2 << 0)
164#define DP0_VIDSRC_COLOR_BAR (3 << 0)
165#define GPIOM 0x0540 /* GPIO Mode Control Register */
166#define GPIOC 0x0544 /* GPIO Direction Control Register */
167#define GPIOO 0x0548 /* GPIO Output Register */
168#define GPIOI 0x054c /* GPIO Input Register */
169#define INTCTL_G 0x0560 /* General Interrupts Control Register */
170#define INTSTS_G 0x0564 /* General Interrupts Status Register */
171
172#define INT_SYSERR BIT(16)
173#define INT_GPIO_H(x) (1 << (x == 0 ? 2 : 10))
174#define INT_GPIO_LC(x) (1 << (x == 0 ? 3 : 11))
175
176#define TEST_INT_C 0x0570 /* Test Interrupts Control Register */
177#define TEST_INT_S 0x0574 /* Test Interrupts Status Register */
178
179#define INT_GP0_LCNT 0x0584 /* Interrupt GPIO0 Low Count Value Register */
180#define INT_GP1_LCNT 0x0588 /* Interrupt GPIO1 Low Count Value Register */
181
182/* Control */
183#define DP0CTL 0x0600
184#define VID_MN_GEN BIT(6) /* Auto-generate M/N values */
185#define EF_EN BIT(5) /* Enable Enhanced Framing */
186#define VID_EN BIT(1) /* Video transmission enable */
187#define DP_EN BIT(0) /* Enable DPTX function */
188
189/* Clocks */
190#define DP0_VIDMNGEN0 0x0610 /* DP0 Video Force M Value Register */
191#define DP0_VIDMNGEN1 0x0614 /* DP0 Video Force N Value Register */
192#define DP0_VMNGENSTATUS 0x0618 /* DP0 Video Current M Value Register */
193#define DP0_AUDMNGEN0 0x0628 /* DP0 Audio Force M Value Register */
194#define DP0_AUDMNGEN1 0x062c /* DP0 Audio Force N Value Register */
195#define DP0_AMNGENSTATUS 0x0630 /* DP0 Audio Current M Value Register */
196
197/* Main Channel */
198#define DP0_SECSAMPLE 0x0640
199#define DP0_VIDSYNCDELAY 0x0644
200#define VID_SYNC_DLY GENMASK(15, 0)
201#define THRESH_DLY GENMASK(31, 16)
202
203#define DP0_TOTALVAL 0x0648
204#define H_TOTAL GENMASK(15, 0)
205#define V_TOTAL GENMASK(31, 16)
206#define DP0_STARTVAL 0x064c
207#define H_START GENMASK(15, 0)
208#define V_START GENMASK(31, 16)
209#define DP0_ACTIVEVAL 0x0650
210#define H_ACT GENMASK(15, 0)
211#define V_ACT GENMASK(31, 16)
212
213#define DP0_SYNCVAL 0x0654
214#define VS_WIDTH GENMASK(30, 16)
215#define HS_WIDTH GENMASK(14, 0)
216#define SYNCVAL_HS_POL_ACTIVE_LOW (1 << 15)
217#define SYNCVAL_VS_POL_ACTIVE_LOW (1 << 31)
218#define DP0_MISC 0x0658
219#define TU_SIZE_RECOMMENDED (63) /* LSCLK cycles per TU */
220#define MAX_TU_SYMBOL GENMASK(28, 23)
221#define TU_SIZE GENMASK(21, 16)
222#define BPC_6 (0 << 5)
223#define BPC_8 (1 << 5)
224
225/* AUX channel */
226#define DP0_AUXCFG0 0x0660
227#define DP0_AUXCFG0_BSIZE GENMASK(11, 8)
228#define DP0_AUXCFG0_ADDR_ONLY BIT(4)
229#define DP0_AUXCFG1 0x0664
230#define AUX_RX_FILTER_EN BIT(16)
231
232#define DP0_AUXADDR 0x0668
233#define DP0_AUXWDATA(i) (0x066c + (i) * 4)
234#define DP0_AUXRDATA(i) (0x067c + (i) * 4)
235#define DP0_AUXSTATUS 0x068c
236#define AUX_BYTES GENMASK(15, 8)
237#define AUX_STATUS GENMASK(7, 4)
238#define AUX_TIMEOUT BIT(1)
239#define AUX_BUSY BIT(0)
240#define DP0_AUXI2CADR 0x0698
241
242/* Link Training */
243#define DP0_SRCCTRL 0x06a0
244#define DP0_SRCCTRL_SCRMBLDIS BIT(13)
245#define DP0_SRCCTRL_EN810B BIT(12)
246#define DP0_SRCCTRL_NOTP (0 << 8)
247#define DP0_SRCCTRL_TP1 (1 << 8)
248#define DP0_SRCCTRL_TP2 (2 << 8)
249#define DP0_SRCCTRL_LANESKEW BIT(7)
250#define DP0_SRCCTRL_SSCG BIT(3)
251#define DP0_SRCCTRL_LANES_1 (0 << 2)
252#define DP0_SRCCTRL_LANES_2 (1 << 2)
253#define DP0_SRCCTRL_BW27 (1 << 1)
254#define DP0_SRCCTRL_BW162 (0 << 1)
255#define DP0_SRCCTRL_AUTOCORRECT BIT(0)
256#define DP0_LTSTAT 0x06d0
257#define LT_LOOPDONE BIT(13)
258#define LT_STATUS_MASK (0x1f << 8)
259#define LT_CHANNEL1_EQ_BITS (DP_CHANNEL_EQ_BITS << 4)
260#define LT_INTERLANE_ALIGN_DONE BIT(3)
261#define LT_CHANNEL0_EQ_BITS (DP_CHANNEL_EQ_BITS)
262#define DP0_SNKLTCHGREQ 0x06d4
263#define DP0_LTLOOPCTRL 0x06d8
264#define DP0_SNKLTCTRL 0x06e4
265#define DP0_TPATDAT0 0x06e8 /* DP0 Test Pattern bits 29 to 0 */
266#define DP0_TPATDAT1 0x06ec /* DP0 Test Pattern bits 59 to 30 */
267#define DP0_TPATDAT2 0x06f0 /* DP0 Test Pattern bits 89 to 60 */
268#define DP0_TPATDAT3 0x06f4 /* DP0 Test Pattern bits 119 to 90 */
269
270#define AUDCFG0 0x0700 /* DP0 Audio Config0 Register */
271#define AUDCFG1 0x0704 /* DP0 Audio Config1 Register */
272#define AUDIFDATA0 0x0708 /* DP0 Audio Info Frame Bytes 3 to 0 */
273#define AUDIFDATA1 0x070c /* DP0 Audio Info Frame Bytes 7 to 4 */
274#define AUDIFDATA2 0x0710 /* DP0 Audio Info Frame Bytes 11 to 8 */
275#define AUDIFDATA3 0x0714 /* DP0 Audio Info Frame Bytes 15 to 12 */
276#define AUDIFDATA4 0x0718 /* DP0 Audio Info Frame Bytes 19 to 16 */
277#define AUDIFDATA5 0x071c /* DP0 Audio Info Frame Bytes 23 to 20 */
278#define AUDIFDATA6 0x0720 /* DP0 Audio Info Frame Bytes 27 to 24 */
279
280#define DP1_SRCCTRL 0x07a0 /* DP1 Control Register */
281
282/* PHY */
283#define DP_PHY_CTRL 0x0800
284#define DP_PHY_RST BIT(28) /* DP PHY Global Soft Reset */
285#define BGREN BIT(25) /* AUX PHY BGR Enable */
286#define PWR_SW_EN BIT(24) /* PHY Power Switch Enable */
287#define PHY_M1_RST BIT(12) /* Reset PHY1 Main Channel */
288#define PHY_RDY BIT(16) /* PHY Main Channels Ready */
289#define PHY_M0_RST BIT(8) /* Reset PHY0 Main Channel */
290#define PHY_2LANE BIT(2) /* PHY Enable 2 lanes */
291#define PHY_A0_EN BIT(1) /* PHY Aux Channel0 Enable */
292#define PHY_M0_EN BIT(0) /* PHY Main Channel0 Enable */
293#define DP_PHY_CFG_WR 0x0810 /* DP PHY Configuration Test Write Register */
294#define DP_PHY_CFG_RD 0x0814 /* DP PHY Configuration Test Read Register */
295#define DP0_AUX_PHY_CTRL 0x0820 /* DP0 AUX PHY Control Register */
296#define DP0_MAIN_PHY_DBG 0x0840 /* DP0 Main PHY Test Debug Register */
297
298/* I2S */
299#define I2SCFG 0x0880 /* I2S Audio Config 0 Register */
300#define I2SCH0STAT0 0x0888 /* I2S Audio Channel 0 Status Bytes 3 to 0 */
301#define I2SCH0STAT1 0x088c /* I2S Audio Channel 0 Status Bytes 7 to 4 */
302#define I2SCH0STAT2 0x0890 /* I2S Audio Channel 0 Status Bytes 11 to 8 */
303#define I2SCH0STAT3 0x0894 /* I2S Audio Channel 0 Status Bytes 15 to 12 */
304#define I2SCH0STAT4 0x0898 /* I2S Audio Channel 0 Status Bytes 19 to 16 */
305#define I2SCH0STAT5 0x089c /* I2S Audio Channel 0 Status Bytes 23 to 20 */
306#define I2SCH1STAT0 0x08a0 /* I2S Audio Channel 1 Status Bytes 3 to 0 */
307#define I2SCH1STAT1 0x08a4 /* I2S Audio Channel 1 Status Bytes 7 to 4 */
308#define I2SCH1STAT2 0x08a8 /* I2S Audio Channel 1 Status Bytes 11 to 8 */
309#define I2SCH1STAT3 0x08ac /* I2S Audio Channel 1 Status Bytes 15 to 12 */
310#define I2SCH1STAT4 0x08b0 /* I2S Audio Channel 1 Status Bytes 19 to 16 */
311#define I2SCH1STAT5 0x08b4 /* I2S Audio Channel 1 Status Bytes 23 to 20 */
312
313/* PLL */
314#define DP0_PLLCTRL 0x0900
315#define DP1_PLLCTRL 0x0904 /* not defined in DS */
316#define PXL_PLLCTRL 0x0908
317#define PLLUPDATE BIT(2)
318#define PLLBYP BIT(1)
319#define PLLEN BIT(0)
320#define PXL_PLLPARAM 0x0914
321#define IN_SEL_REFCLK (0 << 14)
322#define SYS_PLLPARAM 0x0918
323#define REF_FREQ_38M4 (0 << 8) /* 38.4 MHz */
324#define REF_FREQ_19M2 (1 << 8) /* 19.2 MHz */
325#define REF_FREQ_26M (2 << 8) /* 26 MHz */
326#define REF_FREQ_13M (3 << 8) /* 13 MHz */
327#define SYSCLK_SEL_LSCLK (0 << 4)
328#define LSCLK_DIV_1 (0 << 0)
329#define LSCLK_DIV_2 (1 << 0)
330
331/* Test & Debug */
332#define TSTCTL 0x0a00
333#define COLOR_R GENMASK(31, 24)
334#define COLOR_G GENMASK(23, 16)
335#define COLOR_B GENMASK(15, 8)
336#define ENI2CFILTER BIT(4)
337#define COLOR_BAR_MODE GENMASK(1, 0)
338#define COLOR_BAR_MODE_BARS 2
339#define PLL_DBG 0x0a04
340
341static bool tc_test_pattern;
342module_param_named(test, tc_test_pattern, bool, 0644);
343
344struct tc_edp_link {
345 u8 dpcd[DP_RECEIVER_CAP_SIZE];
346 unsigned int rate;
347 u8 num_lanes;
348 u8 assr;
349 bool scrambler_dis;
350 bool spread;
351};
352
353struct tc_data {
354 struct device *dev;
355 struct regmap *regmap;
356 struct drm_dp_aux aux;
357
358 struct drm_bridge bridge;
359 struct drm_bridge *panel_bridge;
360 struct drm_connector connector;
361
362 struct mipi_dsi_device *dsi;
363
364 /* link settings */
365 struct tc_edp_link link;
366
367 /* current mode */
368 struct drm_display_mode mode;
369
370 u32 rev;
371 u8 assr;
372
373 struct gpio_desc *sd_gpio;
374 struct gpio_desc *reset_gpio;
375 struct clk *refclk;
376
377 /* do we have IRQ */
378 bool have_irq;
379
380 /* Input connector type, DSI and not DPI. */
381 bool input_connector_dsi;
382
383 /* HPD pin number (0 or 1) or -ENODEV */
384 int hpd_pin;
385};
386
387static inline struct tc_data *aux_to_tc(struct drm_dp_aux *a)
388{
389 return container_of(a, struct tc_data, aux);
390}
391
392static inline struct tc_data *bridge_to_tc(struct drm_bridge *b)
393{
394 return container_of(b, struct tc_data, bridge);
395}
396
397static inline struct tc_data *connector_to_tc(struct drm_connector *c)
398{
399 return container_of(c, struct tc_data, connector);
400}
401
402static inline int tc_poll_timeout(struct tc_data *tc, unsigned int addr,
403 unsigned int cond_mask,
404 unsigned int cond_value,
405 unsigned long sleep_us, u64 timeout_us)
406{
407 unsigned int val;
408
409 return regmap_read_poll_timeout(tc->regmap, addr, val,
410 (val & cond_mask) == cond_value,
411 sleep_us, timeout_us);
412}
413
414static int tc_aux_wait_busy(struct tc_data *tc)
415{
416 return tc_poll_timeout(tc, DP0_AUXSTATUS, AUX_BUSY, 0, 100, 100000);
417}
418
419static int tc_aux_write_data(struct tc_data *tc, const void *data,
420 size_t size)
421{
422 u32 auxwdata[DP_AUX_MAX_PAYLOAD_BYTES / sizeof(u32)] = { 0 };
423 int ret, count = ALIGN(size, sizeof(u32));
424
425 memcpy(auxwdata, data, size);
426
427 ret = regmap_raw_write(tc->regmap, DP0_AUXWDATA(0), auxwdata, count);
428 if (ret)
429 return ret;
430
431 return size;
432}
433
434static int tc_aux_read_data(struct tc_data *tc, void *data, size_t size)
435{
436 u32 auxrdata[DP_AUX_MAX_PAYLOAD_BYTES / sizeof(u32)];
437 int ret, count = ALIGN(size, sizeof(u32));
438
439 ret = regmap_raw_read(tc->regmap, DP0_AUXRDATA(0), auxrdata, count);
440 if (ret)
441 return ret;
442
443 memcpy(data, auxrdata, size);
444
445 return size;
446}
447
448static u32 tc_auxcfg0(struct drm_dp_aux_msg *msg, size_t size)
449{
450 u32 auxcfg0 = msg->request;
451
452 if (size)
453 auxcfg0 |= FIELD_PREP(DP0_AUXCFG0_BSIZE, size - 1);
454 else
455 auxcfg0 |= DP0_AUXCFG0_ADDR_ONLY;
456
457 return auxcfg0;
458}
459
460static ssize_t tc_aux_transfer(struct drm_dp_aux *aux,
461 struct drm_dp_aux_msg *msg)
462{
463 struct tc_data *tc = aux_to_tc(aux);
464 size_t size = min_t(size_t, DP_AUX_MAX_PAYLOAD_BYTES - 1, msg->size);
465 u8 request = msg->request & ~DP_AUX_I2C_MOT;
466 u32 auxstatus;
467 int ret;
468
469 ret = tc_aux_wait_busy(tc);
470 if (ret)
471 return ret;
472
473 switch (request) {
474 case DP_AUX_NATIVE_READ:
475 case DP_AUX_I2C_READ:
476 break;
477 case DP_AUX_NATIVE_WRITE:
478 case DP_AUX_I2C_WRITE:
479 if (size) {
480 ret = tc_aux_write_data(tc, msg->buffer, size);
481 if (ret < 0)
482 return ret;
483 }
484 break;
485 default:
486 return -EINVAL;
487 }
488
489 /* Store address */
490 ret = regmap_write(tc->regmap, DP0_AUXADDR, msg->address);
491 if (ret)
492 return ret;
493 /* Start transfer */
494 ret = regmap_write(tc->regmap, DP0_AUXCFG0, tc_auxcfg0(msg, size));
495 if (ret)
496 return ret;
497
498 ret = tc_aux_wait_busy(tc);
499 if (ret)
500 return ret;
501
502 ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &auxstatus);
503 if (ret)
504 return ret;
505
506 if (auxstatus & AUX_TIMEOUT)
507 return -ETIMEDOUT;
508 /*
509 * For some reason address-only DP_AUX_I2C_WRITE (MOT), still
510 * reports 1 byte transferred in its status. To deal we that
511 * we ignore aux_bytes field if we know that this was an
512 * address-only transfer
513 */
514 if (size)
515 size = FIELD_GET(AUX_BYTES, auxstatus);
516 msg->reply = FIELD_GET(AUX_STATUS, auxstatus);
517
518 switch (request) {
519 case DP_AUX_NATIVE_READ:
520 case DP_AUX_I2C_READ:
521 if (size)
522 return tc_aux_read_data(tc, msg->buffer, size);
523 break;
524 }
525
526 return size;
527}
528
529static const char * const training_pattern1_errors[] = {
530 "No errors",
531 "Aux write error",
532 "Aux read error",
533 "Max voltage reached error",
534 "Loop counter expired error",
535 "res", "res", "res"
536};
537
538static const char * const training_pattern2_errors[] = {
539 "No errors",
540 "Aux write error",
541 "Aux read error",
542 "Clock recovery failed error",
543 "Loop counter expired error",
544 "res", "res", "res"
545};
546
547static u32 tc_srcctrl(struct tc_data *tc)
548{
549 /*
550 * No training pattern, skew lane 1 data by two LSCLK cycles with
551 * respect to lane 0 data, AutoCorrect Mode = 0
552 */
553 u32 reg = DP0_SRCCTRL_NOTP | DP0_SRCCTRL_LANESKEW | DP0_SRCCTRL_EN810B;
554
555 if (tc->link.scrambler_dis)
556 reg |= DP0_SRCCTRL_SCRMBLDIS; /* Scrambler Disabled */
557 if (tc->link.spread)
558 reg |= DP0_SRCCTRL_SSCG; /* Spread Spectrum Enable */
559 if (tc->link.num_lanes == 2)
560 reg |= DP0_SRCCTRL_LANES_2; /* Two Main Channel Lanes */
561 if (tc->link.rate != 162000)
562 reg |= DP0_SRCCTRL_BW27; /* 2.7 Gbps link */
563 return reg;
564}
565
566static int tc_pllupdate(struct tc_data *tc, unsigned int pllctrl)
567{
568 int ret;
569
570 ret = regmap_write(tc->regmap, pllctrl, PLLUPDATE | PLLEN);
571 if (ret)
572 return ret;
573
574 /* Wait for PLL to lock: up to 7.5 ms, depending on refclk */
575 usleep_range(15000, 20000);
576
577 return 0;
578}
579
580static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
581{
582 int ret;
583 int i_pre, best_pre = 1;
584 int i_post, best_post = 1;
585 int div, best_div = 1;
586 int mul, best_mul = 1;
587 int delta, best_delta;
588 int ext_div[] = {1, 2, 3, 5, 7};
589 int clk_min, clk_max;
590 int best_pixelclock = 0;
591 int vco_hi = 0;
592 u32 pxl_pllparam;
593
594 /*
595 * refclk * mul / (ext_pre_div * pre_div) should be in range:
596 * - DPI ..... 0 to 100 MHz
597 * - (e)DP ... 150 to 650 MHz
598 */
599 if (tc->bridge.type == DRM_MODE_CONNECTOR_DPI) {
600 clk_min = 0;
601 clk_max = 100000000;
602 } else {
603 clk_min = 150000000;
604 clk_max = 650000000;
605 }
606
607 dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock,
608 refclk);
609 best_delta = pixelclock;
610 /* Loop over all possible ext_divs, skipping invalid configurations */
611 for (i_pre = 0; i_pre < ARRAY_SIZE(ext_div); i_pre++) {
612 /*
613 * refclk / ext_pre_div should be in the 1 to 200 MHz range.
614 * We don't allow any refclk > 200 MHz, only check lower bounds.
615 */
616 if (refclk / ext_div[i_pre] < 1000000)
617 continue;
618 for (i_post = 0; i_post < ARRAY_SIZE(ext_div); i_post++) {
619 for (div = 1; div <= 16; div++) {
620 u32 clk, iclk;
621 u64 tmp;
622
623 /* PCLK PLL input unit clock ... 6..40 MHz */
624 iclk = refclk / (div * ext_div[i_pre]);
625 if (iclk < 6000000 || iclk > 40000000)
626 continue;
627
628 tmp = pixelclock * ext_div[i_pre] *
629 ext_div[i_post] * div;
630 do_div(tmp, refclk);
631 mul = tmp;
632
633 /* Check limits */
634 if ((mul < 1) || (mul > 128))
635 continue;
636
637 clk = (refclk / ext_div[i_pre] / div) * mul;
638 if ((clk > clk_max) || (clk < clk_min))
639 continue;
640
641 clk = clk / ext_div[i_post];
642 delta = clk - pixelclock;
643
644 if (abs(delta) < abs(best_delta)) {
645 best_pre = i_pre;
646 best_post = i_post;
647 best_div = div;
648 best_mul = mul;
649 best_delta = delta;
650 best_pixelclock = clk;
651 }
652 }
653 }
654 }
655 if (best_pixelclock == 0) {
656 dev_err(tc->dev, "Failed to calc clock for %d pixelclock\n",
657 pixelclock);
658 return -EINVAL;
659 }
660
661 dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock,
662 best_delta);
663 dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk,
664 ext_div[best_pre], best_div, best_mul, ext_div[best_post]);
665
666 /* if VCO >= 300 MHz */
667 if (refclk / ext_div[best_pre] / best_div * best_mul >= 300000000)
668 vco_hi = 1;
669 /* see DS */
670 if (best_div == 16)
671 best_div = 0;
672 if (best_mul == 128)
673 best_mul = 0;
674
675 /* Power up PLL and switch to bypass */
676 ret = regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP | PLLEN);
677 if (ret)
678 return ret;
679
680 pxl_pllparam = vco_hi << 24; /* For PLL VCO >= 300 MHz = 1 */
681 pxl_pllparam |= ext_div[best_pre] << 20; /* External Pre-divider */
682 pxl_pllparam |= ext_div[best_post] << 16; /* External Post-divider */
683 pxl_pllparam |= IN_SEL_REFCLK; /* Use RefClk as PLL input */
684 pxl_pllparam |= best_div << 8; /* Divider for PLL RefClk */
685 pxl_pllparam |= best_mul; /* Multiplier for PLL */
686
687 ret = regmap_write(tc->regmap, PXL_PLLPARAM, pxl_pllparam);
688 if (ret)
689 return ret;
690
691 /* Force PLL parameter update and disable bypass */
692 return tc_pllupdate(tc, PXL_PLLCTRL);
693}
694
695static int tc_pxl_pll_dis(struct tc_data *tc)
696{
697 /* Enable PLL bypass, power down PLL */
698 return regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP);
699}
700
701static int tc_stream_clock_calc(struct tc_data *tc)
702{
703 /*
704 * If the Stream clock and Link Symbol clock are
705 * asynchronous with each other, the value of M changes over
706 * time. This way of generating link clock and stream
707 * clock is called Asynchronous Clock mode. The value M
708 * must change while the value N stays constant. The
709 * value of N in this Asynchronous Clock mode must be set
710 * to 2^15 or 32,768.
711 *
712 * LSCLK = 1/10 of high speed link clock
713 *
714 * f_STRMCLK = M/N * f_LSCLK
715 * M/N = f_STRMCLK / f_LSCLK
716 *
717 */
718 return regmap_write(tc->regmap, DP0_VIDMNGEN1, 32768);
719}
720
721static int tc_set_syspllparam(struct tc_data *tc)
722{
723 unsigned long rate;
724 u32 pllparam = SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
725
726 rate = clk_get_rate(tc->refclk);
727 switch (rate) {
728 case 38400000:
729 pllparam |= REF_FREQ_38M4;
730 break;
731 case 26000000:
732 pllparam |= REF_FREQ_26M;
733 break;
734 case 19200000:
735 pllparam |= REF_FREQ_19M2;
736 break;
737 case 13000000:
738 pllparam |= REF_FREQ_13M;
739 break;
740 default:
741 dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate);
742 return -EINVAL;
743 }
744
745 return regmap_write(tc->regmap, SYS_PLLPARAM, pllparam);
746}
747
748static int tc_aux_link_setup(struct tc_data *tc)
749{
750 int ret;
751 u32 dp0_auxcfg1;
752
753 /* Setup DP-PHY / PLL */
754 ret = tc_set_syspllparam(tc);
755 if (ret)
756 goto err;
757
758 ret = regmap_write(tc->regmap, DP_PHY_CTRL,
759 BGREN | PWR_SW_EN | PHY_A0_EN);
760 if (ret)
761 goto err;
762 /*
763 * Initially PLLs are in bypass. Force PLL parameter update,
764 * disable PLL bypass, enable PLL
765 */
766 ret = tc_pllupdate(tc, DP0_PLLCTRL);
767 if (ret)
768 goto err;
769
770 ret = tc_pllupdate(tc, DP1_PLLCTRL);
771 if (ret)
772 goto err;
773
774 ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 100, 100000);
775 if (ret == -ETIMEDOUT) {
776 dev_err(tc->dev, "Timeout waiting for PHY to become ready");
777 return ret;
778 } else if (ret) {
779 goto err;
780 }
781
782 /* Setup AUX link */
783 dp0_auxcfg1 = AUX_RX_FILTER_EN;
784 dp0_auxcfg1 |= 0x06 << 8; /* Aux Bit Period Calculator Threshold */
785 dp0_auxcfg1 |= 0x3f << 0; /* Aux Response Timeout Timer */
786
787 ret = regmap_write(tc->regmap, DP0_AUXCFG1, dp0_auxcfg1);
788 if (ret)
789 goto err;
790
791 /* Register DP AUX channel */
792 tc->aux.name = "TC358767 AUX i2c adapter";
793 tc->aux.dev = tc->dev;
794 tc->aux.transfer = tc_aux_transfer;
795 drm_dp_aux_init(&tc->aux);
796
797 return 0;
798err:
799 dev_err(tc->dev, "tc_aux_link_setup failed: %d\n", ret);
800 return ret;
801}
802
803static int tc_get_display_props(struct tc_data *tc)
804{
805 u8 revision, num_lanes;
806 unsigned int rate;
807 int ret;
808 u8 reg;
809
810 /* Read DP Rx Link Capability */
811 ret = drm_dp_dpcd_read(&tc->aux, DP_DPCD_REV, tc->link.dpcd,
812 DP_RECEIVER_CAP_SIZE);
813 if (ret < 0)
814 goto err_dpcd_read;
815
816 revision = tc->link.dpcd[DP_DPCD_REV];
817 rate = drm_dp_max_link_rate(tc->link.dpcd);
818 num_lanes = drm_dp_max_lane_count(tc->link.dpcd);
819
820 if (rate != 162000 && rate != 270000) {
821 dev_dbg(tc->dev, "Falling to 2.7 Gbps rate\n");
822 rate = 270000;
823 }
824
825 tc->link.rate = rate;
826
827 if (num_lanes > 2) {
828 dev_dbg(tc->dev, "Falling to 2 lanes\n");
829 num_lanes = 2;
830 }
831
832 tc->link.num_lanes = num_lanes;
833
834 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, ®);
835 if (ret < 0)
836 goto err_dpcd_read;
837 tc->link.spread = reg & DP_MAX_DOWNSPREAD_0_5;
838
839 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, ®);
840 if (ret < 0)
841 goto err_dpcd_read;
842
843 tc->link.scrambler_dis = false;
844 /* read assr */
845 ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, ®);
846 if (ret < 0)
847 goto err_dpcd_read;
848 tc->link.assr = reg & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;
849
850 dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n",
851 revision >> 4, revision & 0x0f,
852 (tc->link.rate == 162000) ? "1.62Gbps" : "2.7Gbps",
853 tc->link.num_lanes,
854 drm_dp_enhanced_frame_cap(tc->link.dpcd) ?
855 "enhanced" : "default");
856 dev_dbg(tc->dev, "Downspread: %s, scrambler: %s\n",
857 tc->link.spread ? "0.5%" : "0.0%",
858 tc->link.scrambler_dis ? "disabled" : "enabled");
859 dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n",
860 tc->link.assr, tc->assr);
861
862 return 0;
863
864err_dpcd_read:
865 dev_err(tc->dev, "failed to read DPCD: %d\n", ret);
866 return ret;
867}
868
869static int tc_set_common_video_mode(struct tc_data *tc,
870 const struct drm_display_mode *mode)
871{
872 int left_margin = mode->htotal - mode->hsync_end;
873 int right_margin = mode->hsync_start - mode->hdisplay;
874 int hsync_len = mode->hsync_end - mode->hsync_start;
875 int upper_margin = mode->vtotal - mode->vsync_end;
876 int lower_margin = mode->vsync_start - mode->vdisplay;
877 int vsync_len = mode->vsync_end - mode->vsync_start;
878 int ret;
879
880 dev_dbg(tc->dev, "set mode %dx%d\n",
881 mode->hdisplay, mode->vdisplay);
882 dev_dbg(tc->dev, "H margin %d,%d sync %d\n",
883 left_margin, right_margin, hsync_len);
884 dev_dbg(tc->dev, "V margin %d,%d sync %d\n",
885 upper_margin, lower_margin, vsync_len);
886 dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal);
887
888
889 /*
890 * LCD Ctl Frame Size
891 * datasheet is not clear of vsdelay in case of DPI
892 * assume we do not need any delay when DPI is a source of
893 * sync signals
894 */
895 ret = regmap_write(tc->regmap, VPCTRL0,
896 FIELD_PREP(VSDELAY, right_margin + 10) |
897 OPXLFMT_RGB888 | FRMSYNC_DISABLED | MSF_DISABLED);
898 if (ret)
899 return ret;
900
901 ret = regmap_write(tc->regmap, HTIM01,
902 FIELD_PREP(HBPR, ALIGN(left_margin, 2)) |
903 FIELD_PREP(HPW, ALIGN(hsync_len, 2)));
904 if (ret)
905 return ret;
906
907 ret = regmap_write(tc->regmap, HTIM02,
908 FIELD_PREP(HDISPR, ALIGN(mode->hdisplay, 2)) |
909 FIELD_PREP(HFPR, ALIGN(right_margin, 2)));
910 if (ret)
911 return ret;
912
913 ret = regmap_write(tc->regmap, VTIM01,
914 FIELD_PREP(VBPR, upper_margin) |
915 FIELD_PREP(VSPR, vsync_len));
916 if (ret)
917 return ret;
918
919 ret = regmap_write(tc->regmap, VTIM02,
920 FIELD_PREP(VFPR, lower_margin) |
921 FIELD_PREP(VDISPR, mode->vdisplay));
922 if (ret)
923 return ret;
924
925 ret = regmap_write(tc->regmap, VFUEN0, VFUEN); /* update settings */
926 if (ret)
927 return ret;
928
929 /* Test pattern settings */
930 ret = regmap_write(tc->regmap, TSTCTL,
931 FIELD_PREP(COLOR_R, 120) |
932 FIELD_PREP(COLOR_G, 20) |
933 FIELD_PREP(COLOR_B, 99) |
934 ENI2CFILTER |
935 FIELD_PREP(COLOR_BAR_MODE, COLOR_BAR_MODE_BARS));
936
937 return ret;
938}
939
940static int tc_set_dpi_video_mode(struct tc_data *tc,
941 const struct drm_display_mode *mode)
942{
943 u32 value = POCTRL_S2P;
944
945 if (tc->mode.flags & DRM_MODE_FLAG_NHSYNC)
946 value |= POCTRL_HS_POL;
947
948 if (tc->mode.flags & DRM_MODE_FLAG_NVSYNC)
949 value |= POCTRL_VS_POL;
950
951 return regmap_write(tc->regmap, POCTRL, value);
952}
953
954static int tc_set_edp_video_mode(struct tc_data *tc,
955 const struct drm_display_mode *mode)
956{
957 int ret;
958 int vid_sync_dly;
959 int max_tu_symbol;
960
961 int left_margin = mode->htotal - mode->hsync_end;
962 int hsync_len = mode->hsync_end - mode->hsync_start;
963 int upper_margin = mode->vtotal - mode->vsync_end;
964 int vsync_len = mode->vsync_end - mode->vsync_start;
965 u32 dp0_syncval;
966 u32 bits_per_pixel = 24;
967 u32 in_bw, out_bw;
968 u32 dpipxlfmt;
969
970 /*
971 * Recommended maximum number of symbols transferred in a transfer unit:
972 * DIV_ROUND_UP((input active video bandwidth in bytes) * tu_size,
973 * (output active video bandwidth in bytes))
974 * Must be less than tu_size.
975 */
976
977 in_bw = mode->clock * bits_per_pixel / 8;
978 out_bw = tc->link.num_lanes * tc->link.rate;
979 max_tu_symbol = DIV_ROUND_UP(in_bw * TU_SIZE_RECOMMENDED, out_bw);
980
981 /* DP Main Stream Attributes */
982 vid_sync_dly = hsync_len + left_margin + mode->hdisplay;
983 ret = regmap_write(tc->regmap, DP0_VIDSYNCDELAY,
984 FIELD_PREP(THRESH_DLY, max_tu_symbol) |
985 FIELD_PREP(VID_SYNC_DLY, vid_sync_dly));
986
987 ret = regmap_write(tc->regmap, DP0_TOTALVAL,
988 FIELD_PREP(H_TOTAL, mode->htotal) |
989 FIELD_PREP(V_TOTAL, mode->vtotal));
990 if (ret)
991 return ret;
992
993 ret = regmap_write(tc->regmap, DP0_STARTVAL,
994 FIELD_PREP(H_START, left_margin + hsync_len) |
995 FIELD_PREP(V_START, upper_margin + vsync_len));
996 if (ret)
997 return ret;
998
999 ret = regmap_write(tc->regmap, DP0_ACTIVEVAL,
1000 FIELD_PREP(V_ACT, mode->vdisplay) |
1001 FIELD_PREP(H_ACT, mode->hdisplay));
1002 if (ret)
1003 return ret;
1004
1005 dp0_syncval = FIELD_PREP(VS_WIDTH, vsync_len) |
1006 FIELD_PREP(HS_WIDTH, hsync_len);
1007
1008 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1009 dp0_syncval |= SYNCVAL_VS_POL_ACTIVE_LOW;
1010
1011 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1012 dp0_syncval |= SYNCVAL_HS_POL_ACTIVE_LOW;
1013
1014 ret = regmap_write(tc->regmap, DP0_SYNCVAL, dp0_syncval);
1015 if (ret)
1016 return ret;
1017
1018 dpipxlfmt = DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 | DPI_BPP_RGB888;
1019
1020 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1021 dpipxlfmt |= VS_POL_ACTIVE_LOW;
1022
1023 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1024 dpipxlfmt |= HS_POL_ACTIVE_LOW;
1025
1026 ret = regmap_write(tc->regmap, DPIPXLFMT, dpipxlfmt);
1027 if (ret)
1028 return ret;
1029
1030 ret = regmap_write(tc->regmap, DP0_MISC,
1031 FIELD_PREP(MAX_TU_SYMBOL, max_tu_symbol) |
1032 FIELD_PREP(TU_SIZE, TU_SIZE_RECOMMENDED) |
1033 BPC_8);
1034 return ret;
1035}
1036
1037static int tc_wait_link_training(struct tc_data *tc)
1038{
1039 u32 value;
1040 int ret;
1041
1042 ret = tc_poll_timeout(tc, DP0_LTSTAT, LT_LOOPDONE,
1043 LT_LOOPDONE, 500, 100000);
1044 if (ret) {
1045 dev_err(tc->dev, "Link training timeout waiting for LT_LOOPDONE!\n");
1046 return ret;
1047 }
1048
1049 ret = regmap_read(tc->regmap, DP0_LTSTAT, &value);
1050 if (ret)
1051 return ret;
1052
1053 return (value >> 8) & 0x7;
1054}
1055
1056static int tc_main_link_enable(struct tc_data *tc)
1057{
1058 struct drm_dp_aux *aux = &tc->aux;
1059 struct device *dev = tc->dev;
1060 u32 dp_phy_ctrl;
1061 u32 value;
1062 int ret;
1063 u8 tmp[DP_LINK_STATUS_SIZE];
1064
1065 dev_dbg(tc->dev, "link enable\n");
1066
1067 ret = regmap_read(tc->regmap, DP0CTL, &value);
1068 if (ret)
1069 return ret;
1070
1071 if (WARN_ON(value & DP_EN)) {
1072 ret = regmap_write(tc->regmap, DP0CTL, 0);
1073 if (ret)
1074 return ret;
1075 }
1076
1077 ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc));
1078 if (ret)
1079 return ret;
1080 /* SSCG and BW27 on DP1 must be set to the same as on DP0 */
1081 ret = regmap_write(tc->regmap, DP1_SRCCTRL,
1082 (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) |
1083 ((tc->link.rate != 162000) ? DP0_SRCCTRL_BW27 : 0));
1084 if (ret)
1085 return ret;
1086
1087 ret = tc_set_syspllparam(tc);
1088 if (ret)
1089 return ret;
1090
1091 /* Setup Main Link */
1092 dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN | PHY_M0_EN;
1093 if (tc->link.num_lanes == 2)
1094 dp_phy_ctrl |= PHY_2LANE;
1095
1096 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
1097 if (ret)
1098 return ret;
1099
1100 /* PLL setup */
1101 ret = tc_pllupdate(tc, DP0_PLLCTRL);
1102 if (ret)
1103 return ret;
1104
1105 ret = tc_pllupdate(tc, DP1_PLLCTRL);
1106 if (ret)
1107 return ret;
1108
1109 /* Reset/Enable Main Links */
1110 dp_phy_ctrl |= DP_PHY_RST | PHY_M1_RST | PHY_M0_RST;
1111 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
1112 usleep_range(100, 200);
1113 dp_phy_ctrl &= ~(DP_PHY_RST | PHY_M1_RST | PHY_M0_RST);
1114 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
1115
1116 ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 500, 100000);
1117 if (ret) {
1118 dev_err(dev, "timeout waiting for phy become ready");
1119 return ret;
1120 }
1121
1122 /* Set misc: 8 bits per color */
1123 ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8);
1124 if (ret)
1125 return ret;
1126
1127 /*
1128 * ASSR mode
1129 * on TC358767 side ASSR configured through strap pin
1130 * seems there is no way to change this setting from SW
1131 *
1132 * check is tc configured for same mode
1133 */
1134 if (tc->assr != tc->link.assr) {
1135 dev_dbg(dev, "Trying to set display to ASSR: %d\n",
1136 tc->assr);
1137 /* try to set ASSR on display side */
1138 tmp[0] = tc->assr;
1139 ret = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, tmp[0]);
1140 if (ret < 0)
1141 goto err_dpcd_read;
1142 /* read back */
1143 ret = drm_dp_dpcd_readb(aux, DP_EDP_CONFIGURATION_SET, tmp);
1144 if (ret < 0)
1145 goto err_dpcd_read;
1146
1147 if (tmp[0] != tc->assr) {
1148 dev_dbg(dev, "Failed to switch display ASSR to %d, falling back to unscrambled mode\n",
1149 tc->assr);
1150 /* trying with disabled scrambler */
1151 tc->link.scrambler_dis = true;
1152 }
1153 }
1154
1155 /* Setup Link & DPRx Config for Training */
1156 tmp[0] = drm_dp_link_rate_to_bw_code(tc->link.rate);
1157 tmp[1] = tc->link.num_lanes;
1158
1159 if (drm_dp_enhanced_frame_cap(tc->link.dpcd))
1160 tmp[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
1161
1162 ret = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, tmp, 2);
1163 if (ret < 0)
1164 goto err_dpcd_write;
1165
1166 /* DOWNSPREAD_CTRL */
1167 tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00;
1168 /* MAIN_LINK_CHANNEL_CODING_SET */
1169 tmp[1] = DP_SET_ANSI_8B10B;
1170 ret = drm_dp_dpcd_write(aux, DP_DOWNSPREAD_CTRL, tmp, 2);
1171 if (ret < 0)
1172 goto err_dpcd_write;
1173
1174 /* Reset voltage-swing & pre-emphasis */
1175 tmp[0] = tmp[1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 |
1176 DP_TRAIN_PRE_EMPH_LEVEL_0;
1177 ret = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, tmp, 2);
1178 if (ret < 0)
1179 goto err_dpcd_write;
1180
1181 /* Clock-Recovery */
1182
1183 /* Set DPCD 0x102 for Training Pattern 1 */
1184 ret = regmap_write(tc->regmap, DP0_SNKLTCTRL,
1185 DP_LINK_SCRAMBLING_DISABLE |
1186 DP_TRAINING_PATTERN_1);
1187 if (ret)
1188 return ret;
1189
1190 ret = regmap_write(tc->regmap, DP0_LTLOOPCTRL,
1191 (15 << 28) | /* Defer Iteration Count */
1192 (15 << 24) | /* Loop Iteration Count */
1193 (0xd << 0)); /* Loop Timer Delay */
1194 if (ret)
1195 return ret;
1196
1197 ret = regmap_write(tc->regmap, DP0_SRCCTRL,
1198 tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS |
1199 DP0_SRCCTRL_AUTOCORRECT |
1200 DP0_SRCCTRL_TP1);
1201 if (ret)
1202 return ret;
1203
1204 /* Enable DP0 to start Link Training */
1205 ret = regmap_write(tc->regmap, DP0CTL,
1206 (drm_dp_enhanced_frame_cap(tc->link.dpcd) ?
1207 EF_EN : 0) | DP_EN);
1208 if (ret)
1209 return ret;
1210
1211 /* wait */
1212
1213 ret = tc_wait_link_training(tc);
1214 if (ret < 0)
1215 return ret;
1216
1217 if (ret) {
1218 dev_err(tc->dev, "Link training phase 1 failed: %s\n",
1219 training_pattern1_errors[ret]);
1220 return -ENODEV;
1221 }
1222
1223 /* Channel Equalization */
1224
1225 /* Set DPCD 0x102 for Training Pattern 2 */
1226 ret = regmap_write(tc->regmap, DP0_SNKLTCTRL,
1227 DP_LINK_SCRAMBLING_DISABLE |
1228 DP_TRAINING_PATTERN_2);
1229 if (ret)
1230 return ret;
1231
1232 ret = regmap_write(tc->regmap, DP0_SRCCTRL,
1233 tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS |
1234 DP0_SRCCTRL_AUTOCORRECT |
1235 DP0_SRCCTRL_TP2);
1236 if (ret)
1237 return ret;
1238
1239 /* wait */
1240 ret = tc_wait_link_training(tc);
1241 if (ret < 0)
1242 return ret;
1243
1244 if (ret) {
1245 dev_err(tc->dev, "Link training phase 2 failed: %s\n",
1246 training_pattern2_errors[ret]);
1247 return -ENODEV;
1248 }
1249
1250 /*
1251 * Toshiba's documentation suggests to first clear DPCD 0x102, then
1252 * clear the training pattern bit in DP0_SRCCTRL. Testing shows
1253 * that the link sometimes drops if those steps are done in that order,
1254 * but if the steps are done in reverse order, the link stays up.
1255 *
1256 * So we do the steps differently than documented here.
1257 */
1258
1259 /* Clear Training Pattern, set AutoCorrect Mode = 1 */
1260 ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc) |
1261 DP0_SRCCTRL_AUTOCORRECT);
1262 if (ret)
1263 return ret;
1264
1265 /* Clear DPCD 0x102 */
1266 /* Note: Can Not use DP0_SNKLTCTRL (0x06E4) short cut */
1267 tmp[0] = tc->link.scrambler_dis ? DP_LINK_SCRAMBLING_DISABLE : 0x00;
1268 ret = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, tmp[0]);
1269 if (ret < 0)
1270 goto err_dpcd_write;
1271
1272 /* Check link status */
1273 ret = drm_dp_dpcd_read_link_status(aux, tmp);
1274 if (ret < 0)
1275 goto err_dpcd_read;
1276
1277 ret = 0;
1278
1279 value = tmp[0] & DP_CHANNEL_EQ_BITS;
1280
1281 if (value != DP_CHANNEL_EQ_BITS) {
1282 dev_err(tc->dev, "Lane 0 failed: %x\n", value);
1283 ret = -ENODEV;
1284 }
1285
1286 if (tc->link.num_lanes == 2) {
1287 value = (tmp[0] >> 4) & DP_CHANNEL_EQ_BITS;
1288
1289 if (value != DP_CHANNEL_EQ_BITS) {
1290 dev_err(tc->dev, "Lane 1 failed: %x\n", value);
1291 ret = -ENODEV;
1292 }
1293
1294 if (!(tmp[2] & DP_INTERLANE_ALIGN_DONE)) {
1295 dev_err(tc->dev, "Interlane align failed\n");
1296 ret = -ENODEV;
1297 }
1298 }
1299
1300 if (ret) {
1301 dev_err(dev, "0x0202 LANE0_1_STATUS: 0x%02x\n", tmp[0]);
1302 dev_err(dev, "0x0203 LANE2_3_STATUS 0x%02x\n", tmp[1]);
1303 dev_err(dev, "0x0204 LANE_ALIGN_STATUS_UPDATED: 0x%02x\n", tmp[2]);
1304 dev_err(dev, "0x0205 SINK_STATUS: 0x%02x\n", tmp[3]);
1305 dev_err(dev, "0x0206 ADJUST_REQUEST_LANE0_1: 0x%02x\n", tmp[4]);
1306 dev_err(dev, "0x0207 ADJUST_REQUEST_LANE2_3: 0x%02x\n", tmp[5]);
1307 return ret;
1308 }
1309
1310 return 0;
1311err_dpcd_read:
1312 dev_err(tc->dev, "Failed to read DPCD: %d\n", ret);
1313 return ret;
1314err_dpcd_write:
1315 dev_err(tc->dev, "Failed to write DPCD: %d\n", ret);
1316 return ret;
1317}
1318
1319static int tc_main_link_disable(struct tc_data *tc)
1320{
1321 int ret;
1322
1323 dev_dbg(tc->dev, "link disable\n");
1324
1325 ret = regmap_write(tc->regmap, DP0_SRCCTRL, 0);
1326 if (ret)
1327 return ret;
1328
1329 ret = regmap_write(tc->regmap, DP0CTL, 0);
1330 if (ret)
1331 return ret;
1332
1333 return regmap_update_bits(tc->regmap, DP_PHY_CTRL,
1334 PHY_M0_RST | PHY_M1_RST | PHY_M0_EN,
1335 PHY_M0_RST | PHY_M1_RST);
1336}
1337
1338static int tc_dsi_rx_enable(struct tc_data *tc)
1339{
1340 u32 value;
1341 int ret;
1342
1343 regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 25);
1344 regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 25);
1345 regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 25);
1346 regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 25);
1347 regmap_write(tc->regmap, PPI_D0S_ATMR, 0);
1348 regmap_write(tc->regmap, PPI_D1S_ATMR, 0);
1349 regmap_write(tc->regmap, PPI_TX_RX_TA, TTA_GET | TTA_SURE);
1350 regmap_write(tc->regmap, PPI_LPTXTIMECNT, LPX_PERIOD);
1351
1352 value = ((LANEENABLE_L0EN << tc->dsi->lanes) - LANEENABLE_L0EN) |
1353 LANEENABLE_CLEN;
1354 regmap_write(tc->regmap, PPI_LANEENABLE, value);
1355 regmap_write(tc->regmap, DSI_LANEENABLE, value);
1356
1357 /* Set input interface */
1358 value = DP0_AUDSRC_NO_INPUT;
1359 if (tc_test_pattern)
1360 value |= DP0_VIDSRC_COLOR_BAR;
1361 else
1362 value |= DP0_VIDSRC_DSI_RX;
1363 ret = regmap_write(tc->regmap, SYSCTRL, value);
1364 if (ret)
1365 return ret;
1366
1367 usleep_range(120, 150);
1368
1369 regmap_write(tc->regmap, PPI_STARTPPI, PPI_START_FUNCTION);
1370 regmap_write(tc->regmap, DSI_STARTDSI, DSI_RX_START);
1371
1372 return 0;
1373}
1374
1375static int tc_dpi_rx_enable(struct tc_data *tc)
1376{
1377 u32 value;
1378
1379 /* Set input interface */
1380 value = DP0_AUDSRC_NO_INPUT;
1381 if (tc_test_pattern)
1382 value |= DP0_VIDSRC_COLOR_BAR;
1383 else
1384 value |= DP0_VIDSRC_DPI_RX;
1385 return regmap_write(tc->regmap, SYSCTRL, value);
1386}
1387
1388static int tc_dpi_stream_enable(struct tc_data *tc)
1389{
1390 int ret;
1391
1392 dev_dbg(tc->dev, "enable video stream\n");
1393
1394 /* Setup PLL */
1395 ret = tc_set_syspllparam(tc);
1396 if (ret)
1397 return ret;
1398
1399 /*
1400 * Initially PLLs are in bypass. Force PLL parameter update,
1401 * disable PLL bypass, enable PLL
1402 */
1403 ret = tc_pllupdate(tc, DP0_PLLCTRL);
1404 if (ret)
1405 return ret;
1406
1407 ret = tc_pllupdate(tc, DP1_PLLCTRL);
1408 if (ret)
1409 return ret;
1410
1411 /* Pixel PLL must always be enabled for DPI mode */
1412 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk),
1413 1000 * tc->mode.clock);
1414 if (ret)
1415 return ret;
1416
1417 ret = tc_set_common_video_mode(tc, &tc->mode);
1418 if (ret)
1419 return ret;
1420
1421 ret = tc_set_dpi_video_mode(tc, &tc->mode);
1422 if (ret)
1423 return ret;
1424
1425 return tc_dsi_rx_enable(tc);
1426}
1427
1428static int tc_dpi_stream_disable(struct tc_data *tc)
1429{
1430 dev_dbg(tc->dev, "disable video stream\n");
1431
1432 tc_pxl_pll_dis(tc);
1433
1434 return 0;
1435}
1436
1437static int tc_edp_stream_enable(struct tc_data *tc)
1438{
1439 int ret;
1440 u32 value;
1441
1442 dev_dbg(tc->dev, "enable video stream\n");
1443
1444 /*
1445 * Pixel PLL must be enabled for DSI input mode and test pattern.
1446 *
1447 * Per TC9595XBG datasheet Revision 0.1 2018-12-27 Figure 4.18
1448 * "Clock Mode Selection and Clock Sources", either Pixel PLL
1449 * or DPI_PCLK supplies StrmClk. DPI_PCLK is only available in
1450 * case valid Pixel Clock are supplied to the chip DPI input.
1451 * In case built-in test pattern is desired OR DSI input mode
1452 * is used, DPI_PCLK is not available and thus Pixel PLL must
1453 * be used instead.
1454 */
1455 if (tc->input_connector_dsi || tc_test_pattern) {
1456 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk),
1457 1000 * tc->mode.clock);
1458 if (ret)
1459 return ret;
1460 }
1461
1462 ret = tc_set_common_video_mode(tc, &tc->mode);
1463 if (ret)
1464 return ret;
1465
1466 ret = tc_set_edp_video_mode(tc, &tc->mode);
1467 if (ret)
1468 return ret;
1469
1470 /* Set M/N */
1471 ret = tc_stream_clock_calc(tc);
1472 if (ret)
1473 return ret;
1474
1475 value = VID_MN_GEN | DP_EN;
1476 if (drm_dp_enhanced_frame_cap(tc->link.dpcd))
1477 value |= EF_EN;
1478 ret = regmap_write(tc->regmap, DP0CTL, value);
1479 if (ret)
1480 return ret;
1481 /*
1482 * VID_EN assertion should be delayed by at least N * LSCLK
1483 * cycles from the time VID_MN_GEN is enabled in order to
1484 * generate stable values for VID_M. LSCLK is 270 MHz or
1485 * 162 MHz, VID_N is set to 32768 in tc_stream_clock_calc(),
1486 * so a delay of at least 203 us should suffice.
1487 */
1488 usleep_range(500, 1000);
1489 value |= VID_EN;
1490 ret = regmap_write(tc->regmap, DP0CTL, value);
1491 if (ret)
1492 return ret;
1493
1494 /* Set input interface */
1495 if (tc->input_connector_dsi)
1496 return tc_dsi_rx_enable(tc);
1497 else
1498 return tc_dpi_rx_enable(tc);
1499}
1500
1501static int tc_edp_stream_disable(struct tc_data *tc)
1502{
1503 int ret;
1504
1505 dev_dbg(tc->dev, "disable video stream\n");
1506
1507 ret = regmap_update_bits(tc->regmap, DP0CTL, VID_EN, 0);
1508 if (ret)
1509 return ret;
1510
1511 tc_pxl_pll_dis(tc);
1512
1513 return 0;
1514}
1515
1516static void
1517tc_dpi_bridge_atomic_enable(struct drm_bridge *bridge,
1518 struct drm_bridge_state *old_bridge_state)
1519
1520{
1521 struct tc_data *tc = bridge_to_tc(bridge);
1522 int ret;
1523
1524 ret = tc_dpi_stream_enable(tc);
1525 if (ret < 0) {
1526 dev_err(tc->dev, "main link stream start error: %d\n", ret);
1527 tc_main_link_disable(tc);
1528 return;
1529 }
1530}
1531
1532static void
1533tc_dpi_bridge_atomic_disable(struct drm_bridge *bridge,
1534 struct drm_bridge_state *old_bridge_state)
1535{
1536 struct tc_data *tc = bridge_to_tc(bridge);
1537 int ret;
1538
1539 ret = tc_dpi_stream_disable(tc);
1540 if (ret < 0)
1541 dev_err(tc->dev, "main link stream stop error: %d\n", ret);
1542}
1543
1544static void
1545tc_edp_bridge_atomic_enable(struct drm_bridge *bridge,
1546 struct drm_bridge_state *old_bridge_state)
1547{
1548 struct tc_data *tc = bridge_to_tc(bridge);
1549 int ret;
1550
1551 ret = tc_get_display_props(tc);
1552 if (ret < 0) {
1553 dev_err(tc->dev, "failed to read display props: %d\n", ret);
1554 return;
1555 }
1556
1557 ret = tc_main_link_enable(tc);
1558 if (ret < 0) {
1559 dev_err(tc->dev, "main link enable error: %d\n", ret);
1560 return;
1561 }
1562
1563 ret = tc_edp_stream_enable(tc);
1564 if (ret < 0) {
1565 dev_err(tc->dev, "main link stream start error: %d\n", ret);
1566 tc_main_link_disable(tc);
1567 return;
1568 }
1569}
1570
1571static void
1572tc_edp_bridge_atomic_disable(struct drm_bridge *bridge,
1573 struct drm_bridge_state *old_bridge_state)
1574{
1575 struct tc_data *tc = bridge_to_tc(bridge);
1576 int ret;
1577
1578 ret = tc_edp_stream_disable(tc);
1579 if (ret < 0)
1580 dev_err(tc->dev, "main link stream stop error: %d\n", ret);
1581
1582 ret = tc_main_link_disable(tc);
1583 if (ret < 0)
1584 dev_err(tc->dev, "main link disable error: %d\n", ret);
1585}
1586
1587static int tc_dpi_atomic_check(struct drm_bridge *bridge,
1588 struct drm_bridge_state *bridge_state,
1589 struct drm_crtc_state *crtc_state,
1590 struct drm_connector_state *conn_state)
1591{
1592 /* DSI->DPI interface clock limitation: upto 100 MHz */
1593 if (crtc_state->adjusted_mode.clock > 100000)
1594 return -EINVAL;
1595
1596 return 0;
1597}
1598
1599static int tc_edp_atomic_check(struct drm_bridge *bridge,
1600 struct drm_bridge_state *bridge_state,
1601 struct drm_crtc_state *crtc_state,
1602 struct drm_connector_state *conn_state)
1603{
1604 /* DPI->(e)DP interface clock limitation: upto 154 MHz */
1605 if (crtc_state->adjusted_mode.clock > 154000)
1606 return -EINVAL;
1607
1608 return 0;
1609}
1610
1611static enum drm_mode_status
1612tc_dpi_mode_valid(struct drm_bridge *bridge,
1613 const struct drm_display_info *info,
1614 const struct drm_display_mode *mode)
1615{
1616 /* DPI interface clock limitation: upto 100 MHz */
1617 if (mode->clock > 100000)
1618 return MODE_CLOCK_HIGH;
1619
1620 return MODE_OK;
1621}
1622
1623static enum drm_mode_status
1624tc_edp_mode_valid(struct drm_bridge *bridge,
1625 const struct drm_display_info *info,
1626 const struct drm_display_mode *mode)
1627{
1628 struct tc_data *tc = bridge_to_tc(bridge);
1629 u32 req, avail;
1630 u32 bits_per_pixel = 24;
1631
1632 /* DPI interface clock limitation: upto 154 MHz */
1633 if (mode->clock > 154000)
1634 return MODE_CLOCK_HIGH;
1635
1636 req = mode->clock * bits_per_pixel / 8;
1637 avail = tc->link.num_lanes * tc->link.rate;
1638
1639 if (req > avail)
1640 return MODE_BAD;
1641
1642 return MODE_OK;
1643}
1644
1645static void tc_bridge_mode_set(struct drm_bridge *bridge,
1646 const struct drm_display_mode *mode,
1647 const struct drm_display_mode *adj)
1648{
1649 struct tc_data *tc = bridge_to_tc(bridge);
1650
1651 drm_mode_copy(&tc->mode, mode);
1652}
1653
1654static const struct drm_edid *tc_edid_read(struct drm_bridge *bridge,
1655 struct drm_connector *connector)
1656{
1657 struct tc_data *tc = bridge_to_tc(bridge);
1658
1659 return drm_edid_read_ddc(connector, &tc->aux.ddc);
1660}
1661
1662static int tc_connector_get_modes(struct drm_connector *connector)
1663{
1664 struct tc_data *tc = connector_to_tc(connector);
1665 int num_modes;
1666 const struct drm_edid *drm_edid;
1667 int ret;
1668
1669 ret = tc_get_display_props(tc);
1670 if (ret < 0) {
1671 dev_err(tc->dev, "failed to read display props: %d\n", ret);
1672 return 0;
1673 }
1674
1675 if (tc->panel_bridge) {
1676 num_modes = drm_bridge_get_modes(tc->panel_bridge, connector);
1677 if (num_modes > 0)
1678 return num_modes;
1679 }
1680
1681 drm_edid = tc_edid_read(&tc->bridge, connector);
1682 drm_edid_connector_update(connector, drm_edid);
1683 num_modes = drm_edid_connector_add_modes(connector);
1684 drm_edid_free(drm_edid);
1685
1686 return num_modes;
1687}
1688
1689static const struct drm_connector_helper_funcs tc_connector_helper_funcs = {
1690 .get_modes = tc_connector_get_modes,
1691};
1692
1693static enum drm_connector_status tc_bridge_detect(struct drm_bridge *bridge)
1694{
1695 struct tc_data *tc = bridge_to_tc(bridge);
1696 bool conn;
1697 u32 val;
1698 int ret;
1699
1700 ret = regmap_read(tc->regmap, GPIOI, &val);
1701 if (ret)
1702 return connector_status_unknown;
1703
1704 conn = val & BIT(tc->hpd_pin);
1705
1706 if (conn)
1707 return connector_status_connected;
1708 else
1709 return connector_status_disconnected;
1710}
1711
1712static enum drm_connector_status
1713tc_connector_detect(struct drm_connector *connector, bool force)
1714{
1715 struct tc_data *tc = connector_to_tc(connector);
1716
1717 if (tc->hpd_pin >= 0)
1718 return tc_bridge_detect(&tc->bridge);
1719
1720 if (tc->panel_bridge)
1721 return connector_status_connected;
1722 else
1723 return connector_status_unknown;
1724}
1725
1726static const struct drm_connector_funcs tc_connector_funcs = {
1727 .detect = tc_connector_detect,
1728 .fill_modes = drm_helper_probe_single_connector_modes,
1729 .destroy = drm_connector_cleanup,
1730 .reset = drm_atomic_helper_connector_reset,
1731 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1732 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1733};
1734
1735static int tc_dpi_bridge_attach(struct drm_bridge *bridge,
1736 enum drm_bridge_attach_flags flags)
1737{
1738 struct tc_data *tc = bridge_to_tc(bridge);
1739
1740 if (!tc->panel_bridge)
1741 return 0;
1742
1743 return drm_bridge_attach(tc->bridge.encoder, tc->panel_bridge,
1744 &tc->bridge, flags);
1745}
1746
1747static int tc_edp_bridge_attach(struct drm_bridge *bridge,
1748 enum drm_bridge_attach_flags flags)
1749{
1750 u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1751 struct tc_data *tc = bridge_to_tc(bridge);
1752 struct drm_device *drm = bridge->dev;
1753 int ret;
1754
1755 if (tc->panel_bridge) {
1756 /* If a connector is required then this driver shall create it */
1757 ret = drm_bridge_attach(tc->bridge.encoder, tc->panel_bridge,
1758 &tc->bridge, flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR);
1759 if (ret)
1760 return ret;
1761 }
1762
1763 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
1764 return 0;
1765
1766 tc->aux.drm_dev = drm;
1767 ret = drm_dp_aux_register(&tc->aux);
1768 if (ret < 0)
1769 return ret;
1770
1771 /* Create DP/eDP connector */
1772 drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs);
1773 ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs, tc->bridge.type);
1774 if (ret)
1775 goto aux_unregister;
1776
1777 /* Don't poll if don't have HPD connected */
1778 if (tc->hpd_pin >= 0) {
1779 if (tc->have_irq)
1780 tc->connector.polled = DRM_CONNECTOR_POLL_HPD;
1781 else
1782 tc->connector.polled = DRM_CONNECTOR_POLL_CONNECT |
1783 DRM_CONNECTOR_POLL_DISCONNECT;
1784 }
1785
1786 drm_display_info_set_bus_formats(&tc->connector.display_info,
1787 &bus_format, 1);
1788 tc->connector.display_info.bus_flags =
1789 DRM_BUS_FLAG_DE_HIGH |
1790 DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE |
1791 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE;
1792 drm_connector_attach_encoder(&tc->connector, tc->bridge.encoder);
1793
1794 return 0;
1795aux_unregister:
1796 drm_dp_aux_unregister(&tc->aux);
1797 return ret;
1798}
1799
1800static void tc_edp_bridge_detach(struct drm_bridge *bridge)
1801{
1802 drm_dp_aux_unregister(&bridge_to_tc(bridge)->aux);
1803}
1804
1805#define MAX_INPUT_SEL_FORMATS 1
1806
1807static u32 *
1808tc_dpi_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
1809 struct drm_bridge_state *bridge_state,
1810 struct drm_crtc_state *crtc_state,
1811 struct drm_connector_state *conn_state,
1812 u32 output_fmt,
1813 unsigned int *num_input_fmts)
1814{
1815 u32 *input_fmts;
1816
1817 *num_input_fmts = 0;
1818
1819 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
1820 GFP_KERNEL);
1821 if (!input_fmts)
1822 return NULL;
1823
1824 /* This is the DSI-end bus format */
1825 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
1826 *num_input_fmts = 1;
1827
1828 return input_fmts;
1829}
1830
1831static const struct drm_bridge_funcs tc_dpi_bridge_funcs = {
1832 .attach = tc_dpi_bridge_attach,
1833 .mode_valid = tc_dpi_mode_valid,
1834 .mode_set = tc_bridge_mode_set,
1835 .atomic_check = tc_dpi_atomic_check,
1836 .atomic_enable = tc_dpi_bridge_atomic_enable,
1837 .atomic_disable = tc_dpi_bridge_atomic_disable,
1838 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1839 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1840 .atomic_reset = drm_atomic_helper_bridge_reset,
1841 .atomic_get_input_bus_fmts = tc_dpi_atomic_get_input_bus_fmts,
1842};
1843
1844static const struct drm_bridge_funcs tc_edp_bridge_funcs = {
1845 .attach = tc_edp_bridge_attach,
1846 .detach = tc_edp_bridge_detach,
1847 .mode_valid = tc_edp_mode_valid,
1848 .mode_set = tc_bridge_mode_set,
1849 .atomic_check = tc_edp_atomic_check,
1850 .atomic_enable = tc_edp_bridge_atomic_enable,
1851 .atomic_disable = tc_edp_bridge_atomic_disable,
1852 .detect = tc_bridge_detect,
1853 .edid_read = tc_edid_read,
1854 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1855 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1856 .atomic_reset = drm_atomic_helper_bridge_reset,
1857};
1858
1859static bool tc_readable_reg(struct device *dev, unsigned int reg)
1860{
1861 switch (reg) {
1862 /* DSI D-PHY Layer */
1863 case 0x004:
1864 case 0x020:
1865 case 0x024:
1866 case 0x028:
1867 case 0x02c:
1868 case 0x030:
1869 case 0x038:
1870 case 0x040:
1871 case 0x044:
1872 case 0x048:
1873 case 0x04c:
1874 case 0x050:
1875 case 0x054:
1876 /* DSI PPI Layer */
1877 case PPI_STARTPPI:
1878 case 0x108:
1879 case 0x110:
1880 case PPI_LPTXTIMECNT:
1881 case PPI_LANEENABLE:
1882 case PPI_TX_RX_TA:
1883 case 0x140:
1884 case PPI_D0S_ATMR:
1885 case PPI_D1S_ATMR:
1886 case 0x14c:
1887 case 0x150:
1888 case PPI_D0S_CLRSIPOCOUNT:
1889 case PPI_D1S_CLRSIPOCOUNT:
1890 case PPI_D2S_CLRSIPOCOUNT:
1891 case PPI_D3S_CLRSIPOCOUNT:
1892 case 0x180:
1893 case 0x184:
1894 case 0x188:
1895 case 0x18c:
1896 case 0x190:
1897 case 0x1a0:
1898 case 0x1a4:
1899 case 0x1a8:
1900 case 0x1ac:
1901 case 0x1b0:
1902 case 0x1c0:
1903 case 0x1c4:
1904 case 0x1c8:
1905 case 0x1cc:
1906 case 0x1d0:
1907 case 0x1e0:
1908 case 0x1e4:
1909 case 0x1f0:
1910 case 0x1f4:
1911 /* DSI Protocol Layer */
1912 case DSI_STARTDSI:
1913 case DSI_BUSYDSI:
1914 case DSI_LANEENABLE:
1915 case DSI_LANESTATUS0:
1916 case DSI_LANESTATUS1:
1917 case DSI_INTSTATUS:
1918 case 0x224:
1919 case 0x228:
1920 case 0x230:
1921 /* DSI General */
1922 case DSIERRCNT:
1923 /* DSI Application Layer */
1924 case 0x400:
1925 case 0x404:
1926 /* DPI */
1927 case DPIPXLFMT:
1928 /* Parallel Output */
1929 case POCTRL:
1930 /* Video Path0 Configuration */
1931 case VPCTRL0:
1932 case HTIM01:
1933 case HTIM02:
1934 case VTIM01:
1935 case VTIM02:
1936 case VFUEN0:
1937 /* System */
1938 case TC_IDREG:
1939 case 0x504:
1940 case SYSSTAT:
1941 case SYSRSTENB:
1942 case SYSCTRL:
1943 /* I2C */
1944 case 0x520:
1945 /* GPIO */
1946 case GPIOM:
1947 case GPIOC:
1948 case GPIOO:
1949 case GPIOI:
1950 /* Interrupt */
1951 case INTCTL_G:
1952 case INTSTS_G:
1953 case 0x570:
1954 case 0x574:
1955 case INT_GP0_LCNT:
1956 case INT_GP1_LCNT:
1957 /* DisplayPort Control */
1958 case DP0CTL:
1959 /* DisplayPort Clock */
1960 case DP0_VIDMNGEN0:
1961 case DP0_VIDMNGEN1:
1962 case DP0_VMNGENSTATUS:
1963 case 0x628:
1964 case 0x62c:
1965 case 0x630:
1966 /* DisplayPort Main Channel */
1967 case DP0_SECSAMPLE:
1968 case DP0_VIDSYNCDELAY:
1969 case DP0_TOTALVAL:
1970 case DP0_STARTVAL:
1971 case DP0_ACTIVEVAL:
1972 case DP0_SYNCVAL:
1973 case DP0_MISC:
1974 /* DisplayPort Aux Channel */
1975 case DP0_AUXCFG0:
1976 case DP0_AUXCFG1:
1977 case DP0_AUXADDR:
1978 case 0x66c:
1979 case 0x670:
1980 case 0x674:
1981 case 0x678:
1982 case 0x67c:
1983 case 0x680:
1984 case 0x684:
1985 case 0x688:
1986 case DP0_AUXSTATUS:
1987 case DP0_AUXI2CADR:
1988 /* DisplayPort Link Training */
1989 case DP0_SRCCTRL:
1990 case DP0_LTSTAT:
1991 case DP0_SNKLTCHGREQ:
1992 case DP0_LTLOOPCTRL:
1993 case DP0_SNKLTCTRL:
1994 case 0x6e8:
1995 case 0x6ec:
1996 case 0x6f0:
1997 case 0x6f4:
1998 /* DisplayPort Audio */
1999 case 0x700:
2000 case 0x704:
2001 case 0x708:
2002 case 0x70c:
2003 case 0x710:
2004 case 0x714:
2005 case 0x718:
2006 case 0x71c:
2007 case 0x720:
2008 /* DisplayPort Source Control */
2009 case DP1_SRCCTRL:
2010 /* DisplayPort PHY */
2011 case DP_PHY_CTRL:
2012 case 0x810:
2013 case 0x814:
2014 case 0x820:
2015 case 0x840:
2016 /* I2S */
2017 case 0x880:
2018 case 0x888:
2019 case 0x88c:
2020 case 0x890:
2021 case 0x894:
2022 case 0x898:
2023 case 0x89c:
2024 case 0x8a0:
2025 case 0x8a4:
2026 case 0x8a8:
2027 case 0x8ac:
2028 case 0x8b0:
2029 case 0x8b4:
2030 /* PLL */
2031 case DP0_PLLCTRL:
2032 case DP1_PLLCTRL:
2033 case PXL_PLLCTRL:
2034 case PXL_PLLPARAM:
2035 case SYS_PLLPARAM:
2036 /* HDCP */
2037 case 0x980:
2038 case 0x984:
2039 case 0x988:
2040 case 0x98c:
2041 case 0x990:
2042 case 0x994:
2043 case 0x998:
2044 case 0x99c:
2045 case 0x9a0:
2046 case 0x9a4:
2047 case 0x9a8:
2048 case 0x9ac:
2049 /* Debug */
2050 case TSTCTL:
2051 case PLL_DBG:
2052 return true;
2053 }
2054 return false;
2055}
2056
2057static const struct regmap_range tc_volatile_ranges[] = {
2058 regmap_reg_range(PPI_BUSYPPI, PPI_BUSYPPI),
2059 regmap_reg_range(DSI_BUSYDSI, DSI_BUSYDSI),
2060 regmap_reg_range(DSI_LANESTATUS0, DSI_INTSTATUS),
2061 regmap_reg_range(DSIERRCNT, DSIERRCNT),
2062 regmap_reg_range(VFUEN0, VFUEN0),
2063 regmap_reg_range(SYSSTAT, SYSSTAT),
2064 regmap_reg_range(GPIOI, GPIOI),
2065 regmap_reg_range(INTSTS_G, INTSTS_G),
2066 regmap_reg_range(DP0_VMNGENSTATUS, DP0_VMNGENSTATUS),
2067 regmap_reg_range(DP0_AMNGENSTATUS, DP0_AMNGENSTATUS),
2068 regmap_reg_range(DP0_AUXWDATA(0), DP0_AUXSTATUS),
2069 regmap_reg_range(DP0_LTSTAT, DP0_SNKLTCHGREQ),
2070 regmap_reg_range(DP_PHY_CTRL, DP_PHY_CTRL),
2071 regmap_reg_range(DP0_PLLCTRL, PXL_PLLCTRL),
2072};
2073
2074static const struct regmap_access_table tc_volatile_table = {
2075 .yes_ranges = tc_volatile_ranges,
2076 .n_yes_ranges = ARRAY_SIZE(tc_volatile_ranges),
2077};
2078
2079static const struct regmap_range tc_precious_ranges[] = {
2080 regmap_reg_range(SYSSTAT, SYSSTAT),
2081};
2082
2083static const struct regmap_access_table tc_precious_table = {
2084 .yes_ranges = tc_precious_ranges,
2085 .n_yes_ranges = ARRAY_SIZE(tc_precious_ranges),
2086};
2087
2088static const struct regmap_range tc_non_writeable_ranges[] = {
2089 regmap_reg_range(PPI_BUSYPPI, PPI_BUSYPPI),
2090 regmap_reg_range(DSI_BUSYDSI, DSI_BUSYDSI),
2091 regmap_reg_range(DSI_LANESTATUS0, DSI_INTSTATUS),
2092 regmap_reg_range(TC_IDREG, SYSSTAT),
2093 regmap_reg_range(GPIOI, GPIOI),
2094 regmap_reg_range(DP0_LTSTAT, DP0_SNKLTCHGREQ),
2095};
2096
2097static const struct regmap_access_table tc_writeable_table = {
2098 .no_ranges = tc_non_writeable_ranges,
2099 .n_no_ranges = ARRAY_SIZE(tc_non_writeable_ranges),
2100};
2101
2102static const struct regmap_config tc_regmap_config = {
2103 .name = "tc358767",
2104 .reg_bits = 16,
2105 .val_bits = 32,
2106 .reg_stride = 4,
2107 .max_register = PLL_DBG,
2108 .cache_type = REGCACHE_MAPLE,
2109 .readable_reg = tc_readable_reg,
2110 .volatile_table = &tc_volatile_table,
2111 .precious_table = &tc_precious_table,
2112 .wr_table = &tc_writeable_table,
2113 .reg_format_endian = REGMAP_ENDIAN_BIG,
2114 .val_format_endian = REGMAP_ENDIAN_LITTLE,
2115};
2116
2117static irqreturn_t tc_irq_handler(int irq, void *arg)
2118{
2119 struct tc_data *tc = arg;
2120 u32 val;
2121 int r;
2122
2123 r = regmap_read(tc->regmap, INTSTS_G, &val);
2124 if (r)
2125 return IRQ_NONE;
2126
2127 if (!val)
2128 return IRQ_NONE;
2129
2130 if (val & INT_SYSERR) {
2131 u32 stat = 0;
2132
2133 regmap_read(tc->regmap, SYSSTAT, &stat);
2134
2135 dev_err(tc->dev, "syserr %x\n", stat);
2136 }
2137
2138 if (tc->hpd_pin >= 0 && tc->bridge.dev) {
2139 /*
2140 * H is triggered when the GPIO goes high.
2141 *
2142 * LC is triggered when the GPIO goes low and stays low for
2143 * the duration of LCNT
2144 */
2145 bool h = val & INT_GPIO_H(tc->hpd_pin);
2146 bool lc = val & INT_GPIO_LC(tc->hpd_pin);
2147
2148 dev_dbg(tc->dev, "GPIO%d: %s %s\n", tc->hpd_pin,
2149 h ? "H" : "", lc ? "LC" : "");
2150
2151 if (h || lc)
2152 drm_kms_helper_hotplug_event(tc->bridge.dev);
2153 }
2154
2155 regmap_write(tc->regmap, INTSTS_G, val);
2156
2157 return IRQ_HANDLED;
2158}
2159
2160static int tc_mipi_dsi_host_attach(struct tc_data *tc)
2161{
2162 struct device *dev = tc->dev;
2163 struct device_node *host_node;
2164 struct device_node *endpoint;
2165 struct mipi_dsi_device *dsi;
2166 struct mipi_dsi_host *host;
2167 const struct mipi_dsi_device_info info = {
2168 .type = "tc358767",
2169 .channel = 0,
2170 .node = NULL,
2171 };
2172 int dsi_lanes, ret;
2173
2174 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1);
2175 dsi_lanes = drm_of_get_data_lanes_count(endpoint, 1, 4);
2176 host_node = of_graph_get_remote_port_parent(endpoint);
2177 host = of_find_mipi_dsi_host_by_node(host_node);
2178 of_node_put(host_node);
2179 of_node_put(endpoint);
2180
2181 if (!host)
2182 return -EPROBE_DEFER;
2183
2184 if (dsi_lanes < 0)
2185 return dsi_lanes;
2186
2187 dsi = devm_mipi_dsi_device_register_full(dev, host, &info);
2188 if (IS_ERR(dsi))
2189 return dev_err_probe(dev, PTR_ERR(dsi),
2190 "failed to create dsi device\n");
2191
2192 tc->dsi = dsi;
2193 dsi->lanes = dsi_lanes;
2194 dsi->format = MIPI_DSI_FMT_RGB888;
2195 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
2196 MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS;
2197
2198 ret = devm_mipi_dsi_attach(dev, dsi);
2199 if (ret < 0) {
2200 dev_err(dev, "failed to attach dsi to host: %d\n", ret);
2201 return ret;
2202 }
2203
2204 return 0;
2205}
2206
2207static int tc_probe_dpi_bridge_endpoint(struct tc_data *tc)
2208{
2209 struct device *dev = tc->dev;
2210 struct drm_bridge *bridge;
2211 struct drm_panel *panel;
2212 int ret;
2213
2214 /* port@1 is the DPI input/output port */
2215 ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0, &panel, &bridge);
2216 if (ret && ret != -ENODEV)
2217 return ret;
2218
2219 if (panel) {
2220 bridge = devm_drm_panel_bridge_add(dev, panel);
2221 if (IS_ERR(bridge))
2222 return PTR_ERR(bridge);
2223 }
2224
2225 if (bridge) {
2226 tc->panel_bridge = bridge;
2227 tc->bridge.type = DRM_MODE_CONNECTOR_DPI;
2228 tc->bridge.funcs = &tc_dpi_bridge_funcs;
2229
2230 return 0;
2231 }
2232
2233 return ret;
2234}
2235
2236static int tc_probe_edp_bridge_endpoint(struct tc_data *tc)
2237{
2238 struct device *dev = tc->dev;
2239 struct drm_panel *panel;
2240 int ret;
2241
2242 /* port@2 is the output port */
2243 ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &panel, NULL);
2244 if (ret && ret != -ENODEV)
2245 return ret;
2246
2247 if (panel) {
2248 struct drm_bridge *panel_bridge;
2249
2250 panel_bridge = devm_drm_panel_bridge_add(dev, panel);
2251 if (IS_ERR(panel_bridge))
2252 return PTR_ERR(panel_bridge);
2253
2254 tc->panel_bridge = panel_bridge;
2255 tc->bridge.type = DRM_MODE_CONNECTOR_eDP;
2256 } else {
2257 tc->bridge.type = DRM_MODE_CONNECTOR_DisplayPort;
2258 }
2259
2260 tc->bridge.funcs = &tc_edp_bridge_funcs;
2261 if (tc->hpd_pin >= 0)
2262 tc->bridge.ops |= DRM_BRIDGE_OP_DETECT;
2263 tc->bridge.ops |= DRM_BRIDGE_OP_EDID;
2264
2265 return 0;
2266}
2267
2268static int tc_probe_bridge_endpoint(struct tc_data *tc)
2269{
2270 struct device *dev = tc->dev;
2271 struct of_endpoint endpoint;
2272 struct device_node *node = NULL;
2273 const u8 mode_dpi_to_edp = BIT(1) | BIT(2);
2274 const u8 mode_dpi_to_dp = BIT(1);
2275 const u8 mode_dsi_to_edp = BIT(0) | BIT(2);
2276 const u8 mode_dsi_to_dp = BIT(0);
2277 const u8 mode_dsi_to_dpi = BIT(0) | BIT(1);
2278 u8 mode = 0;
2279
2280 /*
2281 * Determine bridge configuration.
2282 *
2283 * Port allocation:
2284 * port@0 - DSI input
2285 * port@1 - DPI input/output
2286 * port@2 - eDP output
2287 *
2288 * Possible connections:
2289 * DPI -> port@1 -> port@2 -> eDP :: [port@0 is not connected]
2290 * DSI -> port@0 -> port@2 -> eDP :: [port@1 is not connected]
2291 * DSI -> port@0 -> port@1 -> DPI :: [port@2 is not connected]
2292 */
2293
2294 for_each_endpoint_of_node(dev->of_node, node) {
2295 of_graph_parse_endpoint(node, &endpoint);
2296 if (endpoint.port > 2) {
2297 of_node_put(node);
2298 return -EINVAL;
2299 }
2300 mode |= BIT(endpoint.port);
2301 }
2302
2303 if (mode == mode_dpi_to_edp || mode == mode_dpi_to_dp) {
2304 tc->input_connector_dsi = false;
2305 return tc_probe_edp_bridge_endpoint(tc);
2306 } else if (mode == mode_dsi_to_dpi) {
2307 tc->input_connector_dsi = true;
2308 return tc_probe_dpi_bridge_endpoint(tc);
2309 } else if (mode == mode_dsi_to_edp || mode == mode_dsi_to_dp) {
2310 tc->input_connector_dsi = true;
2311 return tc_probe_edp_bridge_endpoint(tc);
2312 }
2313
2314 dev_warn(dev, "Invalid mode (0x%x) is not supported!\n", mode);
2315
2316 return -EINVAL;
2317}
2318
2319static int tc_probe(struct i2c_client *client)
2320{
2321 struct device *dev = &client->dev;
2322 struct tc_data *tc;
2323 int ret;
2324
2325 tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL);
2326 if (!tc)
2327 return -ENOMEM;
2328
2329 tc->dev = dev;
2330
2331 ret = tc_probe_bridge_endpoint(tc);
2332 if (ret)
2333 return ret;
2334
2335 tc->refclk = devm_clk_get_enabled(dev, "ref");
2336 if (IS_ERR(tc->refclk))
2337 return dev_err_probe(dev, PTR_ERR(tc->refclk),
2338 "Failed to get and enable the ref clk\n");
2339
2340 /* tRSTW = 100 cycles , at 13 MHz that is ~7.69 us */
2341 usleep_range(10, 15);
2342
2343 /* Shut down GPIO is optional */
2344 tc->sd_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH);
2345 if (IS_ERR(tc->sd_gpio))
2346 return PTR_ERR(tc->sd_gpio);
2347
2348 if (tc->sd_gpio) {
2349 gpiod_set_value_cansleep(tc->sd_gpio, 0);
2350 usleep_range(5000, 10000);
2351 }
2352
2353 /* Reset GPIO is optional */
2354 tc->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
2355 if (IS_ERR(tc->reset_gpio))
2356 return PTR_ERR(tc->reset_gpio);
2357
2358 if (tc->reset_gpio) {
2359 gpiod_set_value_cansleep(tc->reset_gpio, 1);
2360 usleep_range(5000, 10000);
2361 }
2362
2363 tc->regmap = devm_regmap_init_i2c(client, &tc_regmap_config);
2364 if (IS_ERR(tc->regmap)) {
2365 ret = PTR_ERR(tc->regmap);
2366 dev_err(dev, "Failed to initialize regmap: %d\n", ret);
2367 return ret;
2368 }
2369
2370 ret = of_property_read_u32(dev->of_node, "toshiba,hpd-pin",
2371 &tc->hpd_pin);
2372 if (ret) {
2373 tc->hpd_pin = -ENODEV;
2374 } else {
2375 if (tc->hpd_pin < 0 || tc->hpd_pin > 1) {
2376 dev_err(dev, "failed to parse HPD number\n");
2377 return -EINVAL;
2378 }
2379 }
2380
2381 if (client->irq > 0) {
2382 /* enable SysErr */
2383 regmap_write(tc->regmap, INTCTL_G, INT_SYSERR);
2384
2385 ret = devm_request_threaded_irq(dev, client->irq,
2386 NULL, tc_irq_handler,
2387 IRQF_ONESHOT,
2388 "tc358767-irq", tc);
2389 if (ret) {
2390 dev_err(dev, "failed to register dp interrupt\n");
2391 return ret;
2392 }
2393
2394 tc->have_irq = true;
2395 }
2396
2397 ret = regmap_read(tc->regmap, TC_IDREG, &tc->rev);
2398 if (ret) {
2399 dev_err(tc->dev, "can not read device ID: %d\n", ret);
2400 return ret;
2401 }
2402
2403 if ((tc->rev != 0x6601) && (tc->rev != 0x6603)) {
2404 dev_err(tc->dev, "invalid device ID: 0x%08x\n", tc->rev);
2405 return -EINVAL;
2406 }
2407
2408 tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */
2409
2410 if (!tc->reset_gpio) {
2411 /*
2412 * If the reset pin isn't present, do a software reset. It isn't
2413 * as thorough as the hardware reset, as we can't reset the I2C
2414 * communication block for obvious reasons, but it's getting the
2415 * chip into a defined state.
2416 */
2417 regmap_update_bits(tc->regmap, SYSRSTENB,
2418 ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP,
2419 0);
2420 regmap_update_bits(tc->regmap, SYSRSTENB,
2421 ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP,
2422 ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP);
2423 usleep_range(5000, 10000);
2424 }
2425
2426 if (tc->hpd_pin >= 0) {
2427 u32 lcnt_reg = tc->hpd_pin == 0 ? INT_GP0_LCNT : INT_GP1_LCNT;
2428 u32 h_lc = INT_GPIO_H(tc->hpd_pin) | INT_GPIO_LC(tc->hpd_pin);
2429
2430 /* Set LCNT to 2ms */
2431 regmap_write(tc->regmap, lcnt_reg,
2432 clk_get_rate(tc->refclk) * 2 / 1000);
2433 /* We need the "alternate" mode for HPD */
2434 regmap_write(tc->regmap, GPIOM, BIT(tc->hpd_pin));
2435
2436 if (tc->have_irq) {
2437 /* enable H & LC */
2438 regmap_update_bits(tc->regmap, INTCTL_G, h_lc, h_lc);
2439 }
2440 }
2441
2442 if (tc->bridge.type != DRM_MODE_CONNECTOR_DPI) { /* (e)DP output */
2443 ret = tc_aux_link_setup(tc);
2444 if (ret)
2445 return ret;
2446 }
2447
2448 tc->bridge.of_node = dev->of_node;
2449 drm_bridge_add(&tc->bridge);
2450
2451 i2c_set_clientdata(client, tc);
2452
2453 if (tc->input_connector_dsi) { /* DSI input */
2454 ret = tc_mipi_dsi_host_attach(tc);
2455 if (ret) {
2456 drm_bridge_remove(&tc->bridge);
2457 return ret;
2458 }
2459 }
2460
2461 return 0;
2462}
2463
2464static void tc_remove(struct i2c_client *client)
2465{
2466 struct tc_data *tc = i2c_get_clientdata(client);
2467
2468 drm_bridge_remove(&tc->bridge);
2469}
2470
2471static const struct i2c_device_id tc358767_i2c_ids[] = {
2472 { "tc358767", 0 },
2473 { }
2474};
2475MODULE_DEVICE_TABLE(i2c, tc358767_i2c_ids);
2476
2477static const struct of_device_id tc358767_of_ids[] = {
2478 { .compatible = "toshiba,tc358767", },
2479 { }
2480};
2481MODULE_DEVICE_TABLE(of, tc358767_of_ids);
2482
2483static struct i2c_driver tc358767_driver = {
2484 .driver = {
2485 .name = "tc358767",
2486 .of_match_table = tc358767_of_ids,
2487 },
2488 .id_table = tc358767_i2c_ids,
2489 .probe = tc_probe,
2490 .remove = tc_remove,
2491};
2492module_i2c_driver(tc358767_driver);
2493
2494MODULE_AUTHOR("Andrey Gusakov <andrey.gusakov@cogentembedded.com>");
2495MODULE_DESCRIPTION("tc358767 eDP encoder driver");
2496MODULE_LICENSE("GPL");