1/* SPDX-License-Identifier: MIT */
  2
  3#ifndef __AST_REG_H__
  4#define __AST_REG_H__
  5
  6#include <linux/bits.h>
  7
  8/*
  9 * Modesetting
 10 */
 11
 12#define AST_IO_MM_OFFSET		(0x380)
 13#define AST_IO_MM_LENGTH		(128)
 14
 15#define AST_IO_VGAARI_W			(0x40)
 16
 17#define AST_IO_VGAMR_W			(0x42)
 18#define AST_IO_VGAMR_R			(0x4c)
 19#define AST_IO_VGAMR_IOSEL		BIT(0)
 20
 21#define AST_IO_VGAER			(0x43)
 22#define AST_IO_VGAER_VGA_ENABLE		BIT(0)
 23
 24#define AST_IO_VGASRI			(0x44)
 25#define AST_IO_VGADRR			(0x47)
 26#define AST_IO_VGADWR			(0x48)
 27#define AST_IO_VGAPDR		        (0x49)
 28#define AST_IO_VGAGRI			(0x4E)
 29
 30#define AST_IO_VGACRI			(0x54)
 31#define AST_IO_VGACR80_PASSWORD		(0xa8)
 32#define AST_IO_VGACRA1_VGAIO_DISABLED	BIT(1)
 33#define AST_IO_VGACRA1_MMIO_ENABLED	BIT(2)
 34#define AST_IO_VGACRCB_HWC_16BPP	BIT(0) /* set: ARGB4444, cleared: 2bpp palette */
 35#define AST_IO_VGACRCB_HWC_ENABLED	BIT(1)
 36
 37#define AST_IO_VGAIR1_R			(0x5A)
 38#define AST_IO_VGAIR1_VREFRESH		BIT(3)
 39
 40/*
 41 * Display Transmitter Type
 42 */
 43
 44#define TX_TYPE_MASK			GENMASK(3, 1)
 45#define NO_TX				(0 << 1)
 46#define ITE66121_VBIOS_TX		(1 << 1)
 47#define SI164_VBIOS_TX			(2 << 1)
 48#define CH7003_VBIOS_TX			(3 << 1)
 49#define DP501_VBIOS_TX			(4 << 1)
 50#define ANX9807_VBIOS_TX		(5 << 1)
 51#define TX_FW_EMBEDDED_FW_TX		(6 << 1)
 52#define ASTDP_DPMCU_TX			(7 << 1)
 53
 54#define AST_VRAM_INIT_STATUS_MASK	GENMASK(7, 6)
 55//#define AST_VRAM_INIT_BY_BMC		BIT(7)
 56//#define AST_VRAM_INIT_READY		BIT(6)
 57
 58/*
 59 * AST DisplayPort
 60 */
 61
 62/* Define for Soc scratched reg used on ASTDP */
 63#define AST_DP_PHY_SLEEP		BIT(4)
 64#define AST_DP_VIDEO_ENABLE		BIT(0)
 65
 66/*
 67 * CRD1[b5]: DP MCU FW is executing
 68 * CRDC[b0]: DP link success
 69 * CRDF[b0]: DP HPD
 70 * CRE5[b0]: Host reading EDID process is done
 71 */
 72#define ASTDP_MCU_FW_EXECUTING		BIT(5)
 73#define ASTDP_LINK_SUCCESS		BIT(0)
 74#define ASTDP_HPD			BIT(0)
 75#define ASTDP_HOST_EDID_READ_DONE	BIT(0)
 76#define ASTDP_HOST_EDID_READ_DONE_MASK	GENMASK(0, 0)
 77
 78/*
 79 * CRB8[b1]: Enable VSYNC off
 80 * CRB8[b0]: Enable HSYNC off
 81 */
 82#define AST_DPMS_VSYNC_OFF		BIT(1)
 83#define AST_DPMS_HSYNC_OFF		BIT(0)
 84
 85/*
 86 * CRDF[b4]: Mirror of AST_DP_VIDEO_ENABLE
 87 * Precondition:	A. ~AST_DP_PHY_SLEEP  &&
 88 *			B. DP_HPD &&
 89 *			C. DP_LINK_SUCCESS
 90 */
 91#define ASTDP_MIRROR_VIDEO_ENABLE	BIT(4)
 92
 93#define ASTDP_EDID_READ_POINTER_MASK	GENMASK(7, 0)
 94#define ASTDP_EDID_VALID_FLAG_MASK	GENMASK(0, 0)
 95#define ASTDP_EDID_READ_DATA_MASK	GENMASK(7, 0)
 96
 97/*
 98 * ASTDP setmode registers:
 99 * CRE0[7:0]: MISC0 ((0x00: 18-bpp) or (0x20: 24-bpp)
100 * CRE1[7:0]: MISC1 (default: 0x00)
101 * CRE2[7:0]: video format index (0x00 ~ 0x20 or 0x40 ~ 0x50)
102 */
103#define ASTDP_MISC0_24bpp		BIT(5)
104#define ASTDP_MISC1			0
105#define ASTDP_AND_CLEAR_MASK		0x00
106
107#endif