1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 *  Copyright (C) 2010, 2011 Texas Instruments Incorporated
  4 *  Contributed by: Mark Salter (msalter@redhat.com)
  5 */
  6
  7#include <linux/clockchips.h>
  8#include <linux/interrupt.h>
  9#include <linux/io.h>
 10#include <linux/of.h>
 11#include <linux/of_irq.h>
 12#include <linux/of_address.h>
 13#include <asm/soc.h>
 14#include <asm/dscr.h>
 15#include <asm/special_insns.h>
 16#include <asm/timer64.h>
 17
 18struct timer_regs {
 19	u32	reserved0;
 20	u32	emumgt;
 21	u32	reserved1;
 22	u32	reserved2;
 23	u32	cntlo;
 24	u32	cnthi;
 25	u32	prdlo;
 26	u32	prdhi;
 27	u32	tcr;
 28	u32	tgcr;
 29	u32	wdtcr;
 30};
 31
 32static struct timer_regs __iomem *timer;
 33
 34#define TCR_TSTATLO	     0x001
 35#define TCR_INVOUTPLO	     0x002
 36#define TCR_INVINPLO	     0x004
 37#define TCR_CPLO	     0x008
 38#define TCR_ENAMODELO_ONCE   0x040
 39#define TCR_ENAMODELO_CONT   0x080
 40#define TCR_ENAMODELO_MASK   0x0c0
 41#define TCR_PWIDLO_MASK      0x030
 42#define TCR_CLKSRCLO	     0x100
 43#define TCR_TIENLO	     0x200
 44#define TCR_TSTATHI	     (0x001 << 16)
 45#define TCR_INVOUTPHI	     (0x002 << 16)
 46#define TCR_CPHI	     (0x008 << 16)
 47#define TCR_PWIDHI_MASK      (0x030 << 16)
 48#define TCR_ENAMODEHI_ONCE   (0x040 << 16)
 49#define TCR_ENAMODEHI_CONT   (0x080 << 16)
 50#define TCR_ENAMODEHI_MASK   (0x0c0 << 16)
 51
 52#define TGCR_TIMLORS	     0x001
 53#define TGCR_TIMHIRS	     0x002
 54#define TGCR_TIMMODE_UD32    0x004
 55#define TGCR_TIMMODE_WDT64   0x008
 56#define TGCR_TIMMODE_CD32    0x00c
 57#define TGCR_TIMMODE_MASK    0x00c
 58#define TGCR_PSCHI_MASK      (0x00f << 8)
 59#define TGCR_TDDRHI_MASK     (0x00f << 12)
 60
 61/*
 62 * Timer clocks are divided down from the CPU clock
 63 * The divisor is in the EMUMGTCLKSPD register
 64 */
 65#define TIMER_DIVISOR \
 66	((soc_readl(&timer->emumgt) & (0xf << 16)) >> 16)
 67
 68#define TIMER64_RATE (c6x_core_freq / TIMER_DIVISOR)
 69
 70#define TIMER64_MODE_DISABLED 0
 71#define TIMER64_MODE_ONE_SHOT TCR_ENAMODELO_ONCE
 72#define TIMER64_MODE_PERIODIC TCR_ENAMODELO_CONT
 73
 74static int timer64_mode;
 75static int timer64_devstate_id = -1;
 76
 77static void timer64_config(unsigned long period)
 78{
 79	u32 tcr = soc_readl(&timer->tcr) & ~TCR_ENAMODELO_MASK;
 80
 81	soc_writel(tcr, &timer->tcr);
 82	soc_writel(period - 1, &timer->prdlo);
 83	soc_writel(0, &timer->cntlo);
 84	tcr |= timer64_mode;
 85	soc_writel(tcr, &timer->tcr);
 86}
 87
 88static void timer64_enable(void)
 89{
 90	u32 val;
 91
 92	if (timer64_devstate_id >= 0)
 93		dscr_set_devstate(timer64_devstate_id, DSCR_DEVSTATE_ENABLED);
 94
 95	/* disable timer, reset count */
 96	soc_writel(soc_readl(&timer->tcr) & ~TCR_ENAMODELO_MASK, &timer->tcr);
 97	soc_writel(0, &timer->prdlo);
 98
 99	/* use internal clock and 1 cycle pulse width */
100	val = soc_readl(&timer->tcr);
101	soc_writel(val & ~(TCR_CLKSRCLO | TCR_PWIDLO_MASK), &timer->tcr);
102
103	/* dual 32-bit unchained mode */
104	val = soc_readl(&timer->tgcr) & ~TGCR_TIMMODE_MASK;
105	soc_writel(val, &timer->tgcr);
106	soc_writel(val | (TGCR_TIMLORS | TGCR_TIMMODE_UD32), &timer->tgcr);
107}
108
109static void timer64_disable(void)
110{
111	/* disable timer, reset count */
112	soc_writel(soc_readl(&timer->tcr) & ~TCR_ENAMODELO_MASK, &timer->tcr);
113	soc_writel(0, &timer->prdlo);
114
115	if (timer64_devstate_id >= 0)
116		dscr_set_devstate(timer64_devstate_id, DSCR_DEVSTATE_DISABLED);
117}
118
119static int next_event(unsigned long delta,
120		      struct clock_event_device *evt)
121{
122	timer64_config(delta);
123	return 0;
124}
125
126static int set_periodic(struct clock_event_device *evt)
127{
128	timer64_enable();
129	timer64_mode = TIMER64_MODE_PERIODIC;
130	timer64_config(TIMER64_RATE / HZ);
131	return 0;
132}
133
134static int set_oneshot(struct clock_event_device *evt)
135{
136	timer64_enable();
137	timer64_mode = TIMER64_MODE_ONE_SHOT;
138	return 0;
139}
140
141static int shutdown(struct clock_event_device *evt)
142{
143	timer64_mode = TIMER64_MODE_DISABLED;
144	timer64_disable();
145	return 0;
146}
147
148static struct clock_event_device t64_clockevent_device = {
149	.name			= "TIMER64_EVT32_TIMER",
150	.features		= CLOCK_EVT_FEAT_ONESHOT |
151				  CLOCK_EVT_FEAT_PERIODIC,
152	.rating			= 200,
153	.set_state_shutdown	= shutdown,
154	.set_state_periodic	= set_periodic,
155	.set_state_oneshot	= set_oneshot,
156	.set_next_event		= next_event,
157};
158
159static irqreturn_t timer_interrupt(int irq, void *dev_id)
160{
161	struct clock_event_device *cd = &t64_clockevent_device;
162
163	cd->event_handler(cd);
164
165	return IRQ_HANDLED;
166}
167
168void __init timer64_init(void)
169{
170	struct clock_event_device *cd = &t64_clockevent_device;
171	struct device_node *np, *first = NULL;
172	u32 val;
173	int err, found = 0;
174
175	for_each_compatible_node(np, NULL, "ti,c64x+timer64") {
176		err = of_property_read_u32(np, "ti,core-mask", &val);
177		if (!err) {
178			if (val & (1 << get_coreid())) {
179				found = 1;
180				break;
181			}
182		} else if (!first)
183			first = np;
184	}
185	if (!found) {
186		/* try first one with no core-mask */
187		if (first)
188			np = of_node_get(first);
189		else {
190			pr_debug("Cannot find ti,c64x+timer64 timer.\n");
191			return;
192		}
193	}
194
195	timer = of_iomap(np, 0);
196	if (!timer) {
197		pr_debug("%pOF: Cannot map timer registers.\n", np);
198		goto out;
199	}
200	pr_debug("%pOF: Timer registers=%p.\n", np, timer);
201
202	cd->irq	= irq_of_parse_and_map(np, 0);
203	if (cd->irq == NO_IRQ) {
204		pr_debug("%pOF: Cannot find interrupt.\n", np);
205		iounmap(timer);
206		goto out;
207	}
208
209	/* If there is a device state control, save the ID. */
210	err = of_property_read_u32(np, "ti,dscr-dev-enable", &val);
211	if (!err) {
212		timer64_devstate_id = val;
213
214		/*
215		 * It is necessary to enable the timer block here because
216		 * the TIMER_DIVISOR macro needs to read a timer register
217		 * to get the divisor.
218		 */
219		dscr_set_devstate(timer64_devstate_id, DSCR_DEVSTATE_ENABLED);
220	}
221
222	pr_debug("%pOF: Timer irq=%d.\n", np, cd->irq);
223
224	clockevents_calc_mult_shift(cd, c6x_core_freq / TIMER_DIVISOR, 5);
225
226	cd->max_delta_ns	= clockevent_delta2ns(0x7fffffff, cd);
227	cd->max_delta_ticks	= 0x7fffffff;
228	cd->min_delta_ns	= clockevent_delta2ns(250, cd);
229	cd->min_delta_ticks	= 250;
230
231	cd->cpumask		= cpumask_of(smp_processor_id());
232
233	clockevents_register_device(cd);
234	if (request_irq(cd->irq, timer_interrupt, IRQF_TIMER, "timer",
235			&t64_clockevent_device))
236		pr_err("Failed to request irq %d (timer)\n", cd->irq);
237
238out:
239	of_node_put(np);
240	return;
241}