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1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __LINUX_GPIO_DRIVER_H
3#define __LINUX_GPIO_DRIVER_H
4
5#include <linux/device.h>
6#include <linux/types.h>
7#include <linux/irq.h>
8#include <linux/irqchip/chained_irq.h>
9#include <linux/irqdomain.h>
10#include <linux/lockdep.h>
11#include <linux/pinctrl/pinctrl.h>
12#include <linux/pinctrl/pinconf-generic.h>
13
14struct gpio_desc;
15struct of_phandle_args;
16struct device_node;
17struct seq_file;
18struct gpio_device;
19struct module;
20enum gpiod_flags;
21enum gpio_lookup_flags;
22
23struct gpio_chip;
24
25#define GPIO_LINE_DIRECTION_IN 1
26#define GPIO_LINE_DIRECTION_OUT 0
27
28/**
29 * struct gpio_irq_chip - GPIO interrupt controller
30 */
31struct gpio_irq_chip {
32 /**
33 * @chip:
34 *
35 * GPIO IRQ chip implementation, provided by GPIO driver.
36 */
37 struct irq_chip *chip;
38
39 /**
40 * @domain:
41 *
42 * Interrupt translation domain; responsible for mapping between GPIO
43 * hwirq number and Linux IRQ number.
44 */
45 struct irq_domain *domain;
46
47 /**
48 * @domain_ops:
49 *
50 * Table of interrupt domain operations for this IRQ chip.
51 */
52 const struct irq_domain_ops *domain_ops;
53
54#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
55 /**
56 * @fwnode:
57 *
58 * Firmware node corresponding to this gpiochip/irqchip, necessary
59 * for hierarchical irqdomain support.
60 */
61 struct fwnode_handle *fwnode;
62
63 /**
64 * @parent_domain:
65 *
66 * If non-NULL, will be set as the parent of this GPIO interrupt
67 * controller's IRQ domain to establish a hierarchical interrupt
68 * domain. The presence of this will activate the hierarchical
69 * interrupt support.
70 */
71 struct irq_domain *parent_domain;
72
73 /**
74 * @child_to_parent_hwirq:
75 *
76 * This callback translates a child hardware IRQ offset to a parent
77 * hardware IRQ offset on a hierarchical interrupt chip. The child
78 * hardware IRQs correspond to the GPIO index 0..ngpio-1 (see the
79 * ngpio field of struct gpio_chip) and the corresponding parent
80 * hardware IRQ and type (such as IRQ_TYPE_*) shall be returned by
81 * the driver. The driver can calculate this from an offset or using
82 * a lookup table or whatever method is best for this chip. Return
83 * 0 on successful translation in the driver.
84 *
85 * If some ranges of hardware IRQs do not have a corresponding parent
86 * HWIRQ, return -EINVAL, but also make sure to fill in @valid_mask and
87 * @need_valid_mask to make these GPIO lines unavailable for
88 * translation.
89 */
90 int (*child_to_parent_hwirq)(struct gpio_chip *gc,
91 unsigned int child_hwirq,
92 unsigned int child_type,
93 unsigned int *parent_hwirq,
94 unsigned int *parent_type);
95
96 /**
97 * @populate_parent_alloc_arg :
98 *
99 * This optional callback allocates and populates the specific struct
100 * for the parent's IRQ domain. If this is not specified, then
101 * &gpiochip_populate_parent_fwspec_twocell will be used. A four-cell
102 * variant named &gpiochip_populate_parent_fwspec_fourcell is also
103 * available.
104 */
105 void *(*populate_parent_alloc_arg)(struct gpio_chip *gc,
106 unsigned int parent_hwirq,
107 unsigned int parent_type);
108
109 /**
110 * @child_offset_to_irq:
111 *
112 * This optional callback is used to translate the child's GPIO line
113 * offset on the GPIO chip to an IRQ number for the GPIO to_irq()
114 * callback. If this is not specified, then a default callback will be
115 * provided that returns the line offset.
116 */
117 unsigned int (*child_offset_to_irq)(struct gpio_chip *gc,
118 unsigned int pin);
119
120 /**
121 * @child_irq_domain_ops:
122 *
123 * The IRQ domain operations that will be used for this GPIO IRQ
124 * chip. If no operations are provided, then default callbacks will
125 * be populated to setup the IRQ hierarchy. Some drivers need to
126 * supply their own translate function.
127 */
128 struct irq_domain_ops child_irq_domain_ops;
129#endif
130
131 /**
132 * @handler:
133 *
134 * The IRQ handler to use (often a predefined IRQ core function) for
135 * GPIO IRQs, provided by GPIO driver.
136 */
137 irq_flow_handler_t handler;
138
139 /**
140 * @default_type:
141 *
142 * Default IRQ triggering type applied during GPIO driver
143 * initialization, provided by GPIO driver.
144 */
145 unsigned int default_type;
146
147 /**
148 * @lock_key:
149 *
150 * Per GPIO IRQ chip lockdep class for IRQ lock.
151 */
152 struct lock_class_key *lock_key;
153
154 /**
155 * @request_key:
156 *
157 * Per GPIO IRQ chip lockdep class for IRQ request.
158 */
159 struct lock_class_key *request_key;
160
161 /**
162 * @parent_handler:
163 *
164 * The interrupt handler for the GPIO chip's parent interrupts, may be
165 * NULL if the parent interrupts are nested rather than cascaded.
166 */
167 irq_flow_handler_t parent_handler;
168
169 /**
170 * @parent_handler_data:
171 *
172 * Data associated, and passed to, the handler for the parent
173 * interrupt.
174 */
175 void *parent_handler_data;
176
177 /**
178 * @num_parents:
179 *
180 * The number of interrupt parents of a GPIO chip.
181 */
182 unsigned int num_parents;
183
184 /**
185 * @parents:
186 *
187 * A list of interrupt parents of a GPIO chip. This is owned by the
188 * driver, so the core will only reference this list, not modify it.
189 */
190 unsigned int *parents;
191
192 /**
193 * @map:
194 *
195 * A list of interrupt parents for each line of a GPIO chip.
196 */
197 unsigned int *map;
198
199 /**
200 * @threaded:
201 *
202 * True if set the interrupt handling uses nested threads.
203 */
204 bool threaded;
205
206 /**
207 * @init_hw: optional routine to initialize hardware before
208 * an IRQ chip will be added. This is quite useful when
209 * a particular driver wants to clear IRQ related registers
210 * in order to avoid undesired events.
211 */
212 int (*init_hw)(struct gpio_chip *gc);
213
214 /**
215 * @init_valid_mask: optional routine to initialize @valid_mask, to be
216 * used if not all GPIO lines are valid interrupts. Sometimes some
217 * lines just cannot fire interrupts, and this routine, when defined,
218 * is passed a bitmap in "valid_mask" and it will have ngpios
219 * bits from 0..(ngpios-1) set to "1" as in valid. The callback can
220 * then directly set some bits to "0" if they cannot be used for
221 * interrupts.
222 */
223 void (*init_valid_mask)(struct gpio_chip *gc,
224 unsigned long *valid_mask,
225 unsigned int ngpios);
226
227 /**
228 * @valid_mask:
229 *
230 * If not %NULL holds bitmask of GPIOs which are valid to be included
231 * in IRQ domain of the chip.
232 */
233 unsigned long *valid_mask;
234
235 /**
236 * @first:
237 *
238 * Required for static IRQ allocation. If set, irq_domain_add_simple()
239 * will allocate and map all IRQs during initialization.
240 */
241 unsigned int first;
242
243 /**
244 * @irq_enable:
245 *
246 * Store old irq_chip irq_enable callback
247 */
248 void (*irq_enable)(struct irq_data *data);
249
250 /**
251 * @irq_disable:
252 *
253 * Store old irq_chip irq_disable callback
254 */
255 void (*irq_disable)(struct irq_data *data);
256 /**
257 * @irq_unmask:
258 *
259 * Store old irq_chip irq_unmask callback
260 */
261 void (*irq_unmask)(struct irq_data *data);
262
263 /**
264 * @irq_mask:
265 *
266 * Store old irq_chip irq_mask callback
267 */
268 void (*irq_mask)(struct irq_data *data);
269};
270
271/**
272 * struct gpio_chip - abstract a GPIO controller
273 * @label: a functional name for the GPIO device, such as a part
274 * number or the name of the SoC IP-block implementing it.
275 * @gpiodev: the internal state holder, opaque struct
276 * @parent: optional parent device providing the GPIOs
277 * @owner: helps prevent removal of modules exporting active GPIOs
278 * @request: optional hook for chip-specific activation, such as
279 * enabling module power and clock; may sleep
280 * @free: optional hook for chip-specific deactivation, such as
281 * disabling module power and clock; may sleep
282 * @get_direction: returns direction for signal "offset", 0=out, 1=in,
283 * (same as GPIO_LINE_DIRECTION_OUT / GPIO_LINE_DIRECTION_IN),
284 * or negative error. It is recommended to always implement this
285 * function, even on input-only or output-only gpio chips.
286 * @direction_input: configures signal "offset" as input, or returns error
287 * This can be omitted on input-only or output-only gpio chips.
288 * @direction_output: configures signal "offset" as output, or returns error
289 * This can be omitted on input-only or output-only gpio chips.
290 * @get: returns value for signal "offset", 0=low, 1=high, or negative error
291 * @get_multiple: reads values for multiple signals defined by "mask" and
292 * stores them in "bits", returns 0 on success or negative error
293 * @set: assigns output value for signal "offset"
294 * @set_multiple: assigns output values for multiple signals defined by "mask"
295 * @set_config: optional hook for all kinds of settings. Uses the same
296 * packed config format as generic pinconf.
297 * @to_irq: optional hook supporting non-static gpio_to_irq() mappings;
298 * implementation may not sleep
299 * @dbg_show: optional routine to show contents in debugfs; default code
300 * will be used when this is omitted, but custom code can show extra
301 * state (such as pullup/pulldown configuration).
302 * @init_valid_mask: optional routine to initialize @valid_mask, to be used if
303 * not all GPIOs are valid.
304 * @add_pin_ranges: optional routine to initialize pin ranges, to be used when
305 * requires special mapping of the pins that provides GPIO functionality.
306 * It is called after adding GPIO chip and before adding IRQ chip.
307 * @base: identifies the first GPIO number handled by this chip;
308 * or, if negative during registration, requests dynamic ID allocation.
309 * DEPRECATION: providing anything non-negative and nailing the base
310 * offset of GPIO chips is deprecated. Please pass -1 as base to
311 * let gpiolib select the chip base in all possible cases. We want to
312 * get rid of the static GPIO number space in the long run.
313 * @ngpio: the number of GPIOs handled by this controller; the last GPIO
314 * handled is (base + ngpio - 1).
315 * @names: if set, must be an array of strings to use as alternative
316 * names for the GPIOs in this chip. Any entry in the array
317 * may be NULL if there is no alias for the GPIO, however the
318 * array must be @ngpio entries long. A name can include a single printk
319 * format specifier for an unsigned int. It is substituted by the actual
320 * number of the gpio.
321 * @can_sleep: flag must be set iff get()/set() methods sleep, as they
322 * must while accessing GPIO expander chips over I2C or SPI. This
323 * implies that if the chip supports IRQs, these IRQs need to be threaded
324 * as the chip access may sleep when e.g. reading out the IRQ status
325 * registers.
326 * @read_reg: reader function for generic GPIO
327 * @write_reg: writer function for generic GPIO
328 * @be_bits: if the generic GPIO has big endian bit order (bit 31 is representing
329 * line 0, bit 30 is line 1 ... bit 0 is line 31) this is set to true by the
330 * generic GPIO core. It is for internal housekeeping only.
331 * @reg_dat: data (in) register for generic GPIO
332 * @reg_set: output set register (out=high) for generic GPIO
333 * @reg_clr: output clear register (out=low) for generic GPIO
334 * @reg_dir_out: direction out setting register for generic GPIO
335 * @reg_dir_in: direction in setting register for generic GPIO
336 * @bgpio_dir_unreadable: indicates that the direction register(s) cannot
337 * be read and we need to rely on out internal state tracking.
338 * @bgpio_bits: number of register bits used for a generic GPIO i.e.
339 * <register width> * 8
340 * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep
341 * shadowed and real data registers writes together.
342 * @bgpio_data: shadowed data register for generic GPIO to clear/set bits
343 * safely.
344 * @bgpio_dir: shadowed direction register for generic GPIO to clear/set
345 * direction safely. A "1" in this word means the line is set as
346 * output.
347 *
348 * A gpio_chip can help platforms abstract various sources of GPIOs so
349 * they can all be accessed through a common programing interface.
350 * Example sources would be SOC controllers, FPGAs, multifunction
351 * chips, dedicated GPIO expanders, and so on.
352 *
353 * Each chip controls a number of signals, identified in method calls
354 * by "offset" values in the range 0..(@ngpio - 1). When those signals
355 * are referenced through calls like gpio_get_value(gpio), the offset
356 * is calculated by subtracting @base from the gpio number.
357 */
358struct gpio_chip {
359 const char *label;
360 struct gpio_device *gpiodev;
361 struct device *parent;
362 struct module *owner;
363
364 int (*request)(struct gpio_chip *gc,
365 unsigned int offset);
366 void (*free)(struct gpio_chip *gc,
367 unsigned int offset);
368 int (*get_direction)(struct gpio_chip *gc,
369 unsigned int offset);
370 int (*direction_input)(struct gpio_chip *gc,
371 unsigned int offset);
372 int (*direction_output)(struct gpio_chip *gc,
373 unsigned int offset, int value);
374 int (*get)(struct gpio_chip *gc,
375 unsigned int offset);
376 int (*get_multiple)(struct gpio_chip *gc,
377 unsigned long *mask,
378 unsigned long *bits);
379 void (*set)(struct gpio_chip *gc,
380 unsigned int offset, int value);
381 void (*set_multiple)(struct gpio_chip *gc,
382 unsigned long *mask,
383 unsigned long *bits);
384 int (*set_config)(struct gpio_chip *gc,
385 unsigned int offset,
386 unsigned long config);
387 int (*to_irq)(struct gpio_chip *gc,
388 unsigned int offset);
389
390 void (*dbg_show)(struct seq_file *s,
391 struct gpio_chip *gc);
392
393 int (*init_valid_mask)(struct gpio_chip *gc,
394 unsigned long *valid_mask,
395 unsigned int ngpios);
396
397 int (*add_pin_ranges)(struct gpio_chip *gc);
398
399 int base;
400 u16 ngpio;
401 const char *const *names;
402 bool can_sleep;
403
404#if IS_ENABLED(CONFIG_GPIO_GENERIC)
405 unsigned long (*read_reg)(void __iomem *reg);
406 void (*write_reg)(void __iomem *reg, unsigned long data);
407 bool be_bits;
408 void __iomem *reg_dat;
409 void __iomem *reg_set;
410 void __iomem *reg_clr;
411 void __iomem *reg_dir_out;
412 void __iomem *reg_dir_in;
413 bool bgpio_dir_unreadable;
414 int bgpio_bits;
415 spinlock_t bgpio_lock;
416 unsigned long bgpio_data;
417 unsigned long bgpio_dir;
418#endif /* CONFIG_GPIO_GENERIC */
419
420#ifdef CONFIG_GPIOLIB_IRQCHIP
421 /*
422 * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
423 * to handle IRQs for most practical cases.
424 */
425
426 /**
427 * @irq:
428 *
429 * Integrates interrupt chip functionality with the GPIO chip. Can be
430 * used to handle IRQs for most practical cases.
431 */
432 struct gpio_irq_chip irq;
433#endif /* CONFIG_GPIOLIB_IRQCHIP */
434
435 /**
436 * @valid_mask:
437 *
438 * If not %NULL holds bitmask of GPIOs which are valid to be used
439 * from the chip.
440 */
441 unsigned long *valid_mask;
442
443#if defined(CONFIG_OF_GPIO)
444 /*
445 * If CONFIG_OF is enabled, then all GPIO controllers described in the
446 * device tree automatically may have an OF translation
447 */
448
449 /**
450 * @of_node:
451 *
452 * Pointer to a device tree node representing this GPIO controller.
453 */
454 struct device_node *of_node;
455
456 /**
457 * @of_gpio_n_cells:
458 *
459 * Number of cells used to form the GPIO specifier.
460 */
461 unsigned int of_gpio_n_cells;
462
463 /**
464 * @of_xlate:
465 *
466 * Callback to translate a device tree GPIO specifier into a chip-
467 * relative GPIO number and flags.
468 */
469 int (*of_xlate)(struct gpio_chip *gc,
470 const struct of_phandle_args *gpiospec, u32 *flags);
471#endif /* CONFIG_OF_GPIO */
472};
473
474extern const char *gpiochip_is_requested(struct gpio_chip *gc,
475 unsigned int offset);
476
477/**
478 * for_each_requested_gpio_in_range - iterates over requested GPIOs in a given range
479 * @chip: the chip to query
480 * @i: loop variable
481 * @base: first GPIO in the range
482 * @size: amount of GPIOs to check starting from @base
483 * @label: label of current GPIO
484 */
485#define for_each_requested_gpio_in_range(chip, i, base, size, label) \
486 for (i = 0; i < size; i++) \
487 if ((label = gpiochip_is_requested(chip, base + i)) == NULL) {} else
488
489/* Iterates over all requested GPIO of the given @chip */
490#define for_each_requested_gpio(chip, i, label) \
491 for_each_requested_gpio_in_range(chip, i, 0, chip->ngpio, label)
492
493/* add/remove chips */
494extern int gpiochip_add_data_with_key(struct gpio_chip *gc, void *data,
495 struct lock_class_key *lock_key,
496 struct lock_class_key *request_key);
497
498/**
499 * gpiochip_add_data() - register a gpio_chip
500 * @gc: the chip to register, with gc->base initialized
501 * @data: driver-private data associated with this chip
502 *
503 * Context: potentially before irqs will work
504 *
505 * When gpiochip_add_data() is called very early during boot, so that GPIOs
506 * can be freely used, the gc->parent device must be registered before
507 * the gpio framework's arch_initcall(). Otherwise sysfs initialization
508 * for GPIOs will fail rudely.
509 *
510 * gpiochip_add_data() must only be called after gpiolib initialization,
511 * ie after core_initcall().
512 *
513 * If gc->base is negative, this requests dynamic assignment of
514 * a range of valid GPIOs.
515 *
516 * Returns:
517 * A negative errno if the chip can't be registered, such as because the
518 * gc->base is invalid or already associated with a different chip.
519 * Otherwise it returns zero as a success code.
520 */
521#ifdef CONFIG_LOCKDEP
522#define gpiochip_add_data(gc, data) ({ \
523 static struct lock_class_key lock_key; \
524 static struct lock_class_key request_key; \
525 gpiochip_add_data_with_key(gc, data, &lock_key, \
526 &request_key); \
527 })
528#define devm_gpiochip_add_data(dev, gc, data) ({ \
529 static struct lock_class_key lock_key; \
530 static struct lock_class_key request_key; \
531 devm_gpiochip_add_data_with_key(dev, gc, data, &lock_key, \
532 &request_key); \
533 })
534#else
535#define gpiochip_add_data(gc, data) gpiochip_add_data_with_key(gc, data, NULL, NULL)
536#define devm_gpiochip_add_data(dev, gc, data) \
537 devm_gpiochip_add_data_with_key(dev, gc, data, NULL, NULL)
538#endif /* CONFIG_LOCKDEP */
539
540static inline int gpiochip_add(struct gpio_chip *gc)
541{
542 return gpiochip_add_data(gc, NULL);
543}
544extern void gpiochip_remove(struct gpio_chip *gc);
545extern int devm_gpiochip_add_data_with_key(struct device *dev, struct gpio_chip *gc, void *data,
546 struct lock_class_key *lock_key,
547 struct lock_class_key *request_key);
548
549extern struct gpio_chip *gpiochip_find(void *data,
550 int (*match)(struct gpio_chip *gc, void *data));
551
552bool gpiochip_line_is_irq(struct gpio_chip *gc, unsigned int offset);
553int gpiochip_reqres_irq(struct gpio_chip *gc, unsigned int offset);
554void gpiochip_relres_irq(struct gpio_chip *gc, unsigned int offset);
555void gpiochip_disable_irq(struct gpio_chip *gc, unsigned int offset);
556void gpiochip_enable_irq(struct gpio_chip *gc, unsigned int offset);
557
558/* Line status inquiry for drivers */
559bool gpiochip_line_is_open_drain(struct gpio_chip *gc, unsigned int offset);
560bool gpiochip_line_is_open_source(struct gpio_chip *gc, unsigned int offset);
561
562/* Sleep persistence inquiry for drivers */
563bool gpiochip_line_is_persistent(struct gpio_chip *gc, unsigned int offset);
564bool gpiochip_line_is_valid(const struct gpio_chip *gc, unsigned int offset);
565
566/* get driver data */
567void *gpiochip_get_data(struct gpio_chip *gc);
568
569struct bgpio_pdata {
570 const char *label;
571 int base;
572 int ngpio;
573};
574
575#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
576
577void *gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *gc,
578 unsigned int parent_hwirq,
579 unsigned int parent_type);
580void *gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *gc,
581 unsigned int parent_hwirq,
582 unsigned int parent_type);
583
584#else
585
586static inline void *gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *gc,
587 unsigned int parent_hwirq,
588 unsigned int parent_type)
589{
590 return NULL;
591}
592
593static inline void *gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *gc,
594 unsigned int parent_hwirq,
595 unsigned int parent_type)
596{
597 return NULL;
598}
599
600#endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */
601
602int bgpio_init(struct gpio_chip *gc, struct device *dev,
603 unsigned long sz, void __iomem *dat, void __iomem *set,
604 void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
605 unsigned long flags);
606
607#define BGPIOF_BIG_ENDIAN BIT(0)
608#define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */
609#define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */
610#define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3)
611#define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */
612#define BGPIOF_NO_OUTPUT BIT(5) /* only input */
613#define BGPIOF_NO_SET_ON_INPUT BIT(6)
614
615int gpiochip_irq_map(struct irq_domain *d, unsigned int irq,
616 irq_hw_number_t hwirq);
617void gpiochip_irq_unmap(struct irq_domain *d, unsigned int irq);
618
619int gpiochip_irq_domain_activate(struct irq_domain *domain,
620 struct irq_data *data, bool reserve);
621void gpiochip_irq_domain_deactivate(struct irq_domain *domain,
622 struct irq_data *data);
623
624void gpiochip_set_nested_irqchip(struct gpio_chip *gc,
625 struct irq_chip *irqchip,
626 unsigned int parent_irq);
627
628int gpiochip_irqchip_add_key(struct gpio_chip *gc,
629 struct irq_chip *irqchip,
630 unsigned int first_irq,
631 irq_flow_handler_t handler,
632 unsigned int type,
633 bool threaded,
634 struct lock_class_key *lock_key,
635 struct lock_class_key *request_key);
636
637bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gc,
638 unsigned int offset);
639
640int gpiochip_irqchip_add_domain(struct gpio_chip *gc,
641 struct irq_domain *domain);
642
643#ifdef CONFIG_LOCKDEP
644
645/*
646 * Lockdep requires that each irqchip instance be created with a
647 * unique key so as to avoid unnecessary warnings. This upfront
648 * boilerplate static inlines provides such a key for each
649 * unique instance.
650 */
651static inline int gpiochip_irqchip_add(struct gpio_chip *gc,
652 struct irq_chip *irqchip,
653 unsigned int first_irq,
654 irq_flow_handler_t handler,
655 unsigned int type)
656{
657 static struct lock_class_key lock_key;
658 static struct lock_class_key request_key;
659
660 return gpiochip_irqchip_add_key(gc, irqchip, first_irq,
661 handler, type, false,
662 &lock_key, &request_key);
663}
664
665static inline int gpiochip_irqchip_add_nested(struct gpio_chip *gc,
666 struct irq_chip *irqchip,
667 unsigned int first_irq,
668 irq_flow_handler_t handler,
669 unsigned int type)
670{
671
672 static struct lock_class_key lock_key;
673 static struct lock_class_key request_key;
674
675 return gpiochip_irqchip_add_key(gc, irqchip, first_irq,
676 handler, type, true,
677 &lock_key, &request_key);
678}
679#else /* ! CONFIG_LOCKDEP */
680static inline int gpiochip_irqchip_add(struct gpio_chip *gc,
681 struct irq_chip *irqchip,
682 unsigned int first_irq,
683 irq_flow_handler_t handler,
684 unsigned int type)
685{
686 return gpiochip_irqchip_add_key(gc, irqchip, first_irq,
687 handler, type, false, NULL, NULL);
688}
689
690static inline int gpiochip_irqchip_add_nested(struct gpio_chip *gc,
691 struct irq_chip *irqchip,
692 unsigned int first_irq,
693 irq_flow_handler_t handler,
694 unsigned int type)
695{
696 return gpiochip_irqchip_add_key(gc, irqchip, first_irq,
697 handler, type, true, NULL, NULL);
698}
699#endif /* CONFIG_LOCKDEP */
700
701int gpiochip_generic_request(struct gpio_chip *gc, unsigned int offset);
702void gpiochip_generic_free(struct gpio_chip *gc, unsigned int offset);
703int gpiochip_generic_config(struct gpio_chip *gc, unsigned int offset,
704 unsigned long config);
705
706/**
707 * struct gpio_pin_range - pin range controlled by a gpio chip
708 * @node: list for maintaining set of pin ranges, used internally
709 * @pctldev: pinctrl device which handles corresponding pins
710 * @range: actual range of pins controlled by a gpio controller
711 */
712struct gpio_pin_range {
713 struct list_head node;
714 struct pinctrl_dev *pctldev;
715 struct pinctrl_gpio_range range;
716};
717
718#ifdef CONFIG_PINCTRL
719
720int gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name,
721 unsigned int gpio_offset, unsigned int pin_offset,
722 unsigned int npins);
723int gpiochip_add_pingroup_range(struct gpio_chip *gc,
724 struct pinctrl_dev *pctldev,
725 unsigned int gpio_offset, const char *pin_group);
726void gpiochip_remove_pin_ranges(struct gpio_chip *gc);
727
728#else /* ! CONFIG_PINCTRL */
729
730static inline int
731gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name,
732 unsigned int gpio_offset, unsigned int pin_offset,
733 unsigned int npins)
734{
735 return 0;
736}
737static inline int
738gpiochip_add_pingroup_range(struct gpio_chip *gc,
739 struct pinctrl_dev *pctldev,
740 unsigned int gpio_offset, const char *pin_group)
741{
742 return 0;
743}
744
745static inline void
746gpiochip_remove_pin_ranges(struct gpio_chip *gc)
747{
748}
749
750#endif /* CONFIG_PINCTRL */
751
752struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *gc,
753 unsigned int hwnum,
754 const char *label,
755 enum gpio_lookup_flags lflags,
756 enum gpiod_flags dflags);
757void gpiochip_free_own_desc(struct gpio_desc *desc);
758
759void devprop_gpiochip_set_names(struct gpio_chip *gc,
760 const struct fwnode_handle *fwnode);
761
762#ifdef CONFIG_GPIOLIB
763
764/* lock/unlock as IRQ */
765int gpiochip_lock_as_irq(struct gpio_chip *gc, unsigned int offset);
766void gpiochip_unlock_as_irq(struct gpio_chip *gc, unsigned int offset);
767
768
769struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc);
770
771#else /* CONFIG_GPIOLIB */
772
773static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc)
774{
775 /* GPIO can never have been requested */
776 WARN_ON(1);
777 return ERR_PTR(-ENODEV);
778}
779
780static inline int gpiochip_lock_as_irq(struct gpio_chip *gc,
781 unsigned int offset)
782{
783 WARN_ON(1);
784 return -EINVAL;
785}
786
787static inline void gpiochip_unlock_as_irq(struct gpio_chip *gc,
788 unsigned int offset)
789{
790 WARN_ON(1);
791}
792#endif /* CONFIG_GPIOLIB */
793
794#endif /* __LINUX_GPIO_DRIVER_H */
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __LINUX_GPIO_DRIVER_H
3#define __LINUX_GPIO_DRIVER_H
4
5#include <linux/bits.h>
6#include <linux/cleanup.h>
7#include <linux/err.h>
8#include <linux/irqchip/chained_irq.h>
9#include <linux/irqdomain.h>
10#include <linux/irqhandler.h>
11#include <linux/lockdep.h>
12#include <linux/pinctrl/pinconf-generic.h>
13#include <linux/pinctrl/pinctrl.h>
14#include <linux/property.h>
15#include <linux/spinlock_types.h>
16#include <linux/types.h>
17
18#ifdef CONFIG_GENERIC_MSI_IRQ
19#include <asm/msi.h>
20#endif
21
22struct device;
23struct irq_chip;
24struct irq_data;
25struct module;
26struct of_phandle_args;
27struct pinctrl_dev;
28struct seq_file;
29
30struct gpio_chip;
31struct gpio_desc;
32struct gpio_device;
33
34enum gpio_lookup_flags;
35enum gpiod_flags;
36
37union gpio_irq_fwspec {
38 struct irq_fwspec fwspec;
39#ifdef CONFIG_GENERIC_MSI_IRQ
40 msi_alloc_info_t msiinfo;
41#endif
42};
43
44#define GPIO_LINE_DIRECTION_IN 1
45#define GPIO_LINE_DIRECTION_OUT 0
46
47/**
48 * struct gpio_irq_chip - GPIO interrupt controller
49 */
50struct gpio_irq_chip {
51 /**
52 * @chip:
53 *
54 * GPIO IRQ chip implementation, provided by GPIO driver.
55 */
56 struct irq_chip *chip;
57
58 /**
59 * @domain:
60 *
61 * Interrupt translation domain; responsible for mapping between GPIO
62 * hwirq number and Linux IRQ number.
63 */
64 struct irq_domain *domain;
65
66#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
67 /**
68 * @fwnode:
69 *
70 * Firmware node corresponding to this gpiochip/irqchip, necessary
71 * for hierarchical irqdomain support.
72 */
73 struct fwnode_handle *fwnode;
74
75 /**
76 * @parent_domain:
77 *
78 * If non-NULL, will be set as the parent of this GPIO interrupt
79 * controller's IRQ domain to establish a hierarchical interrupt
80 * domain. The presence of this will activate the hierarchical
81 * interrupt support.
82 */
83 struct irq_domain *parent_domain;
84
85 /**
86 * @child_to_parent_hwirq:
87 *
88 * This callback translates a child hardware IRQ offset to a parent
89 * hardware IRQ offset on a hierarchical interrupt chip. The child
90 * hardware IRQs correspond to the GPIO index 0..ngpio-1 (see the
91 * ngpio field of struct gpio_chip) and the corresponding parent
92 * hardware IRQ and type (such as IRQ_TYPE_*) shall be returned by
93 * the driver. The driver can calculate this from an offset or using
94 * a lookup table or whatever method is best for this chip. Return
95 * 0 on successful translation in the driver.
96 *
97 * If some ranges of hardware IRQs do not have a corresponding parent
98 * HWIRQ, return -EINVAL, but also make sure to fill in @valid_mask and
99 * @need_valid_mask to make these GPIO lines unavailable for
100 * translation.
101 */
102 int (*child_to_parent_hwirq)(struct gpio_chip *gc,
103 unsigned int child_hwirq,
104 unsigned int child_type,
105 unsigned int *parent_hwirq,
106 unsigned int *parent_type);
107
108 /**
109 * @populate_parent_alloc_arg :
110 *
111 * This optional callback allocates and populates the specific struct
112 * for the parent's IRQ domain. If this is not specified, then
113 * &gpiochip_populate_parent_fwspec_twocell will be used. A four-cell
114 * variant named &gpiochip_populate_parent_fwspec_fourcell is also
115 * available.
116 */
117 int (*populate_parent_alloc_arg)(struct gpio_chip *gc,
118 union gpio_irq_fwspec *fwspec,
119 unsigned int parent_hwirq,
120 unsigned int parent_type);
121
122 /**
123 * @child_offset_to_irq:
124 *
125 * This optional callback is used to translate the child's GPIO line
126 * offset on the GPIO chip to an IRQ number for the GPIO to_irq()
127 * callback. If this is not specified, then a default callback will be
128 * provided that returns the line offset.
129 */
130 unsigned int (*child_offset_to_irq)(struct gpio_chip *gc,
131 unsigned int pin);
132
133 /**
134 * @child_irq_domain_ops:
135 *
136 * The IRQ domain operations that will be used for this GPIO IRQ
137 * chip. If no operations are provided, then default callbacks will
138 * be populated to setup the IRQ hierarchy. Some drivers need to
139 * supply their own translate function.
140 */
141 struct irq_domain_ops child_irq_domain_ops;
142#endif
143
144 /**
145 * @handler:
146 *
147 * The IRQ handler to use (often a predefined IRQ core function) for
148 * GPIO IRQs, provided by GPIO driver.
149 */
150 irq_flow_handler_t handler;
151
152 /**
153 * @default_type:
154 *
155 * Default IRQ triggering type applied during GPIO driver
156 * initialization, provided by GPIO driver.
157 */
158 unsigned int default_type;
159
160 /**
161 * @lock_key:
162 *
163 * Per GPIO IRQ chip lockdep class for IRQ lock.
164 */
165 struct lock_class_key *lock_key;
166
167 /**
168 * @request_key:
169 *
170 * Per GPIO IRQ chip lockdep class for IRQ request.
171 */
172 struct lock_class_key *request_key;
173
174 /**
175 * @parent_handler:
176 *
177 * The interrupt handler for the GPIO chip's parent interrupts, may be
178 * NULL if the parent interrupts are nested rather than cascaded.
179 */
180 irq_flow_handler_t parent_handler;
181
182 union {
183 /**
184 * @parent_handler_data:
185 *
186 * If @per_parent_data is false, @parent_handler_data is a
187 * single pointer used as the data associated with every
188 * parent interrupt.
189 */
190 void *parent_handler_data;
191
192 /**
193 * @parent_handler_data_array:
194 *
195 * If @per_parent_data is true, @parent_handler_data_array is
196 * an array of @num_parents pointers, and is used to associate
197 * different data for each parent. This cannot be NULL if
198 * @per_parent_data is true.
199 */
200 void **parent_handler_data_array;
201 };
202
203 /**
204 * @num_parents:
205 *
206 * The number of interrupt parents of a GPIO chip.
207 */
208 unsigned int num_parents;
209
210 /**
211 * @parents:
212 *
213 * A list of interrupt parents of a GPIO chip. This is owned by the
214 * driver, so the core will only reference this list, not modify it.
215 */
216 unsigned int *parents;
217
218 /**
219 * @map:
220 *
221 * A list of interrupt parents for each line of a GPIO chip.
222 */
223 unsigned int *map;
224
225 /**
226 * @threaded:
227 *
228 * True if set the interrupt handling uses nested threads.
229 */
230 bool threaded;
231
232 /**
233 * @per_parent_data:
234 *
235 * True if parent_handler_data_array describes a @num_parents
236 * sized array to be used as parent data.
237 */
238 bool per_parent_data;
239
240 /**
241 * @initialized:
242 *
243 * Flag to track GPIO chip irq member's initialization.
244 * This flag will make sure GPIO chip irq members are not used
245 * before they are initialized.
246 */
247 bool initialized;
248
249 /**
250 * @domain_is_allocated_externally:
251 *
252 * True it the irq_domain was allocated outside of gpiolib, in which
253 * case gpiolib won't free the irq_domain itself.
254 */
255 bool domain_is_allocated_externally;
256
257 /**
258 * @init_hw: optional routine to initialize hardware before
259 * an IRQ chip will be added. This is quite useful when
260 * a particular driver wants to clear IRQ related registers
261 * in order to avoid undesired events.
262 */
263 int (*init_hw)(struct gpio_chip *gc);
264
265 /**
266 * @init_valid_mask: optional routine to initialize @valid_mask, to be
267 * used if not all GPIO lines are valid interrupts. Sometimes some
268 * lines just cannot fire interrupts, and this routine, when defined,
269 * is passed a bitmap in "valid_mask" and it will have ngpios
270 * bits from 0..(ngpios-1) set to "1" as in valid. The callback can
271 * then directly set some bits to "0" if they cannot be used for
272 * interrupts.
273 */
274 void (*init_valid_mask)(struct gpio_chip *gc,
275 unsigned long *valid_mask,
276 unsigned int ngpios);
277
278 /**
279 * @valid_mask:
280 *
281 * If not %NULL, holds bitmask of GPIOs which are valid to be included
282 * in IRQ domain of the chip.
283 */
284 unsigned long *valid_mask;
285
286 /**
287 * @first:
288 *
289 * Required for static IRQ allocation. If set, irq_domain_add_simple()
290 * will allocate and map all IRQs during initialization.
291 */
292 unsigned int first;
293
294 /**
295 * @irq_enable:
296 *
297 * Store old irq_chip irq_enable callback
298 */
299 void (*irq_enable)(struct irq_data *data);
300
301 /**
302 * @irq_disable:
303 *
304 * Store old irq_chip irq_disable callback
305 */
306 void (*irq_disable)(struct irq_data *data);
307 /**
308 * @irq_unmask:
309 *
310 * Store old irq_chip irq_unmask callback
311 */
312 void (*irq_unmask)(struct irq_data *data);
313
314 /**
315 * @irq_mask:
316 *
317 * Store old irq_chip irq_mask callback
318 */
319 void (*irq_mask)(struct irq_data *data);
320};
321
322/**
323 * struct gpio_chip - abstract a GPIO controller
324 * @label: a functional name for the GPIO device, such as a part
325 * number or the name of the SoC IP-block implementing it.
326 * @gpiodev: the internal state holder, opaque struct
327 * @parent: optional parent device providing the GPIOs
328 * @fwnode: optional fwnode providing this controller's properties
329 * @owner: helps prevent removal of modules exporting active GPIOs
330 * @request: optional hook for chip-specific activation, such as
331 * enabling module power and clock; may sleep
332 * @free: optional hook for chip-specific deactivation, such as
333 * disabling module power and clock; may sleep
334 * @get_direction: returns direction for signal "offset", 0=out, 1=in,
335 * (same as GPIO_LINE_DIRECTION_OUT / GPIO_LINE_DIRECTION_IN),
336 * or negative error. It is recommended to always implement this
337 * function, even on input-only or output-only gpio chips.
338 * @direction_input: configures signal "offset" as input, returns 0 on success
339 * or a negative error number. This can be omitted on input-only or
340 * output-only gpio chips.
341 * @direction_output: configures signal "offset" as output, returns 0 on
342 * success or a negative error number. This can be omitted on input-only
343 * or output-only gpio chips.
344 * @get: returns value for signal "offset", 0=low, 1=high, or negative error
345 * @get_multiple: reads values for multiple signals defined by "mask" and
346 * stores them in "bits", returns 0 on success or negative error
347 * @set: assigns output value for signal "offset"
348 * @set_multiple: assigns output values for multiple signals defined by "mask"
349 * @set_config: optional hook for all kinds of settings. Uses the same
350 * packed config format as generic pinconf.
351 * @to_irq: optional hook supporting non-static gpiod_to_irq() mappings;
352 * implementation may not sleep
353 * @dbg_show: optional routine to show contents in debugfs; default code
354 * will be used when this is omitted, but custom code can show extra
355 * state (such as pullup/pulldown configuration).
356 * @init_valid_mask: optional routine to initialize @valid_mask, to be used if
357 * not all GPIOs are valid.
358 * @add_pin_ranges: optional routine to initialize pin ranges, to be used when
359 * requires special mapping of the pins that provides GPIO functionality.
360 * It is called after adding GPIO chip and before adding IRQ chip.
361 * @en_hw_timestamp: Dependent on GPIO chip, an optional routine to
362 * enable hardware timestamp.
363 * @dis_hw_timestamp: Dependent on GPIO chip, an optional routine to
364 * disable hardware timestamp.
365 * @base: identifies the first GPIO number handled by this chip;
366 * or, if negative during registration, requests dynamic ID allocation.
367 * DEPRECATION: providing anything non-negative and nailing the base
368 * offset of GPIO chips is deprecated. Please pass -1 as base to
369 * let gpiolib select the chip base in all possible cases. We want to
370 * get rid of the static GPIO number space in the long run.
371 * @ngpio: the number of GPIOs handled by this controller; the last GPIO
372 * handled is (base + ngpio - 1).
373 * @offset: when multiple gpio chips belong to the same device this
374 * can be used as offset within the device so friendly names can
375 * be properly assigned.
376 * @names: if set, must be an array of strings to use as alternative
377 * names for the GPIOs in this chip. Any entry in the array
378 * may be NULL if there is no alias for the GPIO, however the
379 * array must be @ngpio entries long. A name can include a single printk
380 * format specifier for an unsigned int. It is substituted by the actual
381 * number of the gpio.
382 * @can_sleep: flag must be set iff get()/set() methods sleep, as they
383 * must while accessing GPIO expander chips over I2C or SPI. This
384 * implies that if the chip supports IRQs, these IRQs need to be threaded
385 * as the chip access may sleep when e.g. reading out the IRQ status
386 * registers.
387 * @read_reg: reader function for generic GPIO
388 * @write_reg: writer function for generic GPIO
389 * @be_bits: if the generic GPIO has big endian bit order (bit 31 is representing
390 * line 0, bit 30 is line 1 ... bit 0 is line 31) this is set to true by the
391 * generic GPIO core. It is for internal housekeeping only.
392 * @reg_dat: data (in) register for generic GPIO
393 * @reg_set: output set register (out=high) for generic GPIO
394 * @reg_clr: output clear register (out=low) for generic GPIO
395 * @reg_dir_out: direction out setting register for generic GPIO
396 * @reg_dir_in: direction in setting register for generic GPIO
397 * @bgpio_dir_unreadable: indicates that the direction register(s) cannot
398 * be read and we need to rely on out internal state tracking.
399 * @bgpio_bits: number of register bits used for a generic GPIO i.e.
400 * <register width> * 8
401 * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep
402 * shadowed and real data registers writes together.
403 * @bgpio_data: shadowed data register for generic GPIO to clear/set bits
404 * safely.
405 * @bgpio_dir: shadowed direction register for generic GPIO to clear/set
406 * direction safely. A "1" in this word means the line is set as
407 * output.
408 *
409 * A gpio_chip can help platforms abstract various sources of GPIOs so
410 * they can all be accessed through a common programming interface.
411 * Example sources would be SOC controllers, FPGAs, multifunction
412 * chips, dedicated GPIO expanders, and so on.
413 *
414 * Each chip controls a number of signals, identified in method calls
415 * by "offset" values in the range 0..(@ngpio - 1). When those signals
416 * are referenced through calls like gpio_get_value(gpio), the offset
417 * is calculated by subtracting @base from the gpio number.
418 */
419struct gpio_chip {
420 const char *label;
421 struct gpio_device *gpiodev;
422 struct device *parent;
423 struct fwnode_handle *fwnode;
424 struct module *owner;
425
426 int (*request)(struct gpio_chip *gc,
427 unsigned int offset);
428 void (*free)(struct gpio_chip *gc,
429 unsigned int offset);
430 int (*get_direction)(struct gpio_chip *gc,
431 unsigned int offset);
432 int (*direction_input)(struct gpio_chip *gc,
433 unsigned int offset);
434 int (*direction_output)(struct gpio_chip *gc,
435 unsigned int offset, int value);
436 int (*get)(struct gpio_chip *gc,
437 unsigned int offset);
438 int (*get_multiple)(struct gpio_chip *gc,
439 unsigned long *mask,
440 unsigned long *bits);
441 void (*set)(struct gpio_chip *gc,
442 unsigned int offset, int value);
443 void (*set_multiple)(struct gpio_chip *gc,
444 unsigned long *mask,
445 unsigned long *bits);
446 int (*set_config)(struct gpio_chip *gc,
447 unsigned int offset,
448 unsigned long config);
449 int (*to_irq)(struct gpio_chip *gc,
450 unsigned int offset);
451
452 void (*dbg_show)(struct seq_file *s,
453 struct gpio_chip *gc);
454
455 int (*init_valid_mask)(struct gpio_chip *gc,
456 unsigned long *valid_mask,
457 unsigned int ngpios);
458
459 int (*add_pin_ranges)(struct gpio_chip *gc);
460
461 int (*en_hw_timestamp)(struct gpio_chip *gc,
462 u32 offset,
463 unsigned long flags);
464 int (*dis_hw_timestamp)(struct gpio_chip *gc,
465 u32 offset,
466 unsigned long flags);
467 int base;
468 u16 ngpio;
469 u16 offset;
470 const char *const *names;
471 bool can_sleep;
472
473#if IS_ENABLED(CONFIG_GPIO_GENERIC)
474 unsigned long (*read_reg)(void __iomem *reg);
475 void (*write_reg)(void __iomem *reg, unsigned long data);
476 bool be_bits;
477 void __iomem *reg_dat;
478 void __iomem *reg_set;
479 void __iomem *reg_clr;
480 void __iomem *reg_dir_out;
481 void __iomem *reg_dir_in;
482 bool bgpio_dir_unreadable;
483 int bgpio_bits;
484 raw_spinlock_t bgpio_lock;
485 unsigned long bgpio_data;
486 unsigned long bgpio_dir;
487#endif /* CONFIG_GPIO_GENERIC */
488
489#ifdef CONFIG_GPIOLIB_IRQCHIP
490 /*
491 * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
492 * to handle IRQs for most practical cases.
493 */
494
495 /**
496 * @irq:
497 *
498 * Integrates interrupt chip functionality with the GPIO chip. Can be
499 * used to handle IRQs for most practical cases.
500 */
501 struct gpio_irq_chip irq;
502#endif /* CONFIG_GPIOLIB_IRQCHIP */
503
504 /**
505 * @valid_mask:
506 *
507 * If not %NULL, holds bitmask of GPIOs which are valid to be used
508 * from the chip.
509 */
510 unsigned long *valid_mask;
511
512#if defined(CONFIG_OF_GPIO)
513 /*
514 * If CONFIG_OF_GPIO is enabled, then all GPIO controllers described in
515 * the device tree automatically may have an OF translation
516 */
517
518 /**
519 * @of_gpio_n_cells:
520 *
521 * Number of cells used to form the GPIO specifier.
522 */
523 unsigned int of_gpio_n_cells;
524
525 /**
526 * @of_xlate:
527 *
528 * Callback to translate a device tree GPIO specifier into a chip-
529 * relative GPIO number and flags.
530 */
531 int (*of_xlate)(struct gpio_chip *gc,
532 const struct of_phandle_args *gpiospec, u32 *flags);
533#endif /* CONFIG_OF_GPIO */
534};
535
536char *gpiochip_dup_line_label(struct gpio_chip *gc, unsigned int offset);
537
538
539struct _gpiochip_for_each_data {
540 const char **label;
541 unsigned int *i;
542};
543
544DEFINE_CLASS(_gpiochip_for_each_data,
545 struct _gpiochip_for_each_data,
546 if (*_T.label) kfree(*_T.label),
547 ({
548 struct _gpiochip_for_each_data _data = { label, i };
549 *_data.i = 0;
550 _data;
551 }),
552 const char **label, int *i)
553
554/**
555 * for_each_hwgpio - Iterates over all GPIOs for given chip.
556 * @_chip: Chip to iterate over.
557 * @_i: Loop counter.
558 * @_label: Place to store the address of the label if the GPIO is requested.
559 * Set to NULL for unused GPIOs.
560 */
561#define for_each_hwgpio(_chip, _i, _label) \
562 for (CLASS(_gpiochip_for_each_data, _data)(&_label, &_i); \
563 *_data.i < _chip->ngpio; \
564 (*_data.i)++, kfree(*(_data.label)), *_data.label = NULL) \
565 if (IS_ERR(*_data.label = \
566 gpiochip_dup_line_label(_chip, *_data.i))) {} \
567 else
568
569/**
570 * for_each_requested_gpio_in_range - iterates over requested GPIOs in a given range
571 * @_chip: the chip to query
572 * @_i: loop variable
573 * @_base: first GPIO in the range
574 * @_size: amount of GPIOs to check starting from @base
575 * @_label: label of current GPIO
576 */
577#define for_each_requested_gpio_in_range(_chip, _i, _base, _size, _label) \
578 for (CLASS(_gpiochip_for_each_data, _data)(&_label, &_i); \
579 *_data.i < _size; \
580 (*_data.i)++, kfree(*(_data.label)), *_data.label = NULL) \
581 if ((*_data.label = \
582 gpiochip_dup_line_label(_chip, _base + *_data.i)) == NULL) {} \
583 else if (IS_ERR(*_data.label)) {} \
584 else
585
586/* Iterates over all requested GPIO of the given @chip */
587#define for_each_requested_gpio(chip, i, label) \
588 for_each_requested_gpio_in_range(chip, i, 0, chip->ngpio, label)
589
590/* add/remove chips */
591int gpiochip_add_data_with_key(struct gpio_chip *gc, void *data,
592 struct lock_class_key *lock_key,
593 struct lock_class_key *request_key);
594
595/**
596 * gpiochip_add_data() - register a gpio_chip
597 * @gc: the chip to register, with gc->base initialized
598 * @data: driver-private data associated with this chip
599 *
600 * Context: potentially before irqs will work
601 *
602 * When gpiochip_add_data() is called very early during boot, so that GPIOs
603 * can be freely used, the gc->parent device must be registered before
604 * the gpio framework's arch_initcall(). Otherwise sysfs initialization
605 * for GPIOs will fail rudely.
606 *
607 * gpiochip_add_data() must only be called after gpiolib initialization,
608 * i.e. after core_initcall().
609 *
610 * If gc->base is negative, this requests dynamic assignment of
611 * a range of valid GPIOs.
612 *
613 * Returns:
614 * A negative errno if the chip can't be registered, such as because the
615 * gc->base is invalid or already associated with a different chip.
616 * Otherwise it returns zero as a success code.
617 */
618#ifdef CONFIG_LOCKDEP
619#define gpiochip_add_data(gc, data) ({ \
620 static struct lock_class_key lock_key; \
621 static struct lock_class_key request_key; \
622 gpiochip_add_data_with_key(gc, data, &lock_key, \
623 &request_key); \
624 })
625#define devm_gpiochip_add_data(dev, gc, data) ({ \
626 static struct lock_class_key lock_key; \
627 static struct lock_class_key request_key; \
628 devm_gpiochip_add_data_with_key(dev, gc, data, &lock_key, \
629 &request_key); \
630 })
631#else
632#define gpiochip_add_data(gc, data) gpiochip_add_data_with_key(gc, data, NULL, NULL)
633#define devm_gpiochip_add_data(dev, gc, data) \
634 devm_gpiochip_add_data_with_key(dev, gc, data, NULL, NULL)
635#endif /* CONFIG_LOCKDEP */
636
637static inline int gpiochip_add(struct gpio_chip *gc)
638{
639 return gpiochip_add_data(gc, NULL);
640}
641void gpiochip_remove(struct gpio_chip *gc);
642int devm_gpiochip_add_data_with_key(struct device *dev, struct gpio_chip *gc,
643 void *data, struct lock_class_key *lock_key,
644 struct lock_class_key *request_key);
645
646struct gpio_device *gpio_device_find(const void *data,
647 int (*match)(struct gpio_chip *gc,
648 const void *data));
649
650struct gpio_device *gpio_device_get(struct gpio_device *gdev);
651void gpio_device_put(struct gpio_device *gdev);
652
653DEFINE_FREE(gpio_device_put, struct gpio_device *,
654 if (!IS_ERR_OR_NULL(_T)) gpio_device_put(_T))
655
656struct device *gpio_device_to_device(struct gpio_device *gdev);
657
658bool gpiochip_line_is_irq(struct gpio_chip *gc, unsigned int offset);
659int gpiochip_reqres_irq(struct gpio_chip *gc, unsigned int offset);
660void gpiochip_relres_irq(struct gpio_chip *gc, unsigned int offset);
661void gpiochip_disable_irq(struct gpio_chip *gc, unsigned int offset);
662void gpiochip_enable_irq(struct gpio_chip *gc, unsigned int offset);
663
664/* irq_data versions of the above */
665int gpiochip_irq_reqres(struct irq_data *data);
666void gpiochip_irq_relres(struct irq_data *data);
667
668/* Paste this in your irq_chip structure */
669#define GPIOCHIP_IRQ_RESOURCE_HELPERS \
670 .irq_request_resources = gpiochip_irq_reqres, \
671 .irq_release_resources = gpiochip_irq_relres
672
673static inline void gpio_irq_chip_set_chip(struct gpio_irq_chip *girq,
674 const struct irq_chip *chip)
675{
676 /* Yes, dropping const is ugly, but it isn't like we have a choice */
677 girq->chip = (struct irq_chip *)chip;
678}
679
680/* Line status inquiry for drivers */
681bool gpiochip_line_is_open_drain(struct gpio_chip *gc, unsigned int offset);
682bool gpiochip_line_is_open_source(struct gpio_chip *gc, unsigned int offset);
683
684/* Sleep persistence inquiry for drivers */
685bool gpiochip_line_is_persistent(struct gpio_chip *gc, unsigned int offset);
686bool gpiochip_line_is_valid(const struct gpio_chip *gc, unsigned int offset);
687
688/* get driver data */
689void *gpiochip_get_data(struct gpio_chip *gc);
690
691struct bgpio_pdata {
692 const char *label;
693 int base;
694 int ngpio;
695};
696
697#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
698
699int gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *gc,
700 union gpio_irq_fwspec *gfwspec,
701 unsigned int parent_hwirq,
702 unsigned int parent_type);
703int gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *gc,
704 union gpio_irq_fwspec *gfwspec,
705 unsigned int parent_hwirq,
706 unsigned int parent_type);
707
708#endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */
709
710int bgpio_init(struct gpio_chip *gc, struct device *dev,
711 unsigned long sz, void __iomem *dat, void __iomem *set,
712 void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
713 unsigned long flags);
714
715#define BGPIOF_BIG_ENDIAN BIT(0)
716#define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */
717#define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */
718#define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3)
719#define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */
720#define BGPIOF_NO_OUTPUT BIT(5) /* only input */
721#define BGPIOF_NO_SET_ON_INPUT BIT(6)
722
723#ifdef CONFIG_GPIOLIB_IRQCHIP
724int gpiochip_irqchip_add_domain(struct gpio_chip *gc,
725 struct irq_domain *domain);
726#else
727
728#include <asm/bug.h>
729
730static inline int gpiochip_irqchip_add_domain(struct gpio_chip *gc,
731 struct irq_domain *domain)
732{
733 WARN_ON(1);
734 return -EINVAL;
735}
736#endif
737
738int gpiochip_generic_request(struct gpio_chip *gc, unsigned int offset);
739void gpiochip_generic_free(struct gpio_chip *gc, unsigned int offset);
740int gpiochip_generic_config(struct gpio_chip *gc, unsigned int offset,
741 unsigned long config);
742
743/**
744 * struct gpio_pin_range - pin range controlled by a gpio chip
745 * @node: list for maintaining set of pin ranges, used internally
746 * @pctldev: pinctrl device which handles corresponding pins
747 * @range: actual range of pins controlled by a gpio controller
748 */
749struct gpio_pin_range {
750 struct list_head node;
751 struct pinctrl_dev *pctldev;
752 struct pinctrl_gpio_range range;
753};
754
755#ifdef CONFIG_PINCTRL
756
757int gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name,
758 unsigned int gpio_offset, unsigned int pin_offset,
759 unsigned int npins);
760int gpiochip_add_pingroup_range(struct gpio_chip *gc,
761 struct pinctrl_dev *pctldev,
762 unsigned int gpio_offset, const char *pin_group);
763void gpiochip_remove_pin_ranges(struct gpio_chip *gc);
764
765#else /* ! CONFIG_PINCTRL */
766
767static inline int
768gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name,
769 unsigned int gpio_offset, unsigned int pin_offset,
770 unsigned int npins)
771{
772 return 0;
773}
774static inline int
775gpiochip_add_pingroup_range(struct gpio_chip *gc,
776 struct pinctrl_dev *pctldev,
777 unsigned int gpio_offset, const char *pin_group)
778{
779 return 0;
780}
781
782static inline void
783gpiochip_remove_pin_ranges(struct gpio_chip *gc)
784{
785}
786
787#endif /* CONFIG_PINCTRL */
788
789struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *gc,
790 unsigned int hwnum,
791 const char *label,
792 enum gpio_lookup_flags lflags,
793 enum gpiod_flags dflags);
794void gpiochip_free_own_desc(struct gpio_desc *desc);
795
796struct gpio_desc *gpiochip_get_desc(struct gpio_chip *gc, unsigned int hwnum);
797struct gpio_desc *
798gpio_device_get_desc(struct gpio_device *gdev, unsigned int hwnum);
799
800struct gpio_chip *gpio_device_get_chip(struct gpio_device *gdev);
801
802#ifdef CONFIG_GPIOLIB
803
804/* lock/unlock as IRQ */
805int gpiochip_lock_as_irq(struct gpio_chip *gc, unsigned int offset);
806void gpiochip_unlock_as_irq(struct gpio_chip *gc, unsigned int offset);
807
808struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc);
809struct gpio_device *gpiod_to_gpio_device(struct gpio_desc *desc);
810
811/* struct gpio_device getters */
812int gpio_device_get_base(struct gpio_device *gdev);
813const char *gpio_device_get_label(struct gpio_device *gdev);
814
815struct gpio_device *gpio_device_find_by_label(const char *label);
816struct gpio_device *gpio_device_find_by_fwnode(const struct fwnode_handle *fwnode);
817
818#else /* CONFIG_GPIOLIB */
819
820#include <asm/bug.h>
821
822static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc)
823{
824 /* GPIO can never have been requested */
825 WARN_ON(1);
826 return ERR_PTR(-ENODEV);
827}
828
829static inline struct gpio_device *gpiod_to_gpio_device(struct gpio_desc *desc)
830{
831 WARN_ON(1);
832 return ERR_PTR(-ENODEV);
833}
834
835static inline int gpio_device_get_base(struct gpio_device *gdev)
836{
837 WARN_ON(1);
838 return -ENODEV;
839}
840
841static inline const char *gpio_device_get_label(struct gpio_device *gdev)
842{
843 WARN_ON(1);
844 return NULL;
845}
846
847static inline struct gpio_device *gpio_device_find_by_label(const char *label)
848{
849 WARN_ON(1);
850 return NULL;
851}
852
853static inline struct gpio_device *gpio_device_find_by_fwnode(const struct fwnode_handle *fwnode)
854{
855 WARN_ON(1);
856 return NULL;
857}
858
859static inline int gpiochip_lock_as_irq(struct gpio_chip *gc,
860 unsigned int offset)
861{
862 WARN_ON(1);
863 return -EINVAL;
864}
865
866static inline void gpiochip_unlock_as_irq(struct gpio_chip *gc,
867 unsigned int offset)
868{
869 WARN_ON(1);
870}
871#endif /* CONFIG_GPIOLIB */
872
873#define for_each_gpiochip_node(dev, child) \
874 device_for_each_child_node(dev, child) \
875 if (!fwnode_property_present(child, "gpio-controller")) {} else
876
877static inline unsigned int gpiochip_node_count(struct device *dev)
878{
879 struct fwnode_handle *child;
880 unsigned int count = 0;
881
882 for_each_gpiochip_node(dev, child)
883 count++;
884
885 return count;
886}
887
888static inline struct fwnode_handle *gpiochip_node_get_first(struct device *dev)
889{
890 struct fwnode_handle *fwnode;
891
892 for_each_gpiochip_node(dev, fwnode)
893 return fwnode;
894
895 return NULL;
896}
897
898#endif /* __LINUX_GPIO_DRIVER_H */