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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2014 Bart Tanghe <bart.tanghe@thomasmore.be>
4 */
5
6#include <linux/clk.h>
7#include <linux/err.h>
8#include <linux/io.h>
9#include <linux/module.h>
10#include <linux/of.h>
11#include <linux/platform_device.h>
12#include <linux/pwm.h>
13
14#define PWM_CONTROL 0x000
15#define PWM_CONTROL_SHIFT(x) ((x) * 8)
16#define PWM_CONTROL_MASK 0xff
17#define PWM_MODE 0x80 /* set timer in PWM mode */
18#define PWM_ENABLE (1 << 0)
19#define PWM_POLARITY (1 << 4)
20
21#define PERIOD(x) (((x) * 0x10) + 0x10)
22#define DUTY(x) (((x) * 0x10) + 0x14)
23
24#define PERIOD_MIN 0x2
25
26struct bcm2835_pwm {
27 struct pwm_chip chip;
28 struct device *dev;
29 void __iomem *base;
30 struct clk *clk;
31};
32
33static inline struct bcm2835_pwm *to_bcm2835_pwm(struct pwm_chip *chip)
34{
35 return container_of(chip, struct bcm2835_pwm, chip);
36}
37
38static int bcm2835_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
39{
40 struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
41 u32 value;
42
43 value = readl(pc->base + PWM_CONTROL);
44 value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm));
45 value |= (PWM_MODE << PWM_CONTROL_SHIFT(pwm->hwpwm));
46 writel(value, pc->base + PWM_CONTROL);
47
48 return 0;
49}
50
51static void bcm2835_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
52{
53 struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
54 u32 value;
55
56 value = readl(pc->base + PWM_CONTROL);
57 value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm));
58 writel(value, pc->base + PWM_CONTROL);
59}
60
61static int bcm2835_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
62 int duty_ns, int period_ns)
63{
64 struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
65 unsigned long rate = clk_get_rate(pc->clk);
66 unsigned long scaler;
67 u32 period;
68
69 if (!rate) {
70 dev_err(pc->dev, "failed to get clock rate\n");
71 return -EINVAL;
72 }
73
74 scaler = DIV_ROUND_CLOSEST(NSEC_PER_SEC, rate);
75 period = DIV_ROUND_CLOSEST(period_ns, scaler);
76
77 if (period < PERIOD_MIN)
78 return -EINVAL;
79
80 writel(DIV_ROUND_CLOSEST(duty_ns, scaler),
81 pc->base + DUTY(pwm->hwpwm));
82 writel(period, pc->base + PERIOD(pwm->hwpwm));
83
84 return 0;
85}
86
87static int bcm2835_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
88{
89 struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
90 u32 value;
91
92 value = readl(pc->base + PWM_CONTROL);
93 value |= PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm);
94 writel(value, pc->base + PWM_CONTROL);
95
96 return 0;
97}
98
99static void bcm2835_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
100{
101 struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
102 u32 value;
103
104 value = readl(pc->base + PWM_CONTROL);
105 value &= ~(PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm));
106 writel(value, pc->base + PWM_CONTROL);
107}
108
109static int bcm2835_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
110 enum pwm_polarity polarity)
111{
112 struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
113 u32 value;
114
115 value = readl(pc->base + PWM_CONTROL);
116
117 if (polarity == PWM_POLARITY_NORMAL)
118 value &= ~(PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm));
119 else
120 value |= PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm);
121
122 writel(value, pc->base + PWM_CONTROL);
123
124 return 0;
125}
126
127static const struct pwm_ops bcm2835_pwm_ops = {
128 .request = bcm2835_pwm_request,
129 .free = bcm2835_pwm_free,
130 .config = bcm2835_pwm_config,
131 .enable = bcm2835_pwm_enable,
132 .disable = bcm2835_pwm_disable,
133 .set_polarity = bcm2835_set_polarity,
134 .owner = THIS_MODULE,
135};
136
137static int bcm2835_pwm_probe(struct platform_device *pdev)
138{
139 struct bcm2835_pwm *pc;
140 struct resource *res;
141 int ret;
142
143 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
144 if (!pc)
145 return -ENOMEM;
146
147 pc->dev = &pdev->dev;
148
149 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
150 pc->base = devm_ioremap_resource(&pdev->dev, res);
151 if (IS_ERR(pc->base))
152 return PTR_ERR(pc->base);
153
154 pc->clk = devm_clk_get(&pdev->dev, NULL);
155 if (IS_ERR(pc->clk)) {
156 ret = PTR_ERR(pc->clk);
157 if (ret != -EPROBE_DEFER)
158 dev_err(&pdev->dev, "clock not found: %d\n", ret);
159
160 return ret;
161 }
162
163 ret = clk_prepare_enable(pc->clk);
164 if (ret)
165 return ret;
166
167 pc->chip.dev = &pdev->dev;
168 pc->chip.ops = &bcm2835_pwm_ops;
169 pc->chip.base = -1;
170 pc->chip.npwm = 2;
171 pc->chip.of_xlate = of_pwm_xlate_with_flags;
172 pc->chip.of_pwm_n_cells = 3;
173
174 platform_set_drvdata(pdev, pc);
175
176 ret = pwmchip_add(&pc->chip);
177 if (ret < 0)
178 goto add_fail;
179
180 return 0;
181
182add_fail:
183 clk_disable_unprepare(pc->clk);
184 return ret;
185}
186
187static int bcm2835_pwm_remove(struct platform_device *pdev)
188{
189 struct bcm2835_pwm *pc = platform_get_drvdata(pdev);
190
191 clk_disable_unprepare(pc->clk);
192
193 return pwmchip_remove(&pc->chip);
194}
195
196static const struct of_device_id bcm2835_pwm_of_match[] = {
197 { .compatible = "brcm,bcm2835-pwm", },
198 { /* sentinel */ }
199};
200MODULE_DEVICE_TABLE(of, bcm2835_pwm_of_match);
201
202static struct platform_driver bcm2835_pwm_driver = {
203 .driver = {
204 .name = "bcm2835-pwm",
205 .of_match_table = bcm2835_pwm_of_match,
206 },
207 .probe = bcm2835_pwm_probe,
208 .remove = bcm2835_pwm_remove,
209};
210module_platform_driver(bcm2835_pwm_driver);
211
212MODULE_AUTHOR("Bart Tanghe <bart.tanghe@thomasmore.be>");
213MODULE_DESCRIPTION("Broadcom BCM2835 PWM driver");
214MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2014 Bart Tanghe <bart.tanghe@thomasmore.be>
4 */
5
6#include <linux/clk.h>
7#include <linux/err.h>
8#include <linux/io.h>
9#include <linux/module.h>
10#include <linux/of.h>
11#include <linux/platform_device.h>
12#include <linux/pwm.h>
13
14#define PWM_CONTROL 0x000
15#define PWM_CONTROL_SHIFT(x) ((x) * 8)
16#define PWM_CONTROL_MASK 0xff
17#define PWM_MODE 0x80 /* set timer in PWM mode */
18#define PWM_ENABLE (1 << 0)
19#define PWM_POLARITY (1 << 4)
20
21#define PERIOD(x) (((x) * 0x10) + 0x10)
22#define DUTY(x) (((x) * 0x10) + 0x14)
23
24#define PERIOD_MIN 0x2
25
26struct bcm2835_pwm {
27 void __iomem *base;
28 struct clk *clk;
29 unsigned long rate;
30};
31
32static inline struct bcm2835_pwm *to_bcm2835_pwm(struct pwm_chip *chip)
33{
34 return pwmchip_get_drvdata(chip);
35}
36
37static int bcm2835_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
38{
39 struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
40 u32 value;
41
42 value = readl(pc->base + PWM_CONTROL);
43 value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm));
44 value |= (PWM_MODE << PWM_CONTROL_SHIFT(pwm->hwpwm));
45 writel(value, pc->base + PWM_CONTROL);
46
47 return 0;
48}
49
50static void bcm2835_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
51{
52 struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
53 u32 value;
54
55 value = readl(pc->base + PWM_CONTROL);
56 value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm));
57 writel(value, pc->base + PWM_CONTROL);
58}
59
60static int bcm2835_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
61 const struct pwm_state *state)
62{
63
64 struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
65 unsigned long long period_cycles;
66 u64 max_period;
67
68 u32 val;
69
70 /*
71 * period_cycles must be a 32 bit value, so period * rate / NSEC_PER_SEC
72 * must be <= U32_MAX. As U32_MAX * NSEC_PER_SEC < U64_MAX the
73 * multiplication period * rate doesn't overflow.
74 * To calculate the maximal possible period that guarantees the
75 * above inequality:
76 *
77 * round(period * rate / NSEC_PER_SEC) <= U32_MAX
78 * <=> period * rate / NSEC_PER_SEC < U32_MAX + 0.5
79 * <=> period * rate < (U32_MAX + 0.5) * NSEC_PER_SEC
80 * <=> period < ((U32_MAX + 0.5) * NSEC_PER_SEC) / rate
81 * <=> period < ((U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC/2) / rate
82 * <=> period <= ceil((U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC/2) / rate) - 1
83 */
84 max_period = DIV_ROUND_UP_ULL((u64)U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC / 2, pc->rate) - 1;
85
86 if (state->period > max_period)
87 return -EINVAL;
88
89 /* set period */
90 period_cycles = DIV_ROUND_CLOSEST_ULL(state->period * pc->rate, NSEC_PER_SEC);
91
92 /* don't accept a period that is too small */
93 if (period_cycles < PERIOD_MIN)
94 return -EINVAL;
95
96 writel(period_cycles, pc->base + PERIOD(pwm->hwpwm));
97
98 /* set duty cycle */
99 val = DIV_ROUND_CLOSEST_ULL(state->duty_cycle * pc->rate, NSEC_PER_SEC);
100 writel(val, pc->base + DUTY(pwm->hwpwm));
101
102 /* set polarity */
103 val = readl(pc->base + PWM_CONTROL);
104
105 if (state->polarity == PWM_POLARITY_NORMAL)
106 val &= ~(PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm));
107 else
108 val |= PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm);
109
110 /* enable/disable */
111 if (state->enabled)
112 val |= PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm);
113 else
114 val &= ~(PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm));
115
116 writel(val, pc->base + PWM_CONTROL);
117
118 return 0;
119}
120
121static const struct pwm_ops bcm2835_pwm_ops = {
122 .request = bcm2835_pwm_request,
123 .free = bcm2835_pwm_free,
124 .apply = bcm2835_pwm_apply,
125};
126
127static void devm_clk_rate_exclusive_put(void *data)
128{
129 struct clk *clk = data;
130
131 clk_rate_exclusive_put(clk);
132}
133
134static int bcm2835_pwm_probe(struct platform_device *pdev)
135{
136 struct pwm_chip *chip;
137 struct bcm2835_pwm *pc;
138 int ret;
139
140 chip = devm_pwmchip_alloc(&pdev->dev, 2, sizeof(*pc));
141 if (IS_ERR(chip))
142 return PTR_ERR(chip);
143 pc = to_bcm2835_pwm(chip);
144
145 pc->base = devm_platform_ioremap_resource(pdev, 0);
146 if (IS_ERR(pc->base))
147 return PTR_ERR(pc->base);
148
149 pc->clk = devm_clk_get_enabled(&pdev->dev, NULL);
150 if (IS_ERR(pc->clk))
151 return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk),
152 "clock not found\n");
153
154 ret = clk_rate_exclusive_get(pc->clk);
155 if (ret)
156 return dev_err_probe(&pdev->dev, ret,
157 "fail to get exclusive rate\n");
158
159 ret = devm_add_action_or_reset(&pdev->dev, devm_clk_rate_exclusive_put,
160 pc->clk);
161 if (ret)
162 return ret;
163
164 pc->rate = clk_get_rate(pc->clk);
165 if (!pc->rate)
166 return dev_err_probe(&pdev->dev, -EINVAL,
167 "failed to get clock rate\n");
168
169 chip->ops = &bcm2835_pwm_ops;
170 chip->atomic = true;
171
172 platform_set_drvdata(pdev, pc);
173
174 ret = devm_pwmchip_add(&pdev->dev, chip);
175 if (ret < 0)
176 return dev_err_probe(&pdev->dev, ret,
177 "failed to add pwmchip\n");
178
179 return 0;
180}
181
182static int bcm2835_pwm_suspend(struct device *dev)
183{
184 struct bcm2835_pwm *pc = dev_get_drvdata(dev);
185
186 clk_disable_unprepare(pc->clk);
187
188 return 0;
189}
190
191static int bcm2835_pwm_resume(struct device *dev)
192{
193 struct bcm2835_pwm *pc = dev_get_drvdata(dev);
194
195 return clk_prepare_enable(pc->clk);
196}
197
198static DEFINE_SIMPLE_DEV_PM_OPS(bcm2835_pwm_pm_ops, bcm2835_pwm_suspend,
199 bcm2835_pwm_resume);
200
201static const struct of_device_id bcm2835_pwm_of_match[] = {
202 { .compatible = "brcm,bcm2835-pwm", },
203 { /* sentinel */ }
204};
205MODULE_DEVICE_TABLE(of, bcm2835_pwm_of_match);
206
207static struct platform_driver bcm2835_pwm_driver = {
208 .driver = {
209 .name = "bcm2835-pwm",
210 .of_match_table = bcm2835_pwm_of_match,
211 .pm = pm_ptr(&bcm2835_pwm_pm_ops),
212 },
213 .probe = bcm2835_pwm_probe,
214};
215module_platform_driver(bcm2835_pwm_driver);
216
217MODULE_AUTHOR("Bart Tanghe <bart.tanghe@thomasmore.be>");
218MODULE_DESCRIPTION("Broadcom BCM2835 PWM driver");
219MODULE_LICENSE("GPL v2");