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1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef DRIVERS_PCI_H
3#define DRIVERS_PCI_H
4
5#include <linux/pci.h>
6
7/* Number of possible devfns: 0.0 to 1f.7 inclusive */
8#define MAX_NR_DEVFNS 256
9
10#define PCI_FIND_CAP_TTL 48
11
12#define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */
13
14extern const unsigned char pcie_link_speed[];
15extern bool pci_early_dump;
16
17bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
18bool pcie_cap_has_rtctl(const struct pci_dev *dev);
19
20/* Functions internal to the PCI core code */
21
22int pci_create_sysfs_dev_files(struct pci_dev *pdev);
23void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
24#if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
25static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
26{ return; }
27static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
28{ return; }
29#else
30void pci_create_firmware_label_files(struct pci_dev *pdev);
31void pci_remove_firmware_label_files(struct pci_dev *pdev);
32#endif
33void pci_cleanup_rom(struct pci_dev *dev);
34
35enum pci_mmap_api {
36 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
37 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
38};
39int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
40 enum pci_mmap_api mmap_api);
41
42int pci_probe_reset_function(struct pci_dev *dev);
43int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
44int pci_bus_error_reset(struct pci_dev *dev);
45
46#define PCI_PM_D2_DELAY 200
47#define PCI_PM_D3_WAIT 10
48#define PCI_PM_D3COLD_WAIT 100
49#define PCI_PM_BUS_WAIT 50
50
51/**
52 * struct pci_platform_pm_ops - Firmware PM callbacks
53 *
54 * @bridge_d3: Does the bridge allow entering into D3
55 *
56 * @is_manageable: returns 'true' if given device is power manageable by the
57 * platform firmware
58 *
59 * @set_state: invokes the platform firmware to set the device's power state
60 *
61 * @get_state: queries the platform firmware for a device's current power state
62 *
63 * @refresh_state: asks the platform to refresh the device's power state data
64 *
65 * @choose_state: returns PCI power state of given device preferred by the
66 * platform; to be used during system-wide transitions from a
67 * sleeping state to the working state and vice versa
68 *
69 * @set_wakeup: enables/disables wakeup capability for the device
70 *
71 * @need_resume: returns 'true' if the given device (which is currently
72 * suspended) needs to be resumed to be configured for system
73 * wakeup.
74 *
75 * If given platform is generally capable of power managing PCI devices, all of
76 * these callbacks are mandatory.
77 */
78struct pci_platform_pm_ops {
79 bool (*bridge_d3)(struct pci_dev *dev);
80 bool (*is_manageable)(struct pci_dev *dev);
81 int (*set_state)(struct pci_dev *dev, pci_power_t state);
82 pci_power_t (*get_state)(struct pci_dev *dev);
83 void (*refresh_state)(struct pci_dev *dev);
84 pci_power_t (*choose_state)(struct pci_dev *dev);
85 int (*set_wakeup)(struct pci_dev *dev, bool enable);
86 bool (*need_resume)(struct pci_dev *dev);
87};
88
89int pci_set_platform_pm(const struct pci_platform_pm_ops *ops);
90void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
91void pci_refresh_power_state(struct pci_dev *dev);
92int pci_power_up(struct pci_dev *dev);
93void pci_disable_enabled_device(struct pci_dev *dev);
94int pci_finish_runtime_suspend(struct pci_dev *dev);
95void pcie_clear_device_status(struct pci_dev *dev);
96void pcie_clear_root_pme_status(struct pci_dev *dev);
97bool pci_check_pme_status(struct pci_dev *dev);
98void pci_pme_wakeup_bus(struct pci_bus *bus);
99int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
100void pci_pme_restore(struct pci_dev *dev);
101bool pci_dev_need_resume(struct pci_dev *dev);
102void pci_dev_adjust_pme(struct pci_dev *dev);
103void pci_dev_complete_resume(struct pci_dev *pci_dev);
104void pci_config_pm_runtime_get(struct pci_dev *dev);
105void pci_config_pm_runtime_put(struct pci_dev *dev);
106void pci_pm_init(struct pci_dev *dev);
107void pci_ea_init(struct pci_dev *dev);
108void pci_allocate_cap_save_buffers(struct pci_dev *dev);
109void pci_free_cap_save_buffers(struct pci_dev *dev);
110bool pci_bridge_d3_possible(struct pci_dev *dev);
111void pci_bridge_d3_update(struct pci_dev *dev);
112void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev);
113
114static inline void pci_wakeup_event(struct pci_dev *dev)
115{
116 /* Wait 100 ms before the system can be put into a sleep state. */
117 pm_wakeup_event(&dev->dev, 100);
118}
119
120static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
121{
122 return !!(pci_dev->subordinate);
123}
124
125static inline bool pci_power_manageable(struct pci_dev *pci_dev)
126{
127 /*
128 * Currently we allow normal PCI devices and PCI bridges transition
129 * into D3 if their bridge_d3 is set.
130 */
131 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
132}
133
134static inline bool pcie_downstream_port(const struct pci_dev *dev)
135{
136 int type = pci_pcie_type(dev);
137
138 return type == PCI_EXP_TYPE_ROOT_PORT ||
139 type == PCI_EXP_TYPE_DOWNSTREAM ||
140 type == PCI_EXP_TYPE_PCIE_BRIDGE;
141}
142
143int pci_vpd_init(struct pci_dev *dev);
144void pci_vpd_release(struct pci_dev *dev);
145void pcie_vpd_create_sysfs_dev_files(struct pci_dev *dev);
146void pcie_vpd_remove_sysfs_dev_files(struct pci_dev *dev);
147
148/* PCI Virtual Channel */
149int pci_save_vc_state(struct pci_dev *dev);
150void pci_restore_vc_state(struct pci_dev *dev);
151void pci_allocate_vc_save_buffers(struct pci_dev *dev);
152
153/* PCI /proc functions */
154#ifdef CONFIG_PROC_FS
155int pci_proc_attach_device(struct pci_dev *dev);
156int pci_proc_detach_device(struct pci_dev *dev);
157int pci_proc_detach_bus(struct pci_bus *bus);
158#else
159static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
160static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
161static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
162#endif
163
164/* Functions for PCI Hotplug drivers to use */
165int pci_hp_add_bridge(struct pci_dev *dev);
166
167#ifdef HAVE_PCI_LEGACY
168void pci_create_legacy_files(struct pci_bus *bus);
169void pci_remove_legacy_files(struct pci_bus *bus);
170#else
171static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
172static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
173#endif
174
175/* Lock for read/write access to pci device and bus lists */
176extern struct rw_semaphore pci_bus_sem;
177extern struct mutex pci_slot_mutex;
178
179extern raw_spinlock_t pci_lock;
180
181extern unsigned int pci_pm_d3_delay;
182
183#ifdef CONFIG_PCI_MSI
184void pci_no_msi(void);
185#else
186static inline void pci_no_msi(void) { }
187#endif
188
189static inline void pci_msi_set_enable(struct pci_dev *dev, int enable)
190{
191 u16 control;
192
193 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
194 control &= ~PCI_MSI_FLAGS_ENABLE;
195 if (enable)
196 control |= PCI_MSI_FLAGS_ENABLE;
197 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
198}
199
200static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
201{
202 u16 ctrl;
203
204 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
205 ctrl &= ~clear;
206 ctrl |= set;
207 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
208}
209
210void pci_realloc_get_opt(char *);
211
212static inline int pci_no_d1d2(struct pci_dev *dev)
213{
214 unsigned int parent_dstates = 0;
215
216 if (dev->bus->self)
217 parent_dstates = dev->bus->self->no_d1d2;
218 return (dev->no_d1d2 || parent_dstates);
219
220}
221extern const struct attribute_group *pci_dev_groups[];
222extern const struct attribute_group *pcibus_groups[];
223extern const struct device_type pci_dev_type;
224extern const struct attribute_group *pci_bus_groups[];
225
226extern unsigned long pci_hotplug_io_size;
227extern unsigned long pci_hotplug_mmio_size;
228extern unsigned long pci_hotplug_mmio_pref_size;
229extern unsigned long pci_hotplug_bus_size;
230
231/**
232 * pci_match_one_device - Tell if a PCI device structure has a matching
233 * PCI device id structure
234 * @id: single PCI device id structure to match
235 * @dev: the PCI device structure to match against
236 *
237 * Returns the matching pci_device_id structure or %NULL if there is no match.
238 */
239static inline const struct pci_device_id *
240pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
241{
242 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
243 (id->device == PCI_ANY_ID || id->device == dev->device) &&
244 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
245 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
246 !((id->class ^ dev->class) & id->class_mask))
247 return id;
248 return NULL;
249}
250
251/* PCI slot sysfs helper code */
252#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
253
254extern struct kset *pci_slots_kset;
255
256struct pci_slot_attribute {
257 struct attribute attr;
258 ssize_t (*show)(struct pci_slot *, char *);
259 ssize_t (*store)(struct pci_slot *, const char *, size_t);
260};
261#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
262
263enum pci_bar_type {
264 pci_bar_unknown, /* Standard PCI BAR probe */
265 pci_bar_io, /* An I/O port BAR */
266 pci_bar_mem32, /* A 32-bit memory BAR */
267 pci_bar_mem64, /* A 64-bit memory BAR */
268};
269
270struct device *pci_get_host_bridge_device(struct pci_dev *dev);
271void pci_put_host_bridge_device(struct device *dev);
272
273int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
274bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
275 int crs_timeout);
276bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
277 int crs_timeout);
278int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout);
279
280int pci_setup_device(struct pci_dev *dev);
281int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
282 struct resource *res, unsigned int reg);
283void pci_configure_ari(struct pci_dev *dev);
284void __pci_bus_size_bridges(struct pci_bus *bus,
285 struct list_head *realloc_head);
286void __pci_bus_assign_resources(const struct pci_bus *bus,
287 struct list_head *realloc_head,
288 struct list_head *fail_head);
289bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
290
291void pci_reassigndev_resource_alignment(struct pci_dev *dev);
292void pci_disable_bridge_window(struct pci_dev *dev);
293struct pci_bus *pci_bus_get(struct pci_bus *bus);
294void pci_bus_put(struct pci_bus *bus);
295
296/* PCIe link information from Link Capabilities 2 */
297#define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \
298 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
299 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
300 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
301 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
302 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
303 PCI_SPEED_UNKNOWN)
304
305/* PCIe speed to Mb/s reduced by encoding overhead */
306#define PCIE_SPEED2MBS_ENC(speed) \
307 ((speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
308 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
309 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \
310 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \
311 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \
312 0)
313
314const char *pci_speed_string(enum pci_bus_speed speed);
315enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
316enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
317u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
318 enum pcie_link_width *width);
319void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
320void pcie_report_downtraining(struct pci_dev *dev);
321void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
322
323/* Single Root I/O Virtualization */
324struct pci_sriov {
325 int pos; /* Capability position */
326 int nres; /* Number of resources */
327 u32 cap; /* SR-IOV Capabilities */
328 u16 ctrl; /* SR-IOV Control */
329 u16 total_VFs; /* Total VFs associated with the PF */
330 u16 initial_VFs; /* Initial VFs associated with the PF */
331 u16 num_VFs; /* Number of VFs available */
332 u16 offset; /* First VF Routing ID offset */
333 u16 stride; /* Following VF stride */
334 u16 vf_device; /* VF device ID */
335 u32 pgsz; /* Page size for BAR alignment */
336 u8 link; /* Function Dependency Link */
337 u8 max_VF_buses; /* Max buses consumed by VFs */
338 u16 driver_max_VFs; /* Max num VFs driver supports */
339 struct pci_dev *dev; /* Lowest numbered PF */
340 struct pci_dev *self; /* This PF */
341 u32 class; /* VF device */
342 u8 hdr_type; /* VF header type */
343 u16 subsystem_vendor; /* VF subsystem vendor */
344 u16 subsystem_device; /* VF subsystem device */
345 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
346 bool drivers_autoprobe; /* Auto probing of VFs by driver */
347};
348
349/**
350 * pci_dev_set_io_state - Set the new error state if possible.
351 *
352 * @dev - pci device to set new error_state
353 * @new - the state we want dev to be in
354 *
355 * Must be called with device_lock held.
356 *
357 * Returns true if state has been changed to the requested state.
358 */
359static inline bool pci_dev_set_io_state(struct pci_dev *dev,
360 pci_channel_state_t new)
361{
362 bool changed = false;
363
364 device_lock_assert(&dev->dev);
365 switch (new) {
366 case pci_channel_io_perm_failure:
367 switch (dev->error_state) {
368 case pci_channel_io_frozen:
369 case pci_channel_io_normal:
370 case pci_channel_io_perm_failure:
371 changed = true;
372 break;
373 }
374 break;
375 case pci_channel_io_frozen:
376 switch (dev->error_state) {
377 case pci_channel_io_frozen:
378 case pci_channel_io_normal:
379 changed = true;
380 break;
381 }
382 break;
383 case pci_channel_io_normal:
384 switch (dev->error_state) {
385 case pci_channel_io_frozen:
386 case pci_channel_io_normal:
387 changed = true;
388 break;
389 }
390 break;
391 }
392 if (changed)
393 dev->error_state = new;
394 return changed;
395}
396
397static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
398{
399 device_lock(&dev->dev);
400 pci_dev_set_io_state(dev, pci_channel_io_perm_failure);
401 device_unlock(&dev->dev);
402
403 return 0;
404}
405
406static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
407{
408 return dev->error_state == pci_channel_io_perm_failure;
409}
410
411/* pci_dev priv_flags */
412#define PCI_DEV_ADDED 0
413
414static inline void pci_dev_assign_added(struct pci_dev *dev, bool added)
415{
416 assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added);
417}
418
419static inline bool pci_dev_is_added(const struct pci_dev *dev)
420{
421 return test_bit(PCI_DEV_ADDED, &dev->priv_flags);
422}
423
424#ifdef CONFIG_PCIEAER
425#include <linux/aer.h>
426
427#define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */
428
429struct aer_err_info {
430 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
431 int error_dev_num;
432
433 unsigned int id:16;
434
435 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */
436 unsigned int __pad1:5;
437 unsigned int multi_error_valid:1;
438
439 unsigned int first_error:5;
440 unsigned int __pad2:2;
441 unsigned int tlp_header_valid:1;
442
443 unsigned int status; /* COR/UNCOR Error Status */
444 unsigned int mask; /* COR/UNCOR Error Mask */
445 struct aer_header_log_regs tlp; /* TLP Header */
446};
447
448int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info);
449void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
450#endif /* CONFIG_PCIEAER */
451
452#ifdef CONFIG_PCIE_DPC
453void pci_save_dpc_state(struct pci_dev *dev);
454void pci_restore_dpc_state(struct pci_dev *dev);
455void pci_dpc_init(struct pci_dev *pdev);
456void dpc_process_error(struct pci_dev *pdev);
457pci_ers_result_t dpc_reset_link(struct pci_dev *pdev);
458#else
459static inline void pci_save_dpc_state(struct pci_dev *dev) {}
460static inline void pci_restore_dpc_state(struct pci_dev *dev) {}
461static inline void pci_dpc_init(struct pci_dev *pdev) {}
462#endif
463
464#ifdef CONFIG_PCI_ATS
465/* Address Translation Service */
466void pci_ats_init(struct pci_dev *dev);
467void pci_restore_ats_state(struct pci_dev *dev);
468#else
469static inline void pci_ats_init(struct pci_dev *d) { }
470static inline void pci_restore_ats_state(struct pci_dev *dev) { }
471#endif /* CONFIG_PCI_ATS */
472
473#ifdef CONFIG_PCI_PRI
474void pci_pri_init(struct pci_dev *dev);
475void pci_restore_pri_state(struct pci_dev *pdev);
476#else
477static inline void pci_pri_init(struct pci_dev *dev) { }
478static inline void pci_restore_pri_state(struct pci_dev *pdev) { }
479#endif
480
481#ifdef CONFIG_PCI_PASID
482void pci_pasid_init(struct pci_dev *dev);
483void pci_restore_pasid_state(struct pci_dev *pdev);
484#else
485static inline void pci_pasid_init(struct pci_dev *dev) { }
486static inline void pci_restore_pasid_state(struct pci_dev *pdev) { }
487#endif
488
489#ifdef CONFIG_PCI_IOV
490int pci_iov_init(struct pci_dev *dev);
491void pci_iov_release(struct pci_dev *dev);
492void pci_iov_remove(struct pci_dev *dev);
493void pci_iov_update_resource(struct pci_dev *dev, int resno);
494resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
495void pci_restore_iov_state(struct pci_dev *dev);
496int pci_iov_bus_range(struct pci_bus *bus);
497extern const struct attribute_group sriov_dev_attr_group;
498#else
499static inline int pci_iov_init(struct pci_dev *dev)
500{
501 return -ENODEV;
502}
503static inline void pci_iov_release(struct pci_dev *dev)
504
505{
506}
507static inline void pci_iov_remove(struct pci_dev *dev)
508{
509}
510static inline void pci_restore_iov_state(struct pci_dev *dev)
511{
512}
513static inline int pci_iov_bus_range(struct pci_bus *bus)
514{
515 return 0;
516}
517
518#endif /* CONFIG_PCI_IOV */
519
520unsigned long pci_cardbus_resource_alignment(struct resource *);
521
522static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
523 struct resource *res)
524{
525#ifdef CONFIG_PCI_IOV
526 int resno = res - dev->resource;
527
528 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
529 return pci_sriov_resource_alignment(dev, resno);
530#endif
531 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
532 return pci_cardbus_resource_alignment(res);
533 return resource_alignment(res);
534}
535
536void pci_acs_init(struct pci_dev *dev);
537#ifdef CONFIG_PCI_QUIRKS
538int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
539int pci_dev_specific_enable_acs(struct pci_dev *dev);
540int pci_dev_specific_disable_acs_redir(struct pci_dev *dev);
541#else
542static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
543 u16 acs_flags)
544{
545 return -ENOTTY;
546}
547static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
548{
549 return -ENOTTY;
550}
551static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
552{
553 return -ENOTTY;
554}
555#endif
556
557/* PCI error reporting and recovery */
558pci_ers_result_t pcie_do_recovery(struct pci_dev *dev,
559 pci_channel_state_t state,
560 pci_ers_result_t (*reset_link)(struct pci_dev *pdev));
561
562bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
563#ifdef CONFIG_PCIEASPM
564void pcie_aspm_init_link_state(struct pci_dev *pdev);
565void pcie_aspm_exit_link_state(struct pci_dev *pdev);
566void pcie_aspm_pm_state_change(struct pci_dev *pdev);
567void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
568#else
569static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
570static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
571static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { }
572static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
573#endif
574
575#ifdef CONFIG_PCIE_ECRC
576void pcie_set_ecrc_checking(struct pci_dev *dev);
577void pcie_ecrc_get_policy(char *str);
578#else
579static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
580static inline void pcie_ecrc_get_policy(char *str) { }
581#endif
582
583#ifdef CONFIG_PCIE_PTM
584void pci_ptm_init(struct pci_dev *dev);
585int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
586#else
587static inline void pci_ptm_init(struct pci_dev *dev) { }
588static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
589{ return -EINVAL; }
590#endif
591
592struct pci_dev_reset_methods {
593 u16 vendor;
594 u16 device;
595 int (*reset)(struct pci_dev *dev, int probe);
596};
597
598#ifdef CONFIG_PCI_QUIRKS
599int pci_dev_specific_reset(struct pci_dev *dev, int probe);
600#else
601static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
602{
603 return -ENOTTY;
604}
605#endif
606
607#if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
608int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
609 struct resource *res);
610#endif
611
612u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
613int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
614int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
615static inline u64 pci_rebar_size_to_bytes(int size)
616{
617 return 1ULL << (size + 20);
618}
619
620struct device_node;
621
622#ifdef CONFIG_OF
623int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
624int of_get_pci_domain_nr(struct device_node *node);
625int of_pci_get_max_link_speed(struct device_node *node);
626void pci_set_of_node(struct pci_dev *dev);
627void pci_release_of_node(struct pci_dev *dev);
628void pci_set_bus_of_node(struct pci_bus *bus);
629void pci_release_bus_of_node(struct pci_bus *bus);
630
631int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge);
632
633#else
634static inline int
635of_pci_parse_bus_range(struct device_node *node, struct resource *res)
636{
637 return -EINVAL;
638}
639
640static inline int
641of_get_pci_domain_nr(struct device_node *node)
642{
643 return -1;
644}
645
646static inline int
647of_pci_get_max_link_speed(struct device_node *node)
648{
649 return -EINVAL;
650}
651
652static inline void pci_set_of_node(struct pci_dev *dev) { }
653static inline void pci_release_of_node(struct pci_dev *dev) { }
654static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
655static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
656
657static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge)
658{
659 return 0;
660}
661
662#endif /* CONFIG_OF */
663
664#ifdef CONFIG_PCIEAER
665void pci_no_aer(void);
666void pci_aer_init(struct pci_dev *dev);
667void pci_aer_exit(struct pci_dev *dev);
668extern const struct attribute_group aer_stats_attr_group;
669void pci_aer_clear_fatal_status(struct pci_dev *dev);
670int pci_aer_clear_status(struct pci_dev *dev);
671int pci_aer_raw_clear_status(struct pci_dev *dev);
672#else
673static inline void pci_no_aer(void) { }
674static inline void pci_aer_init(struct pci_dev *d) { }
675static inline void pci_aer_exit(struct pci_dev *d) { }
676static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
677static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; }
678static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; }
679#endif
680
681#ifdef CONFIG_ACPI
682int pci_acpi_program_hp_params(struct pci_dev *dev);
683#else
684static inline int pci_acpi_program_hp_params(struct pci_dev *dev)
685{
686 return -ENODEV;
687}
688#endif
689
690#ifdef CONFIG_PCIEASPM
691extern const struct attribute_group aspm_ctrl_attr_group;
692#endif
693
694#endif /* DRIVERS_PCI_H */
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef DRIVERS_PCI_H
3#define DRIVERS_PCI_H
4
5#include <linux/pci.h>
6
7/* Number of possible devfns: 0.0 to 1f.7 inclusive */
8#define MAX_NR_DEVFNS 256
9
10#define PCI_FIND_CAP_TTL 48
11
12#define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */
13
14#define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000
15
16/* Power stable to PERST# inactive from PCIe card Electromechanical Spec */
17#define PCIE_T_PVPERL_MS 100
18
19/*
20 * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization>
21 * Recommends 1ms to 10ms timeout to check L2 ready.
22 */
23#define PCIE_PME_TO_L2_TIMEOUT_US 10000
24
25extern const unsigned char pcie_link_speed[];
26extern bool pci_early_dump;
27
28bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
29bool pcie_cap_has_lnkctl2(const struct pci_dev *dev);
30bool pcie_cap_has_rtctl(const struct pci_dev *dev);
31
32/* Functions internal to the PCI core code */
33
34#ifdef CONFIG_DMI
35extern const struct attribute_group pci_dev_smbios_attr_group;
36#endif
37
38enum pci_mmap_api {
39 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
40 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
41};
42int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
43 enum pci_mmap_api mmap_api);
44
45bool pci_reset_supported(struct pci_dev *dev);
46void pci_init_reset_methods(struct pci_dev *dev);
47int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
48int pci_bus_error_reset(struct pci_dev *dev);
49
50struct pci_cap_saved_data {
51 u16 cap_nr;
52 bool cap_extended;
53 unsigned int size;
54 u32 data[];
55};
56
57struct pci_cap_saved_state {
58 struct hlist_node next;
59 struct pci_cap_saved_data cap;
60};
61
62void pci_allocate_cap_save_buffers(struct pci_dev *dev);
63void pci_free_cap_save_buffers(struct pci_dev *dev);
64int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
65int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
66 u16 cap, unsigned int size);
67struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
68struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
69 u16 cap);
70
71#define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */
72#define PCI_PM_D3HOT_WAIT 10 /* msec */
73#define PCI_PM_D3COLD_WAIT 100 /* msec */
74
75void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
76void pci_refresh_power_state(struct pci_dev *dev);
77int pci_power_up(struct pci_dev *dev);
78void pci_disable_enabled_device(struct pci_dev *dev);
79int pci_finish_runtime_suspend(struct pci_dev *dev);
80void pcie_clear_device_status(struct pci_dev *dev);
81void pcie_clear_root_pme_status(struct pci_dev *dev);
82bool pci_check_pme_status(struct pci_dev *dev);
83void pci_pme_wakeup_bus(struct pci_bus *bus);
84int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
85void pci_pme_restore(struct pci_dev *dev);
86bool pci_dev_need_resume(struct pci_dev *dev);
87void pci_dev_adjust_pme(struct pci_dev *dev);
88void pci_dev_complete_resume(struct pci_dev *pci_dev);
89void pci_config_pm_runtime_get(struct pci_dev *dev);
90void pci_config_pm_runtime_put(struct pci_dev *dev);
91void pci_pm_init(struct pci_dev *dev);
92void pci_ea_init(struct pci_dev *dev);
93void pci_msi_init(struct pci_dev *dev);
94void pci_msix_init(struct pci_dev *dev);
95bool pci_bridge_d3_possible(struct pci_dev *dev);
96void pci_bridge_d3_update(struct pci_dev *dev);
97int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type);
98
99static inline void pci_wakeup_event(struct pci_dev *dev)
100{
101 /* Wait 100 ms before the system can be put into a sleep state. */
102 pm_wakeup_event(&dev->dev, 100);
103}
104
105static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
106{
107 return !!(pci_dev->subordinate);
108}
109
110static inline bool pci_power_manageable(struct pci_dev *pci_dev)
111{
112 /*
113 * Currently we allow normal PCI devices and PCI bridges transition
114 * into D3 if their bridge_d3 is set.
115 */
116 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
117}
118
119static inline bool pcie_downstream_port(const struct pci_dev *dev)
120{
121 int type = pci_pcie_type(dev);
122
123 return type == PCI_EXP_TYPE_ROOT_PORT ||
124 type == PCI_EXP_TYPE_DOWNSTREAM ||
125 type == PCI_EXP_TYPE_PCIE_BRIDGE;
126}
127
128void pci_vpd_init(struct pci_dev *dev);
129void pci_vpd_release(struct pci_dev *dev);
130extern const struct attribute_group pci_dev_vpd_attr_group;
131
132/* PCI Virtual Channel */
133int pci_save_vc_state(struct pci_dev *dev);
134void pci_restore_vc_state(struct pci_dev *dev);
135void pci_allocate_vc_save_buffers(struct pci_dev *dev);
136
137/* PCI /proc functions */
138#ifdef CONFIG_PROC_FS
139int pci_proc_attach_device(struct pci_dev *dev);
140int pci_proc_detach_device(struct pci_dev *dev);
141int pci_proc_detach_bus(struct pci_bus *bus);
142#else
143static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
144static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
145static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
146#endif
147
148/* Functions for PCI Hotplug drivers to use */
149int pci_hp_add_bridge(struct pci_dev *dev);
150
151#if defined(CONFIG_SYSFS) && defined(HAVE_PCI_LEGACY)
152void pci_create_legacy_files(struct pci_bus *bus);
153void pci_remove_legacy_files(struct pci_bus *bus);
154#else
155static inline void pci_create_legacy_files(struct pci_bus *bus) { }
156static inline void pci_remove_legacy_files(struct pci_bus *bus) { }
157#endif
158
159/* Lock for read/write access to pci device and bus lists */
160extern struct rw_semaphore pci_bus_sem;
161extern struct mutex pci_slot_mutex;
162
163extern raw_spinlock_t pci_lock;
164
165extern unsigned int pci_pm_d3hot_delay;
166
167#ifdef CONFIG_PCI_MSI
168void pci_no_msi(void);
169#else
170static inline void pci_no_msi(void) { }
171#endif
172
173void pci_realloc_get_opt(char *);
174
175static inline int pci_no_d1d2(struct pci_dev *dev)
176{
177 unsigned int parent_dstates = 0;
178
179 if (dev->bus->self)
180 parent_dstates = dev->bus->self->no_d1d2;
181 return (dev->no_d1d2 || parent_dstates);
182
183}
184
185#ifdef CONFIG_SYSFS
186int pci_create_sysfs_dev_files(struct pci_dev *pdev);
187void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
188extern const struct attribute_group *pci_dev_groups[];
189extern const struct attribute_group *pci_dev_attr_groups[];
190extern const struct attribute_group *pcibus_groups[];
191extern const struct attribute_group *pci_bus_groups[];
192#else
193static inline int pci_create_sysfs_dev_files(struct pci_dev *pdev) { return 0; }
194static inline void pci_remove_sysfs_dev_files(struct pci_dev *pdev) { }
195#define pci_dev_groups NULL
196#define pci_dev_attr_groups NULL
197#define pcibus_groups NULL
198#define pci_bus_groups NULL
199#endif
200
201extern unsigned long pci_hotplug_io_size;
202extern unsigned long pci_hotplug_mmio_size;
203extern unsigned long pci_hotplug_mmio_pref_size;
204extern unsigned long pci_hotplug_bus_size;
205
206/**
207 * pci_match_one_device - Tell if a PCI device structure has a matching
208 * PCI device id structure
209 * @id: single PCI device id structure to match
210 * @dev: the PCI device structure to match against
211 *
212 * Returns the matching pci_device_id structure or %NULL if there is no match.
213 */
214static inline const struct pci_device_id *
215pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
216{
217 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
218 (id->device == PCI_ANY_ID || id->device == dev->device) &&
219 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
220 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
221 !((id->class ^ dev->class) & id->class_mask))
222 return id;
223 return NULL;
224}
225
226/* PCI slot sysfs helper code */
227#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
228
229extern struct kset *pci_slots_kset;
230
231struct pci_slot_attribute {
232 struct attribute attr;
233 ssize_t (*show)(struct pci_slot *, char *);
234 ssize_t (*store)(struct pci_slot *, const char *, size_t);
235};
236#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
237
238enum pci_bar_type {
239 pci_bar_unknown, /* Standard PCI BAR probe */
240 pci_bar_io, /* An I/O port BAR */
241 pci_bar_mem32, /* A 32-bit memory BAR */
242 pci_bar_mem64, /* A 64-bit memory BAR */
243};
244
245struct device *pci_get_host_bridge_device(struct pci_dev *dev);
246void pci_put_host_bridge_device(struct device *dev);
247
248int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
249bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
250 int crs_timeout);
251bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
252 int crs_timeout);
253int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout);
254
255int pci_setup_device(struct pci_dev *dev);
256int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
257 struct resource *res, unsigned int reg);
258void pci_configure_ari(struct pci_dev *dev);
259void __pci_bus_size_bridges(struct pci_bus *bus,
260 struct list_head *realloc_head);
261void __pci_bus_assign_resources(const struct pci_bus *bus,
262 struct list_head *realloc_head,
263 struct list_head *fail_head);
264bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
265
266const char *pci_resource_name(struct pci_dev *dev, unsigned int i);
267
268void pci_reassigndev_resource_alignment(struct pci_dev *dev);
269void pci_disable_bridge_window(struct pci_dev *dev);
270struct pci_bus *pci_bus_get(struct pci_bus *bus);
271void pci_bus_put(struct pci_bus *bus);
272
273/* PCIe link information from Link Capabilities 2 */
274#define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \
275 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \
276 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
277 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
278 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
279 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
280 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
281 PCI_SPEED_UNKNOWN)
282
283/* PCIe speed to Mb/s reduced by encoding overhead */
284#define PCIE_SPEED2MBS_ENC(speed) \
285 ((speed) == PCIE_SPEED_64_0GT ? 64000*1/1 : \
286 (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
287 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
288 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \
289 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \
290 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \
291 0)
292
293const char *pci_speed_string(enum pci_bus_speed speed);
294enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
295enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
296u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
297 enum pcie_link_width *width);
298void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
299void pcie_report_downtraining(struct pci_dev *dev);
300void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
301
302/* Single Root I/O Virtualization */
303struct pci_sriov {
304 int pos; /* Capability position */
305 int nres; /* Number of resources */
306 u32 cap; /* SR-IOV Capabilities */
307 u16 ctrl; /* SR-IOV Control */
308 u16 total_VFs; /* Total VFs associated with the PF */
309 u16 initial_VFs; /* Initial VFs associated with the PF */
310 u16 num_VFs; /* Number of VFs available */
311 u16 offset; /* First VF Routing ID offset */
312 u16 stride; /* Following VF stride */
313 u16 vf_device; /* VF device ID */
314 u32 pgsz; /* Page size for BAR alignment */
315 u8 link; /* Function Dependency Link */
316 u8 max_VF_buses; /* Max buses consumed by VFs */
317 u16 driver_max_VFs; /* Max num VFs driver supports */
318 struct pci_dev *dev; /* Lowest numbered PF */
319 struct pci_dev *self; /* This PF */
320 u32 class; /* VF device */
321 u8 hdr_type; /* VF header type */
322 u16 subsystem_vendor; /* VF subsystem vendor */
323 u16 subsystem_device; /* VF subsystem device */
324 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
325 bool drivers_autoprobe; /* Auto probing of VFs by driver */
326};
327
328#ifdef CONFIG_PCI_DOE
329void pci_doe_init(struct pci_dev *pdev);
330void pci_doe_destroy(struct pci_dev *pdev);
331void pci_doe_disconnected(struct pci_dev *pdev);
332#else
333static inline void pci_doe_init(struct pci_dev *pdev) { }
334static inline void pci_doe_destroy(struct pci_dev *pdev) { }
335static inline void pci_doe_disconnected(struct pci_dev *pdev) { }
336#endif
337
338/**
339 * pci_dev_set_io_state - Set the new error state if possible.
340 *
341 * @dev: PCI device to set new error_state
342 * @new: the state we want dev to be in
343 *
344 * If the device is experiencing perm_failure, it has to remain in that state.
345 * Any other transition is allowed.
346 *
347 * Returns true if state has been changed to the requested state.
348 */
349static inline bool pci_dev_set_io_state(struct pci_dev *dev,
350 pci_channel_state_t new)
351{
352 pci_channel_state_t old;
353
354 switch (new) {
355 case pci_channel_io_perm_failure:
356 xchg(&dev->error_state, pci_channel_io_perm_failure);
357 return true;
358 case pci_channel_io_frozen:
359 old = cmpxchg(&dev->error_state, pci_channel_io_normal,
360 pci_channel_io_frozen);
361 return old != pci_channel_io_perm_failure;
362 case pci_channel_io_normal:
363 old = cmpxchg(&dev->error_state, pci_channel_io_frozen,
364 pci_channel_io_normal);
365 return old != pci_channel_io_perm_failure;
366 default:
367 return false;
368 }
369}
370
371static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
372{
373 pci_dev_set_io_state(dev, pci_channel_io_perm_failure);
374 pci_doe_disconnected(dev);
375
376 return 0;
377}
378
379/* pci_dev priv_flags */
380#define PCI_DEV_ADDED 0
381#define PCI_DPC_RECOVERED 1
382#define PCI_DPC_RECOVERING 2
383
384static inline void pci_dev_assign_added(struct pci_dev *dev, bool added)
385{
386 assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added);
387}
388
389static inline bool pci_dev_is_added(const struct pci_dev *dev)
390{
391 return test_bit(PCI_DEV_ADDED, &dev->priv_flags);
392}
393
394#ifdef CONFIG_PCIEAER
395#include <linux/aer.h>
396
397#define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */
398
399struct aer_err_info {
400 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
401 int error_dev_num;
402
403 unsigned int id:16;
404
405 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */
406 unsigned int __pad1:5;
407 unsigned int multi_error_valid:1;
408
409 unsigned int first_error:5;
410 unsigned int __pad2:2;
411 unsigned int tlp_header_valid:1;
412
413 unsigned int status; /* COR/UNCOR Error Status */
414 unsigned int mask; /* COR/UNCOR Error Mask */
415 struct pcie_tlp_log tlp; /* TLP Header */
416};
417
418int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info);
419void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
420#endif /* CONFIG_PCIEAER */
421
422#ifdef CONFIG_PCIEPORTBUS
423/* Cached RCEC Endpoint Association */
424struct rcec_ea {
425 u8 nextbusn;
426 u8 lastbusn;
427 u32 bitmap;
428};
429#endif
430
431#ifdef CONFIG_PCIE_DPC
432void pci_save_dpc_state(struct pci_dev *dev);
433void pci_restore_dpc_state(struct pci_dev *dev);
434void pci_dpc_init(struct pci_dev *pdev);
435void dpc_process_error(struct pci_dev *pdev);
436pci_ers_result_t dpc_reset_link(struct pci_dev *pdev);
437bool pci_dpc_recovered(struct pci_dev *pdev);
438#else
439static inline void pci_save_dpc_state(struct pci_dev *dev) { }
440static inline void pci_restore_dpc_state(struct pci_dev *dev) { }
441static inline void pci_dpc_init(struct pci_dev *pdev) { }
442static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; }
443#endif
444
445#ifdef CONFIG_PCIEPORTBUS
446void pci_rcec_init(struct pci_dev *dev);
447void pci_rcec_exit(struct pci_dev *dev);
448void pcie_link_rcec(struct pci_dev *rcec);
449void pcie_walk_rcec(struct pci_dev *rcec,
450 int (*cb)(struct pci_dev *, void *),
451 void *userdata);
452#else
453static inline void pci_rcec_init(struct pci_dev *dev) { }
454static inline void pci_rcec_exit(struct pci_dev *dev) { }
455static inline void pcie_link_rcec(struct pci_dev *rcec) { }
456static inline void pcie_walk_rcec(struct pci_dev *rcec,
457 int (*cb)(struct pci_dev *, void *),
458 void *userdata) { }
459#endif
460
461#ifdef CONFIG_PCI_ATS
462/* Address Translation Service */
463void pci_ats_init(struct pci_dev *dev);
464void pci_restore_ats_state(struct pci_dev *dev);
465#else
466static inline void pci_ats_init(struct pci_dev *d) { }
467static inline void pci_restore_ats_state(struct pci_dev *dev) { }
468#endif /* CONFIG_PCI_ATS */
469
470#ifdef CONFIG_PCI_PRI
471void pci_pri_init(struct pci_dev *dev);
472void pci_restore_pri_state(struct pci_dev *pdev);
473#else
474static inline void pci_pri_init(struct pci_dev *dev) { }
475static inline void pci_restore_pri_state(struct pci_dev *pdev) { }
476#endif
477
478#ifdef CONFIG_PCI_PASID
479void pci_pasid_init(struct pci_dev *dev);
480void pci_restore_pasid_state(struct pci_dev *pdev);
481#else
482static inline void pci_pasid_init(struct pci_dev *dev) { }
483static inline void pci_restore_pasid_state(struct pci_dev *pdev) { }
484#endif
485
486#ifdef CONFIG_PCI_IOV
487int pci_iov_init(struct pci_dev *dev);
488void pci_iov_release(struct pci_dev *dev);
489void pci_iov_remove(struct pci_dev *dev);
490void pci_iov_update_resource(struct pci_dev *dev, int resno);
491resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
492void pci_restore_iov_state(struct pci_dev *dev);
493int pci_iov_bus_range(struct pci_bus *bus);
494extern const struct attribute_group sriov_pf_dev_attr_group;
495extern const struct attribute_group sriov_vf_dev_attr_group;
496#else
497static inline int pci_iov_init(struct pci_dev *dev)
498{
499 return -ENODEV;
500}
501static inline void pci_iov_release(struct pci_dev *dev) { }
502static inline void pci_iov_remove(struct pci_dev *dev) { }
503static inline void pci_restore_iov_state(struct pci_dev *dev) { }
504static inline int pci_iov_bus_range(struct pci_bus *bus)
505{
506 return 0;
507}
508
509#endif /* CONFIG_PCI_IOV */
510
511#ifdef CONFIG_PCIE_PTM
512void pci_ptm_init(struct pci_dev *dev);
513void pci_save_ptm_state(struct pci_dev *dev);
514void pci_restore_ptm_state(struct pci_dev *dev);
515void pci_suspend_ptm(struct pci_dev *dev);
516void pci_resume_ptm(struct pci_dev *dev);
517#else
518static inline void pci_ptm_init(struct pci_dev *dev) { }
519static inline void pci_save_ptm_state(struct pci_dev *dev) { }
520static inline void pci_restore_ptm_state(struct pci_dev *dev) { }
521static inline void pci_suspend_ptm(struct pci_dev *dev) { }
522static inline void pci_resume_ptm(struct pci_dev *dev) { }
523#endif
524
525unsigned long pci_cardbus_resource_alignment(struct resource *);
526
527static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
528 struct resource *res)
529{
530#ifdef CONFIG_PCI_IOV
531 int resno = res - dev->resource;
532
533 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
534 return pci_sriov_resource_alignment(dev, resno);
535#endif
536 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
537 return pci_cardbus_resource_alignment(res);
538 return resource_alignment(res);
539}
540
541void pci_acs_init(struct pci_dev *dev);
542#ifdef CONFIG_PCI_QUIRKS
543int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
544int pci_dev_specific_enable_acs(struct pci_dev *dev);
545int pci_dev_specific_disable_acs_redir(struct pci_dev *dev);
546bool pcie_failed_link_retrain(struct pci_dev *dev);
547#else
548static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
549 u16 acs_flags)
550{
551 return -ENOTTY;
552}
553static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
554{
555 return -ENOTTY;
556}
557static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
558{
559 return -ENOTTY;
560}
561static inline bool pcie_failed_link_retrain(struct pci_dev *dev)
562{
563 return false;
564}
565#endif
566
567/* PCI error reporting and recovery */
568pci_ers_result_t pcie_do_recovery(struct pci_dev *dev,
569 pci_channel_state_t state,
570 pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev));
571
572bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
573int pcie_retrain_link(struct pci_dev *pdev, bool use_lt);
574
575/* ASPM-related functionality we need even without CONFIG_PCIEASPM */
576void pci_save_ltr_state(struct pci_dev *dev);
577void pci_restore_ltr_state(struct pci_dev *dev);
578void pci_configure_aspm_l1ss(struct pci_dev *dev);
579void pci_save_aspm_l1ss_state(struct pci_dev *dev);
580void pci_restore_aspm_l1ss_state(struct pci_dev *dev);
581
582#ifdef CONFIG_PCIEASPM
583void pcie_aspm_init_link_state(struct pci_dev *pdev);
584void pcie_aspm_exit_link_state(struct pci_dev *pdev);
585void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked);
586void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
587void pci_configure_ltr(struct pci_dev *pdev);
588void pci_bridge_reconfigure_ltr(struct pci_dev *pdev);
589#else
590static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
591static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
592static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked) { }
593static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
594static inline void pci_configure_ltr(struct pci_dev *pdev) { }
595static inline void pci_bridge_reconfigure_ltr(struct pci_dev *pdev) { }
596#endif
597
598#ifdef CONFIG_PCIE_ECRC
599void pcie_set_ecrc_checking(struct pci_dev *dev);
600void pcie_ecrc_get_policy(char *str);
601#else
602static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
603static inline void pcie_ecrc_get_policy(char *str) { }
604#endif
605
606struct pci_dev_reset_methods {
607 u16 vendor;
608 u16 device;
609 int (*reset)(struct pci_dev *dev, bool probe);
610};
611
612struct pci_reset_fn_method {
613 int (*reset_fn)(struct pci_dev *pdev, bool probe);
614 char *name;
615};
616
617#ifdef CONFIG_PCI_QUIRKS
618int pci_dev_specific_reset(struct pci_dev *dev, bool probe);
619#else
620static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe)
621{
622 return -ENOTTY;
623}
624#endif
625
626#if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
627int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
628 struct resource *res);
629#else
630static inline int acpi_get_rc_resources(struct device *dev, const char *hid,
631 u16 segment, struct resource *res)
632{
633 return -ENODEV;
634}
635#endif
636
637int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
638int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
639static inline u64 pci_rebar_size_to_bytes(int size)
640{
641 return 1ULL << (size + 20);
642}
643
644struct device_node;
645
646#ifdef CONFIG_OF
647int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
648int of_get_pci_domain_nr(struct device_node *node);
649int of_pci_get_max_link_speed(struct device_node *node);
650u32 of_pci_get_slot_power_limit(struct device_node *node,
651 u8 *slot_power_limit_value,
652 u8 *slot_power_limit_scale);
653int pci_set_of_node(struct pci_dev *dev);
654void pci_release_of_node(struct pci_dev *dev);
655void pci_set_bus_of_node(struct pci_bus *bus);
656void pci_release_bus_of_node(struct pci_bus *bus);
657
658int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge);
659
660#else
661static inline int
662of_pci_parse_bus_range(struct device_node *node, struct resource *res)
663{
664 return -EINVAL;
665}
666
667static inline int
668of_get_pci_domain_nr(struct device_node *node)
669{
670 return -1;
671}
672
673static inline int
674of_pci_get_max_link_speed(struct device_node *node)
675{
676 return -EINVAL;
677}
678
679static inline u32
680of_pci_get_slot_power_limit(struct device_node *node,
681 u8 *slot_power_limit_value,
682 u8 *slot_power_limit_scale)
683{
684 if (slot_power_limit_value)
685 *slot_power_limit_value = 0;
686 if (slot_power_limit_scale)
687 *slot_power_limit_scale = 0;
688 return 0;
689}
690
691static inline int pci_set_of_node(struct pci_dev *dev) { return 0; }
692static inline void pci_release_of_node(struct pci_dev *dev) { }
693static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
694static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
695
696static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge)
697{
698 return 0;
699}
700
701#endif /* CONFIG_OF */
702
703struct of_changeset;
704
705#ifdef CONFIG_PCI_DYNAMIC_OF_NODES
706void of_pci_make_dev_node(struct pci_dev *pdev);
707void of_pci_remove_node(struct pci_dev *pdev);
708int of_pci_add_properties(struct pci_dev *pdev, struct of_changeset *ocs,
709 struct device_node *np);
710#else
711static inline void of_pci_make_dev_node(struct pci_dev *pdev) { }
712static inline void of_pci_remove_node(struct pci_dev *pdev) { }
713#endif
714
715#ifdef CONFIG_PCIEAER
716void pci_no_aer(void);
717void pci_aer_init(struct pci_dev *dev);
718void pci_aer_exit(struct pci_dev *dev);
719extern const struct attribute_group aer_stats_attr_group;
720void pci_aer_clear_fatal_status(struct pci_dev *dev);
721int pci_aer_clear_status(struct pci_dev *dev);
722int pci_aer_raw_clear_status(struct pci_dev *dev);
723void pci_save_aer_state(struct pci_dev *dev);
724void pci_restore_aer_state(struct pci_dev *dev);
725#else
726static inline void pci_no_aer(void) { }
727static inline void pci_aer_init(struct pci_dev *d) { }
728static inline void pci_aer_exit(struct pci_dev *d) { }
729static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
730static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; }
731static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; }
732static inline void pci_save_aer_state(struct pci_dev *dev) { }
733static inline void pci_restore_aer_state(struct pci_dev *dev) { }
734#endif
735
736#ifdef CONFIG_ACPI
737int pci_acpi_program_hp_params(struct pci_dev *dev);
738extern const struct attribute_group pci_dev_acpi_attr_group;
739void pci_set_acpi_fwnode(struct pci_dev *dev);
740int pci_dev_acpi_reset(struct pci_dev *dev, bool probe);
741bool acpi_pci_power_manageable(struct pci_dev *dev);
742bool acpi_pci_bridge_d3(struct pci_dev *dev);
743int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state);
744pci_power_t acpi_pci_get_power_state(struct pci_dev *dev);
745void acpi_pci_refresh_power_state(struct pci_dev *dev);
746int acpi_pci_wakeup(struct pci_dev *dev, bool enable);
747bool acpi_pci_need_resume(struct pci_dev *dev);
748pci_power_t acpi_pci_choose_state(struct pci_dev *pdev);
749#else
750static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe)
751{
752 return -ENOTTY;
753}
754static inline void pci_set_acpi_fwnode(struct pci_dev *dev) { }
755static inline int pci_acpi_program_hp_params(struct pci_dev *dev)
756{
757 return -ENODEV;
758}
759static inline bool acpi_pci_power_manageable(struct pci_dev *dev)
760{
761 return false;
762}
763static inline bool acpi_pci_bridge_d3(struct pci_dev *dev)
764{
765 return false;
766}
767static inline int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state)
768{
769 return -ENODEV;
770}
771static inline pci_power_t acpi_pci_get_power_state(struct pci_dev *dev)
772{
773 return PCI_UNKNOWN;
774}
775static inline void acpi_pci_refresh_power_state(struct pci_dev *dev) { }
776static inline int acpi_pci_wakeup(struct pci_dev *dev, bool enable)
777{
778 return -ENODEV;
779}
780static inline bool acpi_pci_need_resume(struct pci_dev *dev)
781{
782 return false;
783}
784static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev)
785{
786 return PCI_POWER_ERROR;
787}
788#endif
789
790#ifdef CONFIG_PCIEASPM
791extern const struct attribute_group aspm_ctrl_attr_group;
792#endif
793
794extern const struct attribute_group pci_dev_reset_method_attr_group;
795
796#ifdef CONFIG_X86_INTEL_MID
797bool pci_use_mid_pm(void);
798int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state);
799pci_power_t mid_pci_get_power_state(struct pci_dev *pdev);
800#else
801static inline bool pci_use_mid_pm(void)
802{
803 return false;
804}
805static inline int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state)
806{
807 return -ENODEV;
808}
809static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev)
810{
811 return PCI_UNKNOWN;
812}
813#endif
814
815/*
816 * Managed PCI resources. This manages device on/off, INTx/MSI/MSI-X
817 * on/off and BAR regions. pci_dev itself records MSI/MSI-X status, so
818 * there's no need to track it separately. pci_devres is initialized
819 * when a device is enabled using managed PCI device enable interface.
820 *
821 * TODO: Struct pci_devres and find_pci_dr() only need to be here because
822 * they're used in pci.c. Port or move these functions to devres.c and
823 * then remove them from here.
824 */
825struct pci_devres {
826 unsigned int enabled:1;
827 unsigned int pinned:1;
828 unsigned int orig_intx:1;
829 unsigned int restore_intx:1;
830 unsigned int mwi:1;
831 u32 region_mask;
832};
833
834struct pci_devres *find_pci_dr(struct pci_dev *pdev);
835
836/*
837 * Config Address for PCI Configuration Mechanism #1
838 *
839 * See PCI Local Bus Specification, Revision 3.0,
840 * Section 3.2.2.3.2, Figure 3-2, p. 50.
841 */
842
843#define PCI_CONF1_BUS_SHIFT 16 /* Bus number */
844#define PCI_CONF1_DEV_SHIFT 11 /* Device number */
845#define PCI_CONF1_FUNC_SHIFT 8 /* Function number */
846
847#define PCI_CONF1_BUS_MASK 0xff
848#define PCI_CONF1_DEV_MASK 0x1f
849#define PCI_CONF1_FUNC_MASK 0x7
850#define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */
851
852#define PCI_CONF1_ENABLE BIT(31)
853#define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT)
854#define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT)
855#define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT)
856#define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK)
857
858#define PCI_CONF1_ADDRESS(bus, dev, func, reg) \
859 (PCI_CONF1_ENABLE | \
860 PCI_CONF1_BUS(bus) | \
861 PCI_CONF1_DEV(dev) | \
862 PCI_CONF1_FUNC(func) | \
863 PCI_CONF1_REG(reg))
864
865/*
866 * Extension of PCI Config Address for accessing extended PCIe registers
867 *
868 * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs
869 * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address
870 * are used for specifying additional 4 high bits of PCI Express register.
871 */
872
873#define PCI_CONF1_EXT_REG_SHIFT 16
874#define PCI_CONF1_EXT_REG_MASK 0xf00
875#define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT)
876
877#define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \
878 (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \
879 PCI_CONF1_EXT_REG(reg))
880
881#endif /* DRIVERS_PCI_H */