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1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <drm/amdgpu_drm.h>
25#include "amdgpu.h"
26#include "atomfirmware.h"
27#include "amdgpu_atomfirmware.h"
28#include "atom.h"
29#include "atombios.h"
30#include "soc15_hw_ip.h"
31
32bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device *adev)
33{
34 int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
35 firmwareinfo);
36 uint16_t data_offset;
37
38 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
39 NULL, NULL, &data_offset)) {
40 struct atom_firmware_info_v3_1 *firmware_info =
41 (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
42 data_offset);
43
44 if (le32_to_cpu(firmware_info->firmware_capability) &
45 ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION)
46 return true;
47 }
48 return false;
49}
50
51void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev)
52{
53 int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
54 firmwareinfo);
55 uint16_t data_offset;
56
57 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
58 NULL, NULL, &data_offset)) {
59 struct atom_firmware_info_v3_1 *firmware_info =
60 (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
61 data_offset);
62
63 adev->bios_scratch_reg_offset =
64 le32_to_cpu(firmware_info->bios_scratch_reg_startaddr);
65 }
66}
67
68int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev)
69{
70 struct atom_context *ctx = adev->mode_info.atom_context;
71 int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
72 vram_usagebyfirmware);
73 struct vram_usagebyfirmware_v2_1 * firmware_usage;
74 uint32_t start_addr, size;
75 uint16_t data_offset;
76 int usage_bytes = 0;
77
78 if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
79 firmware_usage = (struct vram_usagebyfirmware_v2_1 *)(ctx->bios + data_offset);
80 DRM_DEBUG("atom firmware requested %08x %dkb fw %dkb drv\n",
81 le32_to_cpu(firmware_usage->start_address_in_kb),
82 le16_to_cpu(firmware_usage->used_by_firmware_in_kb),
83 le16_to_cpu(firmware_usage->used_by_driver_in_kb));
84
85 start_addr = le32_to_cpu(firmware_usage->start_address_in_kb);
86 size = le16_to_cpu(firmware_usage->used_by_firmware_in_kb);
87
88 if ((uint32_t)(start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) ==
89 (uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION <<
90 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) {
91 /* Firmware request VRAM reservation for SR-IOV */
92 adev->fw_vram_usage.start_offset = (start_addr &
93 (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
94 adev->fw_vram_usage.size = size << 10;
95 /* Use the default scratch size */
96 usage_bytes = 0;
97 } else {
98 usage_bytes = le16_to_cpu(firmware_usage->used_by_driver_in_kb) << 10;
99 }
100 }
101 ctx->scratch_size_bytes = 0;
102 if (usage_bytes == 0)
103 usage_bytes = 20 * 1024;
104 /* allocate some scratch memory */
105 ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
106 if (!ctx->scratch)
107 return -ENOMEM;
108 ctx->scratch_size_bytes = usage_bytes;
109 return 0;
110}
111
112union igp_info {
113 struct atom_integrated_system_info_v1_11 v11;
114 struct atom_integrated_system_info_v1_12 v12;
115};
116
117union umc_info {
118 struct atom_umc_info_v3_1 v31;
119};
120
121union vram_info {
122 struct atom_vram_info_header_v2_3 v23;
123 struct atom_vram_info_header_v2_4 v24;
124 struct atom_vram_info_header_v2_5 v25;
125};
126
127union vram_module {
128 struct atom_vram_module_v9 v9;
129 struct atom_vram_module_v10 v10;
130 struct atom_vram_module_v11 v11;
131};
132
133static int convert_atom_mem_type_to_vram_type(struct amdgpu_device *adev,
134 int atom_mem_type)
135{
136 int vram_type;
137
138 if (adev->flags & AMD_IS_APU) {
139 switch (atom_mem_type) {
140 case Ddr2MemType:
141 case LpDdr2MemType:
142 vram_type = AMDGPU_VRAM_TYPE_DDR2;
143 break;
144 case Ddr3MemType:
145 case LpDdr3MemType:
146 vram_type = AMDGPU_VRAM_TYPE_DDR3;
147 break;
148 case Ddr4MemType:
149 case LpDdr4MemType:
150 vram_type = AMDGPU_VRAM_TYPE_DDR4;
151 break;
152 default:
153 vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
154 break;
155 }
156 } else {
157 switch (atom_mem_type) {
158 case ATOM_DGPU_VRAM_TYPE_GDDR5:
159 vram_type = AMDGPU_VRAM_TYPE_GDDR5;
160 break;
161 case ATOM_DGPU_VRAM_TYPE_HBM2:
162 vram_type = AMDGPU_VRAM_TYPE_HBM;
163 break;
164 case ATOM_DGPU_VRAM_TYPE_GDDR6:
165 vram_type = AMDGPU_VRAM_TYPE_GDDR6;
166 break;
167 default:
168 vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
169 break;
170 }
171 }
172
173 return vram_type;
174}
175
176
177int
178amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
179 int *vram_width, int *vram_type,
180 int *vram_vendor)
181{
182 struct amdgpu_mode_info *mode_info = &adev->mode_info;
183 int index, i = 0;
184 u16 data_offset, size;
185 union igp_info *igp_info;
186 union vram_info *vram_info;
187 union vram_module *vram_module;
188 u8 frev, crev;
189 u8 mem_type;
190 u8 mem_vendor;
191 u32 mem_channel_number;
192 u32 mem_channel_width;
193 u32 module_id;
194
195 if (adev->flags & AMD_IS_APU)
196 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
197 integratedsysteminfo);
198 else
199 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
200 vram_info);
201
202 if (amdgpu_atom_parse_data_header(mode_info->atom_context,
203 index, &size,
204 &frev, &crev, &data_offset)) {
205 if (adev->flags & AMD_IS_APU) {
206 igp_info = (union igp_info *)
207 (mode_info->atom_context->bios + data_offset);
208 switch (crev) {
209 case 11:
210 mem_channel_number = igp_info->v11.umachannelnumber;
211 /* channel width is 64 */
212 if (vram_width)
213 *vram_width = mem_channel_number * 64;
214 mem_type = igp_info->v11.memorytype;
215 if (vram_type)
216 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
217 break;
218 case 12:
219 mem_channel_number = igp_info->v12.umachannelnumber;
220 /* channel width is 64 */
221 if (vram_width)
222 *vram_width = mem_channel_number * 64;
223 mem_type = igp_info->v12.memorytype;
224 if (vram_type)
225 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
226 break;
227 default:
228 return -EINVAL;
229 }
230 } else {
231 vram_info = (union vram_info *)
232 (mode_info->atom_context->bios + data_offset);
233 module_id = (RREG32(adev->bios_scratch_reg_offset + 4) & 0x00ff0000) >> 16;
234 switch (crev) {
235 case 3:
236 if (module_id > vram_info->v23.vram_module_num)
237 module_id = 0;
238 vram_module = (union vram_module *)vram_info->v23.vram_module;
239 while (i < module_id) {
240 vram_module = (union vram_module *)
241 ((u8 *)vram_module + vram_module->v9.vram_module_size);
242 i++;
243 }
244 mem_type = vram_module->v9.memory_type;
245 if (vram_type)
246 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
247 mem_channel_number = vram_module->v9.channel_num;
248 mem_channel_width = vram_module->v9.channel_width;
249 if (vram_width)
250 *vram_width = mem_channel_number * (1 << mem_channel_width);
251 mem_vendor = (vram_module->v9.vender_rev_id) & 0xF;
252 if (vram_vendor)
253 *vram_vendor = mem_vendor;
254 break;
255 case 4:
256 if (module_id > vram_info->v24.vram_module_num)
257 module_id = 0;
258 vram_module = (union vram_module *)vram_info->v24.vram_module;
259 while (i < module_id) {
260 vram_module = (union vram_module *)
261 ((u8 *)vram_module + vram_module->v10.vram_module_size);
262 i++;
263 }
264 mem_type = vram_module->v10.memory_type;
265 if (vram_type)
266 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
267 mem_channel_number = vram_module->v10.channel_num;
268 mem_channel_width = vram_module->v10.channel_width;
269 if (vram_width)
270 *vram_width = mem_channel_number * (1 << mem_channel_width);
271 mem_vendor = (vram_module->v10.vender_rev_id) & 0xF;
272 if (vram_vendor)
273 *vram_vendor = mem_vendor;
274 break;
275 case 5:
276 if (module_id > vram_info->v25.vram_module_num)
277 module_id = 0;
278 vram_module = (union vram_module *)vram_info->v25.vram_module;
279 while (i < module_id) {
280 vram_module = (union vram_module *)
281 ((u8 *)vram_module + vram_module->v11.vram_module_size);
282 i++;
283 }
284 mem_type = vram_module->v11.memory_type;
285 if (vram_type)
286 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
287 mem_channel_number = vram_module->v11.channel_num;
288 mem_channel_width = vram_module->v11.channel_width;
289 if (vram_width)
290 *vram_width = mem_channel_number * (1 << mem_channel_width);
291 mem_vendor = (vram_module->v11.vender_rev_id) & 0xF;
292 if (vram_vendor)
293 *vram_vendor = mem_vendor;
294 break;
295 default:
296 return -EINVAL;
297 }
298 }
299
300 }
301
302 return 0;
303}
304
305/*
306 * Return true if vbios enabled ecc by default, if umc info table is available
307 * or false if ecc is not enabled or umc info table is not available
308 */
309bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev)
310{
311 struct amdgpu_mode_info *mode_info = &adev->mode_info;
312 int index;
313 u16 data_offset, size;
314 union umc_info *umc_info;
315 u8 frev, crev;
316 bool ecc_default_enabled = false;
317
318 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
319 umc_info);
320
321 if (amdgpu_atom_parse_data_header(mode_info->atom_context,
322 index, &size, &frev, &crev, &data_offset)) {
323 /* support umc_info 3.1+ */
324 if ((frev == 3 && crev >= 1) || (frev > 3)) {
325 umc_info = (union umc_info *)
326 (mode_info->atom_context->bios + data_offset);
327 ecc_default_enabled =
328 (le32_to_cpu(umc_info->v31.umc_config) &
329 UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
330 }
331 }
332
333 return ecc_default_enabled;
334}
335
336union firmware_info {
337 struct atom_firmware_info_v3_1 v31;
338 struct atom_firmware_info_v3_2 v32;
339 struct atom_firmware_info_v3_3 v33;
340 struct atom_firmware_info_v3_4 v34;
341};
342
343/*
344 * Return true if vbios supports sram ecc or false if not
345 */
346bool amdgpu_atomfirmware_sram_ecc_supported(struct amdgpu_device *adev)
347{
348 struct amdgpu_mode_info *mode_info = &adev->mode_info;
349 int index;
350 u16 data_offset, size;
351 union firmware_info *firmware_info;
352 u8 frev, crev;
353 bool sram_ecc_supported = false;
354
355 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
356 firmwareinfo);
357
358 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context,
359 index, &size, &frev, &crev, &data_offset)) {
360 /* support firmware_info 3.1 + */
361 if ((frev == 3 && crev >=1) || (frev > 3)) {
362 firmware_info = (union firmware_info *)
363 (mode_info->atom_context->bios + data_offset);
364 sram_ecc_supported =
365 (le32_to_cpu(firmware_info->v31.firmware_capability) &
366 ATOM_FIRMWARE_CAP_SRAM_ECC) ? true : false;
367 }
368 }
369
370 return sram_ecc_supported;
371}
372
373union smu_info {
374 struct atom_smu_info_v3_1 v31;
375};
376
377int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev)
378{
379 struct amdgpu_mode_info *mode_info = &adev->mode_info;
380 struct amdgpu_pll *spll = &adev->clock.spll;
381 struct amdgpu_pll *mpll = &adev->clock.mpll;
382 uint8_t frev, crev;
383 uint16_t data_offset;
384 int ret = -EINVAL, index;
385
386 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
387 firmwareinfo);
388 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
389 &frev, &crev, &data_offset)) {
390 union firmware_info *firmware_info =
391 (union firmware_info *)(mode_info->atom_context->bios +
392 data_offset);
393
394 adev->clock.default_sclk =
395 le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz);
396 adev->clock.default_mclk =
397 le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz);
398
399 adev->pm.current_sclk = adev->clock.default_sclk;
400 adev->pm.current_mclk = adev->clock.default_mclk;
401
402 /* not technically a clock, but... */
403 adev->mode_info.firmware_flags =
404 le32_to_cpu(firmware_info->v31.firmware_capability);
405
406 ret = 0;
407 }
408
409 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
410 smu_info);
411 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
412 &frev, &crev, &data_offset)) {
413 union smu_info *smu_info =
414 (union smu_info *)(mode_info->atom_context->bios +
415 data_offset);
416
417 /* system clock */
418 spll->reference_freq = le32_to_cpu(smu_info->v31.core_refclk_10khz);
419
420 spll->reference_div = 0;
421 spll->min_post_div = 1;
422 spll->max_post_div = 1;
423 spll->min_ref_div = 2;
424 spll->max_ref_div = 0xff;
425 spll->min_feedback_div = 4;
426 spll->max_feedback_div = 0xff;
427 spll->best_vco = 0;
428
429 ret = 0;
430 }
431
432 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
433 umc_info);
434 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
435 &frev, &crev, &data_offset)) {
436 union umc_info *umc_info =
437 (union umc_info *)(mode_info->atom_context->bios +
438 data_offset);
439
440 /* memory clock */
441 mpll->reference_freq = le32_to_cpu(umc_info->v31.mem_refclk_10khz);
442
443 mpll->reference_div = 0;
444 mpll->min_post_div = 1;
445 mpll->max_post_div = 1;
446 mpll->min_ref_div = 2;
447 mpll->max_ref_div = 0xff;
448 mpll->min_feedback_div = 4;
449 mpll->max_feedback_div = 0xff;
450 mpll->best_vco = 0;
451
452 ret = 0;
453 }
454
455 return ret;
456}
457
458union gfx_info {
459 struct atom_gfx_info_v2_4 v24;
460};
461
462int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev)
463{
464 struct amdgpu_mode_info *mode_info = &adev->mode_info;
465 int index;
466 uint8_t frev, crev;
467 uint16_t data_offset;
468
469 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
470 gfx_info);
471 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
472 &frev, &crev, &data_offset)) {
473 union gfx_info *gfx_info = (union gfx_info *)
474 (mode_info->atom_context->bios + data_offset);
475 switch (crev) {
476 case 4:
477 adev->gfx.config.max_shader_engines = gfx_info->v24.max_shader_engines;
478 adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh;
479 adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se;
480 adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se;
481 adev->gfx.config.max_texture_channel_caches = gfx_info->v24.max_texture_channel_caches;
482 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs);
483 adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds;
484 adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth;
485 adev->gfx.config.gs_prim_buffer_depth =
486 le16_to_cpu(gfx_info->v24.gc_gsprim_buff_depth);
487 adev->gfx.config.double_offchip_lds_buf =
488 gfx_info->v24.gc_double_offchip_lds_buffer;
489 adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v24.gc_wave_size);
490 adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v24.gc_max_waves_per_simd);
491 adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v24.gc_max_scratch_slots_per_cu;
492 adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v24.gc_lds_size);
493 return 0;
494 default:
495 return -EINVAL;
496 }
497
498 }
499 return -EINVAL;
500}
501
502/*
503 * Check if VBIOS supports GDDR6 training data save/restore
504 */
505static bool gddr6_mem_train_vbios_support(struct amdgpu_device *adev)
506{
507 uint16_t data_offset;
508 int index;
509
510 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
511 firmwareinfo);
512 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
513 NULL, NULL, &data_offset)) {
514 struct atom_firmware_info_v3_1 *firmware_info =
515 (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
516 data_offset);
517
518 DRM_DEBUG("atom firmware capability:0x%08x.\n",
519 le32_to_cpu(firmware_info->firmware_capability));
520
521 if (le32_to_cpu(firmware_info->firmware_capability) &
522 ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING)
523 return true;
524 }
525
526 return false;
527}
528
529int amdgpu_mem_train_support(struct amdgpu_device *adev)
530{
531 int ret;
532 uint32_t major, minor, revision, hw_v;
533
534 if (gddr6_mem_train_vbios_support(adev)) {
535 amdgpu_discovery_get_ip_version(adev, MP0_HWID, &major, &minor, &revision);
536 hw_v = HW_REV(major, minor, revision);
537 /*
538 * treat 0 revision as a special case since register for MP0 and MMHUB is missing
539 * for some Navi10 A0, preventing driver from discovering the hwip information since
540 * none of the functions will be initialized, it should not cause any problems
541 */
542 switch (hw_v) {
543 case HW_REV(11, 0, 0):
544 case HW_REV(11, 0, 5):
545 case HW_REV(11, 0, 7):
546 ret = 1;
547 break;
548 default:
549 DRM_ERROR("memory training vbios supports but psp hw(%08x)"
550 " doesn't support!\n", hw_v);
551 ret = -1;
552 break;
553 }
554 } else {
555 ret = 0;
556 hw_v = -1;
557 }
558
559
560 DRM_DEBUG("mp0 hw_v %08x, ret:%d.\n", hw_v, ret);
561 return ret;
562}
563
564int amdgpu_atomfirmware_get_fw_reserved_fb_size(struct amdgpu_device *adev)
565{
566 struct atom_context *ctx = adev->mode_info.atom_context;
567 union firmware_info *firmware_info;
568 int index;
569 u16 data_offset, size;
570 u8 frev, crev;
571 int fw_reserved_fb_size;
572
573 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
574 firmwareinfo);
575
576 if (!amdgpu_atom_parse_data_header(ctx, index, &size,
577 &frev, &crev, &data_offset))
578 /* fail to parse data_header */
579 return 0;
580
581 firmware_info = (union firmware_info *)(ctx->bios + data_offset);
582
583 if (frev !=3)
584 return -EINVAL;
585
586 switch (crev) {
587 case 4:
588 fw_reserved_fb_size =
589 (firmware_info->v34.fw_reserved_size_in_kb << 10);
590 break;
591 default:
592 fw_reserved_fb_size = 0;
593 break;
594 }
595
596 return fw_reserved_fb_size;
597}
1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <drm/amdgpu_drm.h>
25#include "amdgpu.h"
26#include "atomfirmware.h"
27#include "amdgpu_atomfirmware.h"
28#include "atom.h"
29#include "atombios.h"
30#include "soc15_hw_ip.h"
31
32union firmware_info {
33 struct atom_firmware_info_v3_1 v31;
34 struct atom_firmware_info_v3_2 v32;
35 struct atom_firmware_info_v3_3 v33;
36 struct atom_firmware_info_v3_4 v34;
37};
38
39/*
40 * Helper function to query firmware capability
41 *
42 * @adev: amdgpu_device pointer
43 *
44 * Return firmware_capability in firmwareinfo table on success or 0 if not
45 */
46uint32_t amdgpu_atomfirmware_query_firmware_capability(struct amdgpu_device *adev)
47{
48 struct amdgpu_mode_info *mode_info = &adev->mode_info;
49 int index;
50 u16 data_offset, size;
51 union firmware_info *firmware_info;
52 u8 frev, crev;
53 u32 fw_cap = 0;
54
55 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
56 firmwareinfo);
57
58 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context,
59 index, &size, &frev, &crev, &data_offset)) {
60 /* support firmware_info 3.1 + */
61 if ((frev == 3 && crev >= 1) || (frev > 3)) {
62 firmware_info = (union firmware_info *)
63 (mode_info->atom_context->bios + data_offset);
64 fw_cap = le32_to_cpu(firmware_info->v31.firmware_capability);
65 }
66 }
67
68 return fw_cap;
69}
70
71/*
72 * Helper function to query gpu virtualizaiton capability
73 *
74 * @adev: amdgpu_device pointer
75 *
76 * Return true if gpu virtualization is supported or false if not
77 */
78bool amdgpu_atomfirmware_gpu_virtualization_supported(struct amdgpu_device *adev)
79{
80 u32 fw_cap;
81
82 fw_cap = adev->mode_info.firmware_flags;
83
84 return (fw_cap & ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION) ? true : false;
85}
86
87void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev)
88{
89 int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
90 firmwareinfo);
91 uint16_t data_offset;
92
93 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
94 NULL, NULL, &data_offset)) {
95 struct atom_firmware_info_v3_1 *firmware_info =
96 (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
97 data_offset);
98
99 adev->bios_scratch_reg_offset =
100 le32_to_cpu(firmware_info->bios_scratch_reg_startaddr);
101 }
102}
103
104static int amdgpu_atomfirmware_allocate_fb_v2_1(struct amdgpu_device *adev,
105 struct vram_usagebyfirmware_v2_1 *fw_usage, int *usage_bytes)
106{
107 u32 start_addr, fw_size, drv_size;
108
109 start_addr = le32_to_cpu(fw_usage->start_address_in_kb);
110 fw_size = le16_to_cpu(fw_usage->used_by_firmware_in_kb);
111 drv_size = le16_to_cpu(fw_usage->used_by_driver_in_kb);
112
113 DRM_DEBUG("atom firmware v2_1 requested %08x %dkb fw %dkb drv\n",
114 start_addr,
115 fw_size,
116 drv_size);
117
118 if ((start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) ==
119 (u32)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION <<
120 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) {
121 /* Firmware request VRAM reservation for SR-IOV */
122 adev->mman.fw_vram_usage_start_offset = (start_addr &
123 (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
124 adev->mman.fw_vram_usage_size = fw_size << 10;
125 /* Use the default scratch size */
126 *usage_bytes = 0;
127 } else {
128 *usage_bytes = drv_size << 10;
129 }
130 return 0;
131}
132
133static int amdgpu_atomfirmware_allocate_fb_v2_2(struct amdgpu_device *adev,
134 struct vram_usagebyfirmware_v2_2 *fw_usage, int *usage_bytes)
135{
136 u32 fw_start_addr, fw_size, drv_start_addr, drv_size;
137
138 fw_start_addr = le32_to_cpu(fw_usage->fw_region_start_address_in_kb);
139 fw_size = le16_to_cpu(fw_usage->used_by_firmware_in_kb);
140
141 drv_start_addr = le32_to_cpu(fw_usage->driver_region0_start_address_in_kb);
142 drv_size = le32_to_cpu(fw_usage->used_by_driver_region0_in_kb);
143
144 DRM_DEBUG("atom requested fw start at %08x %dkb and drv start at %08x %dkb\n",
145 fw_start_addr,
146 fw_size,
147 drv_start_addr,
148 drv_size);
149
150 if (amdgpu_sriov_vf(adev) &&
151 ((fw_start_addr & (ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION <<
152 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) == 0)) {
153 /* Firmware request VRAM reservation for SR-IOV */
154 adev->mman.fw_vram_usage_start_offset = (fw_start_addr &
155 (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
156 adev->mman.fw_vram_usage_size = fw_size << 10;
157 }
158
159 if (amdgpu_sriov_vf(adev) &&
160 ((drv_start_addr & (ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION <<
161 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) == 0)) {
162 /* driver request VRAM reservation for SR-IOV */
163 adev->mman.drv_vram_usage_start_offset = (drv_start_addr &
164 (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
165 adev->mman.drv_vram_usage_size = drv_size << 10;
166 }
167
168 *usage_bytes = 0;
169 return 0;
170}
171
172int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev)
173{
174 struct atom_context *ctx = adev->mode_info.atom_context;
175 int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
176 vram_usagebyfirmware);
177 struct vram_usagebyfirmware_v2_1 *fw_usage_v2_1;
178 struct vram_usagebyfirmware_v2_2 *fw_usage_v2_2;
179 u16 data_offset;
180 u8 frev, crev;
181 int usage_bytes = 0;
182
183 if (amdgpu_atom_parse_data_header(ctx, index, NULL, &frev, &crev, &data_offset)) {
184 if (frev == 2 && crev == 1) {
185 fw_usage_v2_1 =
186 (struct vram_usagebyfirmware_v2_1 *)(ctx->bios + data_offset);
187 amdgpu_atomfirmware_allocate_fb_v2_1(adev,
188 fw_usage_v2_1,
189 &usage_bytes);
190 } else if (frev >= 2 && crev >= 2) {
191 fw_usage_v2_2 =
192 (struct vram_usagebyfirmware_v2_2 *)(ctx->bios + data_offset);
193 amdgpu_atomfirmware_allocate_fb_v2_2(adev,
194 fw_usage_v2_2,
195 &usage_bytes);
196 }
197 }
198
199 ctx->scratch_size_bytes = 0;
200 if (usage_bytes == 0)
201 usage_bytes = 20 * 1024;
202 /* allocate some scratch memory */
203 ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
204 if (!ctx->scratch)
205 return -ENOMEM;
206 ctx->scratch_size_bytes = usage_bytes;
207 return 0;
208}
209
210union igp_info {
211 struct atom_integrated_system_info_v1_11 v11;
212 struct atom_integrated_system_info_v1_12 v12;
213 struct atom_integrated_system_info_v2_1 v21;
214};
215
216union umc_info {
217 struct atom_umc_info_v3_1 v31;
218 struct atom_umc_info_v3_2 v32;
219 struct atom_umc_info_v3_3 v33;
220 struct atom_umc_info_v4_0 v40;
221};
222
223union vram_info {
224 struct atom_vram_info_header_v2_3 v23;
225 struct atom_vram_info_header_v2_4 v24;
226 struct atom_vram_info_header_v2_5 v25;
227 struct atom_vram_info_header_v2_6 v26;
228 struct atom_vram_info_header_v3_0 v30;
229};
230
231union vram_module {
232 struct atom_vram_module_v9 v9;
233 struct atom_vram_module_v10 v10;
234 struct atom_vram_module_v11 v11;
235 struct atom_vram_module_v3_0 v30;
236};
237
238static int convert_atom_mem_type_to_vram_type(struct amdgpu_device *adev,
239 int atom_mem_type)
240{
241 int vram_type;
242
243 if (adev->flags & AMD_IS_APU) {
244 switch (atom_mem_type) {
245 case Ddr2MemType:
246 case LpDdr2MemType:
247 vram_type = AMDGPU_VRAM_TYPE_DDR2;
248 break;
249 case Ddr3MemType:
250 case LpDdr3MemType:
251 vram_type = AMDGPU_VRAM_TYPE_DDR3;
252 break;
253 case Ddr4MemType:
254 vram_type = AMDGPU_VRAM_TYPE_DDR4;
255 break;
256 case LpDdr4MemType:
257 vram_type = AMDGPU_VRAM_TYPE_LPDDR4;
258 break;
259 case Ddr5MemType:
260 vram_type = AMDGPU_VRAM_TYPE_DDR5;
261 break;
262 case LpDdr5MemType:
263 vram_type = AMDGPU_VRAM_TYPE_LPDDR5;
264 break;
265 default:
266 vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
267 break;
268 }
269 } else {
270 switch (atom_mem_type) {
271 case ATOM_DGPU_VRAM_TYPE_GDDR5:
272 vram_type = AMDGPU_VRAM_TYPE_GDDR5;
273 break;
274 case ATOM_DGPU_VRAM_TYPE_HBM2:
275 case ATOM_DGPU_VRAM_TYPE_HBM2E:
276 case ATOM_DGPU_VRAM_TYPE_HBM3:
277 vram_type = AMDGPU_VRAM_TYPE_HBM;
278 break;
279 case ATOM_DGPU_VRAM_TYPE_GDDR6:
280 vram_type = AMDGPU_VRAM_TYPE_GDDR6;
281 break;
282 default:
283 vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
284 break;
285 }
286 }
287
288 return vram_type;
289}
290
291
292int
293amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
294 int *vram_width, int *vram_type,
295 int *vram_vendor)
296{
297 struct amdgpu_mode_info *mode_info = &adev->mode_info;
298 int index, i = 0;
299 u16 data_offset, size;
300 union igp_info *igp_info;
301 union vram_info *vram_info;
302 union vram_module *vram_module;
303 u8 frev, crev;
304 u8 mem_type;
305 u8 mem_vendor;
306 u32 mem_channel_number;
307 u32 mem_channel_width;
308 u32 module_id;
309
310 if (adev->flags & AMD_IS_APU)
311 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
312 integratedsysteminfo);
313 else
314 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
315 vram_info);
316
317 if (amdgpu_atom_parse_data_header(mode_info->atom_context,
318 index, &size,
319 &frev, &crev, &data_offset)) {
320 if (adev->flags & AMD_IS_APU) {
321 igp_info = (union igp_info *)
322 (mode_info->atom_context->bios + data_offset);
323 switch (frev) {
324 case 1:
325 switch (crev) {
326 case 11:
327 case 12:
328 mem_channel_number = igp_info->v11.umachannelnumber;
329 if (!mem_channel_number)
330 mem_channel_number = 1;
331 mem_type = igp_info->v11.memorytype;
332 if (mem_type == LpDdr5MemType)
333 mem_channel_width = 32;
334 else
335 mem_channel_width = 64;
336 if (vram_width)
337 *vram_width = mem_channel_number * mem_channel_width;
338 if (vram_type)
339 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
340 break;
341 default:
342 return -EINVAL;
343 }
344 break;
345 case 2:
346 switch (crev) {
347 case 1:
348 case 2:
349 mem_channel_number = igp_info->v21.umachannelnumber;
350 if (!mem_channel_number)
351 mem_channel_number = 1;
352 mem_type = igp_info->v21.memorytype;
353 if (mem_type == LpDdr5MemType)
354 mem_channel_width = 32;
355 else
356 mem_channel_width = 64;
357 if (vram_width)
358 *vram_width = mem_channel_number * mem_channel_width;
359 if (vram_type)
360 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
361 break;
362 default:
363 return -EINVAL;
364 }
365 break;
366 default:
367 return -EINVAL;
368 }
369 } else {
370 vram_info = (union vram_info *)
371 (mode_info->atom_context->bios + data_offset);
372 module_id = (RREG32(adev->bios_scratch_reg_offset + 4) & 0x00ff0000) >> 16;
373 if (frev == 3) {
374 switch (crev) {
375 /* v30 */
376 case 0:
377 vram_module = (union vram_module *)vram_info->v30.vram_module;
378 mem_vendor = (vram_module->v30.dram_vendor_id) & 0xF;
379 if (vram_vendor)
380 *vram_vendor = mem_vendor;
381 mem_type = vram_info->v30.memory_type;
382 if (vram_type)
383 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
384 mem_channel_number = vram_info->v30.channel_num;
385 mem_channel_width = vram_info->v30.channel_width;
386 if (vram_width)
387 *vram_width = mem_channel_number * (1 << mem_channel_width);
388 break;
389 default:
390 return -EINVAL;
391 }
392 } else if (frev == 2) {
393 switch (crev) {
394 /* v23 */
395 case 3:
396 if (module_id > vram_info->v23.vram_module_num)
397 module_id = 0;
398 vram_module = (union vram_module *)vram_info->v23.vram_module;
399 while (i < module_id) {
400 vram_module = (union vram_module *)
401 ((u8 *)vram_module + vram_module->v9.vram_module_size);
402 i++;
403 }
404 mem_type = vram_module->v9.memory_type;
405 if (vram_type)
406 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
407 mem_channel_number = vram_module->v9.channel_num;
408 mem_channel_width = vram_module->v9.channel_width;
409 if (vram_width)
410 *vram_width = mem_channel_number * (1 << mem_channel_width);
411 mem_vendor = (vram_module->v9.vender_rev_id) & 0xF;
412 if (vram_vendor)
413 *vram_vendor = mem_vendor;
414 break;
415 /* v24 */
416 case 4:
417 if (module_id > vram_info->v24.vram_module_num)
418 module_id = 0;
419 vram_module = (union vram_module *)vram_info->v24.vram_module;
420 while (i < module_id) {
421 vram_module = (union vram_module *)
422 ((u8 *)vram_module + vram_module->v10.vram_module_size);
423 i++;
424 }
425 mem_type = vram_module->v10.memory_type;
426 if (vram_type)
427 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
428 mem_channel_number = vram_module->v10.channel_num;
429 mem_channel_width = vram_module->v10.channel_width;
430 if (vram_width)
431 *vram_width = mem_channel_number * (1 << mem_channel_width);
432 mem_vendor = (vram_module->v10.vender_rev_id) & 0xF;
433 if (vram_vendor)
434 *vram_vendor = mem_vendor;
435 break;
436 /* v25 */
437 case 5:
438 if (module_id > vram_info->v25.vram_module_num)
439 module_id = 0;
440 vram_module = (union vram_module *)vram_info->v25.vram_module;
441 while (i < module_id) {
442 vram_module = (union vram_module *)
443 ((u8 *)vram_module + vram_module->v11.vram_module_size);
444 i++;
445 }
446 mem_type = vram_module->v11.memory_type;
447 if (vram_type)
448 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
449 mem_channel_number = vram_module->v11.channel_num;
450 mem_channel_width = vram_module->v11.channel_width;
451 if (vram_width)
452 *vram_width = mem_channel_number * (1 << mem_channel_width);
453 mem_vendor = (vram_module->v11.vender_rev_id) & 0xF;
454 if (vram_vendor)
455 *vram_vendor = mem_vendor;
456 break;
457 /* v26 */
458 case 6:
459 if (module_id > vram_info->v26.vram_module_num)
460 module_id = 0;
461 vram_module = (union vram_module *)vram_info->v26.vram_module;
462 while (i < module_id) {
463 vram_module = (union vram_module *)
464 ((u8 *)vram_module + vram_module->v9.vram_module_size);
465 i++;
466 }
467 mem_type = vram_module->v9.memory_type;
468 if (vram_type)
469 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
470 mem_channel_number = vram_module->v9.channel_num;
471 mem_channel_width = vram_module->v9.channel_width;
472 if (vram_width)
473 *vram_width = mem_channel_number * (1 << mem_channel_width);
474 mem_vendor = (vram_module->v9.vender_rev_id) & 0xF;
475 if (vram_vendor)
476 *vram_vendor = mem_vendor;
477 break;
478 default:
479 return -EINVAL;
480 }
481 } else {
482 /* invalid frev */
483 return -EINVAL;
484 }
485 }
486
487 }
488
489 return 0;
490}
491
492/*
493 * Return true if vbios enabled ecc by default, if umc info table is available
494 * or false if ecc is not enabled or umc info table is not available
495 */
496bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev)
497{
498 struct amdgpu_mode_info *mode_info = &adev->mode_info;
499 int index;
500 u16 data_offset, size;
501 union umc_info *umc_info;
502 u8 frev, crev;
503 bool ecc_default_enabled = false;
504 u8 umc_config;
505 u32 umc_config1;
506
507 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
508 umc_info);
509
510 if (amdgpu_atom_parse_data_header(mode_info->atom_context,
511 index, &size, &frev, &crev, &data_offset)) {
512 umc_info = (union umc_info *)(mode_info->atom_context->bios + data_offset);
513 if (frev == 3) {
514 switch (crev) {
515 case 1:
516 umc_config = le32_to_cpu(umc_info->v31.umc_config);
517 ecc_default_enabled =
518 (umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
519 break;
520 case 2:
521 umc_config = le32_to_cpu(umc_info->v32.umc_config);
522 ecc_default_enabled =
523 (umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
524 break;
525 case 3:
526 umc_config = le32_to_cpu(umc_info->v33.umc_config);
527 umc_config1 = le32_to_cpu(umc_info->v33.umc_config1);
528 ecc_default_enabled =
529 ((umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ||
530 (umc_config1 & UMC_CONFIG1__ENABLE_ECC_CAPABLE)) ? true : false;
531 break;
532 default:
533 /* unsupported crev */
534 return false;
535 }
536 } else if (frev == 4) {
537 switch (crev) {
538 case 0:
539 umc_config1 = le32_to_cpu(umc_info->v40.umc_config1);
540 ecc_default_enabled =
541 (umc_config1 & UMC_CONFIG1__ENABLE_ECC_CAPABLE) ? true : false;
542 break;
543 default:
544 /* unsupported crev */
545 return false;
546 }
547 } else {
548 /* unsupported frev */
549 return false;
550 }
551 }
552
553 return ecc_default_enabled;
554}
555
556/*
557 * Helper function to query sram ecc capablity
558 *
559 * @adev: amdgpu_device pointer
560 *
561 * Return true if vbios supports sram ecc or false if not
562 */
563bool amdgpu_atomfirmware_sram_ecc_supported(struct amdgpu_device *adev)
564{
565 u32 fw_cap;
566
567 fw_cap = adev->mode_info.firmware_flags;
568
569 return (fw_cap & ATOM_FIRMWARE_CAP_SRAM_ECC) ? true : false;
570}
571
572/*
573 * Helper function to query dynamic boot config capability
574 *
575 * @adev: amdgpu_device pointer
576 *
577 * Return true if vbios supports dynamic boot config or false if not
578 */
579bool amdgpu_atomfirmware_dynamic_boot_config_supported(struct amdgpu_device *adev)
580{
581 u32 fw_cap;
582
583 fw_cap = adev->mode_info.firmware_flags;
584
585 return (fw_cap & ATOM_FIRMWARE_CAP_DYNAMIC_BOOT_CFG_ENABLE) ? true : false;
586}
587
588/**
589 * amdgpu_atomfirmware_ras_rom_addr -- Get the RAS EEPROM addr from VBIOS
590 * @adev: amdgpu_device pointer
591 * @i2c_address: pointer to u8; if not NULL, will contain
592 * the RAS EEPROM address if the function returns true
593 *
594 * Return true if VBIOS supports RAS EEPROM address reporting,
595 * else return false. If true and @i2c_address is not NULL,
596 * will contain the RAS ROM address.
597 */
598bool amdgpu_atomfirmware_ras_rom_addr(struct amdgpu_device *adev,
599 u8 *i2c_address)
600{
601 struct amdgpu_mode_info *mode_info = &adev->mode_info;
602 int index;
603 u16 data_offset, size;
604 union firmware_info *firmware_info;
605 u8 frev, crev;
606
607 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
608 firmwareinfo);
609
610 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context,
611 index, &size, &frev, &crev,
612 &data_offset)) {
613 /* support firmware_info 3.4 + */
614 if ((frev == 3 && crev >= 4) || (frev > 3)) {
615 firmware_info = (union firmware_info *)
616 (mode_info->atom_context->bios + data_offset);
617 /* The ras_rom_i2c_slave_addr should ideally
618 * be a 19-bit EEPROM address, which would be
619 * used as is by the driver; see top of
620 * amdgpu_eeprom.c.
621 *
622 * When this is the case, 0 is of course a
623 * valid RAS EEPROM address, in which case,
624 * we'll drop the first "if (firm...)" and only
625 * leave the check for the pointer.
626 *
627 * The reason this works right now is because
628 * ras_rom_i2c_slave_addr contains the EEPROM
629 * device type qualifier 1010b in the top 4
630 * bits.
631 */
632 if (firmware_info->v34.ras_rom_i2c_slave_addr) {
633 if (i2c_address)
634 *i2c_address = firmware_info->v34.ras_rom_i2c_slave_addr;
635 return true;
636 }
637 }
638 }
639
640 return false;
641}
642
643
644union smu_info {
645 struct atom_smu_info_v3_1 v31;
646 struct atom_smu_info_v4_0 v40;
647};
648
649union gfx_info {
650 struct atom_gfx_info_v2_2 v22;
651 struct atom_gfx_info_v2_4 v24;
652 struct atom_gfx_info_v2_7 v27;
653 struct atom_gfx_info_v3_0 v30;
654};
655
656int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev)
657{
658 struct amdgpu_mode_info *mode_info = &adev->mode_info;
659 struct amdgpu_pll *spll = &adev->clock.spll;
660 struct amdgpu_pll *mpll = &adev->clock.mpll;
661 uint8_t frev, crev;
662 uint16_t data_offset;
663 int ret = -EINVAL, index;
664
665 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
666 firmwareinfo);
667 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
668 &frev, &crev, &data_offset)) {
669 union firmware_info *firmware_info =
670 (union firmware_info *)(mode_info->atom_context->bios +
671 data_offset);
672
673 adev->clock.default_sclk =
674 le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz);
675 adev->clock.default_mclk =
676 le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz);
677
678 adev->pm.current_sclk = adev->clock.default_sclk;
679 adev->pm.current_mclk = adev->clock.default_mclk;
680
681 ret = 0;
682 }
683
684 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
685 smu_info);
686 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
687 &frev, &crev, &data_offset)) {
688 union smu_info *smu_info =
689 (union smu_info *)(mode_info->atom_context->bios +
690 data_offset);
691
692 /* system clock */
693 if (frev == 3)
694 spll->reference_freq = le32_to_cpu(smu_info->v31.core_refclk_10khz);
695 else if (frev == 4)
696 spll->reference_freq = le32_to_cpu(smu_info->v40.core_refclk_10khz);
697
698 spll->reference_div = 0;
699 spll->min_post_div = 1;
700 spll->max_post_div = 1;
701 spll->min_ref_div = 2;
702 spll->max_ref_div = 0xff;
703 spll->min_feedback_div = 4;
704 spll->max_feedback_div = 0xff;
705 spll->best_vco = 0;
706
707 ret = 0;
708 }
709
710 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
711 umc_info);
712 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
713 &frev, &crev, &data_offset)) {
714 union umc_info *umc_info =
715 (union umc_info *)(mode_info->atom_context->bios +
716 data_offset);
717
718 /* memory clock */
719 mpll->reference_freq = le32_to_cpu(umc_info->v31.mem_refclk_10khz);
720
721 mpll->reference_div = 0;
722 mpll->min_post_div = 1;
723 mpll->max_post_div = 1;
724 mpll->min_ref_div = 2;
725 mpll->max_ref_div = 0xff;
726 mpll->min_feedback_div = 4;
727 mpll->max_feedback_div = 0xff;
728 mpll->best_vco = 0;
729
730 ret = 0;
731 }
732
733 /* if asic is Navi+, the rlc reference clock is used for system clock
734 * from vbios gfx_info table */
735 if (adev->asic_type >= CHIP_NAVI10) {
736 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
737 gfx_info);
738 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
739 &frev, &crev, &data_offset)) {
740 union gfx_info *gfx_info = (union gfx_info *)
741 (mode_info->atom_context->bios + data_offset);
742 if ((frev == 3) ||
743 (frev == 2 && crev == 6)) {
744 spll->reference_freq = le32_to_cpu(gfx_info->v30.golden_tsc_count_lower_refclk);
745 ret = 0;
746 } else if ((frev == 2) &&
747 (crev >= 2) &&
748 (crev != 6)) {
749 spll->reference_freq = le32_to_cpu(gfx_info->v22.rlc_gpu_timer_refclk);
750 ret = 0;
751 } else {
752 BUG();
753 }
754 }
755 }
756
757 return ret;
758}
759
760int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev)
761{
762 struct amdgpu_mode_info *mode_info = &adev->mode_info;
763 int index;
764 uint8_t frev, crev;
765 uint16_t data_offset;
766
767 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
768 gfx_info);
769 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
770 &frev, &crev, &data_offset)) {
771 union gfx_info *gfx_info = (union gfx_info *)
772 (mode_info->atom_context->bios + data_offset);
773 if (frev == 2) {
774 switch (crev) {
775 case 4:
776 adev->gfx.config.max_shader_engines = gfx_info->v24.max_shader_engines;
777 adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh;
778 adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se;
779 adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se;
780 adev->gfx.config.max_texture_channel_caches = gfx_info->v24.max_texture_channel_caches;
781 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs);
782 adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds;
783 adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth;
784 adev->gfx.config.gs_prim_buffer_depth =
785 le16_to_cpu(gfx_info->v24.gc_gsprim_buff_depth);
786 adev->gfx.config.double_offchip_lds_buf =
787 gfx_info->v24.gc_double_offchip_lds_buffer;
788 adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v24.gc_wave_size);
789 adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v24.gc_max_waves_per_simd);
790 adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v24.gc_max_scratch_slots_per_cu;
791 adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v24.gc_lds_size);
792 return 0;
793 case 7:
794 adev->gfx.config.max_shader_engines = gfx_info->v27.max_shader_engines;
795 adev->gfx.config.max_cu_per_sh = gfx_info->v27.max_cu_per_sh;
796 adev->gfx.config.max_sh_per_se = gfx_info->v27.max_sh_per_se;
797 adev->gfx.config.max_backends_per_se = gfx_info->v27.max_backends_per_se;
798 adev->gfx.config.max_texture_channel_caches = gfx_info->v27.max_texture_channel_caches;
799 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v27.gc_num_gprs);
800 adev->gfx.config.max_gs_threads = gfx_info->v27.gc_num_max_gs_thds;
801 adev->gfx.config.gs_vgt_table_depth = gfx_info->v27.gc_gs_table_depth;
802 adev->gfx.config.gs_prim_buffer_depth = le16_to_cpu(gfx_info->v27.gc_gsprim_buff_depth);
803 adev->gfx.config.double_offchip_lds_buf = gfx_info->v27.gc_double_offchip_lds_buffer;
804 adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v27.gc_wave_size);
805 adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v27.gc_max_waves_per_simd);
806 adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v27.gc_max_scratch_slots_per_cu;
807 adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v27.gc_lds_size);
808 return 0;
809 default:
810 return -EINVAL;
811 }
812 } else if (frev == 3) {
813 switch (crev) {
814 case 0:
815 adev->gfx.config.max_shader_engines = gfx_info->v30.max_shader_engines;
816 adev->gfx.config.max_cu_per_sh = gfx_info->v30.max_cu_per_sh;
817 adev->gfx.config.max_sh_per_se = gfx_info->v30.max_sh_per_se;
818 adev->gfx.config.max_backends_per_se = gfx_info->v30.max_backends_per_se;
819 adev->gfx.config.max_texture_channel_caches = gfx_info->v30.max_texture_channel_caches;
820 return 0;
821 default:
822 return -EINVAL;
823 }
824 } else {
825 return -EINVAL;
826 }
827
828 }
829 return -EINVAL;
830}
831
832/*
833 * Helper function to query two stage mem training capability
834 *
835 * @adev: amdgpu_device pointer
836 *
837 * Return true if two stage mem training is supported or false if not
838 */
839bool amdgpu_atomfirmware_mem_training_supported(struct amdgpu_device *adev)
840{
841 u32 fw_cap;
842
843 fw_cap = adev->mode_info.firmware_flags;
844
845 return (fw_cap & ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING) ? true : false;
846}
847
848int amdgpu_atomfirmware_get_fw_reserved_fb_size(struct amdgpu_device *adev)
849{
850 struct atom_context *ctx = adev->mode_info.atom_context;
851 union firmware_info *firmware_info;
852 int index;
853 u16 data_offset, size;
854 u8 frev, crev;
855 int fw_reserved_fb_size;
856
857 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
858 firmwareinfo);
859
860 if (!amdgpu_atom_parse_data_header(ctx, index, &size,
861 &frev, &crev, &data_offset))
862 /* fail to parse data_header */
863 return 0;
864
865 firmware_info = (union firmware_info *)(ctx->bios + data_offset);
866
867 if (frev != 3)
868 return -EINVAL;
869
870 switch (crev) {
871 case 4:
872 fw_reserved_fb_size =
873 (firmware_info->v34.fw_reserved_size_in_kb << 10);
874 break;
875 default:
876 fw_reserved_fb_size = 0;
877 break;
878 }
879
880 return fw_reserved_fb_size;
881}
882
883/*
884 * Helper function to execute asic_init table
885 *
886 * @adev: amdgpu_device pointer
887 * @fb_reset: flag to indicate whether fb is reset or not
888 *
889 * Return 0 if succeed, otherwise failed
890 */
891int amdgpu_atomfirmware_asic_init(struct amdgpu_device *adev, bool fb_reset)
892{
893 struct amdgpu_mode_info *mode_info = &adev->mode_info;
894 struct atom_context *ctx;
895 uint8_t frev, crev;
896 uint16_t data_offset;
897 uint32_t bootup_sclk_in10khz, bootup_mclk_in10khz;
898 struct asic_init_ps_allocation_v2_1 asic_init_ps_v2_1;
899 int index;
900
901 if (!mode_info)
902 return -EINVAL;
903
904 ctx = mode_info->atom_context;
905 if (!ctx)
906 return -EINVAL;
907
908 /* query bootup sclk/mclk from firmware_info table */
909 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
910 firmwareinfo);
911 if (amdgpu_atom_parse_data_header(ctx, index, NULL,
912 &frev, &crev, &data_offset)) {
913 union firmware_info *firmware_info =
914 (union firmware_info *)(ctx->bios +
915 data_offset);
916
917 bootup_sclk_in10khz =
918 le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz);
919 bootup_mclk_in10khz =
920 le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz);
921 } else {
922 return -EINVAL;
923 }
924
925 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
926 asic_init);
927 if (amdgpu_atom_parse_cmd_header(mode_info->atom_context, index, &frev, &crev)) {
928 if (frev == 2 && crev >= 1) {
929 memset(&asic_init_ps_v2_1, 0, sizeof(asic_init_ps_v2_1));
930 asic_init_ps_v2_1.param.engineparam.sclkfreqin10khz = bootup_sclk_in10khz;
931 asic_init_ps_v2_1.param.memparam.mclkfreqin10khz = bootup_mclk_in10khz;
932 asic_init_ps_v2_1.param.engineparam.engineflag = b3NORMAL_ENGINE_INIT;
933 if (!fb_reset)
934 asic_init_ps_v2_1.param.memparam.memflag = b3DRAM_SELF_REFRESH_EXIT;
935 else
936 asic_init_ps_v2_1.param.memparam.memflag = 0;
937 } else {
938 return -EINVAL;
939 }
940 } else {
941 return -EINVAL;
942 }
943
944 return amdgpu_atom_execute_table(ctx, ATOM_CMD_INIT, (uint32_t *)&asic_init_ps_v2_1,
945 sizeof(asic_init_ps_v2_1));
946}