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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2016-2017 NVIDIA Corporation
4 *
5 * Author: Thierry Reding <treding@nvidia.com>
6 */
7
8#include <linux/gpio/driver.h>
9#include <linux/interrupt.h>
10#include <linux/irq.h>
11#include <linux/module.h>
12#include <linux/of_device.h>
13#include <linux/platform_device.h>
14
15#include <dt-bindings/gpio/tegra186-gpio.h>
16#include <dt-bindings/gpio/tegra194-gpio.h>
17
18/* security registers */
19#define TEGRA186_GPIO_CTL_SCR 0x0c
20#define TEGRA186_GPIO_CTL_SCR_SEC_WEN BIT(28)
21#define TEGRA186_GPIO_CTL_SCR_SEC_REN BIT(27)
22
23#define TEGRA186_GPIO_INT_ROUTE_MAPPING(p, x) (0x14 + (p) * 0x20 + (x) * 4)
24
25/* control registers */
26#define TEGRA186_GPIO_ENABLE_CONFIG 0x00
27#define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0)
28#define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1)
29#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2)
30#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2)
31#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2)
32#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2)
33#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2)
34#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4)
35#define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE BIT(5)
36#define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6)
37
38#define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04
39#define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff)
40
41#define TEGRA186_GPIO_INPUT 0x08
42#define TEGRA186_GPIO_INPUT_HIGH BIT(0)
43
44#define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c
45#define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0)
46
47#define TEGRA186_GPIO_OUTPUT_VALUE 0x10
48#define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0)
49
50#define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14
51
52#define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4)
53
54struct tegra_gpio_port {
55 const char *name;
56 unsigned int bank;
57 unsigned int port;
58 unsigned int pins;
59};
60
61struct tegra186_pin_range {
62 unsigned int offset;
63 const char *group;
64};
65
66struct tegra_gpio_soc {
67 const struct tegra_gpio_port *ports;
68 unsigned int num_ports;
69 const char *name;
70 unsigned int instance;
71
72 const struct tegra186_pin_range *pin_ranges;
73 unsigned int num_pin_ranges;
74 const char *pinmux;
75};
76
77struct tegra_gpio {
78 struct gpio_chip gpio;
79 struct irq_chip intc;
80 unsigned int num_irq;
81 unsigned int *irq;
82
83 const struct tegra_gpio_soc *soc;
84
85 void __iomem *secure;
86 void __iomem *base;
87};
88
89static const struct tegra_gpio_port *
90tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin)
91{
92 unsigned int start = 0, i;
93
94 for (i = 0; i < gpio->soc->num_ports; i++) {
95 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
96
97 if (*pin >= start && *pin < start + port->pins) {
98 *pin -= start;
99 return port;
100 }
101
102 start += port->pins;
103 }
104
105 return NULL;
106}
107
108static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio,
109 unsigned int pin)
110{
111 const struct tegra_gpio_port *port;
112 unsigned int offset;
113
114 port = tegra186_gpio_get_port(gpio, &pin);
115 if (!port)
116 return NULL;
117
118 offset = port->bank * 0x1000 + port->port * 0x200;
119
120 return gpio->base + offset + pin * 0x20;
121}
122
123static int tegra186_gpio_get_direction(struct gpio_chip *chip,
124 unsigned int offset)
125{
126 struct tegra_gpio *gpio = gpiochip_get_data(chip);
127 void __iomem *base;
128 u32 value;
129
130 base = tegra186_gpio_get_base(gpio, offset);
131 if (WARN_ON(base == NULL))
132 return -ENODEV;
133
134 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
135 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
136 return GPIO_LINE_DIRECTION_OUT;
137
138 return GPIO_LINE_DIRECTION_IN;
139}
140
141static int tegra186_gpio_direction_input(struct gpio_chip *chip,
142 unsigned int offset)
143{
144 struct tegra_gpio *gpio = gpiochip_get_data(chip);
145 void __iomem *base;
146 u32 value;
147
148 base = tegra186_gpio_get_base(gpio, offset);
149 if (WARN_ON(base == NULL))
150 return -ENODEV;
151
152 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
153 value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
154 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
155
156 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
157 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
158 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT;
159 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
160
161 return 0;
162}
163
164static int tegra186_gpio_direction_output(struct gpio_chip *chip,
165 unsigned int offset, int level)
166{
167 struct tegra_gpio *gpio = gpiochip_get_data(chip);
168 void __iomem *base;
169 u32 value;
170
171 /* configure output level first */
172 chip->set(chip, offset, level);
173
174 base = tegra186_gpio_get_base(gpio, offset);
175 if (WARN_ON(base == NULL))
176 return -EINVAL;
177
178 /* set the direction */
179 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
180 value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
181 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
182
183 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
184 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
185 value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT;
186 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
187
188 return 0;
189}
190
191static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset)
192{
193 struct tegra_gpio *gpio = gpiochip_get_data(chip);
194 void __iomem *base;
195 u32 value;
196
197 base = tegra186_gpio_get_base(gpio, offset);
198 if (WARN_ON(base == NULL))
199 return -ENODEV;
200
201 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
202 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
203 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
204 else
205 value = readl(base + TEGRA186_GPIO_INPUT);
206
207 return value & BIT(0);
208}
209
210static void tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset,
211 int level)
212{
213 struct tegra_gpio *gpio = gpiochip_get_data(chip);
214 void __iomem *base;
215 u32 value;
216
217 base = tegra186_gpio_get_base(gpio, offset);
218 if (WARN_ON(base == NULL))
219 return;
220
221 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
222 if (level == 0)
223 value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
224 else
225 value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
226
227 writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE);
228}
229
230static int tegra186_gpio_set_config(struct gpio_chip *chip,
231 unsigned int offset,
232 unsigned long config)
233{
234 struct tegra_gpio *gpio = gpiochip_get_data(chip);
235 u32 debounce, value;
236 void __iomem *base;
237
238 base = tegra186_gpio_get_base(gpio, offset);
239 if (base == NULL)
240 return -ENXIO;
241
242 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
243 return -ENOTSUPP;
244
245 debounce = pinconf_to_config_argument(config);
246
247 /*
248 * The Tegra186 GPIO controller supports a maximum of 255 ms debounce
249 * time.
250 */
251 if (debounce > 255000)
252 return -EINVAL;
253
254 debounce = DIV_ROUND_UP(debounce, USEC_PER_MSEC);
255
256 value = TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(debounce);
257 writel(value, base + TEGRA186_GPIO_DEBOUNCE_CONTROL);
258
259 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
260 value |= TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE;
261 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
262
263 return 0;
264}
265
266static int tegra186_gpio_add_pin_ranges(struct gpio_chip *chip)
267{
268 struct tegra_gpio *gpio = gpiochip_get_data(chip);
269 struct pinctrl_dev *pctldev;
270 struct device_node *np;
271 unsigned int i, j;
272 int err;
273
274 if (!gpio->soc->pinmux || gpio->soc->num_pin_ranges == 0)
275 return 0;
276
277 np = of_find_compatible_node(NULL, NULL, gpio->soc->pinmux);
278 if (!np)
279 return -ENODEV;
280
281 pctldev = of_pinctrl_get(np);
282 of_node_put(np);
283 if (!pctldev)
284 return -EPROBE_DEFER;
285
286 for (i = 0; i < gpio->soc->num_pin_ranges; i++) {
287 unsigned int pin = gpio->soc->pin_ranges[i].offset, port;
288 const char *group = gpio->soc->pin_ranges[i].group;
289
290 port = pin / 8;
291 pin = pin % 8;
292
293 if (port >= gpio->soc->num_ports) {
294 dev_warn(chip->parent, "invalid port %u for %s\n",
295 port, group);
296 continue;
297 }
298
299 for (j = 0; j < port; j++)
300 pin += gpio->soc->ports[j].pins;
301
302 err = gpiochip_add_pingroup_range(chip, pctldev, pin, group);
303 if (err < 0)
304 return err;
305 }
306
307 return 0;
308}
309
310static int tegra186_gpio_of_xlate(struct gpio_chip *chip,
311 const struct of_phandle_args *spec,
312 u32 *flags)
313{
314 struct tegra_gpio *gpio = gpiochip_get_data(chip);
315 unsigned int port, pin, i, offset = 0;
316
317 if (WARN_ON(chip->of_gpio_n_cells < 2))
318 return -EINVAL;
319
320 if (WARN_ON(spec->args_count < chip->of_gpio_n_cells))
321 return -EINVAL;
322
323 port = spec->args[0] / 8;
324 pin = spec->args[0] % 8;
325
326 if (port >= gpio->soc->num_ports) {
327 dev_err(chip->parent, "invalid port number: %u\n", port);
328 return -EINVAL;
329 }
330
331 for (i = 0; i < port; i++)
332 offset += gpio->soc->ports[i].pins;
333
334 if (flags)
335 *flags = spec->args[1];
336
337 return offset + pin;
338}
339
340static void tegra186_irq_ack(struct irq_data *data)
341{
342 struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data);
343 void __iomem *base;
344
345 base = tegra186_gpio_get_base(gpio, data->hwirq);
346 if (WARN_ON(base == NULL))
347 return;
348
349 writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR);
350}
351
352static void tegra186_irq_mask(struct irq_data *data)
353{
354 struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data);
355 void __iomem *base;
356 u32 value;
357
358 base = tegra186_gpio_get_base(gpio, data->hwirq);
359 if (WARN_ON(base == NULL))
360 return;
361
362 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
363 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
364 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
365}
366
367static void tegra186_irq_unmask(struct irq_data *data)
368{
369 struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data);
370 void __iomem *base;
371 u32 value;
372
373 base = tegra186_gpio_get_base(gpio, data->hwirq);
374 if (WARN_ON(base == NULL))
375 return;
376
377 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
378 value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
379 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
380}
381
382static int tegra186_irq_set_type(struct irq_data *data, unsigned int type)
383{
384 struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data);
385 void __iomem *base;
386 u32 value;
387
388 base = tegra186_gpio_get_base(gpio, data->hwirq);
389 if (WARN_ON(base == NULL))
390 return -ENODEV;
391
392 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
393 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK;
394 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
395
396 switch (type & IRQ_TYPE_SENSE_MASK) {
397 case IRQ_TYPE_NONE:
398 break;
399
400 case IRQ_TYPE_EDGE_RISING:
401 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
402 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
403 break;
404
405 case IRQ_TYPE_EDGE_FALLING:
406 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
407 break;
408
409 case IRQ_TYPE_EDGE_BOTH:
410 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
411 break;
412
413 case IRQ_TYPE_LEVEL_HIGH:
414 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
415 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
416 break;
417
418 case IRQ_TYPE_LEVEL_LOW:
419 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
420 break;
421
422 default:
423 return -EINVAL;
424 }
425
426 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
427
428 if ((type & IRQ_TYPE_EDGE_BOTH) == 0)
429 irq_set_handler_locked(data, handle_level_irq);
430 else
431 irq_set_handler_locked(data, handle_edge_irq);
432
433 return irq_chip_set_type_parent(data, type);
434}
435
436static void tegra186_gpio_irq(struct irq_desc *desc)
437{
438 struct tegra_gpio *gpio = irq_desc_get_handler_data(desc);
439 struct irq_domain *domain = gpio->gpio.irq.domain;
440 struct irq_chip *chip = irq_desc_get_chip(desc);
441 unsigned int parent = irq_desc_get_irq(desc);
442 unsigned int i, offset = 0;
443
444 chained_irq_enter(chip, desc);
445
446 for (i = 0; i < gpio->soc->num_ports; i++) {
447 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
448 unsigned int pin, irq;
449 unsigned long value;
450 void __iomem *base;
451
452 base = gpio->base + port->bank * 0x1000 + port->port * 0x200;
453
454 /* skip ports that are not associated with this bank */
455 if (parent != gpio->irq[port->bank])
456 goto skip;
457
458 value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1));
459
460 for_each_set_bit(pin, &value, port->pins) {
461 irq = irq_find_mapping(domain, offset + pin);
462 if (WARN_ON(irq == 0))
463 continue;
464
465 generic_handle_irq(irq);
466 }
467
468skip:
469 offset += port->pins;
470 }
471
472 chained_irq_exit(chip, desc);
473}
474
475static int tegra186_gpio_irq_domain_translate(struct irq_domain *domain,
476 struct irq_fwspec *fwspec,
477 unsigned long *hwirq,
478 unsigned int *type)
479{
480 struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data);
481 unsigned int port, pin, i, offset = 0;
482
483 if (WARN_ON(gpio->gpio.of_gpio_n_cells < 2))
484 return -EINVAL;
485
486 if (WARN_ON(fwspec->param_count < gpio->gpio.of_gpio_n_cells))
487 return -EINVAL;
488
489 port = fwspec->param[0] / 8;
490 pin = fwspec->param[0] % 8;
491
492 if (port >= gpio->soc->num_ports)
493 return -EINVAL;
494
495 for (i = 0; i < port; i++)
496 offset += gpio->soc->ports[i].pins;
497
498 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
499 *hwirq = offset + pin;
500
501 return 0;
502}
503
504static void *tegra186_gpio_populate_parent_fwspec(struct gpio_chip *chip,
505 unsigned int parent_hwirq,
506 unsigned int parent_type)
507{
508 struct tegra_gpio *gpio = gpiochip_get_data(chip);
509 struct irq_fwspec *fwspec;
510
511 fwspec = kmalloc(sizeof(*fwspec), GFP_KERNEL);
512 if (!fwspec)
513 return NULL;
514
515 fwspec->fwnode = chip->irq.parent_domain->fwnode;
516 fwspec->param_count = 3;
517 fwspec->param[0] = gpio->soc->instance;
518 fwspec->param[1] = parent_hwirq;
519 fwspec->param[2] = parent_type;
520
521 return fwspec;
522}
523
524static int tegra186_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
525 unsigned int hwirq,
526 unsigned int type,
527 unsigned int *parent_hwirq,
528 unsigned int *parent_type)
529{
530 *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq);
531 *parent_type = type;
532
533 return 0;
534}
535
536static unsigned int tegra186_gpio_child_offset_to_irq(struct gpio_chip *chip,
537 unsigned int offset)
538{
539 struct tegra_gpio *gpio = gpiochip_get_data(chip);
540 unsigned int i;
541
542 for (i = 0; i < gpio->soc->num_ports; i++) {
543 if (offset < gpio->soc->ports[i].pins)
544 break;
545
546 offset -= gpio->soc->ports[i].pins;
547 }
548
549 return offset + i * 8;
550}
551
552static const struct of_device_id tegra186_pmc_of_match[] = {
553 { .compatible = "nvidia,tegra186-pmc" },
554 { .compatible = "nvidia,tegra194-pmc" },
555 { /* sentinel */ }
556};
557
558static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio)
559{
560 unsigned int i, j;
561 u32 value;
562
563 for (i = 0; i < gpio->soc->num_ports; i++) {
564 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
565 unsigned int offset, p = port->port;
566 void __iomem *base;
567
568 base = gpio->secure + port->bank * 0x1000 + 0x800;
569
570 value = readl(base + TEGRA186_GPIO_CTL_SCR);
571
572 /*
573 * For controllers that haven't been locked down yet, make
574 * sure to program the default interrupt route mapping.
575 */
576 if ((value & TEGRA186_GPIO_CTL_SCR_SEC_REN) == 0 &&
577 (value & TEGRA186_GPIO_CTL_SCR_SEC_WEN) == 0) {
578 for (j = 0; j < 8; j++) {
579 offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, j);
580
581 value = readl(base + offset);
582 value = BIT(port->pins) - 1;
583 writel(value, base + offset);
584 }
585 }
586 }
587}
588
589static int tegra186_gpio_probe(struct platform_device *pdev)
590{
591 unsigned int i, j, offset;
592 struct gpio_irq_chip *irq;
593 struct tegra_gpio *gpio;
594 struct device_node *np;
595 char **names;
596 int err;
597
598 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
599 if (!gpio)
600 return -ENOMEM;
601
602 gpio->soc = of_device_get_match_data(&pdev->dev);
603
604 gpio->secure = devm_platform_ioremap_resource_byname(pdev, "security");
605 if (IS_ERR(gpio->secure))
606 return PTR_ERR(gpio->secure);
607
608 gpio->base = devm_platform_ioremap_resource_byname(pdev, "gpio");
609 if (IS_ERR(gpio->base))
610 return PTR_ERR(gpio->base);
611
612 err = platform_irq_count(pdev);
613 if (err < 0)
614 return err;
615
616 gpio->num_irq = err;
617
618 gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq),
619 GFP_KERNEL);
620 if (!gpio->irq)
621 return -ENOMEM;
622
623 for (i = 0; i < gpio->num_irq; i++) {
624 err = platform_get_irq(pdev, i);
625 if (err < 0)
626 return err;
627
628 gpio->irq[i] = err;
629 }
630
631 gpio->gpio.label = gpio->soc->name;
632 gpio->gpio.parent = &pdev->dev;
633
634 gpio->gpio.request = gpiochip_generic_request;
635 gpio->gpio.free = gpiochip_generic_free;
636 gpio->gpio.get_direction = tegra186_gpio_get_direction;
637 gpio->gpio.direction_input = tegra186_gpio_direction_input;
638 gpio->gpio.direction_output = tegra186_gpio_direction_output;
639 gpio->gpio.get = tegra186_gpio_get,
640 gpio->gpio.set = tegra186_gpio_set;
641 gpio->gpio.set_config = tegra186_gpio_set_config;
642 gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges;
643
644 gpio->gpio.base = -1;
645
646 for (i = 0; i < gpio->soc->num_ports; i++)
647 gpio->gpio.ngpio += gpio->soc->ports[i].pins;
648
649 names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio,
650 sizeof(*names), GFP_KERNEL);
651 if (!names)
652 return -ENOMEM;
653
654 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
655 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
656 char *name;
657
658 for (j = 0; j < port->pins; j++) {
659 name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL,
660 "P%s.%02x", port->name, j);
661 if (!name)
662 return -ENOMEM;
663
664 names[offset + j] = name;
665 }
666
667 offset += port->pins;
668 }
669
670 gpio->gpio.names = (const char * const *)names;
671
672 gpio->gpio.of_node = pdev->dev.of_node;
673 gpio->gpio.of_gpio_n_cells = 2;
674 gpio->gpio.of_xlate = tegra186_gpio_of_xlate;
675
676 gpio->intc.name = pdev->dev.of_node->name;
677 gpio->intc.irq_ack = tegra186_irq_ack;
678 gpio->intc.irq_mask = tegra186_irq_mask;
679 gpio->intc.irq_unmask = tegra186_irq_unmask;
680 gpio->intc.irq_set_type = tegra186_irq_set_type;
681 gpio->intc.irq_set_wake = irq_chip_set_wake_parent;
682
683 irq = &gpio->gpio.irq;
684 irq->chip = &gpio->intc;
685 irq->fwnode = of_node_to_fwnode(pdev->dev.of_node);
686 irq->child_to_parent_hwirq = tegra186_gpio_child_to_parent_hwirq;
687 irq->populate_parent_alloc_arg = tegra186_gpio_populate_parent_fwspec;
688 irq->child_offset_to_irq = tegra186_gpio_child_offset_to_irq;
689 irq->child_irq_domain_ops.translate = tegra186_gpio_irq_domain_translate;
690 irq->handler = handle_simple_irq;
691 irq->default_type = IRQ_TYPE_NONE;
692 irq->parent_handler = tegra186_gpio_irq;
693 irq->parent_handler_data = gpio;
694 irq->num_parents = gpio->num_irq;
695 irq->parents = gpio->irq;
696
697 np = of_find_matching_node(NULL, tegra186_pmc_of_match);
698 if (np) {
699 irq->parent_domain = irq_find_host(np);
700 of_node_put(np);
701
702 if (!irq->parent_domain)
703 return -EPROBE_DEFER;
704 }
705
706 tegra186_gpio_init_route_mapping(gpio);
707
708 irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio,
709 sizeof(*irq->map), GFP_KERNEL);
710 if (!irq->map)
711 return -ENOMEM;
712
713 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
714 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
715
716 for (j = 0; j < port->pins; j++)
717 irq->map[offset + j] = irq->parents[port->bank];
718
719 offset += port->pins;
720 }
721
722 platform_set_drvdata(pdev, gpio);
723
724 err = devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio);
725 if (err < 0)
726 return err;
727
728 return 0;
729}
730
731static int tegra186_gpio_remove(struct platform_device *pdev)
732{
733 return 0;
734}
735
736#define TEGRA186_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
737 [TEGRA186_MAIN_GPIO_PORT_##_name] = { \
738 .name = #_name, \
739 .bank = _bank, \
740 .port = _port, \
741 .pins = _pins, \
742 }
743
744static const struct tegra_gpio_port tegra186_main_ports[] = {
745 TEGRA186_MAIN_GPIO_PORT( A, 2, 0, 7),
746 TEGRA186_MAIN_GPIO_PORT( B, 3, 0, 7),
747 TEGRA186_MAIN_GPIO_PORT( C, 3, 1, 7),
748 TEGRA186_MAIN_GPIO_PORT( D, 3, 2, 6),
749 TEGRA186_MAIN_GPIO_PORT( E, 2, 1, 8),
750 TEGRA186_MAIN_GPIO_PORT( F, 2, 2, 6),
751 TEGRA186_MAIN_GPIO_PORT( G, 4, 1, 6),
752 TEGRA186_MAIN_GPIO_PORT( H, 1, 0, 7),
753 TEGRA186_MAIN_GPIO_PORT( I, 0, 4, 8),
754 TEGRA186_MAIN_GPIO_PORT( J, 5, 0, 8),
755 TEGRA186_MAIN_GPIO_PORT( K, 5, 1, 1),
756 TEGRA186_MAIN_GPIO_PORT( L, 1, 1, 8),
757 TEGRA186_MAIN_GPIO_PORT( M, 5, 3, 6),
758 TEGRA186_MAIN_GPIO_PORT( N, 0, 0, 7),
759 TEGRA186_MAIN_GPIO_PORT( O, 0, 1, 4),
760 TEGRA186_MAIN_GPIO_PORT( P, 4, 0, 7),
761 TEGRA186_MAIN_GPIO_PORT( Q, 0, 2, 6),
762 TEGRA186_MAIN_GPIO_PORT( R, 0, 5, 6),
763 TEGRA186_MAIN_GPIO_PORT( T, 0, 3, 4),
764 TEGRA186_MAIN_GPIO_PORT( X, 1, 2, 8),
765 TEGRA186_MAIN_GPIO_PORT( Y, 1, 3, 7),
766 TEGRA186_MAIN_GPIO_PORT(BB, 2, 3, 2),
767 TEGRA186_MAIN_GPIO_PORT(CC, 5, 2, 4),
768};
769
770static const struct tegra_gpio_soc tegra186_main_soc = {
771 .num_ports = ARRAY_SIZE(tegra186_main_ports),
772 .ports = tegra186_main_ports,
773 .name = "tegra186-gpio",
774 .instance = 0,
775};
776
777#define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \
778 [TEGRA186_AON_GPIO_PORT_##_name] = { \
779 .name = #_name, \
780 .bank = _bank, \
781 .port = _port, \
782 .pins = _pins, \
783 }
784
785static const struct tegra_gpio_port tegra186_aon_ports[] = {
786 TEGRA186_AON_GPIO_PORT( S, 0, 1, 5),
787 TEGRA186_AON_GPIO_PORT( U, 0, 2, 6),
788 TEGRA186_AON_GPIO_PORT( V, 0, 4, 8),
789 TEGRA186_AON_GPIO_PORT( W, 0, 5, 8),
790 TEGRA186_AON_GPIO_PORT( Z, 0, 7, 4),
791 TEGRA186_AON_GPIO_PORT(AA, 0, 6, 8),
792 TEGRA186_AON_GPIO_PORT(EE, 0, 3, 3),
793 TEGRA186_AON_GPIO_PORT(FF, 0, 0, 5),
794};
795
796static const struct tegra_gpio_soc tegra186_aon_soc = {
797 .num_ports = ARRAY_SIZE(tegra186_aon_ports),
798 .ports = tegra186_aon_ports,
799 .name = "tegra186-gpio-aon",
800 .instance = 1,
801};
802
803#define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
804 [TEGRA194_MAIN_GPIO_PORT_##_name] = { \
805 .name = #_name, \
806 .bank = _bank, \
807 .port = _port, \
808 .pins = _pins, \
809 }
810
811static const struct tegra_gpio_port tegra194_main_ports[] = {
812 TEGRA194_MAIN_GPIO_PORT( A, 1, 2, 8),
813 TEGRA194_MAIN_GPIO_PORT( B, 4, 7, 2),
814 TEGRA194_MAIN_GPIO_PORT( C, 4, 3, 8),
815 TEGRA194_MAIN_GPIO_PORT( D, 4, 4, 4),
816 TEGRA194_MAIN_GPIO_PORT( E, 4, 5, 8),
817 TEGRA194_MAIN_GPIO_PORT( F, 4, 6, 6),
818 TEGRA194_MAIN_GPIO_PORT( G, 4, 0, 8),
819 TEGRA194_MAIN_GPIO_PORT( H, 4, 1, 8),
820 TEGRA194_MAIN_GPIO_PORT( I, 4, 2, 5),
821 TEGRA194_MAIN_GPIO_PORT( J, 5, 1, 6),
822 TEGRA194_MAIN_GPIO_PORT( K, 3, 0, 8),
823 TEGRA194_MAIN_GPIO_PORT( L, 3, 1, 4),
824 TEGRA194_MAIN_GPIO_PORT( M, 2, 3, 8),
825 TEGRA194_MAIN_GPIO_PORT( N, 2, 4, 3),
826 TEGRA194_MAIN_GPIO_PORT( O, 5, 0, 6),
827 TEGRA194_MAIN_GPIO_PORT( P, 2, 5, 8),
828 TEGRA194_MAIN_GPIO_PORT( Q, 2, 6, 8),
829 TEGRA194_MAIN_GPIO_PORT( R, 2, 7, 6),
830 TEGRA194_MAIN_GPIO_PORT( S, 3, 3, 8),
831 TEGRA194_MAIN_GPIO_PORT( T, 3, 4, 8),
832 TEGRA194_MAIN_GPIO_PORT( U, 3, 5, 1),
833 TEGRA194_MAIN_GPIO_PORT( V, 1, 0, 8),
834 TEGRA194_MAIN_GPIO_PORT( W, 1, 1, 2),
835 TEGRA194_MAIN_GPIO_PORT( X, 2, 0, 8),
836 TEGRA194_MAIN_GPIO_PORT( Y, 2, 1, 8),
837 TEGRA194_MAIN_GPIO_PORT( Z, 2, 2, 8),
838 TEGRA194_MAIN_GPIO_PORT(FF, 3, 2, 2),
839 TEGRA194_MAIN_GPIO_PORT(GG, 0, 0, 2)
840};
841
842static const struct tegra186_pin_range tegra194_main_pin_ranges[] = {
843 { TEGRA194_MAIN_GPIO(GG, 0), "pex_l5_clkreq_n_pgg0" },
844 { TEGRA194_MAIN_GPIO(GG, 1), "pex_l5_rst_n_pgg1" },
845};
846
847static const struct tegra_gpio_soc tegra194_main_soc = {
848 .num_ports = ARRAY_SIZE(tegra194_main_ports),
849 .ports = tegra194_main_ports,
850 .name = "tegra194-gpio",
851 .instance = 0,
852 .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges),
853 .pin_ranges = tegra194_main_pin_ranges,
854 .pinmux = "nvidia,tegra194-pinmux",
855};
856
857#define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \
858 [TEGRA194_AON_GPIO_PORT_##_name] = { \
859 .name = #_name, \
860 .bank = _bank, \
861 .port = _port, \
862 .pins = _pins, \
863 }
864
865static const struct tegra_gpio_port tegra194_aon_ports[] = {
866 TEGRA194_AON_GPIO_PORT(AA, 0, 3, 8),
867 TEGRA194_AON_GPIO_PORT(BB, 0, 4, 4),
868 TEGRA194_AON_GPIO_PORT(CC, 0, 1, 8),
869 TEGRA194_AON_GPIO_PORT(DD, 0, 2, 3),
870 TEGRA194_AON_GPIO_PORT(EE, 0, 0, 7)
871};
872
873static const struct tegra_gpio_soc tegra194_aon_soc = {
874 .num_ports = ARRAY_SIZE(tegra194_aon_ports),
875 .ports = tegra194_aon_ports,
876 .name = "tegra194-gpio-aon",
877 .instance = 1,
878};
879
880static const struct of_device_id tegra186_gpio_of_match[] = {
881 {
882 .compatible = "nvidia,tegra186-gpio",
883 .data = &tegra186_main_soc
884 }, {
885 .compatible = "nvidia,tegra186-gpio-aon",
886 .data = &tegra186_aon_soc
887 }, {
888 .compatible = "nvidia,tegra194-gpio",
889 .data = &tegra194_main_soc
890 }, {
891 .compatible = "nvidia,tegra194-gpio-aon",
892 .data = &tegra194_aon_soc
893 }, {
894 /* sentinel */
895 }
896};
897MODULE_DEVICE_TABLE(of, tegra186_gpio_of_match);
898
899static struct platform_driver tegra186_gpio_driver = {
900 .driver = {
901 .name = "tegra186-gpio",
902 .of_match_table = tegra186_gpio_of_match,
903 },
904 .probe = tegra186_gpio_probe,
905 .remove = tegra186_gpio_remove,
906};
907module_platform_driver(tegra186_gpio_driver);
908
909MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver");
910MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
911MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2016-2022 NVIDIA Corporation
4 *
5 * Author: Thierry Reding <treding@nvidia.com>
6 * Dipen Patel <dpatel@nvidia.com>
7 */
8
9#include <linux/gpio/driver.h>
10#include <linux/hte.h>
11#include <linux/interrupt.h>
12#include <linux/irq.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/platform_device.h>
16#include <linux/seq_file.h>
17
18#include <dt-bindings/gpio/tegra186-gpio.h>
19#include <dt-bindings/gpio/tegra194-gpio.h>
20#include <dt-bindings/gpio/tegra234-gpio.h>
21#include <dt-bindings/gpio/tegra241-gpio.h>
22
23/* security registers */
24#define TEGRA186_GPIO_CTL_SCR 0x0c
25#define TEGRA186_GPIO_CTL_SCR_SEC_WEN BIT(28)
26#define TEGRA186_GPIO_CTL_SCR_SEC_REN BIT(27)
27
28#define TEGRA186_GPIO_INT_ROUTE_MAPPING(p, x) (0x14 + (p) * 0x20 + (x) * 4)
29
30#define TEGRA186_GPIO_VM 0x00
31#define TEGRA186_GPIO_VM_RW_MASK 0x03
32#define TEGRA186_GPIO_SCR 0x04
33#define TEGRA186_GPIO_SCR_PIN_SIZE 0x08
34#define TEGRA186_GPIO_SCR_PORT_SIZE 0x40
35#define TEGRA186_GPIO_SCR_SEC_WEN BIT(28)
36#define TEGRA186_GPIO_SCR_SEC_REN BIT(27)
37#define TEGRA186_GPIO_SCR_SEC_G1W BIT(9)
38#define TEGRA186_GPIO_SCR_SEC_G1R BIT(1)
39
40/* control registers */
41#define TEGRA186_GPIO_ENABLE_CONFIG 0x00
42#define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0)
43#define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1)
44#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2)
45#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2)
46#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2)
47#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2)
48#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2)
49#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4)
50#define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE BIT(5)
51#define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6)
52#define TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC BIT(7)
53
54#define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04
55#define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff)
56
57#define TEGRA186_GPIO_INPUT 0x08
58#define TEGRA186_GPIO_INPUT_HIGH BIT(0)
59
60#define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c
61#define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0)
62
63#define TEGRA186_GPIO_OUTPUT_VALUE 0x10
64#define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0)
65
66#define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14
67
68#define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4)
69
70struct tegra_gpio_port {
71 const char *name;
72 unsigned int bank;
73 unsigned int port;
74 unsigned int pins;
75};
76
77struct tegra186_pin_range {
78 unsigned int offset;
79 const char *group;
80};
81
82struct tegra_gpio_soc {
83 const struct tegra_gpio_port *ports;
84 unsigned int num_ports;
85 const char *name;
86 unsigned int instance;
87
88 unsigned int num_irqs_per_bank;
89
90 const struct tegra186_pin_range *pin_ranges;
91 unsigned int num_pin_ranges;
92 const char *pinmux;
93 bool has_gte;
94 bool has_vm_support;
95};
96
97struct tegra_gpio {
98 struct gpio_chip gpio;
99 unsigned int num_irq;
100 unsigned int *irq;
101
102 const struct tegra_gpio_soc *soc;
103 unsigned int num_irqs_per_bank;
104 unsigned int num_banks;
105
106 void __iomem *secure;
107 void __iomem *base;
108};
109
110static const struct tegra_gpio_port *
111tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin)
112{
113 unsigned int start = 0, i;
114
115 for (i = 0; i < gpio->soc->num_ports; i++) {
116 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
117
118 if (*pin >= start && *pin < start + port->pins) {
119 *pin -= start;
120 return port;
121 }
122
123 start += port->pins;
124 }
125
126 return NULL;
127}
128
129static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio,
130 unsigned int pin)
131{
132 const struct tegra_gpio_port *port;
133 unsigned int offset;
134
135 port = tegra186_gpio_get_port(gpio, &pin);
136 if (!port)
137 return NULL;
138
139 offset = port->bank * 0x1000 + port->port * 0x200;
140
141 return gpio->base + offset + pin * 0x20;
142}
143
144static void __iomem *tegra186_gpio_get_secure_base(struct tegra_gpio *gpio,
145 unsigned int pin)
146{
147 const struct tegra_gpio_port *port;
148 unsigned int offset;
149
150 port = tegra186_gpio_get_port(gpio, &pin);
151 if (!port)
152 return NULL;
153
154 offset = port->bank * 0x1000 + port->port * TEGRA186_GPIO_SCR_PORT_SIZE;
155
156 return gpio->secure + offset + pin * TEGRA186_GPIO_SCR_PIN_SIZE;
157}
158
159static inline bool tegra186_gpio_is_accessible(struct tegra_gpio *gpio, unsigned int pin)
160{
161 void __iomem *secure;
162 u32 value;
163
164 secure = tegra186_gpio_get_secure_base(gpio, pin);
165
166 if (gpio->soc->has_vm_support) {
167 value = readl(secure + TEGRA186_GPIO_VM);
168 if ((value & TEGRA186_GPIO_VM_RW_MASK) != TEGRA186_GPIO_VM_RW_MASK)
169 return false;
170 }
171
172 value = __raw_readl(secure + TEGRA186_GPIO_SCR);
173
174 /*
175 * When SCR_SEC_[R|W]EN is unset, then we have full read/write access to all the
176 * registers for given GPIO pin.
177 * When SCR_SEC[R|W]EN is set, then there is need to further check the accompanying
178 * SCR_SEC_G1[R|W] bit to determine read/write access to all the registers for given
179 * GPIO pin.
180 */
181
182 if (((value & TEGRA186_GPIO_SCR_SEC_REN) == 0 ||
183 ((value & TEGRA186_GPIO_SCR_SEC_REN) && (value & TEGRA186_GPIO_SCR_SEC_G1R))) &&
184 ((value & TEGRA186_GPIO_SCR_SEC_WEN) == 0 ||
185 ((value & TEGRA186_GPIO_SCR_SEC_WEN) && (value & TEGRA186_GPIO_SCR_SEC_G1W))))
186 return true;
187
188 return false;
189}
190
191static int tegra186_init_valid_mask(struct gpio_chip *chip,
192 unsigned long *valid_mask, unsigned int ngpios)
193{
194 struct tegra_gpio *gpio = gpiochip_get_data(chip);
195 unsigned int j;
196
197 for (j = 0; j < ngpios; j++) {
198 if (!tegra186_gpio_is_accessible(gpio, j))
199 clear_bit(j, valid_mask);
200 }
201 return 0;
202}
203
204static int tegra186_gpio_get_direction(struct gpio_chip *chip,
205 unsigned int offset)
206{
207 struct tegra_gpio *gpio = gpiochip_get_data(chip);
208 void __iomem *base;
209 u32 value;
210
211 base = tegra186_gpio_get_base(gpio, offset);
212 if (WARN_ON(base == NULL))
213 return -ENODEV;
214
215 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
216 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
217 return GPIO_LINE_DIRECTION_OUT;
218
219 return GPIO_LINE_DIRECTION_IN;
220}
221
222static int tegra186_gpio_direction_input(struct gpio_chip *chip,
223 unsigned int offset)
224{
225 struct tegra_gpio *gpio = gpiochip_get_data(chip);
226 void __iomem *base;
227 u32 value;
228
229 base = tegra186_gpio_get_base(gpio, offset);
230 if (WARN_ON(base == NULL))
231 return -ENODEV;
232
233 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
234 value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
235 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
236
237 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
238 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
239 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT;
240 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
241
242 return 0;
243}
244
245static int tegra186_gpio_direction_output(struct gpio_chip *chip,
246 unsigned int offset, int level)
247{
248 struct tegra_gpio *gpio = gpiochip_get_data(chip);
249 void __iomem *base;
250 u32 value;
251
252 /* configure output level first */
253 chip->set(chip, offset, level);
254
255 base = tegra186_gpio_get_base(gpio, offset);
256 if (WARN_ON(base == NULL))
257 return -EINVAL;
258
259 /* set the direction */
260 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
261 value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
262 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
263
264 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
265 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
266 value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT;
267 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
268
269 return 0;
270}
271
272#define HTE_BOTH_EDGES (HTE_RISING_EDGE_TS | HTE_FALLING_EDGE_TS)
273
274static int tegra186_gpio_en_hw_ts(struct gpio_chip *gc, u32 offset,
275 unsigned long flags)
276{
277 struct tegra_gpio *gpio;
278 void __iomem *base;
279 int value;
280
281 if (!gc)
282 return -EINVAL;
283
284 gpio = gpiochip_get_data(gc);
285 if (!gpio)
286 return -ENODEV;
287
288 base = tegra186_gpio_get_base(gpio, offset);
289 if (WARN_ON(base == NULL))
290 return -EINVAL;
291
292 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
293 value |= TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC;
294
295 if (flags == HTE_BOTH_EDGES) {
296 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
297 } else if (flags == HTE_RISING_EDGE_TS) {
298 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
299 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
300 } else if (flags == HTE_FALLING_EDGE_TS) {
301 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
302 }
303
304 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
305
306 return 0;
307}
308
309static int tegra186_gpio_dis_hw_ts(struct gpio_chip *gc, u32 offset,
310 unsigned long flags)
311{
312 struct tegra_gpio *gpio;
313 void __iomem *base;
314 int value;
315
316 if (!gc)
317 return -EINVAL;
318
319 gpio = gpiochip_get_data(gc);
320 if (!gpio)
321 return -ENODEV;
322
323 base = tegra186_gpio_get_base(gpio, offset);
324 if (WARN_ON(base == NULL))
325 return -EINVAL;
326
327 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
328 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC;
329 if (flags == HTE_BOTH_EDGES) {
330 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
331 } else if (flags == HTE_RISING_EDGE_TS) {
332 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
333 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
334 } else if (flags == HTE_FALLING_EDGE_TS) {
335 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
336 }
337 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
338
339 return 0;
340}
341
342static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset)
343{
344 struct tegra_gpio *gpio = gpiochip_get_data(chip);
345 void __iomem *base;
346 u32 value;
347
348 base = tegra186_gpio_get_base(gpio, offset);
349 if (WARN_ON(base == NULL))
350 return -ENODEV;
351
352 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
353 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
354 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
355 else
356 value = readl(base + TEGRA186_GPIO_INPUT);
357
358 return value & BIT(0);
359}
360
361static void tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset,
362 int level)
363{
364 struct tegra_gpio *gpio = gpiochip_get_data(chip);
365 void __iomem *base;
366 u32 value;
367
368 base = tegra186_gpio_get_base(gpio, offset);
369 if (WARN_ON(base == NULL))
370 return;
371
372 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
373 if (level == 0)
374 value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
375 else
376 value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
377
378 writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE);
379}
380
381static int tegra186_gpio_set_config(struct gpio_chip *chip,
382 unsigned int offset,
383 unsigned long config)
384{
385 struct tegra_gpio *gpio = gpiochip_get_data(chip);
386 u32 debounce, value;
387 void __iomem *base;
388
389 base = tegra186_gpio_get_base(gpio, offset);
390 if (base == NULL)
391 return -ENXIO;
392
393 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
394 return -ENOTSUPP;
395
396 debounce = pinconf_to_config_argument(config);
397
398 /*
399 * The Tegra186 GPIO controller supports a maximum of 255 ms debounce
400 * time.
401 */
402 if (debounce > 255000)
403 return -EINVAL;
404
405 debounce = DIV_ROUND_UP(debounce, USEC_PER_MSEC);
406
407 value = TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(debounce);
408 writel(value, base + TEGRA186_GPIO_DEBOUNCE_CONTROL);
409
410 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
411 value |= TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE;
412 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
413
414 return 0;
415}
416
417static int tegra186_gpio_add_pin_ranges(struct gpio_chip *chip)
418{
419 struct tegra_gpio *gpio = gpiochip_get_data(chip);
420 struct pinctrl_dev *pctldev;
421 struct device_node *np;
422 unsigned int i, j;
423 int err;
424
425 if (!gpio->soc->pinmux || gpio->soc->num_pin_ranges == 0)
426 return 0;
427
428 np = of_find_compatible_node(NULL, NULL, gpio->soc->pinmux);
429 if (!np)
430 return -ENODEV;
431
432 pctldev = of_pinctrl_get(np);
433 of_node_put(np);
434 if (!pctldev)
435 return -EPROBE_DEFER;
436
437 for (i = 0; i < gpio->soc->num_pin_ranges; i++) {
438 unsigned int pin = gpio->soc->pin_ranges[i].offset, port;
439 const char *group = gpio->soc->pin_ranges[i].group;
440
441 port = pin / 8;
442 pin = pin % 8;
443
444 if (port >= gpio->soc->num_ports) {
445 dev_warn(chip->parent, "invalid port %u for %s\n",
446 port, group);
447 continue;
448 }
449
450 for (j = 0; j < port; j++)
451 pin += gpio->soc->ports[j].pins;
452
453 err = gpiochip_add_pingroup_range(chip, pctldev, pin, group);
454 if (err < 0)
455 return err;
456 }
457
458 return 0;
459}
460
461static int tegra186_gpio_of_xlate(struct gpio_chip *chip,
462 const struct of_phandle_args *spec,
463 u32 *flags)
464{
465 struct tegra_gpio *gpio = gpiochip_get_data(chip);
466 unsigned int port, pin, i, offset = 0;
467
468 if (WARN_ON(chip->of_gpio_n_cells < 2))
469 return -EINVAL;
470
471 if (WARN_ON(spec->args_count < chip->of_gpio_n_cells))
472 return -EINVAL;
473
474 port = spec->args[0] / 8;
475 pin = spec->args[0] % 8;
476
477 if (port >= gpio->soc->num_ports) {
478 dev_err(chip->parent, "invalid port number: %u\n", port);
479 return -EINVAL;
480 }
481
482 for (i = 0; i < port; i++)
483 offset += gpio->soc->ports[i].pins;
484
485 if (flags)
486 *flags = spec->args[1];
487
488 return offset + pin;
489}
490
491#define to_tegra_gpio(x) container_of((x), struct tegra_gpio, gpio)
492
493static void tegra186_irq_ack(struct irq_data *data)
494{
495 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
496 struct tegra_gpio *gpio = to_tegra_gpio(gc);
497 void __iomem *base;
498
499 base = tegra186_gpio_get_base(gpio, data->hwirq);
500 if (WARN_ON(base == NULL))
501 return;
502
503 writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR);
504}
505
506static void tegra186_irq_mask(struct irq_data *data)
507{
508 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
509 struct tegra_gpio *gpio = to_tegra_gpio(gc);
510 void __iomem *base;
511 u32 value;
512
513 base = tegra186_gpio_get_base(gpio, data->hwirq);
514 if (WARN_ON(base == NULL))
515 return;
516
517 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
518 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
519 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
520
521 gpiochip_disable_irq(&gpio->gpio, data->hwirq);
522}
523
524static void tegra186_irq_unmask(struct irq_data *data)
525{
526 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
527 struct tegra_gpio *gpio = to_tegra_gpio(gc);
528 void __iomem *base;
529 u32 value;
530
531 base = tegra186_gpio_get_base(gpio, data->hwirq);
532 if (WARN_ON(base == NULL))
533 return;
534
535 gpiochip_enable_irq(&gpio->gpio, data->hwirq);
536
537 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
538 value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
539 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
540}
541
542static int tegra186_irq_set_type(struct irq_data *data, unsigned int type)
543{
544 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
545 struct tegra_gpio *gpio = to_tegra_gpio(gc);
546 void __iomem *base;
547 u32 value;
548
549 base = tegra186_gpio_get_base(gpio, data->hwirq);
550 if (WARN_ON(base == NULL))
551 return -ENODEV;
552
553 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
554 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK;
555 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
556
557 switch (type & IRQ_TYPE_SENSE_MASK) {
558 case IRQ_TYPE_NONE:
559 break;
560
561 case IRQ_TYPE_EDGE_RISING:
562 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
563 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
564 break;
565
566 case IRQ_TYPE_EDGE_FALLING:
567 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
568 break;
569
570 case IRQ_TYPE_EDGE_BOTH:
571 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
572 break;
573
574 case IRQ_TYPE_LEVEL_HIGH:
575 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
576 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
577 break;
578
579 case IRQ_TYPE_LEVEL_LOW:
580 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
581 break;
582
583 default:
584 return -EINVAL;
585 }
586
587 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
588
589 if ((type & IRQ_TYPE_EDGE_BOTH) == 0)
590 irq_set_handler_locked(data, handle_level_irq);
591 else
592 irq_set_handler_locked(data, handle_edge_irq);
593
594 if (data->parent_data)
595 return irq_chip_set_type_parent(data, type);
596
597 return 0;
598}
599
600static int tegra186_irq_set_wake(struct irq_data *data, unsigned int on)
601{
602 if (data->parent_data)
603 return irq_chip_set_wake_parent(data, on);
604
605 return 0;
606}
607
608static void tegra186_irq_print_chip(struct irq_data *data, struct seq_file *p)
609{
610 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
611
612 seq_printf(p, dev_name(gc->parent));
613}
614
615static const struct irq_chip tegra186_gpio_irq_chip = {
616 .irq_ack = tegra186_irq_ack,
617 .irq_mask = tegra186_irq_mask,
618 .irq_unmask = tegra186_irq_unmask,
619 .irq_set_type = tegra186_irq_set_type,
620 .irq_set_wake = tegra186_irq_set_wake,
621 .irq_print_chip = tegra186_irq_print_chip,
622 .flags = IRQCHIP_IMMUTABLE,
623 GPIOCHIP_IRQ_RESOURCE_HELPERS,
624};
625
626static void tegra186_gpio_irq(struct irq_desc *desc)
627{
628 struct tegra_gpio *gpio = irq_desc_get_handler_data(desc);
629 struct irq_domain *domain = gpio->gpio.irq.domain;
630 struct irq_chip *chip = irq_desc_get_chip(desc);
631 unsigned int parent = irq_desc_get_irq(desc);
632 unsigned int i, j, offset = 0;
633
634 chained_irq_enter(chip, desc);
635
636 for (i = 0; i < gpio->soc->num_ports; i++) {
637 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
638 unsigned int pin;
639 unsigned long value;
640 void __iomem *base;
641
642 base = gpio->base + port->bank * 0x1000 + port->port * 0x200;
643
644 /* skip ports that are not associated with this bank */
645 for (j = 0; j < gpio->num_irqs_per_bank; j++) {
646 if (parent == gpio->irq[port->bank * gpio->num_irqs_per_bank + j])
647 break;
648 }
649
650 if (j == gpio->num_irqs_per_bank)
651 goto skip;
652
653 value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1));
654
655 for_each_set_bit(pin, &value, port->pins) {
656 int ret = generic_handle_domain_irq(domain, offset + pin);
657 WARN_RATELIMIT(ret, "hwirq = %d", offset + pin);
658 }
659
660skip:
661 offset += port->pins;
662 }
663
664 chained_irq_exit(chip, desc);
665}
666
667static int tegra186_gpio_irq_domain_translate(struct irq_domain *domain,
668 struct irq_fwspec *fwspec,
669 unsigned long *hwirq,
670 unsigned int *type)
671{
672 struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data);
673 unsigned int port, pin, i, offset = 0;
674
675 if (WARN_ON(gpio->gpio.of_gpio_n_cells < 2))
676 return -EINVAL;
677
678 if (WARN_ON(fwspec->param_count < gpio->gpio.of_gpio_n_cells))
679 return -EINVAL;
680
681 port = fwspec->param[0] / 8;
682 pin = fwspec->param[0] % 8;
683
684 if (port >= gpio->soc->num_ports)
685 return -EINVAL;
686
687 for (i = 0; i < port; i++)
688 offset += gpio->soc->ports[i].pins;
689
690 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
691 *hwirq = offset + pin;
692
693 return 0;
694}
695
696static int tegra186_gpio_populate_parent_fwspec(struct gpio_chip *chip,
697 union gpio_irq_fwspec *gfwspec,
698 unsigned int parent_hwirq,
699 unsigned int parent_type)
700{
701 struct tegra_gpio *gpio = gpiochip_get_data(chip);
702 struct irq_fwspec *fwspec = &gfwspec->fwspec;
703
704 fwspec->fwnode = chip->irq.parent_domain->fwnode;
705 fwspec->param_count = 3;
706 fwspec->param[0] = gpio->soc->instance;
707 fwspec->param[1] = parent_hwirq;
708 fwspec->param[2] = parent_type;
709
710 return 0;
711}
712
713static int tegra186_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
714 unsigned int hwirq,
715 unsigned int type,
716 unsigned int *parent_hwirq,
717 unsigned int *parent_type)
718{
719 *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq);
720 *parent_type = type;
721
722 return 0;
723}
724
725static unsigned int tegra186_gpio_child_offset_to_irq(struct gpio_chip *chip,
726 unsigned int offset)
727{
728 struct tegra_gpio *gpio = gpiochip_get_data(chip);
729 unsigned int i;
730
731 for (i = 0; i < gpio->soc->num_ports; i++) {
732 if (offset < gpio->soc->ports[i].pins)
733 break;
734
735 offset -= gpio->soc->ports[i].pins;
736 }
737
738 return offset + i * 8;
739}
740
741static const struct of_device_id tegra186_pmc_of_match[] = {
742 { .compatible = "nvidia,tegra186-pmc" },
743 { .compatible = "nvidia,tegra194-pmc" },
744 { .compatible = "nvidia,tegra234-pmc" },
745 { /* sentinel */ }
746};
747
748static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio)
749{
750 struct device *dev = gpio->gpio.parent;
751 unsigned int i;
752 u32 value;
753
754 for (i = 0; i < gpio->soc->num_ports; i++) {
755 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
756 unsigned int offset, p = port->port;
757 void __iomem *base;
758
759 base = gpio->secure + port->bank * 0x1000 + 0x800;
760
761 value = readl(base + TEGRA186_GPIO_CTL_SCR);
762
763 /*
764 * For controllers that haven't been locked down yet, make
765 * sure to program the default interrupt route mapping.
766 */
767 if ((value & TEGRA186_GPIO_CTL_SCR_SEC_REN) == 0 &&
768 (value & TEGRA186_GPIO_CTL_SCR_SEC_WEN) == 0) {
769 /*
770 * On Tegra194 and later, each pin can be routed to one or more
771 * interrupts.
772 */
773 dev_dbg(dev, "programming default interrupt routing for port %s\n",
774 port->name);
775
776 offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, 0);
777
778 /*
779 * By default we only want to route GPIO pins to IRQ 0. This works
780 * only under the assumption that we're running as the host kernel
781 * and hence all GPIO pins are owned by Linux.
782 *
783 * For cases where Linux is the guest OS, the hypervisor will have
784 * to configure the interrupt routing and pass only the valid
785 * interrupts via device tree.
786 */
787 value = readl(base + offset);
788 value = BIT(port->pins) - 1;
789 writel(value, base + offset);
790 }
791 }
792}
793
794static unsigned int tegra186_gpio_irqs_per_bank(struct tegra_gpio *gpio)
795{
796 struct device *dev = gpio->gpio.parent;
797
798 if (gpio->num_irq > gpio->num_banks) {
799 if (gpio->num_irq % gpio->num_banks != 0)
800 goto error;
801 }
802
803 if (gpio->num_irq < gpio->num_banks)
804 goto error;
805
806 gpio->num_irqs_per_bank = gpio->num_irq / gpio->num_banks;
807
808 if (gpio->num_irqs_per_bank > gpio->soc->num_irqs_per_bank)
809 goto error;
810
811 return 0;
812
813error:
814 dev_err(dev, "invalid number of interrupts (%u) for %u banks\n",
815 gpio->num_irq, gpio->num_banks);
816 return -EINVAL;
817}
818
819static int tegra186_gpio_probe(struct platform_device *pdev)
820{
821 unsigned int i, j, offset;
822 struct gpio_irq_chip *irq;
823 struct tegra_gpio *gpio;
824 struct device_node *np;
825 char **names;
826 int err;
827
828 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
829 if (!gpio)
830 return -ENOMEM;
831
832 gpio->soc = device_get_match_data(&pdev->dev);
833 gpio->gpio.label = gpio->soc->name;
834 gpio->gpio.parent = &pdev->dev;
835
836 /* count the number of banks in the controller */
837 for (i = 0; i < gpio->soc->num_ports; i++)
838 if (gpio->soc->ports[i].bank > gpio->num_banks)
839 gpio->num_banks = gpio->soc->ports[i].bank;
840
841 gpio->num_banks++;
842
843 /* get register apertures */
844 gpio->secure = devm_platform_ioremap_resource_byname(pdev, "security");
845 if (IS_ERR(gpio->secure)) {
846 gpio->secure = devm_platform_ioremap_resource(pdev, 0);
847 if (IS_ERR(gpio->secure))
848 return PTR_ERR(gpio->secure);
849 }
850
851 gpio->base = devm_platform_ioremap_resource_byname(pdev, "gpio");
852 if (IS_ERR(gpio->base)) {
853 gpio->base = devm_platform_ioremap_resource(pdev, 1);
854 if (IS_ERR(gpio->base))
855 return PTR_ERR(gpio->base);
856 }
857
858 err = platform_irq_count(pdev);
859 if (err < 0)
860 return err;
861
862 gpio->num_irq = err;
863
864 err = tegra186_gpio_irqs_per_bank(gpio);
865 if (err < 0)
866 return err;
867
868 gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq),
869 GFP_KERNEL);
870 if (!gpio->irq)
871 return -ENOMEM;
872
873 for (i = 0; i < gpio->num_irq; i++) {
874 err = platform_get_irq(pdev, i);
875 if (err < 0)
876 return err;
877
878 gpio->irq[i] = err;
879 }
880
881 gpio->gpio.request = gpiochip_generic_request;
882 gpio->gpio.free = gpiochip_generic_free;
883 gpio->gpio.get_direction = tegra186_gpio_get_direction;
884 gpio->gpio.direction_input = tegra186_gpio_direction_input;
885 gpio->gpio.direction_output = tegra186_gpio_direction_output;
886 gpio->gpio.get = tegra186_gpio_get;
887 gpio->gpio.set = tegra186_gpio_set;
888 gpio->gpio.set_config = tegra186_gpio_set_config;
889 gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges;
890 gpio->gpio.init_valid_mask = tegra186_init_valid_mask;
891 if (gpio->soc->has_gte) {
892 gpio->gpio.en_hw_timestamp = tegra186_gpio_en_hw_ts;
893 gpio->gpio.dis_hw_timestamp = tegra186_gpio_dis_hw_ts;
894 }
895
896 gpio->gpio.base = -1;
897
898 for (i = 0; i < gpio->soc->num_ports; i++)
899 gpio->gpio.ngpio += gpio->soc->ports[i].pins;
900
901 names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio,
902 sizeof(*names), GFP_KERNEL);
903 if (!names)
904 return -ENOMEM;
905
906 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
907 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
908 char *name;
909
910 for (j = 0; j < port->pins; j++) {
911 name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL,
912 "P%s.%02x", port->name, j);
913 if (!name)
914 return -ENOMEM;
915
916 names[offset + j] = name;
917 }
918
919 offset += port->pins;
920 }
921
922 gpio->gpio.names = (const char * const *)names;
923
924#if defined(CONFIG_OF_GPIO)
925 gpio->gpio.of_gpio_n_cells = 2;
926 gpio->gpio.of_xlate = tegra186_gpio_of_xlate;
927#endif /* CONFIG_OF_GPIO */
928
929 irq = &gpio->gpio.irq;
930 gpio_irq_chip_set_chip(irq, &tegra186_gpio_irq_chip);
931 irq->fwnode = of_node_to_fwnode(pdev->dev.of_node);
932 irq->child_to_parent_hwirq = tegra186_gpio_child_to_parent_hwirq;
933 irq->populate_parent_alloc_arg = tegra186_gpio_populate_parent_fwspec;
934 irq->child_offset_to_irq = tegra186_gpio_child_offset_to_irq;
935 irq->child_irq_domain_ops.translate = tegra186_gpio_irq_domain_translate;
936 irq->handler = handle_simple_irq;
937 irq->default_type = IRQ_TYPE_NONE;
938 irq->parent_handler = tegra186_gpio_irq;
939 irq->parent_handler_data = gpio;
940 irq->num_parents = gpio->num_irq;
941
942 /*
943 * To simplify things, use a single interrupt per bank for now. Some
944 * chips support up to 8 interrupts per bank, which can be useful to
945 * distribute the load and decrease the processing latency for GPIOs
946 * but it also requires a more complicated interrupt routing than we
947 * currently program.
948 */
949 if (gpio->num_irqs_per_bank > 1) {
950 irq->parents = devm_kcalloc(&pdev->dev, gpio->num_banks,
951 sizeof(*irq->parents), GFP_KERNEL);
952 if (!irq->parents)
953 return -ENOMEM;
954
955 for (i = 0; i < gpio->num_banks; i++)
956 irq->parents[i] = gpio->irq[i * gpio->num_irqs_per_bank];
957
958 irq->num_parents = gpio->num_banks;
959 } else {
960 irq->num_parents = gpio->num_irq;
961 irq->parents = gpio->irq;
962 }
963
964 if (gpio->soc->num_irqs_per_bank > 1)
965 tegra186_gpio_init_route_mapping(gpio);
966
967 np = of_find_matching_node(NULL, tegra186_pmc_of_match);
968 if (np) {
969 if (of_device_is_available(np)) {
970 irq->parent_domain = irq_find_host(np);
971 of_node_put(np);
972
973 if (!irq->parent_domain)
974 return -EPROBE_DEFER;
975 } else {
976 of_node_put(np);
977 }
978 }
979
980 irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio,
981 sizeof(*irq->map), GFP_KERNEL);
982 if (!irq->map)
983 return -ENOMEM;
984
985 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
986 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
987
988 for (j = 0; j < port->pins; j++)
989 irq->map[offset + j] = irq->parents[port->bank];
990
991 offset += port->pins;
992 }
993
994 return devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio);
995}
996
997#define TEGRA186_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
998 [TEGRA186_MAIN_GPIO_PORT_##_name] = { \
999 .name = #_name, \
1000 .bank = _bank, \
1001 .port = _port, \
1002 .pins = _pins, \
1003 }
1004
1005static const struct tegra_gpio_port tegra186_main_ports[] = {
1006 TEGRA186_MAIN_GPIO_PORT( A, 2, 0, 7),
1007 TEGRA186_MAIN_GPIO_PORT( B, 3, 0, 7),
1008 TEGRA186_MAIN_GPIO_PORT( C, 3, 1, 7),
1009 TEGRA186_MAIN_GPIO_PORT( D, 3, 2, 6),
1010 TEGRA186_MAIN_GPIO_PORT( E, 2, 1, 8),
1011 TEGRA186_MAIN_GPIO_PORT( F, 2, 2, 6),
1012 TEGRA186_MAIN_GPIO_PORT( G, 4, 1, 6),
1013 TEGRA186_MAIN_GPIO_PORT( H, 1, 0, 7),
1014 TEGRA186_MAIN_GPIO_PORT( I, 0, 4, 8),
1015 TEGRA186_MAIN_GPIO_PORT( J, 5, 0, 8),
1016 TEGRA186_MAIN_GPIO_PORT( K, 5, 1, 1),
1017 TEGRA186_MAIN_GPIO_PORT( L, 1, 1, 8),
1018 TEGRA186_MAIN_GPIO_PORT( M, 5, 3, 6),
1019 TEGRA186_MAIN_GPIO_PORT( N, 0, 0, 7),
1020 TEGRA186_MAIN_GPIO_PORT( O, 0, 1, 4),
1021 TEGRA186_MAIN_GPIO_PORT( P, 4, 0, 7),
1022 TEGRA186_MAIN_GPIO_PORT( Q, 0, 2, 6),
1023 TEGRA186_MAIN_GPIO_PORT( R, 0, 5, 6),
1024 TEGRA186_MAIN_GPIO_PORT( T, 0, 3, 4),
1025 TEGRA186_MAIN_GPIO_PORT( X, 1, 2, 8),
1026 TEGRA186_MAIN_GPIO_PORT( Y, 1, 3, 7),
1027 TEGRA186_MAIN_GPIO_PORT(BB, 2, 3, 2),
1028 TEGRA186_MAIN_GPIO_PORT(CC, 5, 2, 4),
1029};
1030
1031static const struct tegra_gpio_soc tegra186_main_soc = {
1032 .num_ports = ARRAY_SIZE(tegra186_main_ports),
1033 .ports = tegra186_main_ports,
1034 .name = "tegra186-gpio",
1035 .instance = 0,
1036 .num_irqs_per_bank = 1,
1037 .has_vm_support = false,
1038};
1039
1040#define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \
1041 [TEGRA186_AON_GPIO_PORT_##_name] = { \
1042 .name = #_name, \
1043 .bank = _bank, \
1044 .port = _port, \
1045 .pins = _pins, \
1046 }
1047
1048static const struct tegra_gpio_port tegra186_aon_ports[] = {
1049 TEGRA186_AON_GPIO_PORT( S, 0, 1, 5),
1050 TEGRA186_AON_GPIO_PORT( U, 0, 2, 6),
1051 TEGRA186_AON_GPIO_PORT( V, 0, 4, 8),
1052 TEGRA186_AON_GPIO_PORT( W, 0, 5, 8),
1053 TEGRA186_AON_GPIO_PORT( Z, 0, 7, 4),
1054 TEGRA186_AON_GPIO_PORT(AA, 0, 6, 8),
1055 TEGRA186_AON_GPIO_PORT(EE, 0, 3, 3),
1056 TEGRA186_AON_GPIO_PORT(FF, 0, 0, 5),
1057};
1058
1059static const struct tegra_gpio_soc tegra186_aon_soc = {
1060 .num_ports = ARRAY_SIZE(tegra186_aon_ports),
1061 .ports = tegra186_aon_ports,
1062 .name = "tegra186-gpio-aon",
1063 .instance = 1,
1064 .num_irqs_per_bank = 1,
1065 .has_vm_support = false,
1066};
1067
1068#define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
1069 [TEGRA194_MAIN_GPIO_PORT_##_name] = { \
1070 .name = #_name, \
1071 .bank = _bank, \
1072 .port = _port, \
1073 .pins = _pins, \
1074 }
1075
1076static const struct tegra_gpio_port tegra194_main_ports[] = {
1077 TEGRA194_MAIN_GPIO_PORT( A, 1, 2, 8),
1078 TEGRA194_MAIN_GPIO_PORT( B, 4, 7, 2),
1079 TEGRA194_MAIN_GPIO_PORT( C, 4, 3, 8),
1080 TEGRA194_MAIN_GPIO_PORT( D, 4, 4, 4),
1081 TEGRA194_MAIN_GPIO_PORT( E, 4, 5, 8),
1082 TEGRA194_MAIN_GPIO_PORT( F, 4, 6, 6),
1083 TEGRA194_MAIN_GPIO_PORT( G, 4, 0, 8),
1084 TEGRA194_MAIN_GPIO_PORT( H, 4, 1, 8),
1085 TEGRA194_MAIN_GPIO_PORT( I, 4, 2, 5),
1086 TEGRA194_MAIN_GPIO_PORT( J, 5, 1, 6),
1087 TEGRA194_MAIN_GPIO_PORT( K, 3, 0, 8),
1088 TEGRA194_MAIN_GPIO_PORT( L, 3, 1, 4),
1089 TEGRA194_MAIN_GPIO_PORT( M, 2, 3, 8),
1090 TEGRA194_MAIN_GPIO_PORT( N, 2, 4, 3),
1091 TEGRA194_MAIN_GPIO_PORT( O, 5, 0, 6),
1092 TEGRA194_MAIN_GPIO_PORT( P, 2, 5, 8),
1093 TEGRA194_MAIN_GPIO_PORT( Q, 2, 6, 8),
1094 TEGRA194_MAIN_GPIO_PORT( R, 2, 7, 6),
1095 TEGRA194_MAIN_GPIO_PORT( S, 3, 3, 8),
1096 TEGRA194_MAIN_GPIO_PORT( T, 3, 4, 8),
1097 TEGRA194_MAIN_GPIO_PORT( U, 3, 5, 1),
1098 TEGRA194_MAIN_GPIO_PORT( V, 1, 0, 8),
1099 TEGRA194_MAIN_GPIO_PORT( W, 1, 1, 2),
1100 TEGRA194_MAIN_GPIO_PORT( X, 2, 0, 8),
1101 TEGRA194_MAIN_GPIO_PORT( Y, 2, 1, 8),
1102 TEGRA194_MAIN_GPIO_PORT( Z, 2, 2, 8),
1103 TEGRA194_MAIN_GPIO_PORT(FF, 3, 2, 2),
1104 TEGRA194_MAIN_GPIO_PORT(GG, 0, 0, 2)
1105};
1106
1107static const struct tegra186_pin_range tegra194_main_pin_ranges[] = {
1108 { TEGRA194_MAIN_GPIO(GG, 0), "pex_l5_clkreq_n_pgg0" },
1109 { TEGRA194_MAIN_GPIO(GG, 1), "pex_l5_rst_n_pgg1" },
1110};
1111
1112static const struct tegra_gpio_soc tegra194_main_soc = {
1113 .num_ports = ARRAY_SIZE(tegra194_main_ports),
1114 .ports = tegra194_main_ports,
1115 .name = "tegra194-gpio",
1116 .instance = 0,
1117 .num_irqs_per_bank = 8,
1118 .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges),
1119 .pin_ranges = tegra194_main_pin_ranges,
1120 .pinmux = "nvidia,tegra194-pinmux",
1121 .has_vm_support = true,
1122};
1123
1124#define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \
1125 [TEGRA194_AON_GPIO_PORT_##_name] = { \
1126 .name = #_name, \
1127 .bank = _bank, \
1128 .port = _port, \
1129 .pins = _pins, \
1130 }
1131
1132static const struct tegra_gpio_port tegra194_aon_ports[] = {
1133 TEGRA194_AON_GPIO_PORT(AA, 0, 3, 8),
1134 TEGRA194_AON_GPIO_PORT(BB, 0, 4, 4),
1135 TEGRA194_AON_GPIO_PORT(CC, 0, 1, 8),
1136 TEGRA194_AON_GPIO_PORT(DD, 0, 2, 3),
1137 TEGRA194_AON_GPIO_PORT(EE, 0, 0, 7)
1138};
1139
1140static const struct tegra_gpio_soc tegra194_aon_soc = {
1141 .num_ports = ARRAY_SIZE(tegra194_aon_ports),
1142 .ports = tegra194_aon_ports,
1143 .name = "tegra194-gpio-aon",
1144 .instance = 1,
1145 .num_irqs_per_bank = 8,
1146 .has_gte = true,
1147 .has_vm_support = false,
1148};
1149
1150#define TEGRA234_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
1151 [TEGRA234_MAIN_GPIO_PORT_##_name] = { \
1152 .name = #_name, \
1153 .bank = _bank, \
1154 .port = _port, \
1155 .pins = _pins, \
1156 }
1157
1158static const struct tegra_gpio_port tegra234_main_ports[] = {
1159 TEGRA234_MAIN_GPIO_PORT( A, 0, 0, 8),
1160 TEGRA234_MAIN_GPIO_PORT( B, 0, 3, 1),
1161 TEGRA234_MAIN_GPIO_PORT( C, 5, 1, 8),
1162 TEGRA234_MAIN_GPIO_PORT( D, 5, 2, 4),
1163 TEGRA234_MAIN_GPIO_PORT( E, 5, 3, 8),
1164 TEGRA234_MAIN_GPIO_PORT( F, 5, 4, 6),
1165 TEGRA234_MAIN_GPIO_PORT( G, 4, 0, 8),
1166 TEGRA234_MAIN_GPIO_PORT( H, 4, 1, 8),
1167 TEGRA234_MAIN_GPIO_PORT( I, 4, 2, 7),
1168 TEGRA234_MAIN_GPIO_PORT( J, 5, 0, 6),
1169 TEGRA234_MAIN_GPIO_PORT( K, 3, 0, 8),
1170 TEGRA234_MAIN_GPIO_PORT( L, 3, 1, 4),
1171 TEGRA234_MAIN_GPIO_PORT( M, 2, 0, 8),
1172 TEGRA234_MAIN_GPIO_PORT( N, 2, 1, 8),
1173 TEGRA234_MAIN_GPIO_PORT( P, 2, 2, 8),
1174 TEGRA234_MAIN_GPIO_PORT( Q, 2, 3, 8),
1175 TEGRA234_MAIN_GPIO_PORT( R, 2, 4, 6),
1176 TEGRA234_MAIN_GPIO_PORT( X, 1, 0, 8),
1177 TEGRA234_MAIN_GPIO_PORT( Y, 1, 1, 8),
1178 TEGRA234_MAIN_GPIO_PORT( Z, 1, 2, 8),
1179 TEGRA234_MAIN_GPIO_PORT(AC, 0, 1, 8),
1180 TEGRA234_MAIN_GPIO_PORT(AD, 0, 2, 4),
1181 TEGRA234_MAIN_GPIO_PORT(AE, 3, 3, 2),
1182 TEGRA234_MAIN_GPIO_PORT(AF, 3, 4, 4),
1183 TEGRA234_MAIN_GPIO_PORT(AG, 3, 2, 8),
1184};
1185
1186static const struct tegra_gpio_soc tegra234_main_soc = {
1187 .num_ports = ARRAY_SIZE(tegra234_main_ports),
1188 .ports = tegra234_main_ports,
1189 .name = "tegra234-gpio",
1190 .instance = 0,
1191 .num_irqs_per_bank = 8,
1192 .has_vm_support = true,
1193};
1194
1195#define TEGRA234_AON_GPIO_PORT(_name, _bank, _port, _pins) \
1196 [TEGRA234_AON_GPIO_PORT_##_name] = { \
1197 .name = #_name, \
1198 .bank = _bank, \
1199 .port = _port, \
1200 .pins = _pins, \
1201 }
1202
1203static const struct tegra_gpio_port tegra234_aon_ports[] = {
1204 TEGRA234_AON_GPIO_PORT(AA, 0, 4, 8),
1205 TEGRA234_AON_GPIO_PORT(BB, 0, 5, 4),
1206 TEGRA234_AON_GPIO_PORT(CC, 0, 2, 8),
1207 TEGRA234_AON_GPIO_PORT(DD, 0, 3, 3),
1208 TEGRA234_AON_GPIO_PORT(EE, 0, 0, 8),
1209 TEGRA234_AON_GPIO_PORT(GG, 0, 1, 1),
1210};
1211
1212static const struct tegra_gpio_soc tegra234_aon_soc = {
1213 .num_ports = ARRAY_SIZE(tegra234_aon_ports),
1214 .ports = tegra234_aon_ports,
1215 .name = "tegra234-gpio-aon",
1216 .instance = 1,
1217 .num_irqs_per_bank = 8,
1218 .has_gte = true,
1219 .has_vm_support = false,
1220};
1221
1222#define TEGRA241_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
1223 [TEGRA241_MAIN_GPIO_PORT_##_name] = { \
1224 .name = #_name, \
1225 .bank = _bank, \
1226 .port = _port, \
1227 .pins = _pins, \
1228 }
1229
1230static const struct tegra_gpio_port tegra241_main_ports[] = {
1231 TEGRA241_MAIN_GPIO_PORT(A, 0, 0, 8),
1232 TEGRA241_MAIN_GPIO_PORT(B, 0, 1, 8),
1233 TEGRA241_MAIN_GPIO_PORT(C, 0, 2, 2),
1234 TEGRA241_MAIN_GPIO_PORT(D, 0, 3, 6),
1235 TEGRA241_MAIN_GPIO_PORT(E, 0, 4, 8),
1236 TEGRA241_MAIN_GPIO_PORT(F, 1, 0, 8),
1237 TEGRA241_MAIN_GPIO_PORT(G, 1, 1, 8),
1238 TEGRA241_MAIN_GPIO_PORT(H, 1, 2, 8),
1239 TEGRA241_MAIN_GPIO_PORT(J, 1, 3, 8),
1240 TEGRA241_MAIN_GPIO_PORT(K, 1, 4, 4),
1241 TEGRA241_MAIN_GPIO_PORT(L, 1, 5, 6),
1242};
1243
1244static const struct tegra_gpio_soc tegra241_main_soc = {
1245 .num_ports = ARRAY_SIZE(tegra241_main_ports),
1246 .ports = tegra241_main_ports,
1247 .name = "tegra241-gpio",
1248 .instance = 0,
1249 .num_irqs_per_bank = 8,
1250 .has_vm_support = false,
1251};
1252
1253#define TEGRA241_AON_GPIO_PORT(_name, _bank, _port, _pins) \
1254 [TEGRA241_AON_GPIO_PORT_##_name] = { \
1255 .name = #_name, \
1256 .bank = _bank, \
1257 .port = _port, \
1258 .pins = _pins, \
1259 }
1260
1261static const struct tegra_gpio_port tegra241_aon_ports[] = {
1262 TEGRA241_AON_GPIO_PORT(AA, 0, 0, 8),
1263 TEGRA241_AON_GPIO_PORT(BB, 0, 0, 4),
1264};
1265
1266static const struct tegra_gpio_soc tegra241_aon_soc = {
1267 .num_ports = ARRAY_SIZE(tegra241_aon_ports),
1268 .ports = tegra241_aon_ports,
1269 .name = "tegra241-gpio-aon",
1270 .instance = 1,
1271 .num_irqs_per_bank = 8,
1272 .has_vm_support = false,
1273};
1274
1275static const struct of_device_id tegra186_gpio_of_match[] = {
1276 {
1277 .compatible = "nvidia,tegra186-gpio",
1278 .data = &tegra186_main_soc
1279 }, {
1280 .compatible = "nvidia,tegra186-gpio-aon",
1281 .data = &tegra186_aon_soc
1282 }, {
1283 .compatible = "nvidia,tegra194-gpio",
1284 .data = &tegra194_main_soc
1285 }, {
1286 .compatible = "nvidia,tegra194-gpio-aon",
1287 .data = &tegra194_aon_soc
1288 }, {
1289 .compatible = "nvidia,tegra234-gpio",
1290 .data = &tegra234_main_soc
1291 }, {
1292 .compatible = "nvidia,tegra234-gpio-aon",
1293 .data = &tegra234_aon_soc
1294 }, {
1295 /* sentinel */
1296 }
1297};
1298MODULE_DEVICE_TABLE(of, tegra186_gpio_of_match);
1299
1300static const struct acpi_device_id tegra186_gpio_acpi_match[] = {
1301 { .id = "NVDA0108", .driver_data = (kernel_ulong_t)&tegra186_main_soc },
1302 { .id = "NVDA0208", .driver_data = (kernel_ulong_t)&tegra186_aon_soc },
1303 { .id = "NVDA0308", .driver_data = (kernel_ulong_t)&tegra194_main_soc },
1304 { .id = "NVDA0408", .driver_data = (kernel_ulong_t)&tegra194_aon_soc },
1305 { .id = "NVDA0508", .driver_data = (kernel_ulong_t)&tegra241_main_soc },
1306 { .id = "NVDA0608", .driver_data = (kernel_ulong_t)&tegra241_aon_soc },
1307 {}
1308};
1309MODULE_DEVICE_TABLE(acpi, tegra186_gpio_acpi_match);
1310
1311static struct platform_driver tegra186_gpio_driver = {
1312 .driver = {
1313 .name = "tegra186-gpio",
1314 .of_match_table = tegra186_gpio_of_match,
1315 .acpi_match_table = tegra186_gpio_acpi_match,
1316 },
1317 .probe = tegra186_gpio_probe,
1318};
1319module_platform_driver(tegra186_gpio_driver);
1320
1321MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver");
1322MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
1323MODULE_LICENSE("GPL v2");