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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Driver Header File for FPGA Device Feature List (DFL) Support
4 *
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
6 *
7 * Authors:
8 * Kang Luwei <luwei.kang@intel.com>
9 * Zhang Yi <yi.z.zhang@intel.com>
10 * Wu Hao <hao.wu@intel.com>
11 * Xiao Guangrong <guangrong.xiao@linux.intel.com>
12 */
13
14#ifndef __FPGA_DFL_H
15#define __FPGA_DFL_H
16
17#include <linux/bitfield.h>
18#include <linux/cdev.h>
19#include <linux/delay.h>
20#include <linux/eventfd.h>
21#include <linux/fs.h>
22#include <linux/interrupt.h>
23#include <linux/iopoll.h>
24#include <linux/io-64-nonatomic-lo-hi.h>
25#include <linux/platform_device.h>
26#include <linux/slab.h>
27#include <linux/uuid.h>
28#include <linux/fpga/fpga-region.h>
29
30/* maximum supported number of ports */
31#define MAX_DFL_FPGA_PORT_NUM 4
32/* plus one for fme device */
33#define MAX_DFL_FEATURE_DEV_NUM (MAX_DFL_FPGA_PORT_NUM + 1)
34
35/* Reserved 0xfe for Header Group Register and 0xff for AFU */
36#define FEATURE_ID_FIU_HEADER 0xfe
37#define FEATURE_ID_AFU 0xff
38
39#define FME_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER
40#define FME_FEATURE_ID_THERMAL_MGMT 0x1
41#define FME_FEATURE_ID_POWER_MGMT 0x2
42#define FME_FEATURE_ID_GLOBAL_IPERF 0x3
43#define FME_FEATURE_ID_GLOBAL_ERR 0x4
44#define FME_FEATURE_ID_PR_MGMT 0x5
45#define FME_FEATURE_ID_HSSI 0x6
46#define FME_FEATURE_ID_GLOBAL_DPERF 0x7
47
48#define PORT_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER
49#define PORT_FEATURE_ID_AFU FEATURE_ID_AFU
50#define PORT_FEATURE_ID_ERROR 0x10
51#define PORT_FEATURE_ID_UMSG 0x11
52#define PORT_FEATURE_ID_UINT 0x12
53#define PORT_FEATURE_ID_STP 0x13
54
55/*
56 * Device Feature Header Register Set
57 *
58 * For FIUs, they all have DFH + GUID + NEXT_AFU as common header registers.
59 * For AFUs, they have DFH + GUID as common header registers.
60 * For private features, they only have DFH register as common header.
61 */
62#define DFH 0x0
63#define GUID_L 0x8
64#define GUID_H 0x10
65#define NEXT_AFU 0x18
66
67#define DFH_SIZE 0x8
68
69/* Device Feature Header Register Bitfield */
70#define DFH_ID GENMASK_ULL(11, 0) /* Feature ID */
71#define DFH_ID_FIU_FME 0
72#define DFH_ID_FIU_PORT 1
73#define DFH_REVISION GENMASK_ULL(15, 12) /* Feature revision */
74#define DFH_NEXT_HDR_OFST GENMASK_ULL(39, 16) /* Offset to next DFH */
75#define DFH_EOL BIT_ULL(40) /* End of list */
76#define DFH_TYPE GENMASK_ULL(63, 60) /* Feature type */
77#define DFH_TYPE_AFU 1
78#define DFH_TYPE_PRIVATE 3
79#define DFH_TYPE_FIU 4
80
81/* Next AFU Register Bitfield */
82#define NEXT_AFU_NEXT_DFH_OFST GENMASK_ULL(23, 0) /* Offset to next AFU */
83
84/* FME Header Register Set */
85#define FME_HDR_DFH DFH
86#define FME_HDR_GUID_L GUID_L
87#define FME_HDR_GUID_H GUID_H
88#define FME_HDR_NEXT_AFU NEXT_AFU
89#define FME_HDR_CAP 0x30
90#define FME_HDR_PORT_OFST(n) (0x38 + ((n) * 0x8))
91#define FME_HDR_BITSTREAM_ID 0x60
92#define FME_HDR_BITSTREAM_MD 0x68
93
94/* FME Fab Capability Register Bitfield */
95#define FME_CAP_FABRIC_VERID GENMASK_ULL(7, 0) /* Fabric version ID */
96#define FME_CAP_SOCKET_ID BIT_ULL(8) /* Socket ID */
97#define FME_CAP_PCIE0_LINK_AVL BIT_ULL(12) /* PCIE0 Link */
98#define FME_CAP_PCIE1_LINK_AVL BIT_ULL(13) /* PCIE1 Link */
99#define FME_CAP_COHR_LINK_AVL BIT_ULL(14) /* Coherent Link */
100#define FME_CAP_IOMMU_AVL BIT_ULL(16) /* IOMMU available */
101#define FME_CAP_NUM_PORTS GENMASK_ULL(19, 17) /* Number of ports */
102#define FME_CAP_ADDR_WIDTH GENMASK_ULL(29, 24) /* Address bus width */
103#define FME_CAP_CACHE_SIZE GENMASK_ULL(43, 32) /* cache size in KB */
104#define FME_CAP_CACHE_ASSOC GENMASK_ULL(47, 44) /* Associativity */
105
106/* FME Port Offset Register Bitfield */
107/* Offset to port device feature header */
108#define FME_PORT_OFST_DFH_OFST GENMASK_ULL(23, 0)
109/* PCI Bar ID for this port */
110#define FME_PORT_OFST_BAR_ID GENMASK_ULL(34, 32)
111/* AFU MMIO access permission. 1 - VF, 0 - PF. */
112#define FME_PORT_OFST_ACC_CTRL BIT_ULL(55)
113#define FME_PORT_OFST_ACC_PF 0
114#define FME_PORT_OFST_ACC_VF 1
115#define FME_PORT_OFST_IMP BIT_ULL(60)
116
117/* FME Error Capability Register */
118#define FME_ERROR_CAP 0x70
119
120/* FME Error Capability Register Bitfield */
121#define FME_ERROR_CAP_SUPP_INT BIT_ULL(0) /* Interrupt Support */
122#define FME_ERROR_CAP_INT_VECT GENMASK_ULL(12, 1) /* Interrupt vector */
123
124/* PORT Header Register Set */
125#define PORT_HDR_DFH DFH
126#define PORT_HDR_GUID_L GUID_L
127#define PORT_HDR_GUID_H GUID_H
128#define PORT_HDR_NEXT_AFU NEXT_AFU
129#define PORT_HDR_CAP 0x30
130#define PORT_HDR_CTRL 0x38
131#define PORT_HDR_STS 0x40
132#define PORT_HDR_USRCLK_CMD0 0x50
133#define PORT_HDR_USRCLK_CMD1 0x58
134#define PORT_HDR_USRCLK_STS0 0x60
135#define PORT_HDR_USRCLK_STS1 0x68
136
137/* Port Capability Register Bitfield */
138#define PORT_CAP_PORT_NUM GENMASK_ULL(1, 0) /* ID of this port */
139#define PORT_CAP_MMIO_SIZE GENMASK_ULL(23, 8) /* MMIO size in KB */
140#define PORT_CAP_SUPP_INT_NUM GENMASK_ULL(35, 32) /* Interrupts num */
141
142/* Port Control Register Bitfield */
143#define PORT_CTRL_SFTRST BIT_ULL(0) /* Port soft reset */
144/* Latency tolerance reporting. '1' >= 40us, '0' < 40us.*/
145#define PORT_CTRL_LATENCY BIT_ULL(2)
146#define PORT_CTRL_SFTRST_ACK BIT_ULL(4) /* HW ack for reset */
147
148/* Port Status Register Bitfield */
149#define PORT_STS_AP2_EVT BIT_ULL(13) /* AP2 event detected */
150#define PORT_STS_AP1_EVT BIT_ULL(12) /* AP1 event detected */
151#define PORT_STS_PWR_STATE GENMASK_ULL(11, 8) /* AFU power states */
152#define PORT_STS_PWR_STATE_NORM 0
153#define PORT_STS_PWR_STATE_AP1 1 /* 50% throttling */
154#define PORT_STS_PWR_STATE_AP2 2 /* 90% throttling */
155#define PORT_STS_PWR_STATE_AP6 6 /* 100% throttling */
156
157/* Port Error Capability Register */
158#define PORT_ERROR_CAP 0x38
159
160/* Port Error Capability Register Bitfield */
161#define PORT_ERROR_CAP_SUPP_INT BIT_ULL(0) /* Interrupt Support */
162#define PORT_ERROR_CAP_INT_VECT GENMASK_ULL(12, 1) /* Interrupt vector */
163
164/* Port Uint Capability Register */
165#define PORT_UINT_CAP 0x8
166
167/* Port Uint Capability Register Bitfield */
168#define PORT_UINT_CAP_INT_NUM GENMASK_ULL(11, 0) /* Interrupts num */
169#define PORT_UINT_CAP_FST_VECT GENMASK_ULL(23, 12) /* First Vector */
170
171/**
172 * struct dfl_fpga_port_ops - port ops
173 *
174 * @name: name of this port ops, to match with port platform device.
175 * @owner: pointer to the module which owns this port ops.
176 * @node: node to link port ops to global list.
177 * @get_id: get port id from hardware.
178 * @enable_set: enable/disable the port.
179 */
180struct dfl_fpga_port_ops {
181 const char *name;
182 struct module *owner;
183 struct list_head node;
184 int (*get_id)(struct platform_device *pdev);
185 int (*enable_set)(struct platform_device *pdev, bool enable);
186};
187
188void dfl_fpga_port_ops_add(struct dfl_fpga_port_ops *ops);
189void dfl_fpga_port_ops_del(struct dfl_fpga_port_ops *ops);
190struct dfl_fpga_port_ops *dfl_fpga_port_ops_get(struct platform_device *pdev);
191void dfl_fpga_port_ops_put(struct dfl_fpga_port_ops *ops);
192int dfl_fpga_check_port_id(struct platform_device *pdev, void *pport_id);
193
194/**
195 * struct dfl_feature_id - dfl private feature id
196 *
197 * @id: unique dfl private feature id.
198 */
199struct dfl_feature_id {
200 u64 id;
201};
202
203/**
204 * struct dfl_feature_driver - dfl private feature driver
205 *
206 * @id_table: id_table for dfl private features supported by this driver.
207 * @ops: ops of this dfl private feature driver.
208 */
209struct dfl_feature_driver {
210 const struct dfl_feature_id *id_table;
211 const struct dfl_feature_ops *ops;
212};
213
214/**
215 * struct dfl_feature_irq_ctx - dfl private feature interrupt context
216 *
217 * @irq: Linux IRQ number of this interrupt.
218 * @trigger: eventfd context to signal when interrupt happens.
219 * @name: irq name needed when requesting irq.
220 */
221struct dfl_feature_irq_ctx {
222 int irq;
223 struct eventfd_ctx *trigger;
224 char *name;
225};
226
227/**
228 * struct dfl_feature - sub feature of the feature devices
229 *
230 * @dev: ptr to pdev of the feature device which has the sub feature.
231 * @id: sub feature id.
232 * @resource_index: each sub feature has one mmio resource for its registers.
233 * this index is used to find its mmio resource from the
234 * feature dev (platform device)'s reources.
235 * @ioaddr: mapped mmio resource address.
236 * @irq_ctx: interrupt context list.
237 * @nr_irqs: number of interrupt contexts.
238 * @ops: ops of this sub feature.
239 * @priv: priv data of this feature.
240 */
241struct dfl_feature {
242 struct platform_device *dev;
243 u64 id;
244 int resource_index;
245 void __iomem *ioaddr;
246 struct dfl_feature_irq_ctx *irq_ctx;
247 unsigned int nr_irqs;
248 const struct dfl_feature_ops *ops;
249 void *priv;
250};
251
252#define FEATURE_DEV_ID_UNUSED (-1)
253
254/**
255 * struct dfl_feature_platform_data - platform data for feature devices
256 *
257 * @node: node to link feature devs to container device's port_dev_list.
258 * @lock: mutex to protect platform data.
259 * @cdev: cdev of feature dev.
260 * @dev: ptr to platform device linked with this platform data.
261 * @dfl_cdev: ptr to container device.
262 * @id: id used for this feature device.
263 * @disable_count: count for port disable.
264 * @excl_open: set on feature device exclusive open.
265 * @open_count: count for feature device open.
266 * @num: number for sub features.
267 * @private: ptr to feature dev private data.
268 * @features: sub features of this feature dev.
269 */
270struct dfl_feature_platform_data {
271 struct list_head node;
272 struct mutex lock;
273 struct cdev cdev;
274 struct platform_device *dev;
275 struct dfl_fpga_cdev *dfl_cdev;
276 int id;
277 unsigned int disable_count;
278 bool excl_open;
279 int open_count;
280 void *private;
281 int num;
282 struct dfl_feature features[];
283};
284
285static inline
286int dfl_feature_dev_use_begin(struct dfl_feature_platform_data *pdata,
287 bool excl)
288{
289 if (pdata->excl_open)
290 return -EBUSY;
291
292 if (excl) {
293 if (pdata->open_count)
294 return -EBUSY;
295
296 pdata->excl_open = true;
297 }
298 pdata->open_count++;
299
300 return 0;
301}
302
303static inline
304void dfl_feature_dev_use_end(struct dfl_feature_platform_data *pdata)
305{
306 pdata->excl_open = false;
307
308 if (WARN_ON(pdata->open_count <= 0))
309 return;
310
311 pdata->open_count--;
312}
313
314static inline
315int dfl_feature_dev_use_count(struct dfl_feature_platform_data *pdata)
316{
317 return pdata->open_count;
318}
319
320static inline
321void dfl_fpga_pdata_set_private(struct dfl_feature_platform_data *pdata,
322 void *private)
323{
324 pdata->private = private;
325}
326
327static inline
328void *dfl_fpga_pdata_get_private(struct dfl_feature_platform_data *pdata)
329{
330 return pdata->private;
331}
332
333struct dfl_feature_ops {
334 int (*init)(struct platform_device *pdev, struct dfl_feature *feature);
335 void (*uinit)(struct platform_device *pdev,
336 struct dfl_feature *feature);
337 long (*ioctl)(struct platform_device *pdev, struct dfl_feature *feature,
338 unsigned int cmd, unsigned long arg);
339};
340
341#define DFL_FPGA_FEATURE_DEV_FME "dfl-fme"
342#define DFL_FPGA_FEATURE_DEV_PORT "dfl-port"
343
344void dfl_fpga_dev_feature_uinit(struct platform_device *pdev);
345int dfl_fpga_dev_feature_init(struct platform_device *pdev,
346 struct dfl_feature_driver *feature_drvs);
347
348int dfl_fpga_dev_ops_register(struct platform_device *pdev,
349 const struct file_operations *fops,
350 struct module *owner);
351void dfl_fpga_dev_ops_unregister(struct platform_device *pdev);
352
353static inline
354struct platform_device *dfl_fpga_inode_to_feature_dev(struct inode *inode)
355{
356 struct dfl_feature_platform_data *pdata;
357
358 pdata = container_of(inode->i_cdev, struct dfl_feature_platform_data,
359 cdev);
360 return pdata->dev;
361}
362
363#define dfl_fpga_dev_for_each_feature(pdata, feature) \
364 for ((feature) = (pdata)->features; \
365 (feature) < (pdata)->features + (pdata)->num; (feature)++)
366
367static inline
368struct dfl_feature *dfl_get_feature_by_id(struct device *dev, u64 id)
369{
370 struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
371 struct dfl_feature *feature;
372
373 dfl_fpga_dev_for_each_feature(pdata, feature)
374 if (feature->id == id)
375 return feature;
376
377 return NULL;
378}
379
380static inline
381void __iomem *dfl_get_feature_ioaddr_by_id(struct device *dev, u64 id)
382{
383 struct dfl_feature *feature = dfl_get_feature_by_id(dev, id);
384
385 if (feature && feature->ioaddr)
386 return feature->ioaddr;
387
388 WARN_ON(1);
389 return NULL;
390}
391
392static inline bool is_dfl_feature_present(struct device *dev, u64 id)
393{
394 return !!dfl_get_feature_ioaddr_by_id(dev, id);
395}
396
397static inline
398struct device *dfl_fpga_pdata_to_parent(struct dfl_feature_platform_data *pdata)
399{
400 return pdata->dev->dev.parent->parent;
401}
402
403static inline bool dfl_feature_is_fme(void __iomem *base)
404{
405 u64 v = readq(base + DFH);
406
407 return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) &&
408 (FIELD_GET(DFH_ID, v) == DFH_ID_FIU_FME);
409}
410
411static inline bool dfl_feature_is_port(void __iomem *base)
412{
413 u64 v = readq(base + DFH);
414
415 return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) &&
416 (FIELD_GET(DFH_ID, v) == DFH_ID_FIU_PORT);
417}
418
419static inline u8 dfl_feature_revision(void __iomem *base)
420{
421 return (u8)FIELD_GET(DFH_REVISION, readq(base + DFH));
422}
423
424/**
425 * struct dfl_fpga_enum_info - DFL FPGA enumeration information
426 *
427 * @dev: parent device.
428 * @dfls: list of device feature lists.
429 * @nr_irqs: number of irqs for all feature devices.
430 * @irq_table: Linux IRQ numbers for all irqs, indexed by hw irq numbers.
431 */
432struct dfl_fpga_enum_info {
433 struct device *dev;
434 struct list_head dfls;
435 unsigned int nr_irqs;
436 int *irq_table;
437};
438
439/**
440 * struct dfl_fpga_enum_dfl - DFL FPGA enumeration device feature list info
441 *
442 * @start: base address of this device feature list.
443 * @len: size of this device feature list.
444 * @ioaddr: mapped base address of this device feature list.
445 * @node: node in list of device feature lists.
446 */
447struct dfl_fpga_enum_dfl {
448 resource_size_t start;
449 resource_size_t len;
450
451 void __iomem *ioaddr;
452
453 struct list_head node;
454};
455
456struct dfl_fpga_enum_info *dfl_fpga_enum_info_alloc(struct device *dev);
457int dfl_fpga_enum_info_add_dfl(struct dfl_fpga_enum_info *info,
458 resource_size_t start, resource_size_t len,
459 void __iomem *ioaddr);
460int dfl_fpga_enum_info_add_irq(struct dfl_fpga_enum_info *info,
461 unsigned int nr_irqs, int *irq_table);
462void dfl_fpga_enum_info_free(struct dfl_fpga_enum_info *info);
463
464/**
465 * struct dfl_fpga_cdev - container device of DFL based FPGA
466 *
467 * @parent: parent device of this container device.
468 * @region: base fpga region.
469 * @fme_dev: FME feature device under this container device.
470 * @lock: mutex lock to protect the port device list.
471 * @port_dev_list: list of all port feature devices under this container device.
472 * @released_port_num: released port number under this container device.
473 */
474struct dfl_fpga_cdev {
475 struct device *parent;
476 struct fpga_region *region;
477 struct device *fme_dev;
478 struct mutex lock;
479 struct list_head port_dev_list;
480 int released_port_num;
481};
482
483struct dfl_fpga_cdev *
484dfl_fpga_feature_devs_enumerate(struct dfl_fpga_enum_info *info);
485void dfl_fpga_feature_devs_remove(struct dfl_fpga_cdev *cdev);
486
487/*
488 * need to drop the device reference with put_device() after use port platform
489 * device returned by __dfl_fpga_cdev_find_port and dfl_fpga_cdev_find_port
490 * functions.
491 */
492struct platform_device *
493__dfl_fpga_cdev_find_port(struct dfl_fpga_cdev *cdev, void *data,
494 int (*match)(struct platform_device *, void *));
495
496static inline struct platform_device *
497dfl_fpga_cdev_find_port(struct dfl_fpga_cdev *cdev, void *data,
498 int (*match)(struct platform_device *, void *))
499{
500 struct platform_device *pdev;
501
502 mutex_lock(&cdev->lock);
503 pdev = __dfl_fpga_cdev_find_port(cdev, data, match);
504 mutex_unlock(&cdev->lock);
505
506 return pdev;
507}
508
509int dfl_fpga_cdev_release_port(struct dfl_fpga_cdev *cdev, int port_id);
510int dfl_fpga_cdev_assign_port(struct dfl_fpga_cdev *cdev, int port_id);
511void dfl_fpga_cdev_config_ports_pf(struct dfl_fpga_cdev *cdev);
512int dfl_fpga_cdev_config_ports_vf(struct dfl_fpga_cdev *cdev, int num_vf);
513int dfl_fpga_set_irq_triggers(struct dfl_feature *feature, unsigned int start,
514 unsigned int count, int32_t *fds);
515long dfl_feature_ioctl_get_num_irqs(struct platform_device *pdev,
516 struct dfl_feature *feature,
517 unsigned long arg);
518long dfl_feature_ioctl_set_irq(struct platform_device *pdev,
519 struct dfl_feature *feature,
520 unsigned long arg);
521
522#endif /* __FPGA_DFL_H */
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Driver Header File for FPGA Device Feature List (DFL) Support
4 *
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
6 *
7 * Authors:
8 * Kang Luwei <luwei.kang@intel.com>
9 * Zhang Yi <yi.z.zhang@intel.com>
10 * Wu Hao <hao.wu@intel.com>
11 * Xiao Guangrong <guangrong.xiao@linux.intel.com>
12 */
13
14#ifndef __FPGA_DFL_H
15#define __FPGA_DFL_H
16
17#include <linux/bitfield.h>
18#include <linux/cdev.h>
19#include <linux/delay.h>
20#include <linux/eventfd.h>
21#include <linux/fs.h>
22#include <linux/interrupt.h>
23#include <linux/iopoll.h>
24#include <linux/io-64-nonatomic-lo-hi.h>
25#include <linux/mod_devicetable.h>
26#include <linux/platform_device.h>
27#include <linux/slab.h>
28#include <linux/uuid.h>
29#include <linux/fpga/fpga-region.h>
30
31/* maximum supported number of ports */
32#define MAX_DFL_FPGA_PORT_NUM 4
33/* plus one for fme device */
34#define MAX_DFL_FEATURE_DEV_NUM (MAX_DFL_FPGA_PORT_NUM + 1)
35
36/* Reserved 0xfe for Header Group Register and 0xff for AFU */
37#define FEATURE_ID_FIU_HEADER 0xfe
38#define FEATURE_ID_AFU 0xff
39
40#define FME_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER
41#define FME_FEATURE_ID_THERMAL_MGMT 0x1
42#define FME_FEATURE_ID_POWER_MGMT 0x2
43#define FME_FEATURE_ID_GLOBAL_IPERF 0x3
44#define FME_FEATURE_ID_GLOBAL_ERR 0x4
45#define FME_FEATURE_ID_PR_MGMT 0x5
46#define FME_FEATURE_ID_HSSI 0x6
47#define FME_FEATURE_ID_GLOBAL_DPERF 0x7
48
49#define PORT_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER
50#define PORT_FEATURE_ID_AFU FEATURE_ID_AFU
51#define PORT_FEATURE_ID_ERROR 0x10
52#define PORT_FEATURE_ID_UMSG 0x11
53#define PORT_FEATURE_ID_UINT 0x12
54#define PORT_FEATURE_ID_STP 0x13
55
56/*
57 * Device Feature Header Register Set
58 *
59 * For FIUs, they all have DFH + GUID + NEXT_AFU as common header registers.
60 * For AFUs, they have DFH + GUID as common header registers.
61 * For private features, they only have DFH register as common header.
62 */
63#define DFH 0x0
64#define GUID_L 0x8
65#define GUID_H 0x10
66#define NEXT_AFU 0x18
67
68#define DFH_SIZE 0x8
69
70/* Device Feature Header Register Bitfield */
71#define DFH_ID GENMASK_ULL(11, 0) /* Feature ID */
72#define DFH_ID_FIU_FME 0
73#define DFH_ID_FIU_PORT 1
74#define DFH_REVISION GENMASK_ULL(15, 12) /* Feature revision */
75#define DFH_NEXT_HDR_OFST GENMASK_ULL(39, 16) /* Offset to next DFH */
76#define DFH_EOL BIT_ULL(40) /* End of list */
77#define DFH_VERSION GENMASK_ULL(59, 52) /* DFH version */
78#define DFH_TYPE GENMASK_ULL(63, 60) /* Feature type */
79#define DFH_TYPE_AFU 1
80#define DFH_TYPE_PRIVATE 3
81#define DFH_TYPE_FIU 4
82
83/*
84 * DFHv1 Register Offset definitons
85 * In DHFv1, DFH + GUID + CSR_START + CSR_SIZE_GROUP + PARAM_HDR + PARAM_DATA
86 * as common header registers
87 */
88#define DFHv1_CSR_ADDR 0x18 /* CSR Register start address */
89#define DFHv1_CSR_SIZE_GRP 0x20 /* Size of Reg Block and Group/tag */
90#define DFHv1_PARAM_HDR 0x28 /* Optional First Param header */
91
92/*
93 * CSR Rel Bit, 1'b0 = relative (offset from feature DFH start),
94 * 1'b1 = absolute (ARM or other non-PCIe use)
95 */
96#define DFHv1_CSR_ADDR_REL BIT_ULL(0)
97
98/* CSR Header Register Bit Definitions */
99#define DFHv1_CSR_ADDR_MASK GENMASK_ULL(63, 1) /* 63:1 of CSR address */
100
101/* CSR SIZE Goup Register Bit Definitions */
102#define DFHv1_CSR_SIZE_GRP_INSTANCE_ID GENMASK_ULL(15, 0) /* Enumeration instantiated IP */
103#define DFHv1_CSR_SIZE_GRP_GROUPING_ID GENMASK_ULL(30, 16) /* Group Features/interfaces */
104#define DFHv1_CSR_SIZE_GRP_HAS_PARAMS BIT_ULL(31) /* Presence of Parameters */
105#define DFHv1_CSR_SIZE_GRP_SIZE GENMASK_ULL(63, 32) /* Size of CSR Block in bytes */
106
107/* PARAM Header Register Bit Definitions */
108#define DFHv1_PARAM_HDR_ID GENMASK_ULL(15, 0) /* Id of this Param */
109#define DFHv1_PARAM_HDR_VER GENMASK_ULL(31, 16) /* Version Param */
110#define DFHv1_PARAM_HDR_NEXT_OFFSET GENMASK_ULL(63, 35) /* Offset of next Param */
111#define DFHv1_PARAM_HDR_NEXT_EOP BIT_ULL(32)
112#define DFHv1_PARAM_DATA 0x08 /* Offset of Param data from Param header */
113
114#define DFHv1_PARAM_ID_MSI_X 0x1
115#define DFHv1_PARAM_MSI_X_NUMV GENMASK_ULL(63, 32)
116#define DFHv1_PARAM_MSI_X_STARTV GENMASK_ULL(31, 0)
117
118/* Next AFU Register Bitfield */
119#define NEXT_AFU_NEXT_DFH_OFST GENMASK_ULL(23, 0) /* Offset to next AFU */
120
121/* FME Header Register Set */
122#define FME_HDR_DFH DFH
123#define FME_HDR_GUID_L GUID_L
124#define FME_HDR_GUID_H GUID_H
125#define FME_HDR_NEXT_AFU NEXT_AFU
126#define FME_HDR_CAP 0x30
127#define FME_HDR_PORT_OFST(n) (0x38 + ((n) * 0x8))
128#define FME_PORT_OFST_BAR_SKIP 7
129#define FME_HDR_BITSTREAM_ID 0x60
130#define FME_HDR_BITSTREAM_MD 0x68
131
132/* FME Fab Capability Register Bitfield */
133#define FME_CAP_FABRIC_VERID GENMASK_ULL(7, 0) /* Fabric version ID */
134#define FME_CAP_SOCKET_ID BIT_ULL(8) /* Socket ID */
135#define FME_CAP_PCIE0_LINK_AVL BIT_ULL(12) /* PCIE0 Link */
136#define FME_CAP_PCIE1_LINK_AVL BIT_ULL(13) /* PCIE1 Link */
137#define FME_CAP_COHR_LINK_AVL BIT_ULL(14) /* Coherent Link */
138#define FME_CAP_IOMMU_AVL BIT_ULL(16) /* IOMMU available */
139#define FME_CAP_NUM_PORTS GENMASK_ULL(19, 17) /* Number of ports */
140#define FME_CAP_ADDR_WIDTH GENMASK_ULL(29, 24) /* Address bus width */
141#define FME_CAP_CACHE_SIZE GENMASK_ULL(43, 32) /* cache size in KB */
142#define FME_CAP_CACHE_ASSOC GENMASK_ULL(47, 44) /* Associativity */
143
144/* FME Port Offset Register Bitfield */
145/* Offset to port device feature header */
146#define FME_PORT_OFST_DFH_OFST GENMASK_ULL(23, 0)
147/* PCI Bar ID for this port */
148#define FME_PORT_OFST_BAR_ID GENMASK_ULL(34, 32)
149/* AFU MMIO access permission. 1 - VF, 0 - PF. */
150#define FME_PORT_OFST_ACC_CTRL BIT_ULL(55)
151#define FME_PORT_OFST_ACC_PF 0
152#define FME_PORT_OFST_ACC_VF 1
153#define FME_PORT_OFST_IMP BIT_ULL(60)
154
155/* FME Error Capability Register */
156#define FME_ERROR_CAP 0x70
157
158/* FME Error Capability Register Bitfield */
159#define FME_ERROR_CAP_SUPP_INT BIT_ULL(0) /* Interrupt Support */
160#define FME_ERROR_CAP_INT_VECT GENMASK_ULL(12, 1) /* Interrupt vector */
161
162/* PORT Header Register Set */
163#define PORT_HDR_DFH DFH
164#define PORT_HDR_GUID_L GUID_L
165#define PORT_HDR_GUID_H GUID_H
166#define PORT_HDR_NEXT_AFU NEXT_AFU
167#define PORT_HDR_CAP 0x30
168#define PORT_HDR_CTRL 0x38
169#define PORT_HDR_STS 0x40
170#define PORT_HDR_USRCLK_CMD0 0x50
171#define PORT_HDR_USRCLK_CMD1 0x58
172#define PORT_HDR_USRCLK_STS0 0x60
173#define PORT_HDR_USRCLK_STS1 0x68
174
175/* Port Capability Register Bitfield */
176#define PORT_CAP_PORT_NUM GENMASK_ULL(1, 0) /* ID of this port */
177#define PORT_CAP_MMIO_SIZE GENMASK_ULL(23, 8) /* MMIO size in KB */
178#define PORT_CAP_SUPP_INT_NUM GENMASK_ULL(35, 32) /* Interrupts num */
179
180/* Port Control Register Bitfield */
181#define PORT_CTRL_SFTRST BIT_ULL(0) /* Port soft reset */
182/* Latency tolerance reporting. '1' >= 40us, '0' < 40us.*/
183#define PORT_CTRL_LATENCY BIT_ULL(2)
184#define PORT_CTRL_SFTRST_ACK BIT_ULL(4) /* HW ack for reset */
185
186/* Port Status Register Bitfield */
187#define PORT_STS_AP2_EVT BIT_ULL(13) /* AP2 event detected */
188#define PORT_STS_AP1_EVT BIT_ULL(12) /* AP1 event detected */
189#define PORT_STS_PWR_STATE GENMASK_ULL(11, 8) /* AFU power states */
190#define PORT_STS_PWR_STATE_NORM 0
191#define PORT_STS_PWR_STATE_AP1 1 /* 50% throttling */
192#define PORT_STS_PWR_STATE_AP2 2 /* 90% throttling */
193#define PORT_STS_PWR_STATE_AP6 6 /* 100% throttling */
194
195/* Port Error Capability Register */
196#define PORT_ERROR_CAP 0x38
197
198/* Port Error Capability Register Bitfield */
199#define PORT_ERROR_CAP_SUPP_INT BIT_ULL(0) /* Interrupt Support */
200#define PORT_ERROR_CAP_INT_VECT GENMASK_ULL(12, 1) /* Interrupt vector */
201
202/* Port Uint Capability Register */
203#define PORT_UINT_CAP 0x8
204
205/* Port Uint Capability Register Bitfield */
206#define PORT_UINT_CAP_INT_NUM GENMASK_ULL(11, 0) /* Interrupts num */
207#define PORT_UINT_CAP_FST_VECT GENMASK_ULL(23, 12) /* First Vector */
208
209/**
210 * struct dfl_fpga_port_ops - port ops
211 *
212 * @name: name of this port ops, to match with port platform device.
213 * @owner: pointer to the module which owns this port ops.
214 * @node: node to link port ops to global list.
215 * @get_id: get port id from hardware.
216 * @enable_set: enable/disable the port.
217 */
218struct dfl_fpga_port_ops {
219 const char *name;
220 struct module *owner;
221 struct list_head node;
222 int (*get_id)(struct platform_device *pdev);
223 int (*enable_set)(struct platform_device *pdev, bool enable);
224};
225
226void dfl_fpga_port_ops_add(struct dfl_fpga_port_ops *ops);
227void dfl_fpga_port_ops_del(struct dfl_fpga_port_ops *ops);
228struct dfl_fpga_port_ops *dfl_fpga_port_ops_get(struct platform_device *pdev);
229void dfl_fpga_port_ops_put(struct dfl_fpga_port_ops *ops);
230int dfl_fpga_check_port_id(struct platform_device *pdev, void *pport_id);
231
232/**
233 * struct dfl_feature_id - dfl private feature id
234 *
235 * @id: unique dfl private feature id.
236 */
237struct dfl_feature_id {
238 u16 id;
239};
240
241/**
242 * struct dfl_feature_driver - dfl private feature driver
243 *
244 * @id_table: id_table for dfl private features supported by this driver.
245 * @ops: ops of this dfl private feature driver.
246 */
247struct dfl_feature_driver {
248 const struct dfl_feature_id *id_table;
249 const struct dfl_feature_ops *ops;
250};
251
252/**
253 * struct dfl_feature_irq_ctx - dfl private feature interrupt context
254 *
255 * @irq: Linux IRQ number of this interrupt.
256 * @trigger: eventfd context to signal when interrupt happens.
257 * @name: irq name needed when requesting irq.
258 */
259struct dfl_feature_irq_ctx {
260 int irq;
261 struct eventfd_ctx *trigger;
262 char *name;
263};
264
265/**
266 * struct dfl_feature - sub feature of the feature devices
267 *
268 * @dev: ptr to pdev of the feature device which has the sub feature.
269 * @id: sub feature id.
270 * @revision: revision of this sub feature.
271 * @resource_index: each sub feature has one mmio resource for its registers.
272 * this index is used to find its mmio resource from the
273 * feature dev (platform device)'s resources.
274 * @ioaddr: mapped mmio resource address.
275 * @irq_ctx: interrupt context list.
276 * @nr_irqs: number of interrupt contexts.
277 * @ops: ops of this sub feature.
278 * @ddev: ptr to the dfl device of this sub feature.
279 * @priv: priv data of this feature.
280 * @dfh_version: version of the DFH
281 * @param_size: size of dfh parameters
282 * @params: point to memory copy of dfh parameters
283 */
284struct dfl_feature {
285 struct platform_device *dev;
286 u16 id;
287 u8 revision;
288 int resource_index;
289 void __iomem *ioaddr;
290 struct dfl_feature_irq_ctx *irq_ctx;
291 unsigned int nr_irqs;
292 const struct dfl_feature_ops *ops;
293 struct dfl_device *ddev;
294 void *priv;
295 u8 dfh_version;
296 unsigned int param_size;
297 void *params;
298};
299
300#define FEATURE_DEV_ID_UNUSED (-1)
301
302/**
303 * struct dfl_feature_platform_data - platform data for feature devices
304 *
305 * @node: node to link feature devs to container device's port_dev_list.
306 * @lock: mutex to protect platform data.
307 * @cdev: cdev of feature dev.
308 * @dev: ptr to platform device linked with this platform data.
309 * @dfl_cdev: ptr to container device.
310 * @id: id used for this feature device.
311 * @disable_count: count for port disable.
312 * @excl_open: set on feature device exclusive open.
313 * @open_count: count for feature device open.
314 * @num: number for sub features.
315 * @private: ptr to feature dev private data.
316 * @features: sub features of this feature dev.
317 */
318struct dfl_feature_platform_data {
319 struct list_head node;
320 struct mutex lock;
321 struct cdev cdev;
322 struct platform_device *dev;
323 struct dfl_fpga_cdev *dfl_cdev;
324 int id;
325 unsigned int disable_count;
326 bool excl_open;
327 int open_count;
328 void *private;
329 int num;
330 struct dfl_feature features[];
331};
332
333static inline
334int dfl_feature_dev_use_begin(struct dfl_feature_platform_data *pdata,
335 bool excl)
336{
337 if (pdata->excl_open)
338 return -EBUSY;
339
340 if (excl) {
341 if (pdata->open_count)
342 return -EBUSY;
343
344 pdata->excl_open = true;
345 }
346 pdata->open_count++;
347
348 return 0;
349}
350
351static inline
352void dfl_feature_dev_use_end(struct dfl_feature_platform_data *pdata)
353{
354 pdata->excl_open = false;
355
356 if (WARN_ON(pdata->open_count <= 0))
357 return;
358
359 pdata->open_count--;
360}
361
362static inline
363int dfl_feature_dev_use_count(struct dfl_feature_platform_data *pdata)
364{
365 return pdata->open_count;
366}
367
368static inline
369void dfl_fpga_pdata_set_private(struct dfl_feature_platform_data *pdata,
370 void *private)
371{
372 pdata->private = private;
373}
374
375static inline
376void *dfl_fpga_pdata_get_private(struct dfl_feature_platform_data *pdata)
377{
378 return pdata->private;
379}
380
381struct dfl_feature_ops {
382 int (*init)(struct platform_device *pdev, struct dfl_feature *feature);
383 void (*uinit)(struct platform_device *pdev,
384 struct dfl_feature *feature);
385 long (*ioctl)(struct platform_device *pdev, struct dfl_feature *feature,
386 unsigned int cmd, unsigned long arg);
387};
388
389#define DFL_FPGA_FEATURE_DEV_FME "dfl-fme"
390#define DFL_FPGA_FEATURE_DEV_PORT "dfl-port"
391
392void dfl_fpga_dev_feature_uinit(struct platform_device *pdev);
393int dfl_fpga_dev_feature_init(struct platform_device *pdev,
394 struct dfl_feature_driver *feature_drvs);
395
396int dfl_fpga_dev_ops_register(struct platform_device *pdev,
397 const struct file_operations *fops,
398 struct module *owner);
399void dfl_fpga_dev_ops_unregister(struct platform_device *pdev);
400
401static inline
402struct platform_device *dfl_fpga_inode_to_feature_dev(struct inode *inode)
403{
404 struct dfl_feature_platform_data *pdata;
405
406 pdata = container_of(inode->i_cdev, struct dfl_feature_platform_data,
407 cdev);
408 return pdata->dev;
409}
410
411#define dfl_fpga_dev_for_each_feature(pdata, feature) \
412 for ((feature) = (pdata)->features; \
413 (feature) < (pdata)->features + (pdata)->num; (feature)++)
414
415static inline
416struct dfl_feature *dfl_get_feature_by_id(struct device *dev, u16 id)
417{
418 struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
419 struct dfl_feature *feature;
420
421 dfl_fpga_dev_for_each_feature(pdata, feature)
422 if (feature->id == id)
423 return feature;
424
425 return NULL;
426}
427
428static inline
429void __iomem *dfl_get_feature_ioaddr_by_id(struct device *dev, u16 id)
430{
431 struct dfl_feature *feature = dfl_get_feature_by_id(dev, id);
432
433 if (feature && feature->ioaddr)
434 return feature->ioaddr;
435
436 WARN_ON(1);
437 return NULL;
438}
439
440static inline bool is_dfl_feature_present(struct device *dev, u16 id)
441{
442 return !!dfl_get_feature_ioaddr_by_id(dev, id);
443}
444
445static inline
446struct device *dfl_fpga_pdata_to_parent(struct dfl_feature_platform_data *pdata)
447{
448 return pdata->dev->dev.parent->parent;
449}
450
451static inline bool dfl_feature_is_fme(void __iomem *base)
452{
453 u64 v = readq(base + DFH);
454
455 return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) &&
456 (FIELD_GET(DFH_ID, v) == DFH_ID_FIU_FME);
457}
458
459static inline bool dfl_feature_is_port(void __iomem *base)
460{
461 u64 v = readq(base + DFH);
462
463 return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) &&
464 (FIELD_GET(DFH_ID, v) == DFH_ID_FIU_PORT);
465}
466
467static inline u8 dfl_feature_revision(void __iomem *base)
468{
469 return (u8)FIELD_GET(DFH_REVISION, readq(base + DFH));
470}
471
472/**
473 * struct dfl_fpga_enum_info - DFL FPGA enumeration information
474 *
475 * @dev: parent device.
476 * @dfls: list of device feature lists.
477 * @nr_irqs: number of irqs for all feature devices.
478 * @irq_table: Linux IRQ numbers for all irqs, indexed by hw irq numbers.
479 */
480struct dfl_fpga_enum_info {
481 struct device *dev;
482 struct list_head dfls;
483 unsigned int nr_irqs;
484 int *irq_table;
485};
486
487/**
488 * struct dfl_fpga_enum_dfl - DFL FPGA enumeration device feature list info
489 *
490 * @start: base address of this device feature list.
491 * @len: size of this device feature list.
492 * @node: node in list of device feature lists.
493 */
494struct dfl_fpga_enum_dfl {
495 resource_size_t start;
496 resource_size_t len;
497 struct list_head node;
498};
499
500struct dfl_fpga_enum_info *dfl_fpga_enum_info_alloc(struct device *dev);
501int dfl_fpga_enum_info_add_dfl(struct dfl_fpga_enum_info *info,
502 resource_size_t start, resource_size_t len);
503int dfl_fpga_enum_info_add_irq(struct dfl_fpga_enum_info *info,
504 unsigned int nr_irqs, int *irq_table);
505void dfl_fpga_enum_info_free(struct dfl_fpga_enum_info *info);
506
507/**
508 * struct dfl_fpga_cdev - container device of DFL based FPGA
509 *
510 * @parent: parent device of this container device.
511 * @region: base fpga region.
512 * @fme_dev: FME feature device under this container device.
513 * @lock: mutex lock to protect the port device list.
514 * @port_dev_list: list of all port feature devices under this container device.
515 * @released_port_num: released port number under this container device.
516 */
517struct dfl_fpga_cdev {
518 struct device *parent;
519 struct fpga_region *region;
520 struct device *fme_dev;
521 struct mutex lock;
522 struct list_head port_dev_list;
523 int released_port_num;
524};
525
526struct dfl_fpga_cdev *
527dfl_fpga_feature_devs_enumerate(struct dfl_fpga_enum_info *info);
528void dfl_fpga_feature_devs_remove(struct dfl_fpga_cdev *cdev);
529
530/*
531 * need to drop the device reference with put_device() after use port platform
532 * device returned by __dfl_fpga_cdev_find_port and dfl_fpga_cdev_find_port
533 * functions.
534 */
535struct platform_device *
536__dfl_fpga_cdev_find_port(struct dfl_fpga_cdev *cdev, void *data,
537 int (*match)(struct platform_device *, void *));
538
539static inline struct platform_device *
540dfl_fpga_cdev_find_port(struct dfl_fpga_cdev *cdev, void *data,
541 int (*match)(struct platform_device *, void *))
542{
543 struct platform_device *pdev;
544
545 mutex_lock(&cdev->lock);
546 pdev = __dfl_fpga_cdev_find_port(cdev, data, match);
547 mutex_unlock(&cdev->lock);
548
549 return pdev;
550}
551
552int dfl_fpga_cdev_release_port(struct dfl_fpga_cdev *cdev, int port_id);
553int dfl_fpga_cdev_assign_port(struct dfl_fpga_cdev *cdev, int port_id);
554void dfl_fpga_cdev_config_ports_pf(struct dfl_fpga_cdev *cdev);
555int dfl_fpga_cdev_config_ports_vf(struct dfl_fpga_cdev *cdev, int num_vf);
556int dfl_fpga_set_irq_triggers(struct dfl_feature *feature, unsigned int start,
557 unsigned int count, int32_t *fds);
558long dfl_feature_ioctl_get_num_irqs(struct platform_device *pdev,
559 struct dfl_feature *feature,
560 unsigned long arg);
561long dfl_feature_ioctl_set_irq(struct platform_device *pdev,
562 struct dfl_feature *feature,
563 unsigned long arg);
564
565#endif /* __FPGA_DFL_H */