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1// SPDX-License-Identifier: GPL-2.0
2//
3// Register cache access API
4//
5// Copyright 2011 Wolfson Microelectronics plc
6//
7// Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
8
9#include <linux/bsearch.h>
10#include <linux/device.h>
11#include <linux/export.h>
12#include <linux/slab.h>
13#include <linux/sort.h>
14
15#include "trace.h"
16#include "internal.h"
17
18static const struct regcache_ops *cache_types[] = {
19 ®cache_rbtree_ops,
20#if IS_ENABLED(CONFIG_REGCACHE_COMPRESSED)
21 ®cache_lzo_ops,
22#endif
23 ®cache_flat_ops,
24};
25
26static int regcache_hw_init(struct regmap *map)
27{
28 int i, j;
29 int ret;
30 int count;
31 unsigned int reg, val;
32 void *tmp_buf;
33
34 if (!map->num_reg_defaults_raw)
35 return -EINVAL;
36
37 /* calculate the size of reg_defaults */
38 for (count = 0, i = 0; i < map->num_reg_defaults_raw; i++)
39 if (regmap_readable(map, i * map->reg_stride) &&
40 !regmap_volatile(map, i * map->reg_stride))
41 count++;
42
43 /* all registers are unreadable or volatile, so just bypass */
44 if (!count) {
45 map->cache_bypass = true;
46 return 0;
47 }
48
49 map->num_reg_defaults = count;
50 map->reg_defaults = kmalloc_array(count, sizeof(struct reg_default),
51 GFP_KERNEL);
52 if (!map->reg_defaults)
53 return -ENOMEM;
54
55 if (!map->reg_defaults_raw) {
56 bool cache_bypass = map->cache_bypass;
57 dev_warn(map->dev, "No cache defaults, reading back from HW\n");
58
59 /* Bypass the cache access till data read from HW */
60 map->cache_bypass = true;
61 tmp_buf = kmalloc(map->cache_size_raw, GFP_KERNEL);
62 if (!tmp_buf) {
63 ret = -ENOMEM;
64 goto err_free;
65 }
66 ret = regmap_raw_read(map, 0, tmp_buf,
67 map->cache_size_raw);
68 map->cache_bypass = cache_bypass;
69 if (ret == 0) {
70 map->reg_defaults_raw = tmp_buf;
71 map->cache_free = 1;
72 } else {
73 kfree(tmp_buf);
74 }
75 }
76
77 /* fill the reg_defaults */
78 for (i = 0, j = 0; i < map->num_reg_defaults_raw; i++) {
79 reg = i * map->reg_stride;
80
81 if (!regmap_readable(map, reg))
82 continue;
83
84 if (regmap_volatile(map, reg))
85 continue;
86
87 if (map->reg_defaults_raw) {
88 val = regcache_get_val(map, map->reg_defaults_raw, i);
89 } else {
90 bool cache_bypass = map->cache_bypass;
91
92 map->cache_bypass = true;
93 ret = regmap_read(map, reg, &val);
94 map->cache_bypass = cache_bypass;
95 if (ret != 0) {
96 dev_err(map->dev, "Failed to read %d: %d\n",
97 reg, ret);
98 goto err_free;
99 }
100 }
101
102 map->reg_defaults[j].reg = reg;
103 map->reg_defaults[j].def = val;
104 j++;
105 }
106
107 return 0;
108
109err_free:
110 kfree(map->reg_defaults);
111
112 return ret;
113}
114
115int regcache_init(struct regmap *map, const struct regmap_config *config)
116{
117 int ret;
118 int i;
119 void *tmp_buf;
120
121 if (map->cache_type == REGCACHE_NONE) {
122 if (config->reg_defaults || config->num_reg_defaults_raw)
123 dev_warn(map->dev,
124 "No cache used with register defaults set!\n");
125
126 map->cache_bypass = true;
127 return 0;
128 }
129
130 if (config->reg_defaults && !config->num_reg_defaults) {
131 dev_err(map->dev,
132 "Register defaults are set without the number!\n");
133 return -EINVAL;
134 }
135
136 for (i = 0; i < config->num_reg_defaults; i++)
137 if (config->reg_defaults[i].reg % map->reg_stride)
138 return -EINVAL;
139
140 for (i = 0; i < ARRAY_SIZE(cache_types); i++)
141 if (cache_types[i]->type == map->cache_type)
142 break;
143
144 if (i == ARRAY_SIZE(cache_types)) {
145 dev_err(map->dev, "Could not match compress type: %d\n",
146 map->cache_type);
147 return -EINVAL;
148 }
149
150 map->num_reg_defaults = config->num_reg_defaults;
151 map->num_reg_defaults_raw = config->num_reg_defaults_raw;
152 map->reg_defaults_raw = config->reg_defaults_raw;
153 map->cache_word_size = DIV_ROUND_UP(config->val_bits, 8);
154 map->cache_size_raw = map->cache_word_size * config->num_reg_defaults_raw;
155
156 map->cache = NULL;
157 map->cache_ops = cache_types[i];
158
159 if (!map->cache_ops->read ||
160 !map->cache_ops->write ||
161 !map->cache_ops->name)
162 return -EINVAL;
163
164 /* We still need to ensure that the reg_defaults
165 * won't vanish from under us. We'll need to make
166 * a copy of it.
167 */
168 if (config->reg_defaults) {
169 tmp_buf = kmemdup(config->reg_defaults, map->num_reg_defaults *
170 sizeof(struct reg_default), GFP_KERNEL);
171 if (!tmp_buf)
172 return -ENOMEM;
173 map->reg_defaults = tmp_buf;
174 } else if (map->num_reg_defaults_raw) {
175 /* Some devices such as PMICs don't have cache defaults,
176 * we cope with this by reading back the HW registers and
177 * crafting the cache defaults by hand.
178 */
179 ret = regcache_hw_init(map);
180 if (ret < 0)
181 return ret;
182 if (map->cache_bypass)
183 return 0;
184 }
185
186 if (!map->max_register)
187 map->max_register = map->num_reg_defaults_raw;
188
189 if (map->cache_ops->init) {
190 dev_dbg(map->dev, "Initializing %s cache\n",
191 map->cache_ops->name);
192 ret = map->cache_ops->init(map);
193 if (ret)
194 goto err_free;
195 }
196 return 0;
197
198err_free:
199 kfree(map->reg_defaults);
200 if (map->cache_free)
201 kfree(map->reg_defaults_raw);
202
203 return ret;
204}
205
206void regcache_exit(struct regmap *map)
207{
208 if (map->cache_type == REGCACHE_NONE)
209 return;
210
211 BUG_ON(!map->cache_ops);
212
213 kfree(map->reg_defaults);
214 if (map->cache_free)
215 kfree(map->reg_defaults_raw);
216
217 if (map->cache_ops->exit) {
218 dev_dbg(map->dev, "Destroying %s cache\n",
219 map->cache_ops->name);
220 map->cache_ops->exit(map);
221 }
222}
223
224/**
225 * regcache_read - Fetch the value of a given register from the cache.
226 *
227 * @map: map to configure.
228 * @reg: The register index.
229 * @value: The value to be returned.
230 *
231 * Return a negative value on failure, 0 on success.
232 */
233int regcache_read(struct regmap *map,
234 unsigned int reg, unsigned int *value)
235{
236 int ret;
237
238 if (map->cache_type == REGCACHE_NONE)
239 return -ENOSYS;
240
241 BUG_ON(!map->cache_ops);
242
243 if (!regmap_volatile(map, reg)) {
244 ret = map->cache_ops->read(map, reg, value);
245
246 if (ret == 0)
247 trace_regmap_reg_read_cache(map, reg, *value);
248
249 return ret;
250 }
251
252 return -EINVAL;
253}
254
255/**
256 * regcache_write - Set the value of a given register in the cache.
257 *
258 * @map: map to configure.
259 * @reg: The register index.
260 * @value: The new register value.
261 *
262 * Return a negative value on failure, 0 on success.
263 */
264int regcache_write(struct regmap *map,
265 unsigned int reg, unsigned int value)
266{
267 if (map->cache_type == REGCACHE_NONE)
268 return 0;
269
270 BUG_ON(!map->cache_ops);
271
272 if (!regmap_volatile(map, reg))
273 return map->cache_ops->write(map, reg, value);
274
275 return 0;
276}
277
278static bool regcache_reg_needs_sync(struct regmap *map, unsigned int reg,
279 unsigned int val)
280{
281 int ret;
282
283 /* If we don't know the chip just got reset, then sync everything. */
284 if (!map->no_sync_defaults)
285 return true;
286
287 /* Is this the hardware default? If so skip. */
288 ret = regcache_lookup_reg(map, reg);
289 if (ret >= 0 && val == map->reg_defaults[ret].def)
290 return false;
291 return true;
292}
293
294static int regcache_default_sync(struct regmap *map, unsigned int min,
295 unsigned int max)
296{
297 unsigned int reg;
298
299 for (reg = min; reg <= max; reg += map->reg_stride) {
300 unsigned int val;
301 int ret;
302
303 if (regmap_volatile(map, reg) ||
304 !regmap_writeable(map, reg))
305 continue;
306
307 ret = regcache_read(map, reg, &val);
308 if (ret)
309 return ret;
310
311 if (!regcache_reg_needs_sync(map, reg, val))
312 continue;
313
314 map->cache_bypass = true;
315 ret = _regmap_write(map, reg, val);
316 map->cache_bypass = false;
317 if (ret) {
318 dev_err(map->dev, "Unable to sync register %#x. %d\n",
319 reg, ret);
320 return ret;
321 }
322 dev_dbg(map->dev, "Synced register %#x, value %#x\n", reg, val);
323 }
324
325 return 0;
326}
327
328/**
329 * regcache_sync - Sync the register cache with the hardware.
330 *
331 * @map: map to configure.
332 *
333 * Any registers that should not be synced should be marked as
334 * volatile. In general drivers can choose not to use the provided
335 * syncing functionality if they so require.
336 *
337 * Return a negative value on failure, 0 on success.
338 */
339int regcache_sync(struct regmap *map)
340{
341 int ret = 0;
342 unsigned int i;
343 const char *name;
344 bool bypass;
345
346 BUG_ON(!map->cache_ops);
347
348 map->lock(map->lock_arg);
349 /* Remember the initial bypass state */
350 bypass = map->cache_bypass;
351 dev_dbg(map->dev, "Syncing %s cache\n",
352 map->cache_ops->name);
353 name = map->cache_ops->name;
354 trace_regcache_sync(map, name, "start");
355
356 if (!map->cache_dirty)
357 goto out;
358
359 map->async = true;
360
361 /* Apply any patch first */
362 map->cache_bypass = true;
363 for (i = 0; i < map->patch_regs; i++) {
364 ret = _regmap_write(map, map->patch[i].reg, map->patch[i].def);
365 if (ret != 0) {
366 dev_err(map->dev, "Failed to write %x = %x: %d\n",
367 map->patch[i].reg, map->patch[i].def, ret);
368 goto out;
369 }
370 }
371 map->cache_bypass = false;
372
373 if (map->cache_ops->sync)
374 ret = map->cache_ops->sync(map, 0, map->max_register);
375 else
376 ret = regcache_default_sync(map, 0, map->max_register);
377
378 if (ret == 0)
379 map->cache_dirty = false;
380
381out:
382 /* Restore the bypass state */
383 map->async = false;
384 map->cache_bypass = bypass;
385 map->no_sync_defaults = false;
386 map->unlock(map->lock_arg);
387
388 regmap_async_complete(map);
389
390 trace_regcache_sync(map, name, "stop");
391
392 return ret;
393}
394EXPORT_SYMBOL_GPL(regcache_sync);
395
396/**
397 * regcache_sync_region - Sync part of the register cache with the hardware.
398 *
399 * @map: map to sync.
400 * @min: first register to sync
401 * @max: last register to sync
402 *
403 * Write all non-default register values in the specified region to
404 * the hardware.
405 *
406 * Return a negative value on failure, 0 on success.
407 */
408int regcache_sync_region(struct regmap *map, unsigned int min,
409 unsigned int max)
410{
411 int ret = 0;
412 const char *name;
413 bool bypass;
414
415 BUG_ON(!map->cache_ops);
416
417 map->lock(map->lock_arg);
418
419 /* Remember the initial bypass state */
420 bypass = map->cache_bypass;
421
422 name = map->cache_ops->name;
423 dev_dbg(map->dev, "Syncing %s cache from %d-%d\n", name, min, max);
424
425 trace_regcache_sync(map, name, "start region");
426
427 if (!map->cache_dirty)
428 goto out;
429
430 map->async = true;
431
432 if (map->cache_ops->sync)
433 ret = map->cache_ops->sync(map, min, max);
434 else
435 ret = regcache_default_sync(map, min, max);
436
437out:
438 /* Restore the bypass state */
439 map->cache_bypass = bypass;
440 map->async = false;
441 map->no_sync_defaults = false;
442 map->unlock(map->lock_arg);
443
444 regmap_async_complete(map);
445
446 trace_regcache_sync(map, name, "stop region");
447
448 return ret;
449}
450EXPORT_SYMBOL_GPL(regcache_sync_region);
451
452/**
453 * regcache_drop_region - Discard part of the register cache
454 *
455 * @map: map to operate on
456 * @min: first register to discard
457 * @max: last register to discard
458 *
459 * Discard part of the register cache.
460 *
461 * Return a negative value on failure, 0 on success.
462 */
463int regcache_drop_region(struct regmap *map, unsigned int min,
464 unsigned int max)
465{
466 int ret = 0;
467
468 if (!map->cache_ops || !map->cache_ops->drop)
469 return -EINVAL;
470
471 map->lock(map->lock_arg);
472
473 trace_regcache_drop_region(map, min, max);
474
475 ret = map->cache_ops->drop(map, min, max);
476
477 map->unlock(map->lock_arg);
478
479 return ret;
480}
481EXPORT_SYMBOL_GPL(regcache_drop_region);
482
483/**
484 * regcache_cache_only - Put a register map into cache only mode
485 *
486 * @map: map to configure
487 * @enable: flag if changes should be written to the hardware
488 *
489 * When a register map is marked as cache only writes to the register
490 * map API will only update the register cache, they will not cause
491 * any hardware changes. This is useful for allowing portions of
492 * drivers to act as though the device were functioning as normal when
493 * it is disabled for power saving reasons.
494 */
495void regcache_cache_only(struct regmap *map, bool enable)
496{
497 map->lock(map->lock_arg);
498 WARN_ON(map->cache_bypass && enable);
499 map->cache_only = enable;
500 trace_regmap_cache_only(map, enable);
501 map->unlock(map->lock_arg);
502}
503EXPORT_SYMBOL_GPL(regcache_cache_only);
504
505/**
506 * regcache_mark_dirty - Indicate that HW registers were reset to default values
507 *
508 * @map: map to mark
509 *
510 * Inform regcache that the device has been powered down or reset, so that
511 * on resume, regcache_sync() knows to write out all non-default values
512 * stored in the cache.
513 *
514 * If this function is not called, regcache_sync() will assume that
515 * the hardware state still matches the cache state, modulo any writes that
516 * happened when cache_only was true.
517 */
518void regcache_mark_dirty(struct regmap *map)
519{
520 map->lock(map->lock_arg);
521 map->cache_dirty = true;
522 map->no_sync_defaults = true;
523 map->unlock(map->lock_arg);
524}
525EXPORT_SYMBOL_GPL(regcache_mark_dirty);
526
527/**
528 * regcache_cache_bypass - Put a register map into cache bypass mode
529 *
530 * @map: map to configure
531 * @enable: flag if changes should not be written to the cache
532 *
533 * When a register map is marked with the cache bypass option, writes
534 * to the register map API will only update the hardware and not the
535 * the cache directly. This is useful when syncing the cache back to
536 * the hardware.
537 */
538void regcache_cache_bypass(struct regmap *map, bool enable)
539{
540 map->lock(map->lock_arg);
541 WARN_ON(map->cache_only && enable);
542 map->cache_bypass = enable;
543 trace_regmap_cache_bypass(map, enable);
544 map->unlock(map->lock_arg);
545}
546EXPORT_SYMBOL_GPL(regcache_cache_bypass);
547
548bool regcache_set_val(struct regmap *map, void *base, unsigned int idx,
549 unsigned int val)
550{
551 if (regcache_get_val(map, base, idx) == val)
552 return true;
553
554 /* Use device native format if possible */
555 if (map->format.format_val) {
556 map->format.format_val(base + (map->cache_word_size * idx),
557 val, 0);
558 return false;
559 }
560
561 switch (map->cache_word_size) {
562 case 1: {
563 u8 *cache = base;
564
565 cache[idx] = val;
566 break;
567 }
568 case 2: {
569 u16 *cache = base;
570
571 cache[idx] = val;
572 break;
573 }
574 case 4: {
575 u32 *cache = base;
576
577 cache[idx] = val;
578 break;
579 }
580#ifdef CONFIG_64BIT
581 case 8: {
582 u64 *cache = base;
583
584 cache[idx] = val;
585 break;
586 }
587#endif
588 default:
589 BUG();
590 }
591 return false;
592}
593
594unsigned int regcache_get_val(struct regmap *map, const void *base,
595 unsigned int idx)
596{
597 if (!base)
598 return -EINVAL;
599
600 /* Use device native format if possible */
601 if (map->format.parse_val)
602 return map->format.parse_val(regcache_get_val_addr(map, base,
603 idx));
604
605 switch (map->cache_word_size) {
606 case 1: {
607 const u8 *cache = base;
608
609 return cache[idx];
610 }
611 case 2: {
612 const u16 *cache = base;
613
614 return cache[idx];
615 }
616 case 4: {
617 const u32 *cache = base;
618
619 return cache[idx];
620 }
621#ifdef CONFIG_64BIT
622 case 8: {
623 const u64 *cache = base;
624
625 return cache[idx];
626 }
627#endif
628 default:
629 BUG();
630 }
631 /* unreachable */
632 return -1;
633}
634
635static int regcache_default_cmp(const void *a, const void *b)
636{
637 const struct reg_default *_a = a;
638 const struct reg_default *_b = b;
639
640 return _a->reg - _b->reg;
641}
642
643int regcache_lookup_reg(struct regmap *map, unsigned int reg)
644{
645 struct reg_default key;
646 struct reg_default *r;
647
648 key.reg = reg;
649 key.def = 0;
650
651 r = bsearch(&key, map->reg_defaults, map->num_reg_defaults,
652 sizeof(struct reg_default), regcache_default_cmp);
653
654 if (r)
655 return r - map->reg_defaults;
656 else
657 return -ENOENT;
658}
659
660static bool regcache_reg_present(unsigned long *cache_present, unsigned int idx)
661{
662 if (!cache_present)
663 return true;
664
665 return test_bit(idx, cache_present);
666}
667
668static int regcache_sync_block_single(struct regmap *map, void *block,
669 unsigned long *cache_present,
670 unsigned int block_base,
671 unsigned int start, unsigned int end)
672{
673 unsigned int i, regtmp, val;
674 int ret;
675
676 for (i = start; i < end; i++) {
677 regtmp = block_base + (i * map->reg_stride);
678
679 if (!regcache_reg_present(cache_present, i) ||
680 !regmap_writeable(map, regtmp))
681 continue;
682
683 val = regcache_get_val(map, block, i);
684 if (!regcache_reg_needs_sync(map, regtmp, val))
685 continue;
686
687 map->cache_bypass = true;
688
689 ret = _regmap_write(map, regtmp, val);
690
691 map->cache_bypass = false;
692 if (ret != 0) {
693 dev_err(map->dev, "Unable to sync register %#x. %d\n",
694 regtmp, ret);
695 return ret;
696 }
697 dev_dbg(map->dev, "Synced register %#x, value %#x\n",
698 regtmp, val);
699 }
700
701 return 0;
702}
703
704static int regcache_sync_block_raw_flush(struct regmap *map, const void **data,
705 unsigned int base, unsigned int cur)
706{
707 size_t val_bytes = map->format.val_bytes;
708 int ret, count;
709
710 if (*data == NULL)
711 return 0;
712
713 count = (cur - base) / map->reg_stride;
714
715 dev_dbg(map->dev, "Writing %zu bytes for %d registers from 0x%x-0x%x\n",
716 count * val_bytes, count, base, cur - map->reg_stride);
717
718 map->cache_bypass = true;
719
720 ret = _regmap_raw_write(map, base, *data, count * val_bytes, false);
721 if (ret)
722 dev_err(map->dev, "Unable to sync registers %#x-%#x. %d\n",
723 base, cur - map->reg_stride, ret);
724
725 map->cache_bypass = false;
726
727 *data = NULL;
728
729 return ret;
730}
731
732static int regcache_sync_block_raw(struct regmap *map, void *block,
733 unsigned long *cache_present,
734 unsigned int block_base, unsigned int start,
735 unsigned int end)
736{
737 unsigned int i, val;
738 unsigned int regtmp = 0;
739 unsigned int base = 0;
740 const void *data = NULL;
741 int ret;
742
743 for (i = start; i < end; i++) {
744 regtmp = block_base + (i * map->reg_stride);
745
746 if (!regcache_reg_present(cache_present, i) ||
747 !regmap_writeable(map, regtmp)) {
748 ret = regcache_sync_block_raw_flush(map, &data,
749 base, regtmp);
750 if (ret != 0)
751 return ret;
752 continue;
753 }
754
755 val = regcache_get_val(map, block, i);
756 if (!regcache_reg_needs_sync(map, regtmp, val)) {
757 ret = regcache_sync_block_raw_flush(map, &data,
758 base, regtmp);
759 if (ret != 0)
760 return ret;
761 continue;
762 }
763
764 if (!data) {
765 data = regcache_get_val_addr(map, block, i);
766 base = regtmp;
767 }
768 }
769
770 return regcache_sync_block_raw_flush(map, &data, base, regtmp +
771 map->reg_stride);
772}
773
774int regcache_sync_block(struct regmap *map, void *block,
775 unsigned long *cache_present,
776 unsigned int block_base, unsigned int start,
777 unsigned int end)
778{
779 if (regmap_can_raw_write(map) && !map->use_single_write)
780 return regcache_sync_block_raw(map, block, cache_present,
781 block_base, start, end);
782 else
783 return regcache_sync_block_single(map, block, cache_present,
784 block_base, start, end);
785}
1// SPDX-License-Identifier: GPL-2.0
2//
3// Register cache access API
4//
5// Copyright 2011 Wolfson Microelectronics plc
6//
7// Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
8
9#include <linux/bsearch.h>
10#include <linux/device.h>
11#include <linux/export.h>
12#include <linux/slab.h>
13#include <linux/sort.h>
14
15#include "trace.h"
16#include "internal.h"
17
18static const struct regcache_ops *cache_types[] = {
19 ®cache_rbtree_ops,
20 ®cache_maple_ops,
21 ®cache_flat_ops,
22};
23
24static int regcache_hw_init(struct regmap *map)
25{
26 int i, j;
27 int ret;
28 int count;
29 unsigned int reg, val;
30 void *tmp_buf;
31
32 if (!map->num_reg_defaults_raw)
33 return -EINVAL;
34
35 /* calculate the size of reg_defaults */
36 for (count = 0, i = 0; i < map->num_reg_defaults_raw; i++)
37 if (regmap_readable(map, i * map->reg_stride) &&
38 !regmap_volatile(map, i * map->reg_stride))
39 count++;
40
41 /* all registers are unreadable or volatile, so just bypass */
42 if (!count) {
43 map->cache_bypass = true;
44 return 0;
45 }
46
47 map->num_reg_defaults = count;
48 map->reg_defaults = kmalloc_array(count, sizeof(struct reg_default),
49 GFP_KERNEL);
50 if (!map->reg_defaults)
51 return -ENOMEM;
52
53 if (!map->reg_defaults_raw) {
54 bool cache_bypass = map->cache_bypass;
55 dev_warn(map->dev, "No cache defaults, reading back from HW\n");
56
57 /* Bypass the cache access till data read from HW */
58 map->cache_bypass = true;
59 tmp_buf = kmalloc(map->cache_size_raw, GFP_KERNEL);
60 if (!tmp_buf) {
61 ret = -ENOMEM;
62 goto err_free;
63 }
64 ret = regmap_raw_read(map, 0, tmp_buf,
65 map->cache_size_raw);
66 map->cache_bypass = cache_bypass;
67 if (ret == 0) {
68 map->reg_defaults_raw = tmp_buf;
69 map->cache_free = true;
70 } else {
71 kfree(tmp_buf);
72 }
73 }
74
75 /* fill the reg_defaults */
76 for (i = 0, j = 0; i < map->num_reg_defaults_raw; i++) {
77 reg = i * map->reg_stride;
78
79 if (!regmap_readable(map, reg))
80 continue;
81
82 if (regmap_volatile(map, reg))
83 continue;
84
85 if (map->reg_defaults_raw) {
86 val = regcache_get_val(map, map->reg_defaults_raw, i);
87 } else {
88 bool cache_bypass = map->cache_bypass;
89
90 map->cache_bypass = true;
91 ret = regmap_read(map, reg, &val);
92 map->cache_bypass = cache_bypass;
93 if (ret != 0) {
94 dev_err(map->dev, "Failed to read %d: %d\n",
95 reg, ret);
96 goto err_free;
97 }
98 }
99
100 map->reg_defaults[j].reg = reg;
101 map->reg_defaults[j].def = val;
102 j++;
103 }
104
105 return 0;
106
107err_free:
108 kfree(map->reg_defaults);
109
110 return ret;
111}
112
113int regcache_init(struct regmap *map, const struct regmap_config *config)
114{
115 int ret;
116 int i;
117 void *tmp_buf;
118
119 if (map->cache_type == REGCACHE_NONE) {
120 if (config->reg_defaults || config->num_reg_defaults_raw)
121 dev_warn(map->dev,
122 "No cache used with register defaults set!\n");
123
124 map->cache_bypass = true;
125 return 0;
126 }
127
128 if (config->reg_defaults && !config->num_reg_defaults) {
129 dev_err(map->dev,
130 "Register defaults are set without the number!\n");
131 return -EINVAL;
132 }
133
134 if (config->num_reg_defaults && !config->reg_defaults) {
135 dev_err(map->dev,
136 "Register defaults number are set without the reg!\n");
137 return -EINVAL;
138 }
139
140 for (i = 0; i < config->num_reg_defaults; i++)
141 if (config->reg_defaults[i].reg % map->reg_stride)
142 return -EINVAL;
143
144 for (i = 0; i < ARRAY_SIZE(cache_types); i++)
145 if (cache_types[i]->type == map->cache_type)
146 break;
147
148 if (i == ARRAY_SIZE(cache_types)) {
149 dev_err(map->dev, "Could not match cache type: %d\n",
150 map->cache_type);
151 return -EINVAL;
152 }
153
154 map->num_reg_defaults = config->num_reg_defaults;
155 map->num_reg_defaults_raw = config->num_reg_defaults_raw;
156 map->reg_defaults_raw = config->reg_defaults_raw;
157 map->cache_word_size = DIV_ROUND_UP(config->val_bits, 8);
158 map->cache_size_raw = map->cache_word_size * config->num_reg_defaults_raw;
159
160 map->cache = NULL;
161 map->cache_ops = cache_types[i];
162
163 if (!map->cache_ops->read ||
164 !map->cache_ops->write ||
165 !map->cache_ops->name)
166 return -EINVAL;
167
168 /* We still need to ensure that the reg_defaults
169 * won't vanish from under us. We'll need to make
170 * a copy of it.
171 */
172 if (config->reg_defaults) {
173 tmp_buf = kmemdup(config->reg_defaults, map->num_reg_defaults *
174 sizeof(struct reg_default), GFP_KERNEL);
175 if (!tmp_buf)
176 return -ENOMEM;
177 map->reg_defaults = tmp_buf;
178 } else if (map->num_reg_defaults_raw) {
179 /* Some devices such as PMICs don't have cache defaults,
180 * we cope with this by reading back the HW registers and
181 * crafting the cache defaults by hand.
182 */
183 ret = regcache_hw_init(map);
184 if (ret < 0)
185 return ret;
186 if (map->cache_bypass)
187 return 0;
188 }
189
190 if (!map->max_register_is_set && map->num_reg_defaults_raw) {
191 map->max_register = (map->num_reg_defaults_raw - 1) * map->reg_stride;
192 map->max_register_is_set = true;
193 }
194
195 if (map->cache_ops->init) {
196 dev_dbg(map->dev, "Initializing %s cache\n",
197 map->cache_ops->name);
198 ret = map->cache_ops->init(map);
199 if (ret)
200 goto err_free;
201 }
202 return 0;
203
204err_free:
205 kfree(map->reg_defaults);
206 if (map->cache_free)
207 kfree(map->reg_defaults_raw);
208
209 return ret;
210}
211
212void regcache_exit(struct regmap *map)
213{
214 if (map->cache_type == REGCACHE_NONE)
215 return;
216
217 BUG_ON(!map->cache_ops);
218
219 kfree(map->reg_defaults);
220 if (map->cache_free)
221 kfree(map->reg_defaults_raw);
222
223 if (map->cache_ops->exit) {
224 dev_dbg(map->dev, "Destroying %s cache\n",
225 map->cache_ops->name);
226 map->cache_ops->exit(map);
227 }
228}
229
230/**
231 * regcache_read - Fetch the value of a given register from the cache.
232 *
233 * @map: map to configure.
234 * @reg: The register index.
235 * @value: The value to be returned.
236 *
237 * Return a negative value on failure, 0 on success.
238 */
239int regcache_read(struct regmap *map,
240 unsigned int reg, unsigned int *value)
241{
242 int ret;
243
244 if (map->cache_type == REGCACHE_NONE)
245 return -EINVAL;
246
247 BUG_ON(!map->cache_ops);
248
249 if (!regmap_volatile(map, reg)) {
250 ret = map->cache_ops->read(map, reg, value);
251
252 if (ret == 0)
253 trace_regmap_reg_read_cache(map, reg, *value);
254
255 return ret;
256 }
257
258 return -EINVAL;
259}
260
261/**
262 * regcache_write - Set the value of a given register in the cache.
263 *
264 * @map: map to configure.
265 * @reg: The register index.
266 * @value: The new register value.
267 *
268 * Return a negative value on failure, 0 on success.
269 */
270int regcache_write(struct regmap *map,
271 unsigned int reg, unsigned int value)
272{
273 if (map->cache_type == REGCACHE_NONE)
274 return 0;
275
276 BUG_ON(!map->cache_ops);
277
278 if (!regmap_volatile(map, reg))
279 return map->cache_ops->write(map, reg, value);
280
281 return 0;
282}
283
284bool regcache_reg_needs_sync(struct regmap *map, unsigned int reg,
285 unsigned int val)
286{
287 int ret;
288
289 if (!regmap_writeable(map, reg))
290 return false;
291
292 /* If we don't know the chip just got reset, then sync everything. */
293 if (!map->no_sync_defaults)
294 return true;
295
296 /* Is this the hardware default? If so skip. */
297 ret = regcache_lookup_reg(map, reg);
298 if (ret >= 0 && val == map->reg_defaults[ret].def)
299 return false;
300 return true;
301}
302
303static int regcache_default_sync(struct regmap *map, unsigned int min,
304 unsigned int max)
305{
306 unsigned int reg;
307
308 for (reg = min; reg <= max; reg += map->reg_stride) {
309 unsigned int val;
310 int ret;
311
312 if (regmap_volatile(map, reg) ||
313 !regmap_writeable(map, reg))
314 continue;
315
316 ret = regcache_read(map, reg, &val);
317 if (ret == -ENOENT)
318 continue;
319 if (ret)
320 return ret;
321
322 if (!regcache_reg_needs_sync(map, reg, val))
323 continue;
324
325 map->cache_bypass = true;
326 ret = _regmap_write(map, reg, val);
327 map->cache_bypass = false;
328 if (ret) {
329 dev_err(map->dev, "Unable to sync register %#x. %d\n",
330 reg, ret);
331 return ret;
332 }
333 dev_dbg(map->dev, "Synced register %#x, value %#x\n", reg, val);
334 }
335
336 return 0;
337}
338
339static int rbtree_all(const void *key, const struct rb_node *node)
340{
341 return 0;
342}
343
344/**
345 * regcache_sync - Sync the register cache with the hardware.
346 *
347 * @map: map to configure.
348 *
349 * Any registers that should not be synced should be marked as
350 * volatile. In general drivers can choose not to use the provided
351 * syncing functionality if they so require.
352 *
353 * Return a negative value on failure, 0 on success.
354 */
355int regcache_sync(struct regmap *map)
356{
357 int ret = 0;
358 unsigned int i;
359 const char *name;
360 bool bypass;
361 struct rb_node *node;
362
363 if (WARN_ON(map->cache_type == REGCACHE_NONE))
364 return -EINVAL;
365
366 BUG_ON(!map->cache_ops);
367
368 map->lock(map->lock_arg);
369 /* Remember the initial bypass state */
370 bypass = map->cache_bypass;
371 dev_dbg(map->dev, "Syncing %s cache\n",
372 map->cache_ops->name);
373 name = map->cache_ops->name;
374 trace_regcache_sync(map, name, "start");
375
376 if (!map->cache_dirty)
377 goto out;
378
379 /* Apply any patch first */
380 map->cache_bypass = true;
381 for (i = 0; i < map->patch_regs; i++) {
382 ret = _regmap_write(map, map->patch[i].reg, map->patch[i].def);
383 if (ret != 0) {
384 dev_err(map->dev, "Failed to write %x = %x: %d\n",
385 map->patch[i].reg, map->patch[i].def, ret);
386 goto out;
387 }
388 }
389 map->cache_bypass = false;
390
391 if (map->cache_ops->sync)
392 ret = map->cache_ops->sync(map, 0, map->max_register);
393 else
394 ret = regcache_default_sync(map, 0, map->max_register);
395
396 if (ret == 0)
397 map->cache_dirty = false;
398
399out:
400 /* Restore the bypass state */
401 map->cache_bypass = bypass;
402 map->no_sync_defaults = false;
403
404 /*
405 * If we did any paging with cache bypassed and a cached
406 * paging register then the register and cache state might
407 * have gone out of sync, force writes of all the paging
408 * registers.
409 */
410 rb_for_each(node, 0, &map->range_tree, rbtree_all) {
411 struct regmap_range_node *this =
412 rb_entry(node, struct regmap_range_node, node);
413
414 /* If there's nothing in the cache there's nothing to sync */
415 if (regcache_read(map, this->selector_reg, &i) != 0)
416 continue;
417
418 ret = _regmap_write(map, this->selector_reg, i);
419 if (ret != 0) {
420 dev_err(map->dev, "Failed to write %x = %x: %d\n",
421 this->selector_reg, i, ret);
422 break;
423 }
424 }
425
426 map->unlock(map->lock_arg);
427
428 regmap_async_complete(map);
429
430 trace_regcache_sync(map, name, "stop");
431
432 return ret;
433}
434EXPORT_SYMBOL_GPL(regcache_sync);
435
436/**
437 * regcache_sync_region - Sync part of the register cache with the hardware.
438 *
439 * @map: map to sync.
440 * @min: first register to sync
441 * @max: last register to sync
442 *
443 * Write all non-default register values in the specified region to
444 * the hardware.
445 *
446 * Return a negative value on failure, 0 on success.
447 */
448int regcache_sync_region(struct regmap *map, unsigned int min,
449 unsigned int max)
450{
451 int ret = 0;
452 const char *name;
453 bool bypass;
454
455 if (WARN_ON(map->cache_type == REGCACHE_NONE))
456 return -EINVAL;
457
458 BUG_ON(!map->cache_ops);
459
460 map->lock(map->lock_arg);
461
462 /* Remember the initial bypass state */
463 bypass = map->cache_bypass;
464
465 name = map->cache_ops->name;
466 dev_dbg(map->dev, "Syncing %s cache from %d-%d\n", name, min, max);
467
468 trace_regcache_sync(map, name, "start region");
469
470 if (!map->cache_dirty)
471 goto out;
472
473 map->async = true;
474
475 if (map->cache_ops->sync)
476 ret = map->cache_ops->sync(map, min, max);
477 else
478 ret = regcache_default_sync(map, min, max);
479
480out:
481 /* Restore the bypass state */
482 map->cache_bypass = bypass;
483 map->async = false;
484 map->no_sync_defaults = false;
485 map->unlock(map->lock_arg);
486
487 regmap_async_complete(map);
488
489 trace_regcache_sync(map, name, "stop region");
490
491 return ret;
492}
493EXPORT_SYMBOL_GPL(regcache_sync_region);
494
495/**
496 * regcache_drop_region - Discard part of the register cache
497 *
498 * @map: map to operate on
499 * @min: first register to discard
500 * @max: last register to discard
501 *
502 * Discard part of the register cache.
503 *
504 * Return a negative value on failure, 0 on success.
505 */
506int regcache_drop_region(struct regmap *map, unsigned int min,
507 unsigned int max)
508{
509 int ret = 0;
510
511 if (!map->cache_ops || !map->cache_ops->drop)
512 return -EINVAL;
513
514 map->lock(map->lock_arg);
515
516 trace_regcache_drop_region(map, min, max);
517
518 ret = map->cache_ops->drop(map, min, max);
519
520 map->unlock(map->lock_arg);
521
522 return ret;
523}
524EXPORT_SYMBOL_GPL(regcache_drop_region);
525
526/**
527 * regcache_cache_only - Put a register map into cache only mode
528 *
529 * @map: map to configure
530 * @enable: flag if changes should be written to the hardware
531 *
532 * When a register map is marked as cache only writes to the register
533 * map API will only update the register cache, they will not cause
534 * any hardware changes. This is useful for allowing portions of
535 * drivers to act as though the device were functioning as normal when
536 * it is disabled for power saving reasons.
537 */
538void regcache_cache_only(struct regmap *map, bool enable)
539{
540 map->lock(map->lock_arg);
541 WARN_ON(map->cache_type != REGCACHE_NONE &&
542 map->cache_bypass && enable);
543 map->cache_only = enable;
544 trace_regmap_cache_only(map, enable);
545 map->unlock(map->lock_arg);
546}
547EXPORT_SYMBOL_GPL(regcache_cache_only);
548
549/**
550 * regcache_mark_dirty - Indicate that HW registers were reset to default values
551 *
552 * @map: map to mark
553 *
554 * Inform regcache that the device has been powered down or reset, so that
555 * on resume, regcache_sync() knows to write out all non-default values
556 * stored in the cache.
557 *
558 * If this function is not called, regcache_sync() will assume that
559 * the hardware state still matches the cache state, modulo any writes that
560 * happened when cache_only was true.
561 */
562void regcache_mark_dirty(struct regmap *map)
563{
564 map->lock(map->lock_arg);
565 map->cache_dirty = true;
566 map->no_sync_defaults = true;
567 map->unlock(map->lock_arg);
568}
569EXPORT_SYMBOL_GPL(regcache_mark_dirty);
570
571/**
572 * regcache_cache_bypass - Put a register map into cache bypass mode
573 *
574 * @map: map to configure
575 * @enable: flag if changes should not be written to the cache
576 *
577 * When a register map is marked with the cache bypass option, writes
578 * to the register map API will only update the hardware and not
579 * the cache directly. This is useful when syncing the cache back to
580 * the hardware.
581 */
582void regcache_cache_bypass(struct regmap *map, bool enable)
583{
584 map->lock(map->lock_arg);
585 WARN_ON(map->cache_only && enable);
586 map->cache_bypass = enable;
587 trace_regmap_cache_bypass(map, enable);
588 map->unlock(map->lock_arg);
589}
590EXPORT_SYMBOL_GPL(regcache_cache_bypass);
591
592/**
593 * regcache_reg_cached - Check if a register is cached
594 *
595 * @map: map to check
596 * @reg: register to check
597 *
598 * Reports if a register is cached.
599 */
600bool regcache_reg_cached(struct regmap *map, unsigned int reg)
601{
602 unsigned int val;
603 int ret;
604
605 map->lock(map->lock_arg);
606
607 ret = regcache_read(map, reg, &val);
608
609 map->unlock(map->lock_arg);
610
611 return ret == 0;
612}
613EXPORT_SYMBOL_GPL(regcache_reg_cached);
614
615void regcache_set_val(struct regmap *map, void *base, unsigned int idx,
616 unsigned int val)
617{
618 /* Use device native format if possible */
619 if (map->format.format_val) {
620 map->format.format_val(base + (map->cache_word_size * idx),
621 val, 0);
622 return;
623 }
624
625 switch (map->cache_word_size) {
626 case 1: {
627 u8 *cache = base;
628
629 cache[idx] = val;
630 break;
631 }
632 case 2: {
633 u16 *cache = base;
634
635 cache[idx] = val;
636 break;
637 }
638 case 4: {
639 u32 *cache = base;
640
641 cache[idx] = val;
642 break;
643 }
644 default:
645 BUG();
646 }
647}
648
649unsigned int regcache_get_val(struct regmap *map, const void *base,
650 unsigned int idx)
651{
652 if (!base)
653 return -EINVAL;
654
655 /* Use device native format if possible */
656 if (map->format.parse_val)
657 return map->format.parse_val(regcache_get_val_addr(map, base,
658 idx));
659
660 switch (map->cache_word_size) {
661 case 1: {
662 const u8 *cache = base;
663
664 return cache[idx];
665 }
666 case 2: {
667 const u16 *cache = base;
668
669 return cache[idx];
670 }
671 case 4: {
672 const u32 *cache = base;
673
674 return cache[idx];
675 }
676 default:
677 BUG();
678 }
679 /* unreachable */
680 return -1;
681}
682
683static int regcache_default_cmp(const void *a, const void *b)
684{
685 const struct reg_default *_a = a;
686 const struct reg_default *_b = b;
687
688 return _a->reg - _b->reg;
689}
690
691int regcache_lookup_reg(struct regmap *map, unsigned int reg)
692{
693 struct reg_default key;
694 struct reg_default *r;
695
696 key.reg = reg;
697 key.def = 0;
698
699 r = bsearch(&key, map->reg_defaults, map->num_reg_defaults,
700 sizeof(struct reg_default), regcache_default_cmp);
701
702 if (r)
703 return r - map->reg_defaults;
704 else
705 return -ENOENT;
706}
707
708static bool regcache_reg_present(unsigned long *cache_present, unsigned int idx)
709{
710 if (!cache_present)
711 return true;
712
713 return test_bit(idx, cache_present);
714}
715
716int regcache_sync_val(struct regmap *map, unsigned int reg, unsigned int val)
717{
718 int ret;
719
720 if (!regcache_reg_needs_sync(map, reg, val))
721 return 0;
722
723 map->cache_bypass = true;
724
725 ret = _regmap_write(map, reg, val);
726
727 map->cache_bypass = false;
728
729 if (ret != 0) {
730 dev_err(map->dev, "Unable to sync register %#x. %d\n",
731 reg, ret);
732 return ret;
733 }
734 dev_dbg(map->dev, "Synced register %#x, value %#x\n",
735 reg, val);
736
737 return 0;
738}
739
740static int regcache_sync_block_single(struct regmap *map, void *block,
741 unsigned long *cache_present,
742 unsigned int block_base,
743 unsigned int start, unsigned int end)
744{
745 unsigned int i, regtmp, val;
746 int ret;
747
748 for (i = start; i < end; i++) {
749 regtmp = block_base + (i * map->reg_stride);
750
751 if (!regcache_reg_present(cache_present, i) ||
752 !regmap_writeable(map, regtmp))
753 continue;
754
755 val = regcache_get_val(map, block, i);
756 ret = regcache_sync_val(map, regtmp, val);
757 if (ret != 0)
758 return ret;
759 }
760
761 return 0;
762}
763
764static int regcache_sync_block_raw_flush(struct regmap *map, const void **data,
765 unsigned int base, unsigned int cur)
766{
767 size_t val_bytes = map->format.val_bytes;
768 int ret, count;
769
770 if (*data == NULL)
771 return 0;
772
773 count = (cur - base) / map->reg_stride;
774
775 dev_dbg(map->dev, "Writing %zu bytes for %d registers from 0x%x-0x%x\n",
776 count * val_bytes, count, base, cur - map->reg_stride);
777
778 map->cache_bypass = true;
779
780 ret = _regmap_raw_write(map, base, *data, count * val_bytes, false);
781 if (ret)
782 dev_err(map->dev, "Unable to sync registers %#x-%#x. %d\n",
783 base, cur - map->reg_stride, ret);
784
785 map->cache_bypass = false;
786
787 *data = NULL;
788
789 return ret;
790}
791
792static int regcache_sync_block_raw(struct regmap *map, void *block,
793 unsigned long *cache_present,
794 unsigned int block_base, unsigned int start,
795 unsigned int end)
796{
797 unsigned int i, val;
798 unsigned int regtmp = 0;
799 unsigned int base = 0;
800 const void *data = NULL;
801 int ret;
802
803 for (i = start; i < end; i++) {
804 regtmp = block_base + (i * map->reg_stride);
805
806 if (!regcache_reg_present(cache_present, i) ||
807 !regmap_writeable(map, regtmp)) {
808 ret = regcache_sync_block_raw_flush(map, &data,
809 base, regtmp);
810 if (ret != 0)
811 return ret;
812 continue;
813 }
814
815 val = regcache_get_val(map, block, i);
816 if (!regcache_reg_needs_sync(map, regtmp, val)) {
817 ret = regcache_sync_block_raw_flush(map, &data,
818 base, regtmp);
819 if (ret != 0)
820 return ret;
821 continue;
822 }
823
824 if (!data) {
825 data = regcache_get_val_addr(map, block, i);
826 base = regtmp;
827 }
828 }
829
830 return regcache_sync_block_raw_flush(map, &data, base, regtmp +
831 map->reg_stride);
832}
833
834int regcache_sync_block(struct regmap *map, void *block,
835 unsigned long *cache_present,
836 unsigned int block_base, unsigned int start,
837 unsigned int end)
838{
839 if (regmap_can_raw_write(map) && !map->use_single_write)
840 return regcache_sync_block_raw(map, block, cache_present,
841 block_base, start, end);
842 else
843 return regcache_sync_block_single(map, block, cache_present,
844 block_base, start, end);
845}