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1// SPDX-License-Identifier: GPL-2.0-only
2//
3// HiSilicon SPI NOR V3XX Flash Controller Driver for hi16xx chipsets
4//
5// Copyright (c) 2019 HiSilicon Technologies Co., Ltd.
6// Author: John Garry <john.garry@huawei.com>
7
8#include <linux/acpi.h>
9#include <linux/bitops.h>
10#include <linux/dmi.h>
11#include <linux/iopoll.h>
12#include <linux/module.h>
13#include <linux/platform_device.h>
14#include <linux/slab.h>
15#include <linux/spi/spi.h>
16#include <linux/spi/spi-mem.h>
17
18#define HISI_SFC_V3XX_VERSION (0x1f8)
19
20#define HISI_SFC_V3XX_INT_STAT (0x120)
21#define HISI_SFC_V3XX_INT_STAT_PP_ERR BIT(2)
22#define HISI_SFC_V3XX_INT_STAT_ADDR_IACCES BIT(5)
23#define HISI_SFC_V3XX_INT_CLR (0x12c)
24#define HISI_SFC_V3XX_INT_CLR_CLEAR (0xff)
25#define HISI_SFC_V3XX_CMD_CFG (0x300)
26#define HISI_SFC_V3XX_CMD_CFG_DUAL_IN_DUAL_OUT (1 << 17)
27#define HISI_SFC_V3XX_CMD_CFG_DUAL_IO (2 << 17)
28#define HISI_SFC_V3XX_CMD_CFG_FULL_DIO (3 << 17)
29#define HISI_SFC_V3XX_CMD_CFG_QUAD_IN_QUAD_OUT (5 << 17)
30#define HISI_SFC_V3XX_CMD_CFG_QUAD_IO (6 << 17)
31#define HISI_SFC_V3XX_CMD_CFG_FULL_QIO (7 << 17)
32#define HISI_SFC_V3XX_CMD_CFG_DATA_CNT_OFF 9
33#define HISI_SFC_V3XX_CMD_CFG_RW_MSK BIT(8)
34#define HISI_SFC_V3XX_CMD_CFG_DATA_EN_MSK BIT(7)
35#define HISI_SFC_V3XX_CMD_CFG_DUMMY_CNT_OFF 4
36#define HISI_SFC_V3XX_CMD_CFG_ADDR_EN_MSK BIT(3)
37#define HISI_SFC_V3XX_CMD_CFG_CS_SEL_OFF 1
38#define HISI_SFC_V3XX_CMD_CFG_START_MSK BIT(0)
39#define HISI_SFC_V3XX_CMD_INS (0x308)
40#define HISI_SFC_V3XX_CMD_ADDR (0x30c)
41#define HISI_SFC_V3XX_CMD_DATABUF0 (0x400)
42
43struct hisi_sfc_v3xx_host {
44 struct device *dev;
45 void __iomem *regbase;
46 int max_cmd_dword;
47};
48
49#define HISI_SFC_V3XX_WAIT_TIMEOUT_US 1000000
50#define HISI_SFC_V3XX_WAIT_POLL_INTERVAL_US 10
51
52static int hisi_sfc_v3xx_wait_cmd_idle(struct hisi_sfc_v3xx_host *host)
53{
54 u32 reg;
55
56 return readl_poll_timeout(host->regbase + HISI_SFC_V3XX_CMD_CFG, reg,
57 !(reg & HISI_SFC_V3XX_CMD_CFG_START_MSK),
58 HISI_SFC_V3XX_WAIT_POLL_INTERVAL_US,
59 HISI_SFC_V3XX_WAIT_TIMEOUT_US);
60}
61
62static int hisi_sfc_v3xx_adjust_op_size(struct spi_mem *mem,
63 struct spi_mem_op *op)
64{
65 struct spi_device *spi = mem->spi;
66 struct hisi_sfc_v3xx_host *host;
67 uintptr_t addr = (uintptr_t)op->data.buf.in;
68 int max_byte_count;
69
70 host = spi_controller_get_devdata(spi->master);
71
72 max_byte_count = host->max_cmd_dword * 4;
73
74 if (!IS_ALIGNED(addr, 4) && op->data.nbytes >= 4)
75 op->data.nbytes = 4 - (addr % 4);
76 else if (op->data.nbytes > max_byte_count)
77 op->data.nbytes = max_byte_count;
78
79 return 0;
80}
81
82/*
83 * memcpy_{to,from}io doesn't gurantee 32b accesses - which we require for the
84 * DATABUF registers -so use __io{read,write}32_copy when possible. For
85 * trailing bytes, copy them byte-by-byte from the DATABUF register, as we
86 * can't clobber outside the source/dest buffer.
87 *
88 * For efficient data read/write, we try to put any start 32b unaligned data
89 * into a separate transaction in hisi_sfc_v3xx_adjust_op_size().
90 */
91static void hisi_sfc_v3xx_read_databuf(struct hisi_sfc_v3xx_host *host,
92 u8 *to, unsigned int len)
93{
94 void __iomem *from;
95 int i;
96
97 from = host->regbase + HISI_SFC_V3XX_CMD_DATABUF0;
98
99 if (IS_ALIGNED((uintptr_t)to, 4)) {
100 int words = len / 4;
101
102 __ioread32_copy(to, from, words);
103
104 len -= words * 4;
105 if (len) {
106 u32 val;
107
108 to += words * 4;
109 from += words * 4;
110
111 val = __raw_readl(from);
112
113 for (i = 0; i < len; i++, val >>= 8, to++)
114 *to = (u8)val;
115 }
116 } else {
117 for (i = 0; i < DIV_ROUND_UP(len, 4); i++, from += 4) {
118 u32 val = __raw_readl(from);
119 int j;
120
121 for (j = 0; j < 4 && (j + (i * 4) < len);
122 to++, val >>= 8, j++)
123 *to = (u8)val;
124 }
125 }
126}
127
128static void hisi_sfc_v3xx_write_databuf(struct hisi_sfc_v3xx_host *host,
129 const u8 *from, unsigned int len)
130{
131 void __iomem *to;
132 int i;
133
134 to = host->regbase + HISI_SFC_V3XX_CMD_DATABUF0;
135
136 if (IS_ALIGNED((uintptr_t)from, 4)) {
137 int words = len / 4;
138
139 __iowrite32_copy(to, from, words);
140
141 len -= words * 4;
142 if (len) {
143 u32 val = 0;
144
145 to += words * 4;
146 from += words * 4;
147
148 for (i = 0; i < len; i++, from++)
149 val |= *from << i * 8;
150 __raw_writel(val, to);
151 }
152
153 } else {
154 for (i = 0; i < DIV_ROUND_UP(len, 4); i++, to += 4) {
155 u32 val = 0;
156 int j;
157
158 for (j = 0; j < 4 && (j + (i * 4) < len);
159 from++, j++)
160 val |= *from << j * 8;
161 __raw_writel(val, to);
162 }
163 }
164}
165
166static int hisi_sfc_v3xx_generic_exec_op(struct hisi_sfc_v3xx_host *host,
167 const struct spi_mem_op *op,
168 u8 chip_select)
169{
170 int ret, len = op->data.nbytes;
171 u32 int_stat, config = 0;
172
173 if (op->addr.nbytes)
174 config |= HISI_SFC_V3XX_CMD_CFG_ADDR_EN_MSK;
175
176 switch (op->data.buswidth) {
177 case 0 ... 1:
178 break;
179 case 2:
180 if (op->addr.buswidth <= 1) {
181 config |= HISI_SFC_V3XX_CMD_CFG_DUAL_IN_DUAL_OUT;
182 } else if (op->addr.buswidth == 2) {
183 if (op->cmd.buswidth <= 1) {
184 config |= HISI_SFC_V3XX_CMD_CFG_DUAL_IO;
185 } else if (op->cmd.buswidth == 2) {
186 config |= HISI_SFC_V3XX_CMD_CFG_FULL_DIO;
187 } else {
188 return -EIO;
189 }
190 } else {
191 return -EIO;
192 }
193 break;
194 case 4:
195 if (op->addr.buswidth <= 1) {
196 config |= HISI_SFC_V3XX_CMD_CFG_QUAD_IN_QUAD_OUT;
197 } else if (op->addr.buswidth == 4) {
198 if (op->cmd.buswidth <= 1) {
199 config |= HISI_SFC_V3XX_CMD_CFG_QUAD_IO;
200 } else if (op->cmd.buswidth == 4) {
201 config |= HISI_SFC_V3XX_CMD_CFG_FULL_QIO;
202 } else {
203 return -EIO;
204 }
205 } else {
206 return -EIO;
207 }
208 break;
209 default:
210 return -EOPNOTSUPP;
211 }
212
213 if (op->data.dir != SPI_MEM_NO_DATA) {
214 config |= (len - 1) << HISI_SFC_V3XX_CMD_CFG_DATA_CNT_OFF;
215 config |= HISI_SFC_V3XX_CMD_CFG_DATA_EN_MSK;
216 }
217
218 if (op->data.dir == SPI_MEM_DATA_OUT)
219 hisi_sfc_v3xx_write_databuf(host, op->data.buf.out, len);
220 else if (op->data.dir == SPI_MEM_DATA_IN)
221 config |= HISI_SFC_V3XX_CMD_CFG_RW_MSK;
222
223 config |= op->dummy.nbytes << HISI_SFC_V3XX_CMD_CFG_DUMMY_CNT_OFF |
224 chip_select << HISI_SFC_V3XX_CMD_CFG_CS_SEL_OFF |
225 HISI_SFC_V3XX_CMD_CFG_START_MSK;
226
227 writel(op->addr.val, host->regbase + HISI_SFC_V3XX_CMD_ADDR);
228 writel(op->cmd.opcode, host->regbase + HISI_SFC_V3XX_CMD_INS);
229
230 writel(config, host->regbase + HISI_SFC_V3XX_CMD_CFG);
231
232 ret = hisi_sfc_v3xx_wait_cmd_idle(host);
233 if (ret)
234 return ret;
235
236 /*
237 * The interrupt status register indicates whether an error occurs
238 * after per operation. Check it, and clear the interrupts for
239 * next time judgement.
240 */
241 int_stat = readl(host->regbase + HISI_SFC_V3XX_INT_STAT);
242 writel(HISI_SFC_V3XX_INT_CLR_CLEAR,
243 host->regbase + HISI_SFC_V3XX_INT_CLR);
244
245 if (int_stat & HISI_SFC_V3XX_INT_STAT_ADDR_IACCES) {
246 dev_err(host->dev, "fail to access protected address\n");
247 return -EIO;
248 }
249
250 if (int_stat & HISI_SFC_V3XX_INT_STAT_PP_ERR) {
251 dev_err(host->dev, "page program operation failed\n");
252 return -EIO;
253 }
254
255 if (op->data.dir == SPI_MEM_DATA_IN)
256 hisi_sfc_v3xx_read_databuf(host, op->data.buf.in, len);
257
258 return 0;
259}
260
261static int hisi_sfc_v3xx_exec_op(struct spi_mem *mem,
262 const struct spi_mem_op *op)
263{
264 struct hisi_sfc_v3xx_host *host;
265 struct spi_device *spi = mem->spi;
266 u8 chip_select = spi->chip_select;
267
268 host = spi_controller_get_devdata(spi->master);
269
270 return hisi_sfc_v3xx_generic_exec_op(host, op, chip_select);
271}
272
273static const struct spi_controller_mem_ops hisi_sfc_v3xx_mem_ops = {
274 .adjust_op_size = hisi_sfc_v3xx_adjust_op_size,
275 .exec_op = hisi_sfc_v3xx_exec_op,
276};
277
278static int hisi_sfc_v3xx_buswidth_override_bits;
279
280/*
281 * ACPI FW does not allow us to currently set the device buswidth, so quirk it
282 * depending on the board.
283 */
284static int __init hisi_sfc_v3xx_dmi_quirk(const struct dmi_system_id *d)
285{
286 hisi_sfc_v3xx_buswidth_override_bits = SPI_RX_QUAD | SPI_TX_QUAD;
287
288 return 0;
289}
290
291static const struct dmi_system_id hisi_sfc_v3xx_dmi_quirk_table[] = {
292 {
293 .callback = hisi_sfc_v3xx_dmi_quirk,
294 .matches = {
295 DMI_MATCH(DMI_SYS_VENDOR, "Huawei"),
296 DMI_MATCH(DMI_PRODUCT_NAME, "D06"),
297 },
298 },
299 {
300 .callback = hisi_sfc_v3xx_dmi_quirk,
301 .matches = {
302 DMI_MATCH(DMI_SYS_VENDOR, "Huawei"),
303 DMI_MATCH(DMI_PRODUCT_NAME, "TaiShan 2280 V2"),
304 },
305 },
306 {
307 .callback = hisi_sfc_v3xx_dmi_quirk,
308 .matches = {
309 DMI_MATCH(DMI_SYS_VENDOR, "Huawei"),
310 DMI_MATCH(DMI_PRODUCT_NAME, "TaiShan 200 (Model 2280)"),
311 },
312 },
313 {}
314};
315
316static int hisi_sfc_v3xx_probe(struct platform_device *pdev)
317{
318 struct device *dev = &pdev->dev;
319 struct hisi_sfc_v3xx_host *host;
320 struct spi_controller *ctlr;
321 u32 version;
322 int ret;
323
324 ctlr = spi_alloc_master(&pdev->dev, sizeof(*host));
325 if (!ctlr)
326 return -ENOMEM;
327
328 ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD |
329 SPI_TX_DUAL | SPI_TX_QUAD;
330
331 ctlr->buswidth_override_bits = hisi_sfc_v3xx_buswidth_override_bits;
332
333 host = spi_controller_get_devdata(ctlr);
334 host->dev = dev;
335
336 platform_set_drvdata(pdev, host);
337
338 host->regbase = devm_platform_ioremap_resource(pdev, 0);
339 if (IS_ERR(host->regbase)) {
340 ret = PTR_ERR(host->regbase);
341 goto err_put_master;
342 }
343
344 ctlr->bus_num = -1;
345 ctlr->num_chipselect = 1;
346 ctlr->mem_ops = &hisi_sfc_v3xx_mem_ops;
347
348 version = readl(host->regbase + HISI_SFC_V3XX_VERSION);
349
350 switch (version) {
351 case 0x351:
352 host->max_cmd_dword = 64;
353 break;
354 default:
355 host->max_cmd_dword = 16;
356 break;
357 }
358
359 ret = devm_spi_register_controller(dev, ctlr);
360 if (ret)
361 goto err_put_master;
362
363 dev_info(&pdev->dev, "hw version 0x%x\n", version);
364
365 return 0;
366
367err_put_master:
368 spi_master_put(ctlr);
369 return ret;
370}
371
372#if IS_ENABLED(CONFIG_ACPI)
373static const struct acpi_device_id hisi_sfc_v3xx_acpi_ids[] = {
374 {"HISI0341", 0},
375 {}
376};
377MODULE_DEVICE_TABLE(acpi, hisi_sfc_v3xx_acpi_ids);
378#endif
379
380static struct platform_driver hisi_sfc_v3xx_spi_driver = {
381 .driver = {
382 .name = "hisi-sfc-v3xx",
383 .acpi_match_table = ACPI_PTR(hisi_sfc_v3xx_acpi_ids),
384 },
385 .probe = hisi_sfc_v3xx_probe,
386};
387
388static int __init hisi_sfc_v3xx_spi_init(void)
389{
390 dmi_check_system(hisi_sfc_v3xx_dmi_quirk_table);
391
392 return platform_driver_register(&hisi_sfc_v3xx_spi_driver);
393}
394
395static void __exit hisi_sfc_v3xx_spi_exit(void)
396{
397 platform_driver_unregister(&hisi_sfc_v3xx_spi_driver);
398}
399
400module_init(hisi_sfc_v3xx_spi_init);
401module_exit(hisi_sfc_v3xx_spi_exit);
402
403MODULE_LICENSE("GPL");
404MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
405MODULE_DESCRIPTION("HiSilicon SPI NOR V3XX Flash Controller Driver for hi16xx chipsets");
1// SPDX-License-Identifier: GPL-2.0-only
2//
3// HiSilicon SPI NOR V3XX Flash Controller Driver for hi16xx chipsets
4//
5// Copyright (c) 2019 HiSilicon Technologies Co., Ltd.
6// Author: John Garry <john.garry@huawei.com>
7
8#include <linux/bitops.h>
9#include <linux/completion.h>
10#include <linux/dmi.h>
11#include <linux/interrupt.h>
12#include <linux/iopoll.h>
13#include <linux/module.h>
14#include <linux/mod_devicetable.h>
15#include <linux/platform_device.h>
16#include <linux/slab.h>
17#include <linux/spi/spi.h>
18#include <linux/spi/spi-mem.h>
19
20#define HISI_SFC_V3XX_VERSION (0x1f8)
21
22#define HISI_SFC_V3XX_GLB_CFG (0x100)
23#define HISI_SFC_V3XX_GLB_CFG_CS0_ADDR_MODE BIT(2)
24#define HISI_SFC_V3XX_RAW_INT_STAT (0x120)
25#define HISI_SFC_V3XX_INT_STAT (0x124)
26#define HISI_SFC_V3XX_INT_MASK (0x128)
27#define HISI_SFC_V3XX_INT_CLR (0x12c)
28#define HISI_SFC_V3XX_CMD_CFG (0x300)
29#define HISI_SFC_V3XX_CMD_CFG_DATA_CNT_OFF 9
30#define HISI_SFC_V3XX_CMD_CFG_RW_MSK BIT(8)
31#define HISI_SFC_V3XX_CMD_CFG_DATA_EN_MSK BIT(7)
32#define HISI_SFC_V3XX_CMD_CFG_DUMMY_CNT_OFF 4
33#define HISI_SFC_V3XX_CMD_CFG_ADDR_EN_MSK BIT(3)
34#define HISI_SFC_V3XX_CMD_CFG_CS_SEL_OFF 1
35#define HISI_SFC_V3XX_CMD_CFG_START_MSK BIT(0)
36#define HISI_SFC_V3XX_CMD_INS (0x308)
37#define HISI_SFC_V3XX_CMD_ADDR (0x30c)
38#define HISI_SFC_V3XX_CMD_DATABUF0 (0x400)
39
40/* Common definition of interrupt bit masks */
41#define HISI_SFC_V3XX_INT_MASK_ALL (0x1ff) /* all the masks */
42#define HISI_SFC_V3XX_INT_MASK_CPLT BIT(0) /* command execution complete */
43#define HISI_SFC_V3XX_INT_MASK_PP_ERR BIT(2) /* page progrom error */
44#define HISI_SFC_V3XX_INT_MASK_IACCES BIT(5) /* error visiting inaccessible/
45 * protected address
46 */
47
48/* IO Mode definition in HISI_SFC_V3XX_CMD_CFG */
49#define HISI_SFC_V3XX_STD (0 << 17)
50#define HISI_SFC_V3XX_DIDO (1 << 17)
51#define HISI_SFC_V3XX_DIO (2 << 17)
52#define HISI_SFC_V3XX_FULL_DIO (3 << 17)
53#define HISI_SFC_V3XX_QIQO (5 << 17)
54#define HISI_SFC_V3XX_QIO (6 << 17)
55#define HISI_SFC_V3XX_FULL_QIO (7 << 17)
56
57/*
58 * The IO modes lookup table. hisi_sfc_v3xx_io_modes[(z - 1) / 2][y / 2][x / 2]
59 * stands for x-y-z mode, as described in SFDP terminology. -EIO indicates
60 * an invalid mode.
61 */
62static const int hisi_sfc_v3xx_io_modes[2][3][3] = {
63 {
64 { HISI_SFC_V3XX_DIDO, HISI_SFC_V3XX_DIDO, HISI_SFC_V3XX_DIDO },
65 { HISI_SFC_V3XX_DIO, HISI_SFC_V3XX_FULL_DIO, -EIO },
66 { -EIO, -EIO, -EIO },
67 },
68 {
69 { HISI_SFC_V3XX_QIQO, HISI_SFC_V3XX_QIQO, HISI_SFC_V3XX_QIQO },
70 { -EIO, -EIO, -EIO },
71 { HISI_SFC_V3XX_QIO, -EIO, HISI_SFC_V3XX_FULL_QIO },
72 },
73};
74
75struct hisi_sfc_v3xx_host {
76 struct device *dev;
77 void __iomem *regbase;
78 int max_cmd_dword;
79 struct completion *completion;
80 u8 address_mode;
81 int irq;
82};
83
84static void hisi_sfc_v3xx_disable_int(struct hisi_sfc_v3xx_host *host)
85{
86 writel(0, host->regbase + HISI_SFC_V3XX_INT_MASK);
87}
88
89static void hisi_sfc_v3xx_enable_int(struct hisi_sfc_v3xx_host *host)
90{
91 writel(HISI_SFC_V3XX_INT_MASK_ALL, host->regbase + HISI_SFC_V3XX_INT_MASK);
92}
93
94static void hisi_sfc_v3xx_clear_int(struct hisi_sfc_v3xx_host *host)
95{
96 writel(HISI_SFC_V3XX_INT_MASK_ALL, host->regbase + HISI_SFC_V3XX_INT_CLR);
97}
98
99/*
100 * The interrupt status register indicates whether an error occurs
101 * after per operation. Check it, and clear the interrupts for
102 * next time judgement.
103 */
104static int hisi_sfc_v3xx_handle_completion(struct hisi_sfc_v3xx_host *host)
105{
106 u32 reg;
107
108 reg = readl(host->regbase + HISI_SFC_V3XX_RAW_INT_STAT);
109 hisi_sfc_v3xx_clear_int(host);
110
111 if (reg & HISI_SFC_V3XX_INT_MASK_IACCES) {
112 dev_err(host->dev, "fail to access protected address\n");
113 return -EIO;
114 }
115
116 if (reg & HISI_SFC_V3XX_INT_MASK_PP_ERR) {
117 dev_err(host->dev, "page program operation failed\n");
118 return -EIO;
119 }
120
121 /*
122 * The other bits of the interrupt registers is not currently
123 * used and probably not be triggered in this driver. When it
124 * happens, we regard it as an unsupported error here.
125 */
126 if (!(reg & HISI_SFC_V3XX_INT_MASK_CPLT)) {
127 dev_err(host->dev, "unsupported error occurred, status=0x%x\n", reg);
128 return -EIO;
129 }
130
131 return 0;
132}
133
134#define HISI_SFC_V3XX_WAIT_TIMEOUT_US 1000000
135#define HISI_SFC_V3XX_WAIT_POLL_INTERVAL_US 10
136
137static int hisi_sfc_v3xx_wait_cmd_idle(struct hisi_sfc_v3xx_host *host)
138{
139 u32 reg;
140
141 return readl_poll_timeout(host->regbase + HISI_SFC_V3XX_CMD_CFG, reg,
142 !(reg & HISI_SFC_V3XX_CMD_CFG_START_MSK),
143 HISI_SFC_V3XX_WAIT_POLL_INTERVAL_US,
144 HISI_SFC_V3XX_WAIT_TIMEOUT_US);
145}
146
147static int hisi_sfc_v3xx_adjust_op_size(struct spi_mem *mem,
148 struct spi_mem_op *op)
149{
150 struct spi_device *spi = mem->spi;
151 struct hisi_sfc_v3xx_host *host;
152 uintptr_t addr = (uintptr_t)op->data.buf.in;
153 int max_byte_count;
154
155 host = spi_controller_get_devdata(spi->controller);
156
157 max_byte_count = host->max_cmd_dword * 4;
158
159 if (!IS_ALIGNED(addr, 4) && op->data.nbytes >= 4)
160 op->data.nbytes = 4 - (addr % 4);
161 else if (op->data.nbytes > max_byte_count)
162 op->data.nbytes = max_byte_count;
163
164 return 0;
165}
166
167/*
168 * The controller only supports Standard SPI mode, Dual mode and
169 * Quad mode. Double sanitize the ops here to avoid OOB access.
170 */
171static bool hisi_sfc_v3xx_supports_op(struct spi_mem *mem,
172 const struct spi_mem_op *op)
173{
174 struct spi_device *spi = mem->spi;
175 struct hisi_sfc_v3xx_host *host;
176
177 host = spi_controller_get_devdata(spi->controller);
178
179 if (op->data.buswidth > 4 || op->dummy.buswidth > 4 ||
180 op->addr.buswidth > 4 || op->cmd.buswidth > 4)
181 return false;
182
183 if (op->addr.nbytes != host->address_mode && op->addr.nbytes)
184 return false;
185
186 return spi_mem_default_supports_op(mem, op);
187}
188
189/*
190 * memcpy_{to,from}io doesn't gurantee 32b accesses - which we require for the
191 * DATABUF registers -so use __io{read,write}32_copy when possible. For
192 * trailing bytes, copy them byte-by-byte from the DATABUF register, as we
193 * can't clobber outside the source/dest buffer.
194 *
195 * For efficient data read/write, we try to put any start 32b unaligned data
196 * into a separate transaction in hisi_sfc_v3xx_adjust_op_size().
197 */
198static void hisi_sfc_v3xx_read_databuf(struct hisi_sfc_v3xx_host *host,
199 u8 *to, unsigned int len)
200{
201 void __iomem *from;
202 int i;
203
204 from = host->regbase + HISI_SFC_V3XX_CMD_DATABUF0;
205
206 if (IS_ALIGNED((uintptr_t)to, 4)) {
207 int words = len / 4;
208
209 __ioread32_copy(to, from, words);
210
211 len -= words * 4;
212 if (len) {
213 u32 val;
214
215 to += words * 4;
216 from += words * 4;
217
218 val = __raw_readl(from);
219
220 for (i = 0; i < len; i++, val >>= 8, to++)
221 *to = (u8)val;
222 }
223 } else {
224 for (i = 0; i < DIV_ROUND_UP(len, 4); i++, from += 4) {
225 u32 val = __raw_readl(from);
226 int j;
227
228 for (j = 0; j < 4 && (j + (i * 4) < len);
229 to++, val >>= 8, j++)
230 *to = (u8)val;
231 }
232 }
233}
234
235static void hisi_sfc_v3xx_write_databuf(struct hisi_sfc_v3xx_host *host,
236 const u8 *from, unsigned int len)
237{
238 void __iomem *to;
239 int i;
240
241 to = host->regbase + HISI_SFC_V3XX_CMD_DATABUF0;
242
243 if (IS_ALIGNED((uintptr_t)from, 4)) {
244 int words = len / 4;
245
246 __iowrite32_copy(to, from, words);
247
248 len -= words * 4;
249 if (len) {
250 u32 val = 0;
251
252 to += words * 4;
253 from += words * 4;
254
255 for (i = 0; i < len; i++, from++)
256 val |= *from << i * 8;
257 __raw_writel(val, to);
258 }
259
260 } else {
261 for (i = 0; i < DIV_ROUND_UP(len, 4); i++, to += 4) {
262 u32 val = 0;
263 int j;
264
265 for (j = 0; j < 4 && (j + (i * 4) < len);
266 from++, j++)
267 val |= *from << j * 8;
268 __raw_writel(val, to);
269 }
270 }
271}
272
273static int hisi_sfc_v3xx_start_bus(struct hisi_sfc_v3xx_host *host,
274 const struct spi_mem_op *op,
275 u8 chip_select)
276{
277 int len = op->data.nbytes, buswidth_mode;
278 u32 config = 0;
279
280 if (op->addr.nbytes)
281 config |= HISI_SFC_V3XX_CMD_CFG_ADDR_EN_MSK;
282
283 if (op->data.buswidth == 0 || op->data.buswidth == 1) {
284 buswidth_mode = HISI_SFC_V3XX_STD;
285 } else {
286 int data_idx, addr_idx, cmd_idx;
287
288 data_idx = (op->data.buswidth - 1) / 2;
289 addr_idx = op->addr.buswidth / 2;
290 cmd_idx = op->cmd.buswidth / 2;
291 buswidth_mode = hisi_sfc_v3xx_io_modes[data_idx][addr_idx][cmd_idx];
292 }
293 if (buswidth_mode < 0)
294 return buswidth_mode;
295 config |= buswidth_mode;
296
297 if (op->data.dir != SPI_MEM_NO_DATA) {
298 config |= (len - 1) << HISI_SFC_V3XX_CMD_CFG_DATA_CNT_OFF;
299 config |= HISI_SFC_V3XX_CMD_CFG_DATA_EN_MSK;
300 }
301
302 if (op->data.dir == SPI_MEM_DATA_IN)
303 config |= HISI_SFC_V3XX_CMD_CFG_RW_MSK;
304
305 config |= op->dummy.nbytes << HISI_SFC_V3XX_CMD_CFG_DUMMY_CNT_OFF |
306 chip_select << HISI_SFC_V3XX_CMD_CFG_CS_SEL_OFF |
307 HISI_SFC_V3XX_CMD_CFG_START_MSK;
308
309 writel(op->addr.val, host->regbase + HISI_SFC_V3XX_CMD_ADDR);
310 writel(op->cmd.opcode, host->regbase + HISI_SFC_V3XX_CMD_INS);
311
312 writel(config, host->regbase + HISI_SFC_V3XX_CMD_CFG);
313
314 return 0;
315}
316
317static int hisi_sfc_v3xx_generic_exec_op(struct hisi_sfc_v3xx_host *host,
318 const struct spi_mem_op *op,
319 u8 chip_select)
320{
321 DECLARE_COMPLETION_ONSTACK(done);
322 int ret;
323
324 if (host->irq) {
325 host->completion = &done;
326 hisi_sfc_v3xx_enable_int(host);
327 }
328
329 if (op->data.dir == SPI_MEM_DATA_OUT)
330 hisi_sfc_v3xx_write_databuf(host, op->data.buf.out, op->data.nbytes);
331
332 ret = hisi_sfc_v3xx_start_bus(host, op, chip_select);
333 if (ret)
334 return ret;
335
336 if (host->irq) {
337 ret = wait_for_completion_timeout(host->completion,
338 usecs_to_jiffies(HISI_SFC_V3XX_WAIT_TIMEOUT_US));
339 if (!ret)
340 ret = -ETIMEDOUT;
341 else
342 ret = 0;
343
344 hisi_sfc_v3xx_disable_int(host);
345 synchronize_irq(host->irq);
346 host->completion = NULL;
347 } else {
348 ret = hisi_sfc_v3xx_wait_cmd_idle(host);
349 }
350 if (hisi_sfc_v3xx_handle_completion(host) || ret)
351 return -EIO;
352
353 if (op->data.dir == SPI_MEM_DATA_IN)
354 hisi_sfc_v3xx_read_databuf(host, op->data.buf.in, op->data.nbytes);
355
356 return 0;
357}
358
359static int hisi_sfc_v3xx_exec_op(struct spi_mem *mem,
360 const struct spi_mem_op *op)
361{
362 struct hisi_sfc_v3xx_host *host;
363 struct spi_device *spi = mem->spi;
364 u8 chip_select = spi_get_chipselect(spi, 0);
365
366 host = spi_controller_get_devdata(spi->controller);
367
368 return hisi_sfc_v3xx_generic_exec_op(host, op, chip_select);
369}
370
371static const struct spi_controller_mem_ops hisi_sfc_v3xx_mem_ops = {
372 .adjust_op_size = hisi_sfc_v3xx_adjust_op_size,
373 .supports_op = hisi_sfc_v3xx_supports_op,
374 .exec_op = hisi_sfc_v3xx_exec_op,
375};
376
377static irqreturn_t hisi_sfc_v3xx_isr(int irq, void *data)
378{
379 struct hisi_sfc_v3xx_host *host = data;
380 u32 reg;
381
382 reg = readl(host->regbase + HISI_SFC_V3XX_INT_STAT);
383 if (!reg)
384 return IRQ_NONE;
385
386 hisi_sfc_v3xx_disable_int(host);
387
388 complete(host->completion);
389
390 return IRQ_HANDLED;
391}
392
393static int hisi_sfc_v3xx_buswidth_override_bits;
394
395/*
396 * ACPI FW does not allow us to currently set the device buswidth, so quirk it
397 * depending on the board.
398 */
399static int __init hisi_sfc_v3xx_dmi_quirk(const struct dmi_system_id *d)
400{
401 hisi_sfc_v3xx_buswidth_override_bits = SPI_RX_QUAD | SPI_TX_QUAD;
402
403 return 0;
404}
405
406static const struct dmi_system_id hisi_sfc_v3xx_dmi_quirk_table[] = {
407 {
408 .callback = hisi_sfc_v3xx_dmi_quirk,
409 .matches = {
410 DMI_MATCH(DMI_SYS_VENDOR, "Huawei"),
411 DMI_MATCH(DMI_PRODUCT_NAME, "D06"),
412 },
413 },
414 {
415 .callback = hisi_sfc_v3xx_dmi_quirk,
416 .matches = {
417 DMI_MATCH(DMI_SYS_VENDOR, "Huawei"),
418 DMI_MATCH(DMI_PRODUCT_NAME, "TaiShan 2280 V2"),
419 },
420 },
421 {
422 .callback = hisi_sfc_v3xx_dmi_quirk,
423 .matches = {
424 DMI_MATCH(DMI_SYS_VENDOR, "Huawei"),
425 DMI_MATCH(DMI_PRODUCT_NAME, "TaiShan 200 (Model 2280)"),
426 },
427 },
428 {}
429};
430
431static int hisi_sfc_v3xx_probe(struct platform_device *pdev)
432{
433 struct device *dev = &pdev->dev;
434 struct hisi_sfc_v3xx_host *host;
435 struct spi_controller *ctlr;
436 u32 version, glb_config;
437 int ret;
438
439 ctlr = spi_alloc_host(&pdev->dev, sizeof(*host));
440 if (!ctlr)
441 return -ENOMEM;
442
443 ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD |
444 SPI_TX_DUAL | SPI_TX_QUAD;
445
446 ctlr->buswidth_override_bits = hisi_sfc_v3xx_buswidth_override_bits;
447
448 host = spi_controller_get_devdata(ctlr);
449 host->dev = dev;
450
451 platform_set_drvdata(pdev, host);
452
453 host->regbase = devm_platform_ioremap_resource(pdev, 0);
454 if (IS_ERR(host->regbase)) {
455 ret = PTR_ERR(host->regbase);
456 goto err_put_host;
457 }
458
459 host->irq = platform_get_irq_optional(pdev, 0);
460 if (host->irq == -EPROBE_DEFER) {
461 ret = -EPROBE_DEFER;
462 goto err_put_host;
463 }
464
465 hisi_sfc_v3xx_disable_int(host);
466
467 if (host->irq > 0) {
468 ret = devm_request_irq(dev, host->irq, hisi_sfc_v3xx_isr, 0,
469 "hisi-sfc-v3xx", host);
470
471 if (ret) {
472 dev_err(dev, "failed to request irq%d, ret = %d\n", host->irq, ret);
473 host->irq = 0;
474 }
475 } else {
476 host->irq = 0;
477 }
478
479 ctlr->bus_num = -1;
480 ctlr->num_chipselect = 1;
481 ctlr->mem_ops = &hisi_sfc_v3xx_mem_ops;
482
483 /*
484 * The address mode of the controller is either 3 or 4,
485 * which is indicated by the address mode bit in
486 * the global config register. The register is read only
487 * for the OS driver.
488 */
489 glb_config = readl(host->regbase + HISI_SFC_V3XX_GLB_CFG);
490 if (glb_config & HISI_SFC_V3XX_GLB_CFG_CS0_ADDR_MODE)
491 host->address_mode = 4;
492 else
493 host->address_mode = 3;
494
495 version = readl(host->regbase + HISI_SFC_V3XX_VERSION);
496
497 if (version >= 0x351)
498 host->max_cmd_dword = 64;
499 else
500 host->max_cmd_dword = 16;
501
502 ret = devm_spi_register_controller(dev, ctlr);
503 if (ret)
504 goto err_put_host;
505
506 dev_info(&pdev->dev, "hw version 0x%x, %s mode.\n",
507 version, host->irq ? "irq" : "polling");
508
509 return 0;
510
511err_put_host:
512 spi_controller_put(ctlr);
513 return ret;
514}
515
516static const struct acpi_device_id hisi_sfc_v3xx_acpi_ids[] = {
517 {"HISI0341", 0},
518 {}
519};
520MODULE_DEVICE_TABLE(acpi, hisi_sfc_v3xx_acpi_ids);
521
522static struct platform_driver hisi_sfc_v3xx_spi_driver = {
523 .driver = {
524 .name = "hisi-sfc-v3xx",
525 .acpi_match_table = hisi_sfc_v3xx_acpi_ids,
526 },
527 .probe = hisi_sfc_v3xx_probe,
528};
529
530static int __init hisi_sfc_v3xx_spi_init(void)
531{
532 dmi_check_system(hisi_sfc_v3xx_dmi_quirk_table);
533
534 return platform_driver_register(&hisi_sfc_v3xx_spi_driver);
535}
536
537static void __exit hisi_sfc_v3xx_spi_exit(void)
538{
539 platform_driver_unregister(&hisi_sfc_v3xx_spi_driver);
540}
541
542module_init(hisi_sfc_v3xx_spi_init);
543module_exit(hisi_sfc_v3xx_spi_exit);
544
545MODULE_LICENSE("GPL");
546MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
547MODULE_DESCRIPTION("HiSilicon SPI NOR V3XX Flash Controller Driver for hi16xx chipsets");