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1// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2// Copyright(c) 2015-17 Intel Corporation.
3
4/*
5 * Soundwire Intel Master Driver
6 */
7
8#include <linux/acpi.h>
9#include <linux/debugfs.h>
10#include <linux/delay.h>
11#include <linux/module.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/platform_device.h>
15#include <sound/pcm_params.h>
16#include <linux/pm_runtime.h>
17#include <sound/soc.h>
18#include <linux/soundwire/sdw_registers.h>
19#include <linux/soundwire/sdw.h>
20#include <linux/soundwire/sdw_intel.h>
21#include "cadence_master.h"
22#include "bus.h"
23#include "intel.h"
24
25/* Intel SHIM Registers Definition */
26#define SDW_SHIM_LCAP 0x0
27#define SDW_SHIM_LCTL 0x4
28#define SDW_SHIM_IPPTR 0x8
29#define SDW_SHIM_SYNC 0xC
30
31#define SDW_SHIM_CTLSCAP(x) (0x010 + 0x60 * (x))
32#define SDW_SHIM_CTLS0CM(x) (0x012 + 0x60 * (x))
33#define SDW_SHIM_CTLS1CM(x) (0x014 + 0x60 * (x))
34#define SDW_SHIM_CTLS2CM(x) (0x016 + 0x60 * (x))
35#define SDW_SHIM_CTLS3CM(x) (0x018 + 0x60 * (x))
36#define SDW_SHIM_PCMSCAP(x) (0x020 + 0x60 * (x))
37
38#define SDW_SHIM_PCMSYCHM(x, y) (0x022 + (0x60 * (x)) + (0x2 * (y)))
39#define SDW_SHIM_PCMSYCHC(x, y) (0x042 + (0x60 * (x)) + (0x2 * (y)))
40#define SDW_SHIM_PDMSCAP(x) (0x062 + 0x60 * (x))
41#define SDW_SHIM_IOCTL(x) (0x06C + 0x60 * (x))
42#define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * (x))
43
44#define SDW_SHIM_WAKEEN 0x190
45#define SDW_SHIM_WAKESTS 0x192
46
47#define SDW_SHIM_LCTL_SPA BIT(0)
48#define SDW_SHIM_LCTL_CPA BIT(8)
49
50#define SDW_SHIM_SYNC_SYNCPRD_VAL_24 (24000 / SDW_CADENCE_GSYNC_KHZ - 1)
51#define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4 (38400 / SDW_CADENCE_GSYNC_KHZ - 1)
52#define SDW_SHIM_SYNC_SYNCPRD GENMASK(14, 0)
53#define SDW_SHIM_SYNC_SYNCCPU BIT(15)
54#define SDW_SHIM_SYNC_CMDSYNC_MASK GENMASK(19, 16)
55#define SDW_SHIM_SYNC_CMDSYNC BIT(16)
56#define SDW_SHIM_SYNC_SYNCGO BIT(24)
57
58#define SDW_SHIM_PCMSCAP_ISS GENMASK(3, 0)
59#define SDW_SHIM_PCMSCAP_OSS GENMASK(7, 4)
60#define SDW_SHIM_PCMSCAP_BSS GENMASK(12, 8)
61
62#define SDW_SHIM_PCMSYCM_LCHN GENMASK(3, 0)
63#define SDW_SHIM_PCMSYCM_HCHN GENMASK(7, 4)
64#define SDW_SHIM_PCMSYCM_STREAM GENMASK(13, 8)
65#define SDW_SHIM_PCMSYCM_DIR BIT(15)
66
67#define SDW_SHIM_PDMSCAP_ISS GENMASK(3, 0)
68#define SDW_SHIM_PDMSCAP_OSS GENMASK(7, 4)
69#define SDW_SHIM_PDMSCAP_BSS GENMASK(12, 8)
70#define SDW_SHIM_PDMSCAP_CPSS GENMASK(15, 13)
71
72#define SDW_SHIM_IOCTL_MIF BIT(0)
73#define SDW_SHIM_IOCTL_CO BIT(1)
74#define SDW_SHIM_IOCTL_COE BIT(2)
75#define SDW_SHIM_IOCTL_DO BIT(3)
76#define SDW_SHIM_IOCTL_DOE BIT(4)
77#define SDW_SHIM_IOCTL_BKE BIT(5)
78#define SDW_SHIM_IOCTL_WPDD BIT(6)
79#define SDW_SHIM_IOCTL_CIBD BIT(8)
80#define SDW_SHIM_IOCTL_DIBD BIT(9)
81
82#define SDW_SHIM_CTMCTL_DACTQE BIT(0)
83#define SDW_SHIM_CTMCTL_DODS BIT(1)
84#define SDW_SHIM_CTMCTL_DOAIS GENMASK(4, 3)
85
86#define SDW_SHIM_WAKEEN_ENABLE BIT(0)
87#define SDW_SHIM_WAKESTS_STATUS BIT(0)
88
89/* Intel ALH Register definitions */
90#define SDW_ALH_STRMZCFG(x) (0x000 + (0x4 * (x)))
91#define SDW_ALH_NUM_STREAMS 64
92
93#define SDW_ALH_STRMZCFG_DMAT_VAL 0x3
94#define SDW_ALH_STRMZCFG_DMAT GENMASK(7, 0)
95#define SDW_ALH_STRMZCFG_CHN GENMASK(19, 16)
96
97enum intel_pdi_type {
98 INTEL_PDI_IN = 0,
99 INTEL_PDI_OUT = 1,
100 INTEL_PDI_BD = 2,
101};
102
103#define cdns_to_intel(_cdns) container_of(_cdns, struct sdw_intel, cdns)
104
105/*
106 * Read, write helpers for HW registers
107 */
108static inline int intel_readl(void __iomem *base, int offset)
109{
110 return readl(base + offset);
111}
112
113static inline void intel_writel(void __iomem *base, int offset, int value)
114{
115 writel(value, base + offset);
116}
117
118static inline u16 intel_readw(void __iomem *base, int offset)
119{
120 return readw(base + offset);
121}
122
123static inline void intel_writew(void __iomem *base, int offset, u16 value)
124{
125 writew(value, base + offset);
126}
127
128static int intel_wait_bit(void __iomem *base, int offset, u32 mask, u32 target)
129{
130 int timeout = 10;
131 u32 reg_read;
132
133 do {
134 reg_read = readl(base + offset);
135 if ((reg_read & mask) == target)
136 return 0;
137
138 timeout--;
139 usleep_range(50, 100);
140 } while (timeout != 0);
141
142 return -EAGAIN;
143}
144
145static int intel_clear_bit(void __iomem *base, int offset, u32 value, u32 mask)
146{
147 writel(value, base + offset);
148 return intel_wait_bit(base, offset, mask, 0);
149}
150
151static int intel_set_bit(void __iomem *base, int offset, u32 value, u32 mask)
152{
153 writel(value, base + offset);
154 return intel_wait_bit(base, offset, mask, mask);
155}
156
157/*
158 * debugfs
159 */
160#ifdef CONFIG_DEBUG_FS
161
162#define RD_BUF (2 * PAGE_SIZE)
163
164static ssize_t intel_sprintf(void __iomem *mem, bool l,
165 char *buf, size_t pos, unsigned int reg)
166{
167 int value;
168
169 if (l)
170 value = intel_readl(mem, reg);
171 else
172 value = intel_readw(mem, reg);
173
174 return scnprintf(buf + pos, RD_BUF - pos, "%4x\t%4x\n", reg, value);
175}
176
177static int intel_reg_show(struct seq_file *s_file, void *data)
178{
179 struct sdw_intel *sdw = s_file->private;
180 void __iomem *s = sdw->link_res->shim;
181 void __iomem *a = sdw->link_res->alh;
182 char *buf;
183 ssize_t ret;
184 int i, j;
185 unsigned int links, reg;
186
187 buf = kzalloc(RD_BUF, GFP_KERNEL);
188 if (!buf)
189 return -ENOMEM;
190
191 links = intel_readl(s, SDW_SHIM_LCAP) & GENMASK(2, 0);
192
193 ret = scnprintf(buf, RD_BUF, "Register Value\n");
194 ret += scnprintf(buf + ret, RD_BUF - ret, "\nShim\n");
195
196 for (i = 0; i < links; i++) {
197 reg = SDW_SHIM_LCAP + i * 4;
198 ret += intel_sprintf(s, true, buf, ret, reg);
199 }
200
201 for (i = 0; i < links; i++) {
202 ret += scnprintf(buf + ret, RD_BUF - ret, "\nLink%d\n", i);
203 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLSCAP(i));
204 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS0CM(i));
205 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS1CM(i));
206 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS2CM(i));
207 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS3CM(i));
208 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PCMSCAP(i));
209
210 ret += scnprintf(buf + ret, RD_BUF - ret, "\n PCMSyCH registers\n");
211
212 /*
213 * the value 10 is the number of PDIs. We will need a
214 * cleanup to remove hard-coded Intel configurations
215 * from cadence_master.c
216 */
217 for (j = 0; j < 10; j++) {
218 ret += intel_sprintf(s, false, buf, ret,
219 SDW_SHIM_PCMSYCHM(i, j));
220 ret += intel_sprintf(s, false, buf, ret,
221 SDW_SHIM_PCMSYCHC(i, j));
222 }
223 ret += scnprintf(buf + ret, RD_BUF - ret, "\n PDMSCAP, IOCTL, CTMCTL\n");
224
225 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PDMSCAP(i));
226 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_IOCTL(i));
227 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTMCTL(i));
228 }
229
230 ret += scnprintf(buf + ret, RD_BUF - ret, "\nWake registers\n");
231 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKEEN);
232 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKESTS);
233
234 ret += scnprintf(buf + ret, RD_BUF - ret, "\nALH STRMzCFG\n");
235 for (i = 0; i < SDW_ALH_NUM_STREAMS; i++)
236 ret += intel_sprintf(a, true, buf, ret, SDW_ALH_STRMZCFG(i));
237
238 seq_printf(s_file, "%s", buf);
239 kfree(buf);
240
241 return 0;
242}
243DEFINE_SHOW_ATTRIBUTE(intel_reg);
244
245static void intel_debugfs_init(struct sdw_intel *sdw)
246{
247 struct dentry *root = sdw->cdns.bus.debugfs;
248
249 if (!root)
250 return;
251
252 sdw->debugfs = debugfs_create_dir("intel-sdw", root);
253
254 debugfs_create_file("intel-registers", 0400, sdw->debugfs, sdw,
255 &intel_reg_fops);
256
257 sdw_cdns_debugfs_init(&sdw->cdns, sdw->debugfs);
258}
259
260static void intel_debugfs_exit(struct sdw_intel *sdw)
261{
262 debugfs_remove_recursive(sdw->debugfs);
263}
264#else
265static void intel_debugfs_init(struct sdw_intel *sdw) {}
266static void intel_debugfs_exit(struct sdw_intel *sdw) {}
267#endif /* CONFIG_DEBUG_FS */
268
269/*
270 * shim ops
271 */
272
273static int intel_link_power_up(struct sdw_intel *sdw)
274{
275 unsigned int link_id = sdw->instance;
276 void __iomem *shim = sdw->link_res->shim;
277 u32 *shim_mask = sdw->link_res->shim_mask;
278 struct sdw_bus *bus = &sdw->cdns.bus;
279 struct sdw_master_prop *prop = &bus->prop;
280 int spa_mask, cpa_mask;
281 int link_control;
282 int ret = 0;
283 u32 syncprd;
284 u32 sync_reg;
285
286 mutex_lock(sdw->link_res->shim_lock);
287
288 /*
289 * The hardware relies on an internal counter, typically 4kHz,
290 * to generate the SoundWire SSP - which defines a 'safe'
291 * synchronization point between commands and audio transport
292 * and allows for multi link synchronization. The SYNCPRD value
293 * is only dependent on the oscillator clock provided to
294 * the IP, so adjust based on _DSD properties reported in DSDT
295 * tables. The values reported are based on either 24MHz
296 * (CNL/CML) or 38.4 MHz (ICL/TGL+).
297 */
298 if (prop->mclk_freq % 6000000)
299 syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_38_4;
300 else
301 syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_24;
302
303 if (!*shim_mask) {
304 /* we first need to program the SyncPRD/CPU registers */
305 dev_dbg(sdw->cdns.dev,
306 "%s: first link up, programming SYNCPRD\n", __func__);
307
308 /* set SyncPRD period */
309 sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
310 sync_reg |= (syncprd <<
311 SDW_REG_SHIFT(SDW_SHIM_SYNC_SYNCPRD));
312
313 /* Set SyncCPU bit */
314 sync_reg |= SDW_SHIM_SYNC_SYNCCPU;
315 intel_writel(shim, SDW_SHIM_SYNC, sync_reg);
316 }
317
318 /* Link power up sequence */
319 link_control = intel_readl(shim, SDW_SHIM_LCTL);
320 spa_mask = (SDW_SHIM_LCTL_SPA << link_id);
321 cpa_mask = (SDW_SHIM_LCTL_CPA << link_id);
322 link_control |= spa_mask;
323
324 ret = intel_set_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask);
325 if (ret < 0) {
326 dev_err(sdw->cdns.dev, "Failed to power up link: %d\n", ret);
327 goto out;
328 }
329
330 if (!*shim_mask) {
331 /* SyncCPU will change once link is active */
332 ret = intel_wait_bit(shim, SDW_SHIM_SYNC,
333 SDW_SHIM_SYNC_SYNCCPU, 0);
334 if (ret < 0) {
335 dev_err(sdw->cdns.dev,
336 "Failed to set SHIM_SYNC: %d\n", ret);
337 goto out;
338 }
339 }
340
341 *shim_mask |= BIT(link_id);
342
343 sdw->cdns.link_up = true;
344out:
345 mutex_unlock(sdw->link_res->shim_lock);
346
347 return ret;
348}
349
350/* this needs to be called with shim_lock */
351static void intel_shim_glue_to_master_ip(struct sdw_intel *sdw)
352{
353 void __iomem *shim = sdw->link_res->shim;
354 unsigned int link_id = sdw->instance;
355 u16 ioctl;
356
357 /* Switch to MIP from Glue logic */
358 ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id));
359
360 ioctl &= ~(SDW_SHIM_IOCTL_DOE);
361 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
362 usleep_range(10, 15);
363
364 ioctl &= ~(SDW_SHIM_IOCTL_DO);
365 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
366 usleep_range(10, 15);
367
368 ioctl |= (SDW_SHIM_IOCTL_MIF);
369 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
370 usleep_range(10, 15);
371
372 ioctl &= ~(SDW_SHIM_IOCTL_BKE);
373 ioctl &= ~(SDW_SHIM_IOCTL_COE);
374 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
375 usleep_range(10, 15);
376
377 /* at this point Master IP has full control of the I/Os */
378}
379
380/* this needs to be called with shim_lock */
381static void intel_shim_master_ip_to_glue(struct sdw_intel *sdw)
382{
383 unsigned int link_id = sdw->instance;
384 void __iomem *shim = sdw->link_res->shim;
385 u16 ioctl;
386
387 /* Glue logic */
388 ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id));
389 ioctl |= SDW_SHIM_IOCTL_BKE;
390 ioctl |= SDW_SHIM_IOCTL_COE;
391 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
392 usleep_range(10, 15);
393
394 ioctl &= ~(SDW_SHIM_IOCTL_MIF);
395 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
396 usleep_range(10, 15);
397
398 /* at this point Integration Glue has full control of the I/Os */
399}
400
401static int intel_shim_init(struct sdw_intel *sdw, bool clock_stop)
402{
403 void __iomem *shim = sdw->link_res->shim;
404 unsigned int link_id = sdw->instance;
405 int ret = 0;
406 u16 ioctl = 0, act = 0;
407
408 mutex_lock(sdw->link_res->shim_lock);
409
410 /* Initialize Shim */
411 ioctl |= SDW_SHIM_IOCTL_BKE;
412 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
413 usleep_range(10, 15);
414
415 ioctl |= SDW_SHIM_IOCTL_WPDD;
416 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
417 usleep_range(10, 15);
418
419 ioctl |= SDW_SHIM_IOCTL_DO;
420 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
421 usleep_range(10, 15);
422
423 ioctl |= SDW_SHIM_IOCTL_DOE;
424 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
425 usleep_range(10, 15);
426
427 intel_shim_glue_to_master_ip(sdw);
428
429 act |= 0x1 << SDW_REG_SHIFT(SDW_SHIM_CTMCTL_DOAIS);
430 act |= SDW_SHIM_CTMCTL_DACTQE;
431 act |= SDW_SHIM_CTMCTL_DODS;
432 intel_writew(shim, SDW_SHIM_CTMCTL(link_id), act);
433 usleep_range(10, 15);
434
435 mutex_unlock(sdw->link_res->shim_lock);
436
437 return ret;
438}
439
440static void intel_shim_wake(struct sdw_intel *sdw, bool wake_enable)
441{
442 void __iomem *shim = sdw->link_res->shim;
443 unsigned int link_id = sdw->instance;
444 u16 wake_en, wake_sts;
445
446 mutex_lock(sdw->link_res->shim_lock);
447 wake_en = intel_readw(shim, SDW_SHIM_WAKEEN);
448
449 if (wake_enable) {
450 /* Enable the wakeup */
451 wake_en |= (SDW_SHIM_WAKEEN_ENABLE << link_id);
452 intel_writew(shim, SDW_SHIM_WAKEEN, wake_en);
453 } else {
454 /* Disable the wake up interrupt */
455 wake_en &= ~(SDW_SHIM_WAKEEN_ENABLE << link_id);
456 intel_writew(shim, SDW_SHIM_WAKEEN, wake_en);
457
458 /* Clear wake status */
459 wake_sts = intel_readw(shim, SDW_SHIM_WAKESTS);
460 wake_sts |= (SDW_SHIM_WAKEEN_ENABLE << link_id);
461 intel_writew(shim, SDW_SHIM_WAKESTS_STATUS, wake_sts);
462 }
463 mutex_unlock(sdw->link_res->shim_lock);
464}
465
466static int __maybe_unused intel_link_power_down(struct sdw_intel *sdw)
467{
468 int link_control, spa_mask, cpa_mask;
469 unsigned int link_id = sdw->instance;
470 void __iomem *shim = sdw->link_res->shim;
471 u32 *shim_mask = sdw->link_res->shim_mask;
472 int ret = 0;
473
474 mutex_lock(sdw->link_res->shim_lock);
475
476 intel_shim_master_ip_to_glue(sdw);
477
478 /* Link power down sequence */
479 link_control = intel_readl(shim, SDW_SHIM_LCTL);
480 spa_mask = ~(SDW_SHIM_LCTL_SPA << link_id);
481 cpa_mask = (SDW_SHIM_LCTL_CPA << link_id);
482 link_control &= spa_mask;
483
484 ret = intel_clear_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask);
485
486 if (!(*shim_mask & BIT(link_id)))
487 dev_err(sdw->cdns.dev,
488 "%s: Unbalanced power-up/down calls\n", __func__);
489
490 *shim_mask &= ~BIT(link_id);
491
492 mutex_unlock(sdw->link_res->shim_lock);
493
494 if (ret < 0)
495 return ret;
496
497 sdw->cdns.link_up = false;
498 return 0;
499}
500
501static void intel_shim_sync_arm(struct sdw_intel *sdw)
502{
503 void __iomem *shim = sdw->link_res->shim;
504 u32 sync_reg;
505
506 mutex_lock(sdw->link_res->shim_lock);
507
508 /* update SYNC register */
509 sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
510 sync_reg |= (SDW_SHIM_SYNC_CMDSYNC << sdw->instance);
511 intel_writel(shim, SDW_SHIM_SYNC, sync_reg);
512
513 mutex_unlock(sdw->link_res->shim_lock);
514}
515
516static int intel_shim_sync_go_unlocked(struct sdw_intel *sdw)
517{
518 void __iomem *shim = sdw->link_res->shim;
519 u32 sync_reg;
520 int ret;
521
522 /* Read SYNC register */
523 sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
524
525 /*
526 * Set SyncGO bit to synchronously trigger a bank switch for
527 * all the masters. A write to SYNCGO bit clears CMDSYNC bit for all
528 * the Masters.
529 */
530 sync_reg |= SDW_SHIM_SYNC_SYNCGO;
531
532 ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg,
533 SDW_SHIM_SYNC_SYNCGO);
534
535 if (ret < 0)
536 dev_err(sdw->cdns.dev, "SyncGO clear failed: %d\n", ret);
537
538 return ret;
539}
540
541/*
542 * PDI routines
543 */
544static void intel_pdi_init(struct sdw_intel *sdw,
545 struct sdw_cdns_stream_config *config)
546{
547 void __iomem *shim = sdw->link_res->shim;
548 unsigned int link_id = sdw->instance;
549 int pcm_cap, pdm_cap;
550
551 /* PCM Stream Capability */
552 pcm_cap = intel_readw(shim, SDW_SHIM_PCMSCAP(link_id));
553
554 config->pcm_bd = (pcm_cap & SDW_SHIM_PCMSCAP_BSS) >>
555 SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_BSS);
556 config->pcm_in = (pcm_cap & SDW_SHIM_PCMSCAP_ISS) >>
557 SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_ISS);
558 config->pcm_out = (pcm_cap & SDW_SHIM_PCMSCAP_OSS) >>
559 SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_OSS);
560
561 dev_dbg(sdw->cdns.dev, "PCM cap bd:%d in:%d out:%d\n",
562 config->pcm_bd, config->pcm_in, config->pcm_out);
563
564 /* PDM Stream Capability */
565 pdm_cap = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id));
566
567 config->pdm_bd = (pdm_cap & SDW_SHIM_PDMSCAP_BSS) >>
568 SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_BSS);
569 config->pdm_in = (pdm_cap & SDW_SHIM_PDMSCAP_ISS) >>
570 SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_ISS);
571 config->pdm_out = (pdm_cap & SDW_SHIM_PDMSCAP_OSS) >>
572 SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_OSS);
573
574 dev_dbg(sdw->cdns.dev, "PDM cap bd:%d in:%d out:%d\n",
575 config->pdm_bd, config->pdm_in, config->pdm_out);
576}
577
578static int
579intel_pdi_get_ch_cap(struct sdw_intel *sdw, unsigned int pdi_num, bool pcm)
580{
581 void __iomem *shim = sdw->link_res->shim;
582 unsigned int link_id = sdw->instance;
583 int count;
584
585 if (pcm) {
586 count = intel_readw(shim, SDW_SHIM_PCMSYCHC(link_id, pdi_num));
587
588 /*
589 * WORKAROUND: on all existing Intel controllers, pdi
590 * number 2 reports channel count as 1 even though it
591 * supports 8 channels. Performing hardcoding for pdi
592 * number 2.
593 */
594 if (pdi_num == 2)
595 count = 7;
596
597 } else {
598 count = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id));
599 count = ((count & SDW_SHIM_PDMSCAP_CPSS) >>
600 SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_CPSS));
601 }
602
603 /* zero based values for channel count in register */
604 count++;
605
606 return count;
607}
608
609static int intel_pdi_get_ch_update(struct sdw_intel *sdw,
610 struct sdw_cdns_pdi *pdi,
611 unsigned int num_pdi,
612 unsigned int *num_ch, bool pcm)
613{
614 int i, ch_count = 0;
615
616 for (i = 0; i < num_pdi; i++) {
617 pdi->ch_count = intel_pdi_get_ch_cap(sdw, pdi->num, pcm);
618 ch_count += pdi->ch_count;
619 pdi++;
620 }
621
622 *num_ch = ch_count;
623 return 0;
624}
625
626static int intel_pdi_stream_ch_update(struct sdw_intel *sdw,
627 struct sdw_cdns_streams *stream, bool pcm)
628{
629 intel_pdi_get_ch_update(sdw, stream->bd, stream->num_bd,
630 &stream->num_ch_bd, pcm);
631
632 intel_pdi_get_ch_update(sdw, stream->in, stream->num_in,
633 &stream->num_ch_in, pcm);
634
635 intel_pdi_get_ch_update(sdw, stream->out, stream->num_out,
636 &stream->num_ch_out, pcm);
637
638 return 0;
639}
640
641static int intel_pdi_ch_update(struct sdw_intel *sdw)
642{
643 /* First update PCM streams followed by PDM streams */
644 intel_pdi_stream_ch_update(sdw, &sdw->cdns.pcm, true);
645 intel_pdi_stream_ch_update(sdw, &sdw->cdns.pdm, false);
646
647 return 0;
648}
649
650static void
651intel_pdi_shim_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
652{
653 void __iomem *shim = sdw->link_res->shim;
654 unsigned int link_id = sdw->instance;
655 int pdi_conf = 0;
656
657 /* the Bulk and PCM streams are not contiguous */
658 pdi->intel_alh_id = (link_id * 16) + pdi->num + 3;
659 if (pdi->num >= 2)
660 pdi->intel_alh_id += 2;
661
662 /*
663 * Program stream parameters to stream SHIM register
664 * This is applicable for PCM stream only.
665 */
666 if (pdi->type != SDW_STREAM_PCM)
667 return;
668
669 if (pdi->dir == SDW_DATA_DIR_RX)
670 pdi_conf |= SDW_SHIM_PCMSYCM_DIR;
671 else
672 pdi_conf &= ~(SDW_SHIM_PCMSYCM_DIR);
673
674 pdi_conf |= (pdi->intel_alh_id <<
675 SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_STREAM));
676 pdi_conf |= (pdi->l_ch_num << SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_LCHN));
677 pdi_conf |= (pdi->h_ch_num << SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_HCHN));
678
679 intel_writew(shim, SDW_SHIM_PCMSYCHM(link_id, pdi->num), pdi_conf);
680}
681
682static void
683intel_pdi_alh_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
684{
685 void __iomem *alh = sdw->link_res->alh;
686 unsigned int link_id = sdw->instance;
687 unsigned int conf;
688
689 /* the Bulk and PCM streams are not contiguous */
690 pdi->intel_alh_id = (link_id * 16) + pdi->num + 3;
691 if (pdi->num >= 2)
692 pdi->intel_alh_id += 2;
693
694 /* Program Stream config ALH register */
695 conf = intel_readl(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id));
696
697 conf |= (SDW_ALH_STRMZCFG_DMAT_VAL <<
698 SDW_REG_SHIFT(SDW_ALH_STRMZCFG_DMAT));
699
700 conf |= ((pdi->ch_count - 1) <<
701 SDW_REG_SHIFT(SDW_ALH_STRMZCFG_CHN));
702
703 intel_writel(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id), conf);
704}
705
706static int intel_params_stream(struct sdw_intel *sdw,
707 struct snd_pcm_substream *substream,
708 struct snd_soc_dai *dai,
709 struct snd_pcm_hw_params *hw_params,
710 int link_id, int alh_stream_id)
711{
712 struct sdw_intel_link_res *res = sdw->link_res;
713 struct sdw_intel_stream_params_data params_data;
714
715 params_data.substream = substream;
716 params_data.dai = dai;
717 params_data.hw_params = hw_params;
718 params_data.link_id = link_id;
719 params_data.alh_stream_id = alh_stream_id;
720
721 if (res->ops && res->ops->params_stream && res->dev)
722 return res->ops->params_stream(res->dev,
723 ¶ms_data);
724 return -EIO;
725}
726
727static int intel_free_stream(struct sdw_intel *sdw,
728 struct snd_pcm_substream *substream,
729 struct snd_soc_dai *dai,
730 int link_id)
731{
732 struct sdw_intel_link_res *res = sdw->link_res;
733 struct sdw_intel_stream_free_data free_data;
734
735 free_data.substream = substream;
736 free_data.dai = dai;
737 free_data.link_id = link_id;
738
739 if (res->ops && res->ops->free_stream && res->dev)
740 return res->ops->free_stream(res->dev,
741 &free_data);
742
743 return 0;
744}
745
746/*
747 * bank switch routines
748 */
749
750static int intel_pre_bank_switch(struct sdw_bus *bus)
751{
752 struct sdw_cdns *cdns = bus_to_cdns(bus);
753 struct sdw_intel *sdw = cdns_to_intel(cdns);
754
755 /* Write to register only for multi-link */
756 if (!bus->multi_link)
757 return 0;
758
759 intel_shim_sync_arm(sdw);
760
761 return 0;
762}
763
764static int intel_post_bank_switch(struct sdw_bus *bus)
765{
766 struct sdw_cdns *cdns = bus_to_cdns(bus);
767 struct sdw_intel *sdw = cdns_to_intel(cdns);
768 void __iomem *shim = sdw->link_res->shim;
769 int sync_reg, ret;
770
771 /* Write to register only for multi-link */
772 if (!bus->multi_link)
773 return 0;
774
775 mutex_lock(sdw->link_res->shim_lock);
776
777 /* Read SYNC register */
778 sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
779
780 /*
781 * post_bank_switch() ops is called from the bus in loop for
782 * all the Masters in the steam with the expectation that
783 * we trigger the bankswitch for the only first Master in the list
784 * and do nothing for the other Masters
785 *
786 * So, set the SYNCGO bit only if CMDSYNC bit is set for any Master.
787 */
788 if (!(sync_reg & SDW_SHIM_SYNC_CMDSYNC_MASK)) {
789 ret = 0;
790 goto unlock;
791 }
792
793 ret = intel_shim_sync_go_unlocked(sdw);
794unlock:
795 mutex_unlock(sdw->link_res->shim_lock);
796
797 if (ret < 0)
798 dev_err(sdw->cdns.dev, "Post bank switch failed: %d\n", ret);
799
800 return ret;
801}
802
803/*
804 * DAI routines
805 */
806
807static int intel_startup(struct snd_pcm_substream *substream,
808 struct snd_soc_dai *dai)
809{
810 /*
811 * TODO: add pm_runtime support here, the startup callback
812 * will make sure the IP is 'active'
813 */
814 return 0;
815}
816
817static int intel_hw_params(struct snd_pcm_substream *substream,
818 struct snd_pcm_hw_params *params,
819 struct snd_soc_dai *dai)
820{
821 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
822 struct sdw_intel *sdw = cdns_to_intel(cdns);
823 struct sdw_cdns_dma_data *dma;
824 struct sdw_cdns_pdi *pdi;
825 struct sdw_stream_config sconfig;
826 struct sdw_port_config *pconfig;
827 int ch, dir;
828 int ret;
829 bool pcm = true;
830
831 dma = snd_soc_dai_get_dma_data(dai, substream);
832 if (!dma)
833 return -EIO;
834
835 ch = params_channels(params);
836 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
837 dir = SDW_DATA_DIR_RX;
838 else
839 dir = SDW_DATA_DIR_TX;
840
841 if (dma->stream_type == SDW_STREAM_PDM)
842 pcm = false;
843
844 if (pcm)
845 pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pcm, ch, dir, dai->id);
846 else
847 pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pdm, ch, dir, dai->id);
848
849 if (!pdi) {
850 ret = -EINVAL;
851 goto error;
852 }
853
854 /* do run-time configurations for SHIM, ALH and PDI/PORT */
855 intel_pdi_shim_configure(sdw, pdi);
856 intel_pdi_alh_configure(sdw, pdi);
857 sdw_cdns_config_stream(cdns, ch, dir, pdi);
858
859
860 /* Inform DSP about PDI stream number */
861 ret = intel_params_stream(sdw, substream, dai, params,
862 sdw->instance,
863 pdi->intel_alh_id);
864 if (ret)
865 goto error;
866
867 sconfig.direction = dir;
868 sconfig.ch_count = ch;
869 sconfig.frame_rate = params_rate(params);
870 sconfig.type = dma->stream_type;
871
872 if (dma->stream_type == SDW_STREAM_PDM) {
873 sconfig.frame_rate *= 50;
874 sconfig.bps = 1;
875 } else {
876 sconfig.bps = snd_pcm_format_width(params_format(params));
877 }
878
879 /* Port configuration */
880 pconfig = kcalloc(1, sizeof(*pconfig), GFP_KERNEL);
881 if (!pconfig) {
882 ret = -ENOMEM;
883 goto error;
884 }
885
886 pconfig->num = pdi->num;
887 pconfig->ch_mask = (1 << ch) - 1;
888
889 ret = sdw_stream_add_master(&cdns->bus, &sconfig,
890 pconfig, 1, dma->stream);
891 if (ret)
892 dev_err(cdns->dev, "add master to stream failed:%d\n", ret);
893
894 kfree(pconfig);
895error:
896 return ret;
897}
898
899static int intel_prepare(struct snd_pcm_substream *substream,
900 struct snd_soc_dai *dai)
901{
902 struct sdw_cdns_dma_data *dma;
903
904 dma = snd_soc_dai_get_dma_data(dai, substream);
905 if (!dma) {
906 dev_err(dai->dev, "failed to get dma data in %s",
907 __func__);
908 return -EIO;
909 }
910
911 return sdw_prepare_stream(dma->stream);
912}
913
914static int intel_trigger(struct snd_pcm_substream *substream, int cmd,
915 struct snd_soc_dai *dai)
916{
917 struct sdw_cdns_dma_data *dma;
918 int ret;
919
920 dma = snd_soc_dai_get_dma_data(dai, substream);
921 if (!dma) {
922 dev_err(dai->dev, "failed to get dma data in %s", __func__);
923 return -EIO;
924 }
925
926 switch (cmd) {
927 case SNDRV_PCM_TRIGGER_START:
928 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
929 case SNDRV_PCM_TRIGGER_RESUME:
930 ret = sdw_enable_stream(dma->stream);
931 break;
932
933 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
934 case SNDRV_PCM_TRIGGER_SUSPEND:
935 case SNDRV_PCM_TRIGGER_STOP:
936 ret = sdw_disable_stream(dma->stream);
937 break;
938
939 default:
940 ret = -EINVAL;
941 break;
942 }
943
944 if (ret)
945 dev_err(dai->dev,
946 "%s trigger %d failed: %d",
947 __func__, cmd, ret);
948 return ret;
949}
950
951static int
952intel_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
953{
954 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
955 struct sdw_intel *sdw = cdns_to_intel(cdns);
956 struct sdw_cdns_dma_data *dma;
957 int ret;
958
959 dma = snd_soc_dai_get_dma_data(dai, substream);
960 if (!dma)
961 return -EIO;
962
963 ret = sdw_deprepare_stream(dma->stream);
964 if (ret) {
965 dev_err(dai->dev, "sdw_deprepare_stream: failed %d", ret);
966 return ret;
967 }
968
969 ret = sdw_stream_remove_master(&cdns->bus, dma->stream);
970 if (ret < 0) {
971 dev_err(dai->dev, "remove master from stream %s failed: %d\n",
972 dma->stream->name, ret);
973 return ret;
974 }
975
976 ret = intel_free_stream(sdw, substream, dai, sdw->instance);
977 if (ret < 0) {
978 dev_err(dai->dev, "intel_free_stream: failed %d", ret);
979 return ret;
980 }
981
982 return 0;
983}
984
985static void intel_shutdown(struct snd_pcm_substream *substream,
986 struct snd_soc_dai *dai)
987{
988
989}
990
991static int intel_pcm_set_sdw_stream(struct snd_soc_dai *dai,
992 void *stream, int direction)
993{
994 return cdns_set_sdw_stream(dai, stream, true, direction);
995}
996
997static int intel_pdm_set_sdw_stream(struct snd_soc_dai *dai,
998 void *stream, int direction)
999{
1000 return cdns_set_sdw_stream(dai, stream, false, direction);
1001}
1002
1003static void *intel_get_sdw_stream(struct snd_soc_dai *dai,
1004 int direction)
1005{
1006 struct sdw_cdns_dma_data *dma;
1007
1008 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1009 dma = dai->playback_dma_data;
1010 else
1011 dma = dai->capture_dma_data;
1012
1013 if (!dma)
1014 return NULL;
1015
1016 return dma->stream;
1017}
1018
1019static const struct snd_soc_dai_ops intel_pcm_dai_ops = {
1020 .startup = intel_startup,
1021 .hw_params = intel_hw_params,
1022 .prepare = intel_prepare,
1023 .trigger = intel_trigger,
1024 .hw_free = intel_hw_free,
1025 .shutdown = intel_shutdown,
1026 .set_sdw_stream = intel_pcm_set_sdw_stream,
1027 .get_sdw_stream = intel_get_sdw_stream,
1028};
1029
1030static const struct snd_soc_dai_ops intel_pdm_dai_ops = {
1031 .startup = intel_startup,
1032 .hw_params = intel_hw_params,
1033 .prepare = intel_prepare,
1034 .trigger = intel_trigger,
1035 .hw_free = intel_hw_free,
1036 .shutdown = intel_shutdown,
1037 .set_sdw_stream = intel_pdm_set_sdw_stream,
1038 .get_sdw_stream = intel_get_sdw_stream,
1039};
1040
1041static const struct snd_soc_component_driver dai_component = {
1042 .name = "soundwire",
1043};
1044
1045static int intel_create_dai(struct sdw_cdns *cdns,
1046 struct snd_soc_dai_driver *dais,
1047 enum intel_pdi_type type,
1048 u32 num, u32 off, u32 max_ch, bool pcm)
1049{
1050 int i;
1051
1052 if (num == 0)
1053 return 0;
1054
1055 /* TODO: Read supported rates/formats from hardware */
1056 for (i = off; i < (off + num); i++) {
1057 dais[i].name = devm_kasprintf(cdns->dev, GFP_KERNEL,
1058 "SDW%d Pin%d",
1059 cdns->instance, i);
1060 if (!dais[i].name)
1061 return -ENOMEM;
1062
1063 if (type == INTEL_PDI_BD || type == INTEL_PDI_OUT) {
1064 dais[i].playback.channels_min = 1;
1065 dais[i].playback.channels_max = max_ch;
1066 dais[i].playback.rates = SNDRV_PCM_RATE_48000;
1067 dais[i].playback.formats = SNDRV_PCM_FMTBIT_S16_LE;
1068 }
1069
1070 if (type == INTEL_PDI_BD || type == INTEL_PDI_IN) {
1071 dais[i].capture.channels_min = 1;
1072 dais[i].capture.channels_max = max_ch;
1073 dais[i].capture.rates = SNDRV_PCM_RATE_48000;
1074 dais[i].capture.formats = SNDRV_PCM_FMTBIT_S16_LE;
1075 }
1076
1077 if (pcm)
1078 dais[i].ops = &intel_pcm_dai_ops;
1079 else
1080 dais[i].ops = &intel_pdm_dai_ops;
1081 }
1082
1083 return 0;
1084}
1085
1086static int intel_register_dai(struct sdw_intel *sdw)
1087{
1088 struct sdw_cdns *cdns = &sdw->cdns;
1089 struct sdw_cdns_streams *stream;
1090 struct snd_soc_dai_driver *dais;
1091 int num_dai, ret, off = 0;
1092
1093 /* DAIs are created based on total number of PDIs supported */
1094 num_dai = cdns->pcm.num_pdi + cdns->pdm.num_pdi;
1095
1096 dais = devm_kcalloc(cdns->dev, num_dai, sizeof(*dais), GFP_KERNEL);
1097 if (!dais)
1098 return -ENOMEM;
1099
1100 /* Create PCM DAIs */
1101 stream = &cdns->pcm;
1102
1103 ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pcm.num_in,
1104 off, stream->num_ch_in, true);
1105 if (ret)
1106 return ret;
1107
1108 off += cdns->pcm.num_in;
1109 ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pcm.num_out,
1110 off, stream->num_ch_out, true);
1111 if (ret)
1112 return ret;
1113
1114 off += cdns->pcm.num_out;
1115 ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pcm.num_bd,
1116 off, stream->num_ch_bd, true);
1117 if (ret)
1118 return ret;
1119
1120 /* Create PDM DAIs */
1121 stream = &cdns->pdm;
1122 off += cdns->pcm.num_bd;
1123 ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pdm.num_in,
1124 off, stream->num_ch_in, false);
1125 if (ret)
1126 return ret;
1127
1128 off += cdns->pdm.num_in;
1129 ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pdm.num_out,
1130 off, stream->num_ch_out, false);
1131 if (ret)
1132 return ret;
1133
1134 off += cdns->pdm.num_out;
1135 ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pdm.num_bd,
1136 off, stream->num_ch_bd, false);
1137 if (ret)
1138 return ret;
1139
1140 return snd_soc_register_component(cdns->dev, &dai_component,
1141 dais, num_dai);
1142}
1143
1144static int sdw_master_read_intel_prop(struct sdw_bus *bus)
1145{
1146 struct sdw_master_prop *prop = &bus->prop;
1147 struct fwnode_handle *link;
1148 char name[32];
1149 u32 quirk_mask;
1150
1151 /* Find master handle */
1152 snprintf(name, sizeof(name),
1153 "mipi-sdw-link-%d-subproperties", bus->link_id);
1154
1155 link = device_get_named_child_node(bus->dev, name);
1156 if (!link) {
1157 dev_err(bus->dev, "Master node %s not found\n", name);
1158 return -EIO;
1159 }
1160
1161 fwnode_property_read_u32(link,
1162 "intel-sdw-ip-clock",
1163 &prop->mclk_freq);
1164
1165 /* the values reported by BIOS are the 2x clock, not the bus clock */
1166 prop->mclk_freq /= 2;
1167
1168 fwnode_property_read_u32(link,
1169 "intel-quirk-mask",
1170 &quirk_mask);
1171
1172 if (quirk_mask & SDW_INTEL_QUIRK_MASK_BUS_DISABLE)
1173 prop->hw_disabled = true;
1174
1175 return 0;
1176}
1177
1178static int intel_prop_read(struct sdw_bus *bus)
1179{
1180 /* Initialize with default handler to read all DisCo properties */
1181 sdw_master_read_prop(bus);
1182
1183 /* read Intel-specific properties */
1184 sdw_master_read_intel_prop(bus);
1185
1186 return 0;
1187}
1188
1189static struct sdw_master_ops sdw_intel_ops = {
1190 .read_prop = sdw_master_read_prop,
1191 .xfer_msg = cdns_xfer_msg,
1192 .xfer_msg_defer = cdns_xfer_msg_defer,
1193 .reset_page_addr = cdns_reset_page_addr,
1194 .set_bus_conf = cdns_bus_conf,
1195 .pre_bank_switch = intel_pre_bank_switch,
1196 .post_bank_switch = intel_post_bank_switch,
1197};
1198
1199static int intel_init(struct sdw_intel *sdw)
1200{
1201 bool clock_stop;
1202
1203 /* Initialize shim and controller */
1204 intel_link_power_up(sdw);
1205
1206 clock_stop = sdw_cdns_is_clock_stop(&sdw->cdns);
1207
1208 intel_shim_init(sdw, clock_stop);
1209
1210 if (clock_stop)
1211 return 0;
1212
1213 return sdw_cdns_init(&sdw->cdns);
1214}
1215
1216/*
1217 * probe and init
1218 */
1219static int intel_master_probe(struct platform_device *pdev)
1220{
1221 struct device *dev = &pdev->dev;
1222 struct sdw_intel *sdw;
1223 struct sdw_cdns *cdns;
1224 struct sdw_bus *bus;
1225 int ret;
1226
1227 sdw = devm_kzalloc(dev, sizeof(*sdw), GFP_KERNEL);
1228 if (!sdw)
1229 return -ENOMEM;
1230
1231 cdns = &sdw->cdns;
1232 bus = &cdns->bus;
1233
1234 sdw->instance = pdev->id;
1235 sdw->link_res = dev_get_platdata(dev);
1236 cdns->dev = dev;
1237 cdns->registers = sdw->link_res->registers;
1238 cdns->instance = sdw->instance;
1239 cdns->msg_count = 0;
1240
1241 bus->link_id = pdev->id;
1242
1243 sdw_cdns_probe(cdns);
1244
1245 /* Set property read ops */
1246 sdw_intel_ops.read_prop = intel_prop_read;
1247 bus->ops = &sdw_intel_ops;
1248
1249 /* set driver data, accessed by snd_soc_dai_get_drvdata() */
1250 dev_set_drvdata(dev, cdns);
1251
1252 ret = sdw_bus_master_add(bus, dev, dev->fwnode);
1253 if (ret) {
1254 dev_err(dev, "sdw_bus_master_add fail: %d\n", ret);
1255 return ret;
1256 }
1257
1258 if (bus->prop.hw_disabled)
1259 dev_info(dev,
1260 "SoundWire master %d is disabled, will be ignored\n",
1261 bus->link_id);
1262
1263 return 0;
1264}
1265
1266int intel_master_startup(struct platform_device *pdev)
1267{
1268 struct sdw_cdns_stream_config config;
1269 struct device *dev = &pdev->dev;
1270 struct sdw_cdns *cdns = dev_get_drvdata(dev);
1271 struct sdw_intel *sdw = cdns_to_intel(cdns);
1272 struct sdw_bus *bus = &cdns->bus;
1273 int ret;
1274
1275 if (bus->prop.hw_disabled) {
1276 dev_info(dev,
1277 "SoundWire master %d is disabled, ignoring\n",
1278 sdw->instance);
1279 return 0;
1280 }
1281
1282 /* Initialize shim, controller and Cadence IP */
1283 ret = intel_init(sdw);
1284 if (ret)
1285 goto err_init;
1286
1287 /* Read the PDI config and initialize cadence PDI */
1288 intel_pdi_init(sdw, &config);
1289 ret = sdw_cdns_pdi_init(cdns, config);
1290 if (ret)
1291 goto err_init;
1292
1293 intel_pdi_ch_update(sdw);
1294
1295 ret = sdw_cdns_enable_interrupt(cdns, true);
1296 if (ret < 0) {
1297 dev_err(dev, "cannot enable interrupts\n");
1298 goto err_init;
1299 }
1300
1301 ret = sdw_cdns_exit_reset(cdns);
1302 if (ret < 0) {
1303 dev_err(dev, "unable to exit bus reset sequence\n");
1304 goto err_interrupt;
1305 }
1306
1307 /* Register DAIs */
1308 ret = intel_register_dai(sdw);
1309 if (ret) {
1310 dev_err(dev, "DAI registration failed: %d\n", ret);
1311 snd_soc_unregister_component(dev);
1312 goto err_interrupt;
1313 }
1314
1315 intel_debugfs_init(sdw);
1316
1317 return 0;
1318
1319err_interrupt:
1320 sdw_cdns_enable_interrupt(cdns, false);
1321err_init:
1322 return ret;
1323}
1324
1325static int intel_master_remove(struct platform_device *pdev)
1326{
1327 struct device *dev = &pdev->dev;
1328 struct sdw_cdns *cdns = dev_get_drvdata(dev);
1329 struct sdw_intel *sdw = cdns_to_intel(cdns);
1330 struct sdw_bus *bus = &cdns->bus;
1331
1332 if (!bus->prop.hw_disabled) {
1333 intel_debugfs_exit(sdw);
1334 sdw_cdns_enable_interrupt(cdns, false);
1335 snd_soc_unregister_component(dev);
1336 }
1337 sdw_bus_master_delete(bus);
1338
1339 return 0;
1340}
1341
1342int intel_master_process_wakeen_event(struct platform_device *pdev)
1343{
1344 struct device *dev = &pdev->dev;
1345 struct sdw_intel *sdw;
1346 struct sdw_bus *bus;
1347 void __iomem *shim;
1348 u16 wake_sts;
1349
1350 sdw = platform_get_drvdata(pdev);
1351 bus = &sdw->cdns.bus;
1352
1353 if (bus->prop.hw_disabled) {
1354 dev_dbg(dev, "SoundWire master %d is disabled, ignoring\n", bus->link_id);
1355 return 0;
1356 }
1357
1358 shim = sdw->link_res->shim;
1359 wake_sts = intel_readw(shim, SDW_SHIM_WAKESTS);
1360
1361 if (!(wake_sts & BIT(sdw->instance)))
1362 return 0;
1363
1364 /* disable WAKEEN interrupt ASAP to prevent interrupt flood */
1365 intel_shim_wake(sdw, false);
1366
1367 /*
1368 * resume the Master, which will generate a bus reset and result in
1369 * Slaves re-attaching and be re-enumerated. The SoundWire physical
1370 * device which generated the wake will trigger an interrupt, which
1371 * will in turn cause the corresponding Linux Slave device to be
1372 * resumed and the Slave codec driver to check the status.
1373 */
1374 pm_request_resume(dev);
1375
1376 return 0;
1377}
1378
1379static struct platform_driver sdw_intel_drv = {
1380 .probe = intel_master_probe,
1381 .remove = intel_master_remove,
1382 .driver = {
1383 .name = "intel-sdw",
1384 },
1385};
1386
1387module_platform_driver(sdw_intel_drv);
1388
1389MODULE_LICENSE("Dual BSD/GPL");
1390MODULE_ALIAS("platform:intel-sdw");
1391MODULE_DESCRIPTION("Intel Soundwire Master Driver");
1// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2// Copyright(c) 2015-17 Intel Corporation.
3
4/*
5 * Soundwire Intel Master Driver
6 */
7
8#include <linux/acpi.h>
9#include <linux/debugfs.h>
10#include <linux/delay.h>
11#include <linux/io.h>
12#include <sound/pcm_params.h>
13#include <linux/pm_runtime.h>
14#include <sound/soc.h>
15#include <linux/soundwire/sdw_registers.h>
16#include <linux/soundwire/sdw.h>
17#include <linux/soundwire/sdw_intel.h>
18#include "cadence_master.h"
19#include "bus.h"
20#include "intel.h"
21
22static int intel_wait_bit(void __iomem *base, int offset, u32 mask, u32 target)
23{
24 int timeout = 10;
25 u32 reg_read;
26
27 do {
28 reg_read = readl(base + offset);
29 if ((reg_read & mask) == target)
30 return 0;
31
32 timeout--;
33 usleep_range(50, 100);
34 } while (timeout != 0);
35
36 return -EAGAIN;
37}
38
39static int intel_clear_bit(void __iomem *base, int offset, u32 value, u32 mask)
40{
41 writel(value, base + offset);
42 return intel_wait_bit(base, offset, mask, 0);
43}
44
45static int intel_set_bit(void __iomem *base, int offset, u32 value, u32 mask)
46{
47 writel(value, base + offset);
48 return intel_wait_bit(base, offset, mask, mask);
49}
50
51/*
52 * debugfs
53 */
54#ifdef CONFIG_DEBUG_FS
55
56#define RD_BUF (2 * PAGE_SIZE)
57
58static ssize_t intel_sprintf(void __iomem *mem, bool l,
59 char *buf, size_t pos, unsigned int reg)
60{
61 int value;
62
63 if (l)
64 value = intel_readl(mem, reg);
65 else
66 value = intel_readw(mem, reg);
67
68 return scnprintf(buf + pos, RD_BUF - pos, "%4x\t%4x\n", reg, value);
69}
70
71static int intel_reg_show(struct seq_file *s_file, void *data)
72{
73 struct sdw_intel *sdw = s_file->private;
74 void __iomem *s = sdw->link_res->shim;
75 void __iomem *a = sdw->link_res->alh;
76 char *buf;
77 ssize_t ret;
78 int i, j;
79 unsigned int links, reg;
80
81 buf = kzalloc(RD_BUF, GFP_KERNEL);
82 if (!buf)
83 return -ENOMEM;
84
85 links = intel_readl(s, SDW_SHIM_LCAP) & SDW_SHIM_LCAP_LCOUNT_MASK;
86
87 ret = scnprintf(buf, RD_BUF, "Register Value\n");
88 ret += scnprintf(buf + ret, RD_BUF - ret, "\nShim\n");
89
90 for (i = 0; i < links; i++) {
91 reg = SDW_SHIM_LCAP + i * 4;
92 ret += intel_sprintf(s, true, buf, ret, reg);
93 }
94
95 for (i = 0; i < links; i++) {
96 ret += scnprintf(buf + ret, RD_BUF - ret, "\nLink%d\n", i);
97 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLSCAP(i));
98 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS0CM(i));
99 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS1CM(i));
100 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS2CM(i));
101 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS3CM(i));
102 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PCMSCAP(i));
103
104 ret += scnprintf(buf + ret, RD_BUF - ret, "\n PCMSyCH registers\n");
105
106 /*
107 * the value 10 is the number of PDIs. We will need a
108 * cleanup to remove hard-coded Intel configurations
109 * from cadence_master.c
110 */
111 for (j = 0; j < 10; j++) {
112 ret += intel_sprintf(s, false, buf, ret,
113 SDW_SHIM_PCMSYCHM(i, j));
114 ret += intel_sprintf(s, false, buf, ret,
115 SDW_SHIM_PCMSYCHC(i, j));
116 }
117 ret += scnprintf(buf + ret, RD_BUF - ret, "\n IOCTL, CTMCTL\n");
118
119 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_IOCTL(i));
120 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTMCTL(i));
121 }
122
123 ret += scnprintf(buf + ret, RD_BUF - ret, "\nWake registers\n");
124 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKEEN);
125 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKESTS);
126
127 ret += scnprintf(buf + ret, RD_BUF - ret, "\nALH STRMzCFG\n");
128 for (i = 0; i < SDW_ALH_NUM_STREAMS; i++)
129 ret += intel_sprintf(a, true, buf, ret, SDW_ALH_STRMZCFG(i));
130
131 seq_printf(s_file, "%s", buf);
132 kfree(buf);
133
134 return 0;
135}
136DEFINE_SHOW_ATTRIBUTE(intel_reg);
137
138static int intel_set_m_datamode(void *data, u64 value)
139{
140 struct sdw_intel *sdw = data;
141 struct sdw_bus *bus = &sdw->cdns.bus;
142
143 if (value > SDW_PORT_DATA_MODE_STATIC_1)
144 return -EINVAL;
145
146 /* Userspace changed the hardware state behind the kernel's back */
147 add_taint(TAINT_USER, LOCKDEP_STILL_OK);
148
149 bus->params.m_data_mode = value;
150
151 return 0;
152}
153DEFINE_DEBUGFS_ATTRIBUTE(intel_set_m_datamode_fops, NULL,
154 intel_set_m_datamode, "%llu\n");
155
156static int intel_set_s_datamode(void *data, u64 value)
157{
158 struct sdw_intel *sdw = data;
159 struct sdw_bus *bus = &sdw->cdns.bus;
160
161 if (value > SDW_PORT_DATA_MODE_STATIC_1)
162 return -EINVAL;
163
164 /* Userspace changed the hardware state behind the kernel's back */
165 add_taint(TAINT_USER, LOCKDEP_STILL_OK);
166
167 bus->params.s_data_mode = value;
168
169 return 0;
170}
171DEFINE_DEBUGFS_ATTRIBUTE(intel_set_s_datamode_fops, NULL,
172 intel_set_s_datamode, "%llu\n");
173
174static void intel_debugfs_init(struct sdw_intel *sdw)
175{
176 struct dentry *root = sdw->cdns.bus.debugfs;
177
178 if (!root)
179 return;
180
181 sdw->debugfs = debugfs_create_dir("intel-sdw", root);
182
183 debugfs_create_file("intel-registers", 0400, sdw->debugfs, sdw,
184 &intel_reg_fops);
185
186 debugfs_create_file("intel-m-datamode", 0200, sdw->debugfs, sdw,
187 &intel_set_m_datamode_fops);
188
189 debugfs_create_file("intel-s-datamode", 0200, sdw->debugfs, sdw,
190 &intel_set_s_datamode_fops);
191
192 sdw_cdns_debugfs_init(&sdw->cdns, sdw->debugfs);
193}
194
195static void intel_debugfs_exit(struct sdw_intel *sdw)
196{
197 debugfs_remove_recursive(sdw->debugfs);
198}
199#else
200static void intel_debugfs_init(struct sdw_intel *sdw) {}
201static void intel_debugfs_exit(struct sdw_intel *sdw) {}
202#endif /* CONFIG_DEBUG_FS */
203
204/*
205 * shim ops
206 */
207/* this needs to be called with shim_lock */
208static void intel_shim_glue_to_master_ip(struct sdw_intel *sdw)
209{
210 void __iomem *shim = sdw->link_res->shim;
211 unsigned int link_id = sdw->instance;
212 u16 ioctl;
213
214 /* Switch to MIP from Glue logic */
215 ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id));
216
217 ioctl &= ~(SDW_SHIM_IOCTL_DOE);
218 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
219 usleep_range(10, 15);
220
221 ioctl &= ~(SDW_SHIM_IOCTL_DO);
222 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
223 usleep_range(10, 15);
224
225 ioctl |= (SDW_SHIM_IOCTL_MIF);
226 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
227 usleep_range(10, 15);
228
229 ioctl &= ~(SDW_SHIM_IOCTL_BKE);
230 ioctl &= ~(SDW_SHIM_IOCTL_COE);
231 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
232 usleep_range(10, 15);
233
234 /* at this point Master IP has full control of the I/Os */
235}
236
237/* this needs to be called with shim_lock */
238static void intel_shim_master_ip_to_glue(struct sdw_intel *sdw)
239{
240 unsigned int link_id = sdw->instance;
241 void __iomem *shim = sdw->link_res->shim;
242 u16 ioctl;
243
244 /* Glue logic */
245 ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id));
246 ioctl |= SDW_SHIM_IOCTL_BKE;
247 ioctl |= SDW_SHIM_IOCTL_COE;
248 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
249 usleep_range(10, 15);
250
251 ioctl &= ~(SDW_SHIM_IOCTL_MIF);
252 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
253 usleep_range(10, 15);
254
255 /* at this point Integration Glue has full control of the I/Os */
256}
257
258/* this needs to be called with shim_lock */
259static void intel_shim_init(struct sdw_intel *sdw)
260{
261 void __iomem *shim = sdw->link_res->shim;
262 unsigned int link_id = sdw->instance;
263 u16 ioctl = 0, act;
264
265 /* Initialize Shim */
266 ioctl |= SDW_SHIM_IOCTL_BKE;
267 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
268 usleep_range(10, 15);
269
270 ioctl |= SDW_SHIM_IOCTL_WPDD;
271 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
272 usleep_range(10, 15);
273
274 ioctl |= SDW_SHIM_IOCTL_DO;
275 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
276 usleep_range(10, 15);
277
278 ioctl |= SDW_SHIM_IOCTL_DOE;
279 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
280 usleep_range(10, 15);
281
282 intel_shim_glue_to_master_ip(sdw);
283
284 act = intel_readw(shim, SDW_SHIM_CTMCTL(link_id));
285 u16p_replace_bits(&act, 0x1, SDW_SHIM_CTMCTL_DOAIS);
286 act |= SDW_SHIM_CTMCTL_DACTQE;
287 act |= SDW_SHIM_CTMCTL_DODS;
288 intel_writew(shim, SDW_SHIM_CTMCTL(link_id), act);
289 usleep_range(10, 15);
290}
291
292static int intel_shim_check_wake(struct sdw_intel *sdw)
293{
294 void __iomem *shim;
295 u16 wake_sts;
296
297 shim = sdw->link_res->shim;
298 wake_sts = intel_readw(shim, SDW_SHIM_WAKESTS);
299
300 return wake_sts & BIT(sdw->instance);
301}
302
303static void intel_shim_wake(struct sdw_intel *sdw, bool wake_enable)
304{
305 void __iomem *shim = sdw->link_res->shim;
306 unsigned int link_id = sdw->instance;
307 u16 wake_en, wake_sts;
308
309 mutex_lock(sdw->link_res->shim_lock);
310 wake_en = intel_readw(shim, SDW_SHIM_WAKEEN);
311
312 if (wake_enable) {
313 /* Enable the wakeup */
314 wake_en |= (SDW_SHIM_WAKEEN_ENABLE << link_id);
315 intel_writew(shim, SDW_SHIM_WAKEEN, wake_en);
316 } else {
317 /* Disable the wake up interrupt */
318 wake_en &= ~(SDW_SHIM_WAKEEN_ENABLE << link_id);
319 intel_writew(shim, SDW_SHIM_WAKEEN, wake_en);
320
321 /* Clear wake status */
322 wake_sts = intel_readw(shim, SDW_SHIM_WAKESTS);
323 wake_sts |= (SDW_SHIM_WAKESTS_STATUS << link_id);
324 intel_writew(shim, SDW_SHIM_WAKESTS, wake_sts);
325 }
326 mutex_unlock(sdw->link_res->shim_lock);
327}
328
329static bool intel_check_cmdsync_unlocked(struct sdw_intel *sdw)
330{
331 void __iomem *shim = sdw->link_res->shim;
332 int sync_reg;
333
334 sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
335 return !!(sync_reg & SDW_SHIM_SYNC_CMDSYNC_MASK);
336}
337
338static int intel_link_power_up(struct sdw_intel *sdw)
339{
340 unsigned int link_id = sdw->instance;
341 void __iomem *shim = sdw->link_res->shim;
342 u32 *shim_mask = sdw->link_res->shim_mask;
343 struct sdw_bus *bus = &sdw->cdns.bus;
344 struct sdw_master_prop *prop = &bus->prop;
345 u32 spa_mask, cpa_mask;
346 u32 link_control;
347 int ret = 0;
348 u32 syncprd;
349 u32 sync_reg;
350
351 mutex_lock(sdw->link_res->shim_lock);
352
353 /*
354 * The hardware relies on an internal counter, typically 4kHz,
355 * to generate the SoundWire SSP - which defines a 'safe'
356 * synchronization point between commands and audio transport
357 * and allows for multi link synchronization. The SYNCPRD value
358 * is only dependent on the oscillator clock provided to
359 * the IP, so adjust based on _DSD properties reported in DSDT
360 * tables. The values reported are based on either 24MHz
361 * (CNL/CML) or 38.4 MHz (ICL/TGL+).
362 */
363 if (prop->mclk_freq % 6000000)
364 syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_38_4;
365 else
366 syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_24;
367
368 if (!*shim_mask) {
369 dev_dbg(sdw->cdns.dev, "powering up all links\n");
370
371 /* we first need to program the SyncPRD/CPU registers */
372 dev_dbg(sdw->cdns.dev,
373 "first link up, programming SYNCPRD\n");
374
375 /* set SyncPRD period */
376 sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
377 u32p_replace_bits(&sync_reg, syncprd, SDW_SHIM_SYNC_SYNCPRD);
378
379 /* Set SyncCPU bit */
380 sync_reg |= SDW_SHIM_SYNC_SYNCCPU;
381 intel_writel(shim, SDW_SHIM_SYNC, sync_reg);
382
383 /* Link power up sequence */
384 link_control = intel_readl(shim, SDW_SHIM_LCTL);
385
386 /* only power-up enabled links */
387 spa_mask = FIELD_PREP(SDW_SHIM_LCTL_SPA_MASK, sdw->link_res->link_mask);
388 cpa_mask = FIELD_PREP(SDW_SHIM_LCTL_CPA_MASK, sdw->link_res->link_mask);
389
390 link_control |= spa_mask;
391
392 ret = intel_set_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask);
393 if (ret < 0) {
394 dev_err(sdw->cdns.dev, "Failed to power up link: %d\n", ret);
395 goto out;
396 }
397
398 /* SyncCPU will change once link is active */
399 ret = intel_wait_bit(shim, SDW_SHIM_SYNC,
400 SDW_SHIM_SYNC_SYNCCPU, 0);
401 if (ret < 0) {
402 dev_err(sdw->cdns.dev,
403 "Failed to set SHIM_SYNC: %d\n", ret);
404 goto out;
405 }
406 }
407
408 *shim_mask |= BIT(link_id);
409
410 sdw->cdns.link_up = true;
411
412 intel_shim_init(sdw);
413
414out:
415 mutex_unlock(sdw->link_res->shim_lock);
416
417 return ret;
418}
419
420static int intel_link_power_down(struct sdw_intel *sdw)
421{
422 u32 link_control, spa_mask, cpa_mask;
423 unsigned int link_id = sdw->instance;
424 void __iomem *shim = sdw->link_res->shim;
425 u32 *shim_mask = sdw->link_res->shim_mask;
426 int ret = 0;
427
428 mutex_lock(sdw->link_res->shim_lock);
429
430 if (!(*shim_mask & BIT(link_id)))
431 dev_err(sdw->cdns.dev,
432 "%s: Unbalanced power-up/down calls\n", __func__);
433
434 sdw->cdns.link_up = false;
435
436 intel_shim_master_ip_to_glue(sdw);
437
438 *shim_mask &= ~BIT(link_id);
439
440 if (!*shim_mask) {
441
442 dev_dbg(sdw->cdns.dev, "powering down all links\n");
443
444 /* Link power down sequence */
445 link_control = intel_readl(shim, SDW_SHIM_LCTL);
446
447 /* only power-down enabled links */
448 spa_mask = FIELD_PREP(SDW_SHIM_LCTL_SPA_MASK, ~sdw->link_res->link_mask);
449 cpa_mask = FIELD_PREP(SDW_SHIM_LCTL_CPA_MASK, sdw->link_res->link_mask);
450
451 link_control &= spa_mask;
452
453 ret = intel_clear_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask);
454 if (ret < 0) {
455 dev_err(sdw->cdns.dev, "%s: could not power down link\n", __func__);
456
457 /*
458 * we leave the sdw->cdns.link_up flag as false since we've disabled
459 * the link at this point and cannot handle interrupts any longer.
460 */
461 }
462 }
463
464 mutex_unlock(sdw->link_res->shim_lock);
465
466 return ret;
467}
468
469static void intel_shim_sync_arm(struct sdw_intel *sdw)
470{
471 void __iomem *shim = sdw->link_res->shim;
472 u32 sync_reg;
473
474 mutex_lock(sdw->link_res->shim_lock);
475
476 /* update SYNC register */
477 sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
478 sync_reg |= (SDW_SHIM_SYNC_CMDSYNC << sdw->instance);
479 intel_writel(shim, SDW_SHIM_SYNC, sync_reg);
480
481 mutex_unlock(sdw->link_res->shim_lock);
482}
483
484static int intel_shim_sync_go_unlocked(struct sdw_intel *sdw)
485{
486 void __iomem *shim = sdw->link_res->shim;
487 u32 sync_reg;
488
489 /* Read SYNC register */
490 sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
491
492 /*
493 * Set SyncGO bit to synchronously trigger a bank switch for
494 * all the masters. A write to SYNCGO bit clears CMDSYNC bit for all
495 * the Masters.
496 */
497 sync_reg |= SDW_SHIM_SYNC_SYNCGO;
498
499 intel_writel(shim, SDW_SHIM_SYNC, sync_reg);
500
501 return 0;
502}
503
504static int intel_shim_sync_go(struct sdw_intel *sdw)
505{
506 int ret;
507
508 mutex_lock(sdw->link_res->shim_lock);
509
510 ret = intel_shim_sync_go_unlocked(sdw);
511
512 mutex_unlock(sdw->link_res->shim_lock);
513
514 return ret;
515}
516
517/*
518 * PDI routines
519 */
520static void intel_pdi_init(struct sdw_intel *sdw,
521 struct sdw_cdns_stream_config *config)
522{
523 void __iomem *shim = sdw->link_res->shim;
524 unsigned int link_id = sdw->instance;
525 int pcm_cap;
526
527 /* PCM Stream Capability */
528 pcm_cap = intel_readw(shim, SDW_SHIM_PCMSCAP(link_id));
529
530 config->pcm_bd = FIELD_GET(SDW_SHIM_PCMSCAP_BSS, pcm_cap);
531 config->pcm_in = FIELD_GET(SDW_SHIM_PCMSCAP_ISS, pcm_cap);
532 config->pcm_out = FIELD_GET(SDW_SHIM_PCMSCAP_OSS, pcm_cap);
533
534 dev_dbg(sdw->cdns.dev, "PCM cap bd:%d in:%d out:%d\n",
535 config->pcm_bd, config->pcm_in, config->pcm_out);
536}
537
538static int
539intel_pdi_get_ch_cap(struct sdw_intel *sdw, unsigned int pdi_num)
540{
541 void __iomem *shim = sdw->link_res->shim;
542 unsigned int link_id = sdw->instance;
543 int count;
544
545 count = intel_readw(shim, SDW_SHIM_PCMSYCHC(link_id, pdi_num));
546
547 /*
548 * WORKAROUND: on all existing Intel controllers, pdi
549 * number 2 reports channel count as 1 even though it
550 * supports 8 channels. Performing hardcoding for pdi
551 * number 2.
552 */
553 if (pdi_num == 2)
554 count = 7;
555
556 /* zero based values for channel count in register */
557 count++;
558
559 return count;
560}
561
562static int intel_pdi_get_ch_update(struct sdw_intel *sdw,
563 struct sdw_cdns_pdi *pdi,
564 unsigned int num_pdi,
565 unsigned int *num_ch)
566{
567 int i, ch_count = 0;
568
569 for (i = 0; i < num_pdi; i++) {
570 pdi->ch_count = intel_pdi_get_ch_cap(sdw, pdi->num);
571 ch_count += pdi->ch_count;
572 pdi++;
573 }
574
575 *num_ch = ch_count;
576 return 0;
577}
578
579static int intel_pdi_stream_ch_update(struct sdw_intel *sdw,
580 struct sdw_cdns_streams *stream)
581{
582 intel_pdi_get_ch_update(sdw, stream->bd, stream->num_bd,
583 &stream->num_ch_bd);
584
585 intel_pdi_get_ch_update(sdw, stream->in, stream->num_in,
586 &stream->num_ch_in);
587
588 intel_pdi_get_ch_update(sdw, stream->out, stream->num_out,
589 &stream->num_ch_out);
590
591 return 0;
592}
593
594static void
595intel_pdi_shim_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
596{
597 void __iomem *shim = sdw->link_res->shim;
598 unsigned int link_id = sdw->instance;
599 int pdi_conf = 0;
600
601 /* the Bulk and PCM streams are not contiguous */
602 pdi->intel_alh_id = (link_id * 16) + pdi->num + 3;
603 if (pdi->num >= 2)
604 pdi->intel_alh_id += 2;
605
606 /*
607 * Program stream parameters to stream SHIM register
608 * This is applicable for PCM stream only.
609 */
610 if (pdi->type != SDW_STREAM_PCM)
611 return;
612
613 if (pdi->dir == SDW_DATA_DIR_RX)
614 pdi_conf |= SDW_SHIM_PCMSYCM_DIR;
615 else
616 pdi_conf &= ~(SDW_SHIM_PCMSYCM_DIR);
617
618 u32p_replace_bits(&pdi_conf, pdi->intel_alh_id, SDW_SHIM_PCMSYCM_STREAM);
619 u32p_replace_bits(&pdi_conf, pdi->l_ch_num, SDW_SHIM_PCMSYCM_LCHN);
620 u32p_replace_bits(&pdi_conf, pdi->h_ch_num, SDW_SHIM_PCMSYCM_HCHN);
621
622 intel_writew(shim, SDW_SHIM_PCMSYCHM(link_id, pdi->num), pdi_conf);
623}
624
625static void
626intel_pdi_alh_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
627{
628 void __iomem *alh = sdw->link_res->alh;
629 unsigned int link_id = sdw->instance;
630 unsigned int conf;
631
632 /* the Bulk and PCM streams are not contiguous */
633 pdi->intel_alh_id = (link_id * 16) + pdi->num + 3;
634 if (pdi->num >= 2)
635 pdi->intel_alh_id += 2;
636
637 /* Program Stream config ALH register */
638 conf = intel_readl(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id));
639
640 u32p_replace_bits(&conf, SDW_ALH_STRMZCFG_DMAT_VAL, SDW_ALH_STRMZCFG_DMAT);
641 u32p_replace_bits(&conf, pdi->ch_count - 1, SDW_ALH_STRMZCFG_CHN);
642
643 intel_writel(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id), conf);
644}
645
646static int intel_params_stream(struct sdw_intel *sdw,
647 struct snd_pcm_substream *substream,
648 struct snd_soc_dai *dai,
649 struct snd_pcm_hw_params *hw_params,
650 int link_id, int alh_stream_id)
651{
652 struct sdw_intel_link_res *res = sdw->link_res;
653 struct sdw_intel_stream_params_data params_data;
654
655 params_data.substream = substream;
656 params_data.dai = dai;
657 params_data.hw_params = hw_params;
658 params_data.link_id = link_id;
659 params_data.alh_stream_id = alh_stream_id;
660
661 if (res->ops && res->ops->params_stream && res->dev)
662 return res->ops->params_stream(res->dev,
663 ¶ms_data);
664 return -EIO;
665}
666
667/*
668 * DAI routines
669 */
670
671static int intel_hw_params(struct snd_pcm_substream *substream,
672 struct snd_pcm_hw_params *params,
673 struct snd_soc_dai *dai)
674{
675 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
676 struct sdw_intel *sdw = cdns_to_intel(cdns);
677 struct sdw_cdns_dai_runtime *dai_runtime;
678 struct sdw_cdns_pdi *pdi;
679 struct sdw_stream_config sconfig;
680 struct sdw_port_config *pconfig;
681 int ch, dir;
682 int ret;
683
684 dai_runtime = cdns->dai_runtime_array[dai->id];
685 if (!dai_runtime)
686 return -EIO;
687
688 ch = params_channels(params);
689 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
690 dir = SDW_DATA_DIR_RX;
691 else
692 dir = SDW_DATA_DIR_TX;
693
694 pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pcm, ch, dir, dai->id);
695
696 if (!pdi) {
697 ret = -EINVAL;
698 goto error;
699 }
700
701 /* do run-time configurations for SHIM, ALH and PDI/PORT */
702 intel_pdi_shim_configure(sdw, pdi);
703 intel_pdi_alh_configure(sdw, pdi);
704 sdw_cdns_config_stream(cdns, ch, dir, pdi);
705
706 /* store pdi and hw_params, may be needed in prepare step */
707 dai_runtime->paused = false;
708 dai_runtime->suspended = false;
709 dai_runtime->pdi = pdi;
710
711 /* Inform DSP about PDI stream number */
712 ret = intel_params_stream(sdw, substream, dai, params,
713 sdw->instance,
714 pdi->intel_alh_id);
715 if (ret)
716 goto error;
717
718 sconfig.direction = dir;
719 sconfig.ch_count = ch;
720 sconfig.frame_rate = params_rate(params);
721 sconfig.type = dai_runtime->stream_type;
722
723 sconfig.bps = snd_pcm_format_width(params_format(params));
724
725 /* Port configuration */
726 pconfig = kzalloc(sizeof(*pconfig), GFP_KERNEL);
727 if (!pconfig) {
728 ret = -ENOMEM;
729 goto error;
730 }
731
732 pconfig->num = pdi->num;
733 pconfig->ch_mask = (1 << ch) - 1;
734
735 ret = sdw_stream_add_master(&cdns->bus, &sconfig,
736 pconfig, 1, dai_runtime->stream);
737 if (ret)
738 dev_err(cdns->dev, "add master to stream failed:%d\n", ret);
739
740 kfree(pconfig);
741error:
742 return ret;
743}
744
745static int intel_prepare(struct snd_pcm_substream *substream,
746 struct snd_soc_dai *dai)
747{
748 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
749 struct sdw_intel *sdw = cdns_to_intel(cdns);
750 struct sdw_cdns_dai_runtime *dai_runtime;
751 int ch, dir;
752 int ret = 0;
753
754 dai_runtime = cdns->dai_runtime_array[dai->id];
755 if (!dai_runtime) {
756 dev_err(dai->dev, "failed to get dai runtime in %s\n",
757 __func__);
758 return -EIO;
759 }
760
761 if (dai_runtime->suspended) {
762 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
763 struct snd_pcm_hw_params *hw_params;
764
765 hw_params = &rtd->dpcm[substream->stream].hw_params;
766
767 dai_runtime->suspended = false;
768
769 /*
770 * .prepare() is called after system resume, where we
771 * need to reinitialize the SHIM/ALH/Cadence IP.
772 * .prepare() is also called to deal with underflows,
773 * but in those cases we cannot touch ALH/SHIM
774 * registers
775 */
776
777 /* configure stream */
778 ch = params_channels(hw_params);
779 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
780 dir = SDW_DATA_DIR_RX;
781 else
782 dir = SDW_DATA_DIR_TX;
783
784 intel_pdi_shim_configure(sdw, dai_runtime->pdi);
785 intel_pdi_alh_configure(sdw, dai_runtime->pdi);
786 sdw_cdns_config_stream(cdns, ch, dir, dai_runtime->pdi);
787
788 /* Inform DSP about PDI stream number */
789 ret = intel_params_stream(sdw, substream, dai,
790 hw_params,
791 sdw->instance,
792 dai_runtime->pdi->intel_alh_id);
793 }
794
795 return ret;
796}
797
798static int
799intel_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
800{
801 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
802 struct sdw_cdns_dai_runtime *dai_runtime;
803 int ret;
804
805 dai_runtime = cdns->dai_runtime_array[dai->id];
806 if (!dai_runtime)
807 return -EIO;
808
809 /*
810 * The sdw stream state will transition to RELEASED when stream->
811 * master_list is empty. So the stream state will transition to
812 * DEPREPARED for the first cpu-dai and to RELEASED for the last
813 * cpu-dai.
814 */
815 ret = sdw_stream_remove_master(&cdns->bus, dai_runtime->stream);
816 if (ret < 0) {
817 dev_err(dai->dev, "remove master from stream %s failed: %d\n",
818 dai_runtime->stream->name, ret);
819 return ret;
820 }
821
822 dai_runtime->pdi = NULL;
823
824 return 0;
825}
826
827static int intel_pcm_set_sdw_stream(struct snd_soc_dai *dai,
828 void *stream, int direction)
829{
830 return cdns_set_sdw_stream(dai, stream, direction);
831}
832
833static void *intel_get_sdw_stream(struct snd_soc_dai *dai,
834 int direction)
835{
836 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
837 struct sdw_cdns_dai_runtime *dai_runtime;
838
839 dai_runtime = cdns->dai_runtime_array[dai->id];
840 if (!dai_runtime)
841 return ERR_PTR(-EINVAL);
842
843 return dai_runtime->stream;
844}
845
846static int intel_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai)
847{
848 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
849 struct sdw_cdns_dai_runtime *dai_runtime;
850 int ret = 0;
851
852 dai_runtime = cdns->dai_runtime_array[dai->id];
853 if (!dai_runtime) {
854 dev_err(dai->dev, "failed to get dai runtime in %s\n",
855 __func__);
856 return -EIO;
857 }
858
859 switch (cmd) {
860 case SNDRV_PCM_TRIGGER_SUSPEND:
861
862 /*
863 * The .prepare callback is used to deal with xruns and resume operations.
864 * In the case of xruns, the DMAs and SHIM registers cannot be touched,
865 * but for resume operations the DMAs and SHIM registers need to be initialized.
866 * the .trigger callback is used to track the suspend case only.
867 */
868
869 dai_runtime->suspended = true;
870
871 break;
872
873 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
874 dai_runtime->paused = true;
875 break;
876 case SNDRV_PCM_TRIGGER_STOP:
877 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
878 dai_runtime->paused = false;
879 break;
880 default:
881 break;
882 }
883
884 return ret;
885}
886
887static int intel_component_probe(struct snd_soc_component *component)
888{
889 int ret;
890
891 /*
892 * make sure the device is pm_runtime_active before initiating
893 * bus transactions during the card registration.
894 * We use pm_runtime_resume() here, without taking a reference
895 * and releasing it immediately.
896 */
897 ret = pm_runtime_resume(component->dev);
898 if (ret < 0 && ret != -EACCES)
899 return ret;
900
901 return 0;
902}
903
904static int intel_component_dais_suspend(struct snd_soc_component *component)
905{
906 struct snd_soc_dai *dai;
907
908 /*
909 * In the corner case where a SUSPEND happens during a PAUSE, the ALSA core
910 * does not throw the TRIGGER_SUSPEND. This leaves the DAIs in an unbalanced state.
911 * Since the component suspend is called last, we can trap this corner case
912 * and force the DAIs to release their resources.
913 */
914 for_each_component_dais(component, dai) {
915 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
916 struct sdw_cdns_dai_runtime *dai_runtime;
917
918 dai_runtime = cdns->dai_runtime_array[dai->id];
919
920 if (!dai_runtime)
921 continue;
922
923 if (dai_runtime->suspended)
924 continue;
925
926 if (dai_runtime->paused)
927 dai_runtime->suspended = true;
928 }
929
930 return 0;
931}
932
933static const struct snd_soc_dai_ops intel_pcm_dai_ops = {
934 .hw_params = intel_hw_params,
935 .prepare = intel_prepare,
936 .hw_free = intel_hw_free,
937 .trigger = intel_trigger,
938 .set_stream = intel_pcm_set_sdw_stream,
939 .get_stream = intel_get_sdw_stream,
940};
941
942static const struct snd_soc_component_driver dai_component = {
943 .name = "soundwire",
944 .probe = intel_component_probe,
945 .suspend = intel_component_dais_suspend,
946 .legacy_dai_naming = 1,
947};
948
949static int intel_create_dai(struct sdw_cdns *cdns,
950 struct snd_soc_dai_driver *dais,
951 enum intel_pdi_type type,
952 u32 num, u32 off, u32 max_ch)
953{
954 int i;
955
956 if (num == 0)
957 return 0;
958
959 for (i = off; i < (off + num); i++) {
960 dais[i].name = devm_kasprintf(cdns->dev, GFP_KERNEL,
961 "SDW%d Pin%d",
962 cdns->instance, i);
963 if (!dais[i].name)
964 return -ENOMEM;
965
966 if (type == INTEL_PDI_BD || type == INTEL_PDI_OUT) {
967 dais[i].playback.channels_min = 1;
968 dais[i].playback.channels_max = max_ch;
969 }
970
971 if (type == INTEL_PDI_BD || type == INTEL_PDI_IN) {
972 dais[i].capture.channels_min = 1;
973 dais[i].capture.channels_max = max_ch;
974 }
975
976 dais[i].ops = &intel_pcm_dai_ops;
977 }
978
979 return 0;
980}
981
982static int intel_register_dai(struct sdw_intel *sdw)
983{
984 struct sdw_cdns_dai_runtime **dai_runtime_array;
985 struct sdw_cdns_stream_config config;
986 struct sdw_cdns *cdns = &sdw->cdns;
987 struct sdw_cdns_streams *stream;
988 struct snd_soc_dai_driver *dais;
989 int num_dai, ret, off = 0;
990
991 /* Read the PDI config and initialize cadence PDI */
992 intel_pdi_init(sdw, &config);
993 ret = sdw_cdns_pdi_init(cdns, config);
994 if (ret)
995 return ret;
996
997 intel_pdi_stream_ch_update(sdw, &sdw->cdns.pcm);
998
999 /* DAIs are created based on total number of PDIs supported */
1000 num_dai = cdns->pcm.num_pdi;
1001
1002 dai_runtime_array = devm_kcalloc(cdns->dev, num_dai,
1003 sizeof(struct sdw_cdns_dai_runtime *),
1004 GFP_KERNEL);
1005 if (!dai_runtime_array)
1006 return -ENOMEM;
1007 cdns->dai_runtime_array = dai_runtime_array;
1008
1009 dais = devm_kcalloc(cdns->dev, num_dai, sizeof(*dais), GFP_KERNEL);
1010 if (!dais)
1011 return -ENOMEM;
1012
1013 /* Create PCM DAIs */
1014 stream = &cdns->pcm;
1015
1016 ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pcm.num_in,
1017 off, stream->num_ch_in);
1018 if (ret)
1019 return ret;
1020
1021 off += cdns->pcm.num_in;
1022 ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pcm.num_out,
1023 off, stream->num_ch_out);
1024 if (ret)
1025 return ret;
1026
1027 off += cdns->pcm.num_out;
1028 ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pcm.num_bd,
1029 off, stream->num_ch_bd);
1030 if (ret)
1031 return ret;
1032
1033 return devm_snd_soc_register_component(cdns->dev, &dai_component,
1034 dais, num_dai);
1035}
1036
1037
1038const struct sdw_intel_hw_ops sdw_intel_cnl_hw_ops = {
1039 .debugfs_init = intel_debugfs_init,
1040 .debugfs_exit = intel_debugfs_exit,
1041
1042 .register_dai = intel_register_dai,
1043
1044 .check_clock_stop = intel_check_clock_stop,
1045 .start_bus = intel_start_bus,
1046 .start_bus_after_reset = intel_start_bus_after_reset,
1047 .start_bus_after_clock_stop = intel_start_bus_after_clock_stop,
1048 .stop_bus = intel_stop_bus,
1049
1050 .link_power_up = intel_link_power_up,
1051 .link_power_down = intel_link_power_down,
1052
1053 .shim_check_wake = intel_shim_check_wake,
1054 .shim_wake = intel_shim_wake,
1055
1056 .pre_bank_switch = intel_pre_bank_switch,
1057 .post_bank_switch = intel_post_bank_switch,
1058
1059 .sync_arm = intel_shim_sync_arm,
1060 .sync_go_unlocked = intel_shim_sync_go_unlocked,
1061 .sync_go = intel_shim_sync_go,
1062 .sync_check_cmdsync_unlocked = intel_check_cmdsync_unlocked,
1063};
1064EXPORT_SYMBOL_NS(sdw_intel_cnl_hw_ops, SOUNDWIRE_INTEL);
1065