1/* SPDX-License-Identifier: GPL-2.0-only */
  2
  3#ifndef __SOC_MEDIATEK_MT6795_PM_DOMAINS_H
  4#define __SOC_MEDIATEK_MT6795_PM_DOMAINS_H
  5
  6#include "mtk-pm-domains.h"
  7#include <dt-bindings/power/mt6795-power.h>
  8
  9/*
 10 * MT6795 power domain support
 11 */
 12
 13static const struct scpsys_domain_data scpsys_domain_data_mt6795[] = {
 14	[MT6795_POWER_DOMAIN_VDEC] = {
 15		.name = "vdec",
 16		.sta_mask = PWR_STATUS_VDEC,
 17		.ctl_offs = SPM_VDE_PWR_CON,
 18		.pwr_sta_offs = SPM_PWR_STATUS,
 19		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
 20		.sram_pdn_bits = GENMASK(11, 8),
 21		.sram_pdn_ack_bits = GENMASK(12, 12),
 22	},
 23	[MT6795_POWER_DOMAIN_VENC] = {
 24		.name = "venc",
 25		.sta_mask = PWR_STATUS_VENC,
 26		.ctl_offs = SPM_VEN_PWR_CON,
 27		.pwr_sta_offs = SPM_PWR_STATUS,
 28		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
 29		.sram_pdn_bits = GENMASK(11, 8),
 30		.sram_pdn_ack_bits = GENMASK(15, 12),
 31	},
 32	[MT6795_POWER_DOMAIN_ISP] = {
 33		.name = "isp",
 34		.sta_mask = PWR_STATUS_ISP,
 35		.ctl_offs = SPM_ISP_PWR_CON,
 36		.pwr_sta_offs = SPM_PWR_STATUS,
 37		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
 38		.sram_pdn_bits = GENMASK(11, 8),
 39		.sram_pdn_ack_bits = GENMASK(13, 12),
 40	},
 41	[MT6795_POWER_DOMAIN_MM] = {
 42		.name = "mm",
 43		.sta_mask = PWR_STATUS_DISP,
 44		.ctl_offs = SPM_DIS_PWR_CON,
 45		.pwr_sta_offs = SPM_PWR_STATUS,
 46		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
 47		.sram_pdn_bits = GENMASK(11, 8),
 48		.sram_pdn_ack_bits = GENMASK(12, 12),
 49		.bp_cfg = {
 50			BUS_PROT_INFRA_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 |
 51						     MT8173_TOP_AXI_PROT_EN_MM_M1),
 52		},
 53	},
 54	[MT6795_POWER_DOMAIN_MJC] = {
 55		.name = "mjc",
 56		.sta_mask = BIT(20),
 57		.ctl_offs = 0x298,
 58		.pwr_sta_offs = SPM_PWR_STATUS,
 59		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
 60		.sram_pdn_bits = GENMASK(11, 8),
 61		.sram_pdn_ack_bits = GENMASK(15, 12),
 62	},
 63	[MT6795_POWER_DOMAIN_AUDIO] = {
 64		.name = "audio",
 65		.sta_mask = PWR_STATUS_AUDIO,
 66		.ctl_offs = SPM_AUDIO_PWR_CON,
 67		.pwr_sta_offs = SPM_PWR_STATUS,
 68		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
 69		.sram_pdn_bits = GENMASK(11, 8),
 70		.sram_pdn_ack_bits = GENMASK(15, 12),
 71	},
 72	[MT6795_POWER_DOMAIN_MFG_ASYNC] = {
 73		.name = "mfg_async",
 74		.sta_mask = PWR_STATUS_MFG_ASYNC,
 75		.ctl_offs = SPM_MFG_ASYNC_PWR_CON,
 76		.pwr_sta_offs = SPM_PWR_STATUS,
 77		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
 78		.sram_pdn_bits = GENMASK(11, 8),
 79		.sram_pdn_ack_bits = 0,
 80	},
 81	[MT6795_POWER_DOMAIN_MFG_2D] = {
 82		.name = "mfg_2d",
 83		.sta_mask = PWR_STATUS_MFG_2D,
 84		.ctl_offs = SPM_MFG_2D_PWR_CON,
 85		.pwr_sta_offs = SPM_PWR_STATUS,
 86		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
 87		.sram_pdn_bits = GENMASK(11, 8),
 88		.sram_pdn_ack_bits = GENMASK(13, 12),
 89	},
 90	[MT6795_POWER_DOMAIN_MFG] = {
 91		.name = "mfg",
 92		.sta_mask = PWR_STATUS_MFG,
 93		.ctl_offs = SPM_MFG_PWR_CON,
 94		.pwr_sta_offs = SPM_PWR_STATUS,
 95		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
 96		.sram_pdn_bits = GENMASK(13, 8),
 97		.sram_pdn_ack_bits = GENMASK(21, 16),
 98		.bp_cfg = {
 99			BUS_PROT_INFRA_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S |
100						     MT8173_TOP_AXI_PROT_EN_MFG_M0 |
101						     MT8173_TOP_AXI_PROT_EN_MFG_M1 |
102						     MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT),
103		},
104	},
105};
106
107static const struct scpsys_soc_data mt6795_scpsys_data = {
108	.domains_data = scpsys_domain_data_mt6795,
109	.num_domains = ARRAY_SIZE(scpsys_domain_data_mt6795),
110};
111
112#endif /* __SOC_MEDIATEK_MT6795_PM_DOMAINS_H */