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1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Microsemi SoCs pinctrl driver
4 *
5 * Author: <alexandre.belloni@free-electrons.com>
6 * License: Dual MIT/GPL
7 * Copyright (c) 2017 Microsemi Corporation
8 */
9
10#include <linux/gpio/driver.h>
11#include <linux/interrupt.h>
12#include <linux/io.h>
13#include <linux/of_device.h>
14#include <linux/of_irq.h>
15#include <linux/of_platform.h>
16#include <linux/pinctrl/pinctrl.h>
17#include <linux/pinctrl/pinmux.h>
18#include <linux/pinctrl/pinconf.h>
19#include <linux/pinctrl/pinconf-generic.h>
20#include <linux/platform_device.h>
21#include <linux/regmap.h>
22#include <linux/slab.h>
23
24#include "core.h"
25#include "pinconf.h"
26#include "pinmux.h"
27
28#define ocelot_clrsetbits(addr, clear, set) \
29 writel((readl(addr) & ~(clear)) | (set), (addr))
30
31/* PINCONFIG bits (sparx5 only) */
32enum {
33 PINCONF_BIAS,
34 PINCONF_SCHMITT,
35 PINCONF_DRIVE_STRENGTH,
36};
37
38#define BIAS_PD_BIT BIT(4)
39#define BIAS_PU_BIT BIT(3)
40#define BIAS_BITS (BIAS_PD_BIT|BIAS_PU_BIT)
41#define SCHMITT_BIT BIT(2)
42#define DRIVE_BITS GENMASK(1, 0)
43
44/* GPIO standard registers */
45#define OCELOT_GPIO_OUT_SET 0x0
46#define OCELOT_GPIO_OUT_CLR 0x4
47#define OCELOT_GPIO_OUT 0x8
48#define OCELOT_GPIO_IN 0xc
49#define OCELOT_GPIO_OE 0x10
50#define OCELOT_GPIO_INTR 0x14
51#define OCELOT_GPIO_INTR_ENA 0x18
52#define OCELOT_GPIO_INTR_IDENT 0x1c
53#define OCELOT_GPIO_ALT0 0x20
54#define OCELOT_GPIO_ALT1 0x24
55#define OCELOT_GPIO_SD_MAP 0x28
56
57#define OCELOT_FUNC_PER_PIN 4
58
59enum {
60 FUNC_NONE,
61 FUNC_GPIO,
62 FUNC_IRQ0,
63 FUNC_IRQ0_IN,
64 FUNC_IRQ0_OUT,
65 FUNC_IRQ1,
66 FUNC_IRQ1_IN,
67 FUNC_IRQ1_OUT,
68 FUNC_EXT_IRQ,
69 FUNC_MIIM,
70 FUNC_PHY_LED,
71 FUNC_PCI_WAKE,
72 FUNC_MD,
73 FUNC_PTP0,
74 FUNC_PTP1,
75 FUNC_PTP2,
76 FUNC_PTP3,
77 FUNC_PWM,
78 FUNC_RECO_CLK,
79 FUNC_SFP,
80 FUNC_SG0,
81 FUNC_SG1,
82 FUNC_SG2,
83 FUNC_SI,
84 FUNC_SI2,
85 FUNC_TACHO,
86 FUNC_TWI,
87 FUNC_TWI2,
88 FUNC_TWI3,
89 FUNC_TWI_SCL_M,
90 FUNC_UART,
91 FUNC_UART2,
92 FUNC_UART3,
93 FUNC_PLL_STAT,
94 FUNC_EMMC,
95 FUNC_REF_CLK,
96 FUNC_RCVRD_CLK,
97 FUNC_MAX
98};
99
100static const char *const ocelot_function_names[] = {
101 [FUNC_NONE] = "none",
102 [FUNC_GPIO] = "gpio",
103 [FUNC_IRQ0] = "irq0",
104 [FUNC_IRQ0_IN] = "irq0_in",
105 [FUNC_IRQ0_OUT] = "irq0_out",
106 [FUNC_IRQ1] = "irq1",
107 [FUNC_IRQ1_IN] = "irq1_in",
108 [FUNC_IRQ1_OUT] = "irq1_out",
109 [FUNC_EXT_IRQ] = "ext_irq",
110 [FUNC_MIIM] = "miim",
111 [FUNC_PHY_LED] = "phy_led",
112 [FUNC_PCI_WAKE] = "pci_wake",
113 [FUNC_MD] = "md",
114 [FUNC_PTP0] = "ptp0",
115 [FUNC_PTP1] = "ptp1",
116 [FUNC_PTP2] = "ptp2",
117 [FUNC_PTP3] = "ptp3",
118 [FUNC_PWM] = "pwm",
119 [FUNC_RECO_CLK] = "reco_clk",
120 [FUNC_SFP] = "sfp",
121 [FUNC_SG0] = "sg0",
122 [FUNC_SG1] = "sg1",
123 [FUNC_SG2] = "sg2",
124 [FUNC_SI] = "si",
125 [FUNC_SI2] = "si2",
126 [FUNC_TACHO] = "tacho",
127 [FUNC_TWI] = "twi",
128 [FUNC_TWI2] = "twi2",
129 [FUNC_TWI3] = "twi3",
130 [FUNC_TWI_SCL_M] = "twi_scl_m",
131 [FUNC_UART] = "uart",
132 [FUNC_UART2] = "uart2",
133 [FUNC_UART3] = "uart3",
134 [FUNC_PLL_STAT] = "pll_stat",
135 [FUNC_EMMC] = "emmc",
136 [FUNC_REF_CLK] = "ref_clk",
137 [FUNC_RCVRD_CLK] = "rcvrd_clk",
138};
139
140struct ocelot_pmx_func {
141 const char **groups;
142 unsigned int ngroups;
143};
144
145struct ocelot_pin_caps {
146 unsigned int pin;
147 unsigned char functions[OCELOT_FUNC_PER_PIN];
148};
149
150struct ocelot_pinctrl {
151 struct device *dev;
152 struct pinctrl_dev *pctl;
153 struct gpio_chip gpio_chip;
154 struct regmap *map;
155 void __iomem *pincfg;
156 struct pinctrl_desc *desc;
157 struct ocelot_pmx_func func[FUNC_MAX];
158 u8 stride;
159};
160
161#define OCELOT_P(p, f0, f1, f2) \
162static struct ocelot_pin_caps ocelot_pin_##p = { \
163 .pin = p, \
164 .functions = { \
165 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \
166 }, \
167}
168
169OCELOT_P(0, SG0, NONE, NONE);
170OCELOT_P(1, SG0, NONE, NONE);
171OCELOT_P(2, SG0, NONE, NONE);
172OCELOT_P(3, SG0, NONE, NONE);
173OCELOT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M);
174OCELOT_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE);
175OCELOT_P(6, UART, TWI_SCL_M, NONE);
176OCELOT_P(7, UART, TWI_SCL_M, NONE);
177OCELOT_P(8, SI, TWI_SCL_M, IRQ0_OUT);
178OCELOT_P(9, SI, TWI_SCL_M, IRQ1_OUT);
179OCELOT_P(10, PTP2, TWI_SCL_M, SFP);
180OCELOT_P(11, PTP3, TWI_SCL_M, SFP);
181OCELOT_P(12, UART2, TWI_SCL_M, SFP);
182OCELOT_P(13, UART2, TWI_SCL_M, SFP);
183OCELOT_P(14, MIIM, TWI_SCL_M, SFP);
184OCELOT_P(15, MIIM, TWI_SCL_M, SFP);
185OCELOT_P(16, TWI, NONE, SI);
186OCELOT_P(17, TWI, TWI_SCL_M, SI);
187OCELOT_P(18, PTP0, TWI_SCL_M, NONE);
188OCELOT_P(19, PTP1, TWI_SCL_M, NONE);
189OCELOT_P(20, RECO_CLK, TACHO, TWI_SCL_M);
190OCELOT_P(21, RECO_CLK, PWM, TWI_SCL_M);
191
192#define OCELOT_PIN(n) { \
193 .number = n, \
194 .name = "GPIO_"#n, \
195 .drv_data = &ocelot_pin_##n \
196}
197
198static const struct pinctrl_pin_desc ocelot_pins[] = {
199 OCELOT_PIN(0),
200 OCELOT_PIN(1),
201 OCELOT_PIN(2),
202 OCELOT_PIN(3),
203 OCELOT_PIN(4),
204 OCELOT_PIN(5),
205 OCELOT_PIN(6),
206 OCELOT_PIN(7),
207 OCELOT_PIN(8),
208 OCELOT_PIN(9),
209 OCELOT_PIN(10),
210 OCELOT_PIN(11),
211 OCELOT_PIN(12),
212 OCELOT_PIN(13),
213 OCELOT_PIN(14),
214 OCELOT_PIN(15),
215 OCELOT_PIN(16),
216 OCELOT_PIN(17),
217 OCELOT_PIN(18),
218 OCELOT_PIN(19),
219 OCELOT_PIN(20),
220 OCELOT_PIN(21),
221};
222
223#define JAGUAR2_P(p, f0, f1) \
224static struct ocelot_pin_caps jaguar2_pin_##p = { \
225 .pin = p, \
226 .functions = { \
227 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE \
228 }, \
229}
230
231JAGUAR2_P(0, SG0, NONE);
232JAGUAR2_P(1, SG0, NONE);
233JAGUAR2_P(2, SG0, NONE);
234JAGUAR2_P(3, SG0, NONE);
235JAGUAR2_P(4, SG1, NONE);
236JAGUAR2_P(5, SG1, NONE);
237JAGUAR2_P(6, IRQ0_IN, IRQ0_OUT);
238JAGUAR2_P(7, IRQ1_IN, IRQ1_OUT);
239JAGUAR2_P(8, PTP0, NONE);
240JAGUAR2_P(9, PTP1, NONE);
241JAGUAR2_P(10, UART, NONE);
242JAGUAR2_P(11, UART, NONE);
243JAGUAR2_P(12, SG1, NONE);
244JAGUAR2_P(13, SG1, NONE);
245JAGUAR2_P(14, TWI, TWI_SCL_M);
246JAGUAR2_P(15, TWI, NONE);
247JAGUAR2_P(16, SI, TWI_SCL_M);
248JAGUAR2_P(17, SI, TWI_SCL_M);
249JAGUAR2_P(18, SI, TWI_SCL_M);
250JAGUAR2_P(19, PCI_WAKE, NONE);
251JAGUAR2_P(20, IRQ0_OUT, TWI_SCL_M);
252JAGUAR2_P(21, IRQ1_OUT, TWI_SCL_M);
253JAGUAR2_P(22, TACHO, NONE);
254JAGUAR2_P(23, PWM, NONE);
255JAGUAR2_P(24, UART2, NONE);
256JAGUAR2_P(25, UART2, SI);
257JAGUAR2_P(26, PTP2, SI);
258JAGUAR2_P(27, PTP3, SI);
259JAGUAR2_P(28, TWI2, SI);
260JAGUAR2_P(29, TWI2, SI);
261JAGUAR2_P(30, SG2, SI);
262JAGUAR2_P(31, SG2, SI);
263JAGUAR2_P(32, SG2, SI);
264JAGUAR2_P(33, SG2, SI);
265JAGUAR2_P(34, NONE, TWI_SCL_M);
266JAGUAR2_P(35, NONE, TWI_SCL_M);
267JAGUAR2_P(36, NONE, TWI_SCL_M);
268JAGUAR2_P(37, NONE, TWI_SCL_M);
269JAGUAR2_P(38, NONE, TWI_SCL_M);
270JAGUAR2_P(39, NONE, TWI_SCL_M);
271JAGUAR2_P(40, NONE, TWI_SCL_M);
272JAGUAR2_P(41, NONE, TWI_SCL_M);
273JAGUAR2_P(42, NONE, TWI_SCL_M);
274JAGUAR2_P(43, NONE, TWI_SCL_M);
275JAGUAR2_P(44, NONE, SFP);
276JAGUAR2_P(45, NONE, SFP);
277JAGUAR2_P(46, NONE, SFP);
278JAGUAR2_P(47, NONE, SFP);
279JAGUAR2_P(48, SFP, NONE);
280JAGUAR2_P(49, SFP, SI);
281JAGUAR2_P(50, SFP, SI);
282JAGUAR2_P(51, SFP, SI);
283JAGUAR2_P(52, SFP, NONE);
284JAGUAR2_P(53, SFP, NONE);
285JAGUAR2_P(54, SFP, NONE);
286JAGUAR2_P(55, SFP, NONE);
287JAGUAR2_P(56, MIIM, SFP);
288JAGUAR2_P(57, MIIM, SFP);
289JAGUAR2_P(58, MIIM, SFP);
290JAGUAR2_P(59, MIIM, SFP);
291JAGUAR2_P(60, NONE, NONE);
292JAGUAR2_P(61, NONE, NONE);
293JAGUAR2_P(62, NONE, NONE);
294JAGUAR2_P(63, NONE, NONE);
295
296#define JAGUAR2_PIN(n) { \
297 .number = n, \
298 .name = "GPIO_"#n, \
299 .drv_data = &jaguar2_pin_##n \
300}
301
302static const struct pinctrl_pin_desc jaguar2_pins[] = {
303 JAGUAR2_PIN(0),
304 JAGUAR2_PIN(1),
305 JAGUAR2_PIN(2),
306 JAGUAR2_PIN(3),
307 JAGUAR2_PIN(4),
308 JAGUAR2_PIN(5),
309 JAGUAR2_PIN(6),
310 JAGUAR2_PIN(7),
311 JAGUAR2_PIN(8),
312 JAGUAR2_PIN(9),
313 JAGUAR2_PIN(10),
314 JAGUAR2_PIN(11),
315 JAGUAR2_PIN(12),
316 JAGUAR2_PIN(13),
317 JAGUAR2_PIN(14),
318 JAGUAR2_PIN(15),
319 JAGUAR2_PIN(16),
320 JAGUAR2_PIN(17),
321 JAGUAR2_PIN(18),
322 JAGUAR2_PIN(19),
323 JAGUAR2_PIN(20),
324 JAGUAR2_PIN(21),
325 JAGUAR2_PIN(22),
326 JAGUAR2_PIN(23),
327 JAGUAR2_PIN(24),
328 JAGUAR2_PIN(25),
329 JAGUAR2_PIN(26),
330 JAGUAR2_PIN(27),
331 JAGUAR2_PIN(28),
332 JAGUAR2_PIN(29),
333 JAGUAR2_PIN(30),
334 JAGUAR2_PIN(31),
335 JAGUAR2_PIN(32),
336 JAGUAR2_PIN(33),
337 JAGUAR2_PIN(34),
338 JAGUAR2_PIN(35),
339 JAGUAR2_PIN(36),
340 JAGUAR2_PIN(37),
341 JAGUAR2_PIN(38),
342 JAGUAR2_PIN(39),
343 JAGUAR2_PIN(40),
344 JAGUAR2_PIN(41),
345 JAGUAR2_PIN(42),
346 JAGUAR2_PIN(43),
347 JAGUAR2_PIN(44),
348 JAGUAR2_PIN(45),
349 JAGUAR2_PIN(46),
350 JAGUAR2_PIN(47),
351 JAGUAR2_PIN(48),
352 JAGUAR2_PIN(49),
353 JAGUAR2_PIN(50),
354 JAGUAR2_PIN(51),
355 JAGUAR2_PIN(52),
356 JAGUAR2_PIN(53),
357 JAGUAR2_PIN(54),
358 JAGUAR2_PIN(55),
359 JAGUAR2_PIN(56),
360 JAGUAR2_PIN(57),
361 JAGUAR2_PIN(58),
362 JAGUAR2_PIN(59),
363 JAGUAR2_PIN(60),
364 JAGUAR2_PIN(61),
365 JAGUAR2_PIN(62),
366 JAGUAR2_PIN(63),
367};
368
369#define SPARX5_P(p, f0, f1, f2) \
370static struct ocelot_pin_caps sparx5_pin_##p = { \
371 .pin = p, \
372 .functions = { \
373 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \
374 }, \
375}
376
377SPARX5_P(0, SG0, PLL_STAT, NONE);
378SPARX5_P(1, SG0, NONE, NONE);
379SPARX5_P(2, SG0, NONE, NONE);
380SPARX5_P(3, SG0, NONE, NONE);
381SPARX5_P(4, SG1, NONE, NONE);
382SPARX5_P(5, SG1, NONE, NONE);
383SPARX5_P(6, IRQ0_IN, IRQ0_OUT, SFP);
384SPARX5_P(7, IRQ1_IN, IRQ1_OUT, SFP);
385SPARX5_P(8, PTP0, NONE, SFP);
386SPARX5_P(9, PTP1, SFP, TWI_SCL_M);
387SPARX5_P(10, UART, NONE, NONE);
388SPARX5_P(11, UART, NONE, NONE);
389SPARX5_P(12, SG1, NONE, NONE);
390SPARX5_P(13, SG1, NONE, NONE);
391SPARX5_P(14, TWI, TWI_SCL_M, NONE);
392SPARX5_P(15, TWI, NONE, NONE);
393SPARX5_P(16, SI, TWI_SCL_M, SFP);
394SPARX5_P(17, SI, TWI_SCL_M, SFP);
395SPARX5_P(18, SI, TWI_SCL_M, SFP);
396SPARX5_P(19, PCI_WAKE, TWI_SCL_M, SFP);
397SPARX5_P(20, IRQ0_OUT, TWI_SCL_M, SFP);
398SPARX5_P(21, IRQ1_OUT, TACHO, SFP);
399SPARX5_P(22, TACHO, IRQ0_OUT, TWI_SCL_M);
400SPARX5_P(23, PWM, UART3, TWI_SCL_M);
401SPARX5_P(24, PTP2, UART3, TWI_SCL_M);
402SPARX5_P(25, PTP3, SI, TWI_SCL_M);
403SPARX5_P(26, UART2, SI, TWI_SCL_M);
404SPARX5_P(27, UART2, SI, TWI_SCL_M);
405SPARX5_P(28, TWI2, SI, SFP);
406SPARX5_P(29, TWI2, SI, SFP);
407SPARX5_P(30, SG2, SI, PWM);
408SPARX5_P(31, SG2, SI, TWI_SCL_M);
409SPARX5_P(32, SG2, SI, TWI_SCL_M);
410SPARX5_P(33, SG2, SI, SFP);
411SPARX5_P(34, NONE, TWI_SCL_M, EMMC);
412SPARX5_P(35, SFP, TWI_SCL_M, EMMC);
413SPARX5_P(36, SFP, TWI_SCL_M, EMMC);
414SPARX5_P(37, SFP, NONE, EMMC);
415SPARX5_P(38, NONE, TWI_SCL_M, EMMC);
416SPARX5_P(39, SI2, TWI_SCL_M, EMMC);
417SPARX5_P(40, SI2, TWI_SCL_M, EMMC);
418SPARX5_P(41, SI2, TWI_SCL_M, EMMC);
419SPARX5_P(42, SI2, TWI_SCL_M, EMMC);
420SPARX5_P(43, SI2, TWI_SCL_M, EMMC);
421SPARX5_P(44, SI, SFP, EMMC);
422SPARX5_P(45, SI, SFP, EMMC);
423SPARX5_P(46, NONE, SFP, EMMC);
424SPARX5_P(47, NONE, SFP, EMMC);
425SPARX5_P(48, TWI3, SI, SFP);
426SPARX5_P(49, TWI3, NONE, SFP);
427SPARX5_P(50, SFP, NONE, TWI_SCL_M);
428SPARX5_P(51, SFP, SI, TWI_SCL_M);
429SPARX5_P(52, SFP, MIIM, TWI_SCL_M);
430SPARX5_P(53, SFP, MIIM, TWI_SCL_M);
431SPARX5_P(54, SFP, PTP2, TWI_SCL_M);
432SPARX5_P(55, SFP, PTP3, PCI_WAKE);
433SPARX5_P(56, MIIM, SFP, TWI_SCL_M);
434SPARX5_P(57, MIIM, SFP, TWI_SCL_M);
435SPARX5_P(58, MIIM, SFP, TWI_SCL_M);
436SPARX5_P(59, MIIM, SFP, NONE);
437SPARX5_P(60, RECO_CLK, NONE, NONE);
438SPARX5_P(61, RECO_CLK, NONE, NONE);
439SPARX5_P(62, RECO_CLK, PLL_STAT, NONE);
440SPARX5_P(63, RECO_CLK, NONE, NONE);
441
442#define SPARX5_PIN(n) { \
443 .number = n, \
444 .name = "GPIO_"#n, \
445 .drv_data = &sparx5_pin_##n \
446}
447
448static const struct pinctrl_pin_desc sparx5_pins[] = {
449 SPARX5_PIN(0),
450 SPARX5_PIN(1),
451 SPARX5_PIN(2),
452 SPARX5_PIN(3),
453 SPARX5_PIN(4),
454 SPARX5_PIN(5),
455 SPARX5_PIN(6),
456 SPARX5_PIN(7),
457 SPARX5_PIN(8),
458 SPARX5_PIN(9),
459 SPARX5_PIN(10),
460 SPARX5_PIN(11),
461 SPARX5_PIN(12),
462 SPARX5_PIN(13),
463 SPARX5_PIN(14),
464 SPARX5_PIN(15),
465 SPARX5_PIN(16),
466 SPARX5_PIN(17),
467 SPARX5_PIN(18),
468 SPARX5_PIN(19),
469 SPARX5_PIN(20),
470 SPARX5_PIN(21),
471 SPARX5_PIN(22),
472 SPARX5_PIN(23),
473 SPARX5_PIN(24),
474 SPARX5_PIN(25),
475 SPARX5_PIN(26),
476 SPARX5_PIN(27),
477 SPARX5_PIN(28),
478 SPARX5_PIN(29),
479 SPARX5_PIN(30),
480 SPARX5_PIN(31),
481 SPARX5_PIN(32),
482 SPARX5_PIN(33),
483 SPARX5_PIN(34),
484 SPARX5_PIN(35),
485 SPARX5_PIN(36),
486 SPARX5_PIN(37),
487 SPARX5_PIN(38),
488 SPARX5_PIN(39),
489 SPARX5_PIN(40),
490 SPARX5_PIN(41),
491 SPARX5_PIN(42),
492 SPARX5_PIN(43),
493 SPARX5_PIN(44),
494 SPARX5_PIN(45),
495 SPARX5_PIN(46),
496 SPARX5_PIN(47),
497 SPARX5_PIN(48),
498 SPARX5_PIN(49),
499 SPARX5_PIN(50),
500 SPARX5_PIN(51),
501 SPARX5_PIN(52),
502 SPARX5_PIN(53),
503 SPARX5_PIN(54),
504 SPARX5_PIN(55),
505 SPARX5_PIN(56),
506 SPARX5_PIN(57),
507 SPARX5_PIN(58),
508 SPARX5_PIN(59),
509 SPARX5_PIN(60),
510 SPARX5_PIN(61),
511 SPARX5_PIN(62),
512 SPARX5_PIN(63),
513};
514
515static int ocelot_get_functions_count(struct pinctrl_dev *pctldev)
516{
517 return ARRAY_SIZE(ocelot_function_names);
518}
519
520static const char *ocelot_get_function_name(struct pinctrl_dev *pctldev,
521 unsigned int function)
522{
523 return ocelot_function_names[function];
524}
525
526static int ocelot_get_function_groups(struct pinctrl_dev *pctldev,
527 unsigned int function,
528 const char *const **groups,
529 unsigned *const num_groups)
530{
531 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
532
533 *groups = info->func[function].groups;
534 *num_groups = info->func[function].ngroups;
535
536 return 0;
537}
538
539static int ocelot_pin_function_idx(struct ocelot_pinctrl *info,
540 unsigned int pin, unsigned int function)
541{
542 struct ocelot_pin_caps *p = info->desc->pins[pin].drv_data;
543 int i;
544
545 for (i = 0; i < OCELOT_FUNC_PER_PIN; i++) {
546 if (function == p->functions[i])
547 return i;
548 }
549
550 return -1;
551}
552
553#define REG_ALT(msb, info, p) (OCELOT_GPIO_ALT0 * (info)->stride + 4 * ((msb) + ((info)->stride * ((p) / 32))))
554
555static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev,
556 unsigned int selector, unsigned int group)
557{
558 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
559 struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data;
560 unsigned int p = pin->pin % 32;
561 int f;
562
563 f = ocelot_pin_function_idx(info, group, selector);
564 if (f < 0)
565 return -EINVAL;
566
567 /*
568 * f is encoded on two bits.
569 * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of
570 * ALT[1]
571 * This is racy because both registers can't be updated at the same time
572 * but it doesn't matter much for now.
573 * Note: ALT0/ALT1 are organized specially for 64 gpio targets
574 */
575 regmap_update_bits(info->map, REG_ALT(0, info, pin->pin),
576 BIT(p), f << p);
577 regmap_update_bits(info->map, REG_ALT(1, info, pin->pin),
578 BIT(p), f << (p - 1));
579
580 return 0;
581}
582
583#define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32)))
584
585static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev,
586 struct pinctrl_gpio_range *range,
587 unsigned int pin, bool input)
588{
589 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
590 unsigned int p = pin % 32;
591
592 regmap_update_bits(info->map, REG(OCELOT_GPIO_OE, info, pin), BIT(p),
593 input ? 0 : BIT(p));
594
595 return 0;
596}
597
598static int ocelot_gpio_request_enable(struct pinctrl_dev *pctldev,
599 struct pinctrl_gpio_range *range,
600 unsigned int offset)
601{
602 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
603 unsigned int p = offset % 32;
604
605 regmap_update_bits(info->map, REG_ALT(0, info, offset),
606 BIT(p), 0);
607 regmap_update_bits(info->map, REG_ALT(1, info, offset),
608 BIT(p), 0);
609
610 return 0;
611}
612
613static const struct pinmux_ops ocelot_pmx_ops = {
614 .get_functions_count = ocelot_get_functions_count,
615 .get_function_name = ocelot_get_function_name,
616 .get_function_groups = ocelot_get_function_groups,
617 .set_mux = ocelot_pinmux_set_mux,
618 .gpio_set_direction = ocelot_gpio_set_direction,
619 .gpio_request_enable = ocelot_gpio_request_enable,
620};
621
622static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev)
623{
624 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
625
626 return info->desc->npins;
627}
628
629static const char *ocelot_pctl_get_group_name(struct pinctrl_dev *pctldev,
630 unsigned int group)
631{
632 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
633
634 return info->desc->pins[group].name;
635}
636
637static int ocelot_pctl_get_group_pins(struct pinctrl_dev *pctldev,
638 unsigned int group,
639 const unsigned int **pins,
640 unsigned int *num_pins)
641{
642 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
643
644 *pins = &info->desc->pins[group].number;
645 *num_pins = 1;
646
647 return 0;
648}
649
650static int ocelot_hw_get_value(struct ocelot_pinctrl *info,
651 unsigned int pin,
652 unsigned int reg,
653 int *val)
654{
655 int ret = -EOPNOTSUPP;
656
657 if (info->pincfg) {
658 u32 regcfg = readl(info->pincfg + (pin * sizeof(u32)));
659
660 ret = 0;
661 switch (reg) {
662 case PINCONF_BIAS:
663 *val = regcfg & BIAS_BITS;
664 break;
665
666 case PINCONF_SCHMITT:
667 *val = regcfg & SCHMITT_BIT;
668 break;
669
670 case PINCONF_DRIVE_STRENGTH:
671 *val = regcfg & DRIVE_BITS;
672 break;
673
674 default:
675 ret = -EOPNOTSUPP;
676 break;
677 }
678 }
679 return ret;
680}
681
682static int ocelot_hw_set_value(struct ocelot_pinctrl *info,
683 unsigned int pin,
684 unsigned int reg,
685 int val)
686{
687 int ret = -EOPNOTSUPP;
688
689 if (info->pincfg) {
690 void __iomem *regaddr = info->pincfg + (pin * sizeof(u32));
691
692 ret = 0;
693 switch (reg) {
694 case PINCONF_BIAS:
695 ocelot_clrsetbits(regaddr, BIAS_BITS, val);
696 break;
697
698 case PINCONF_SCHMITT:
699 ocelot_clrsetbits(regaddr, SCHMITT_BIT, val);
700 break;
701
702 case PINCONF_DRIVE_STRENGTH:
703 if (val <= 3)
704 ocelot_clrsetbits(regaddr, DRIVE_BITS, val);
705 else
706 ret = -EINVAL;
707 break;
708
709 default:
710 ret = -EOPNOTSUPP;
711 break;
712 }
713 }
714 return ret;
715}
716
717static int ocelot_pinconf_get(struct pinctrl_dev *pctldev,
718 unsigned int pin, unsigned long *config)
719{
720 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
721 u32 param = pinconf_to_config_param(*config);
722 int val, err;
723
724 switch (param) {
725 case PIN_CONFIG_BIAS_DISABLE:
726 case PIN_CONFIG_BIAS_PULL_UP:
727 case PIN_CONFIG_BIAS_PULL_DOWN:
728 err = ocelot_hw_get_value(info, pin, PINCONF_BIAS, &val);
729 if (err)
730 return err;
731 if (param == PIN_CONFIG_BIAS_DISABLE)
732 val = (val == 0 ? true : false);
733 else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
734 val = (val & BIAS_PD_BIT ? true : false);
735 else /* PIN_CONFIG_BIAS_PULL_UP */
736 val = (val & BIAS_PU_BIT ? true : false);
737 break;
738
739 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
740 err = ocelot_hw_get_value(info, pin, PINCONF_SCHMITT, &val);
741 if (err)
742 return err;
743
744 val = (val & SCHMITT_BIT ? true : false);
745 break;
746
747 case PIN_CONFIG_DRIVE_STRENGTH:
748 err = ocelot_hw_get_value(info, pin, PINCONF_DRIVE_STRENGTH,
749 &val);
750 if (err)
751 return err;
752 break;
753
754 case PIN_CONFIG_OUTPUT:
755 err = regmap_read(info->map, REG(OCELOT_GPIO_OUT, info, pin),
756 &val);
757 if (err)
758 return err;
759 val = !!(val & BIT(pin % 32));
760 break;
761
762 case PIN_CONFIG_INPUT_ENABLE:
763 case PIN_CONFIG_OUTPUT_ENABLE:
764 err = regmap_read(info->map, REG(OCELOT_GPIO_OE, info, pin),
765 &val);
766 if (err)
767 return err;
768 val = val & BIT(pin % 32);
769 if (param == PIN_CONFIG_OUTPUT_ENABLE)
770 val = !!val;
771 else
772 val = !val;
773 break;
774
775 default:
776 return -EOPNOTSUPP;
777 }
778
779 *config = pinconf_to_config_packed(param, val);
780
781 return 0;
782}
783
784static int ocelot_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
785 unsigned long *configs, unsigned int num_configs)
786{
787 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
788 u32 param, arg, p;
789 int cfg, err = 0;
790
791 for (cfg = 0; cfg < num_configs; cfg++) {
792 param = pinconf_to_config_param(configs[cfg]);
793 arg = pinconf_to_config_argument(configs[cfg]);
794
795 switch (param) {
796 case PIN_CONFIG_BIAS_DISABLE:
797 case PIN_CONFIG_BIAS_PULL_UP:
798 case PIN_CONFIG_BIAS_PULL_DOWN:
799 arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 :
800 (param == PIN_CONFIG_BIAS_PULL_UP) ? BIAS_PU_BIT :
801 BIAS_PD_BIT;
802
803 err = ocelot_hw_set_value(info, pin, PINCONF_BIAS, arg);
804 if (err)
805 goto err;
806
807 break;
808
809 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
810 arg = arg ? SCHMITT_BIT : 0;
811 err = ocelot_hw_set_value(info, pin, PINCONF_SCHMITT,
812 arg);
813 if (err)
814 goto err;
815
816 break;
817
818 case PIN_CONFIG_DRIVE_STRENGTH:
819 err = ocelot_hw_set_value(info, pin,
820 PINCONF_DRIVE_STRENGTH,
821 arg);
822 if (err)
823 goto err;
824
825 break;
826
827 case PIN_CONFIG_OUTPUT_ENABLE:
828 case PIN_CONFIG_INPUT_ENABLE:
829 case PIN_CONFIG_OUTPUT:
830 p = pin % 32;
831 if (arg)
832 regmap_write(info->map,
833 REG(OCELOT_GPIO_OUT_SET, info,
834 pin),
835 BIT(p));
836 else
837 regmap_write(info->map,
838 REG(OCELOT_GPIO_OUT_CLR, info,
839 pin),
840 BIT(p));
841 regmap_update_bits(info->map,
842 REG(OCELOT_GPIO_OE, info, pin),
843 BIT(p),
844 param == PIN_CONFIG_INPUT_ENABLE ?
845 0 : BIT(p));
846 break;
847
848 default:
849 err = -EOPNOTSUPP;
850 }
851 }
852err:
853 return err;
854}
855
856static const struct pinconf_ops ocelot_confops = {
857 .is_generic = true,
858 .pin_config_get = ocelot_pinconf_get,
859 .pin_config_set = ocelot_pinconf_set,
860 .pin_config_config_dbg_show = pinconf_generic_dump_config,
861};
862
863static const struct pinctrl_ops ocelot_pctl_ops = {
864 .get_groups_count = ocelot_pctl_get_groups_count,
865 .get_group_name = ocelot_pctl_get_group_name,
866 .get_group_pins = ocelot_pctl_get_group_pins,
867 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
868 .dt_free_map = pinconf_generic_dt_free_map,
869};
870
871static struct pinctrl_desc ocelot_desc = {
872 .name = "ocelot-pinctrl",
873 .pins = ocelot_pins,
874 .npins = ARRAY_SIZE(ocelot_pins),
875 .pctlops = &ocelot_pctl_ops,
876 .pmxops = &ocelot_pmx_ops,
877 .owner = THIS_MODULE,
878};
879
880static struct pinctrl_desc jaguar2_desc = {
881 .name = "jaguar2-pinctrl",
882 .pins = jaguar2_pins,
883 .npins = ARRAY_SIZE(jaguar2_pins),
884 .pctlops = &ocelot_pctl_ops,
885 .pmxops = &ocelot_pmx_ops,
886 .owner = THIS_MODULE,
887};
888
889static struct pinctrl_desc sparx5_desc = {
890 .name = "sparx5-pinctrl",
891 .pins = sparx5_pins,
892 .npins = ARRAY_SIZE(sparx5_pins),
893 .pctlops = &ocelot_pctl_ops,
894 .pmxops = &ocelot_pmx_ops,
895 .confops = &ocelot_confops,
896 .owner = THIS_MODULE,
897};
898
899static int ocelot_create_group_func_map(struct device *dev,
900 struct ocelot_pinctrl *info)
901{
902 int f, npins, i;
903 u8 *pins = kcalloc(info->desc->npins, sizeof(u8), GFP_KERNEL);
904
905 if (!pins)
906 return -ENOMEM;
907
908 for (f = 0; f < FUNC_MAX; f++) {
909 for (npins = 0, i = 0; i < info->desc->npins; i++) {
910 if (ocelot_pin_function_idx(info, i, f) >= 0)
911 pins[npins++] = i;
912 }
913
914 if (!npins)
915 continue;
916
917 info->func[f].ngroups = npins;
918 info->func[f].groups = devm_kcalloc(dev, npins, sizeof(char *),
919 GFP_KERNEL);
920 if (!info->func[f].groups) {
921 kfree(pins);
922 return -ENOMEM;
923 }
924
925 for (i = 0; i < npins; i++)
926 info->func[f].groups[i] =
927 info->desc->pins[pins[i]].name;
928 }
929
930 kfree(pins);
931
932 return 0;
933}
934
935static int ocelot_pinctrl_register(struct platform_device *pdev,
936 struct ocelot_pinctrl *info)
937{
938 int ret;
939
940 ret = ocelot_create_group_func_map(&pdev->dev, info);
941 if (ret) {
942 dev_err(&pdev->dev, "Unable to create group func map.\n");
943 return ret;
944 }
945
946 info->pctl = devm_pinctrl_register(&pdev->dev, info->desc, info);
947 if (IS_ERR(info->pctl)) {
948 dev_err(&pdev->dev, "Failed to register pinctrl\n");
949 return PTR_ERR(info->pctl);
950 }
951
952 return 0;
953}
954
955static int ocelot_gpio_get(struct gpio_chip *chip, unsigned int offset)
956{
957 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
958 unsigned int val;
959
960 regmap_read(info->map, REG(OCELOT_GPIO_IN, info, offset), &val);
961
962 return !!(val & BIT(offset % 32));
963}
964
965static void ocelot_gpio_set(struct gpio_chip *chip, unsigned int offset,
966 int value)
967{
968 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
969
970 if (value)
971 regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset),
972 BIT(offset % 32));
973 else
974 regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset),
975 BIT(offset % 32));
976}
977
978static int ocelot_gpio_get_direction(struct gpio_chip *chip,
979 unsigned int offset)
980{
981 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
982 unsigned int val;
983
984 regmap_read(info->map, REG(OCELOT_GPIO_OE, info, offset), &val);
985
986 if (val & BIT(offset % 32))
987 return GPIO_LINE_DIRECTION_OUT;
988
989 return GPIO_LINE_DIRECTION_IN;
990}
991
992static int ocelot_gpio_direction_input(struct gpio_chip *chip,
993 unsigned int offset)
994{
995 return pinctrl_gpio_direction_input(chip->base + offset);
996}
997
998static int ocelot_gpio_direction_output(struct gpio_chip *chip,
999 unsigned int offset, int value)
1000{
1001 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1002 unsigned int pin = BIT(offset % 32);
1003
1004 if (value)
1005 regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset),
1006 pin);
1007 else
1008 regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset),
1009 pin);
1010
1011 return pinctrl_gpio_direction_output(chip->base + offset);
1012}
1013
1014static const struct gpio_chip ocelot_gpiolib_chip = {
1015 .request = gpiochip_generic_request,
1016 .free = gpiochip_generic_free,
1017 .set = ocelot_gpio_set,
1018 .get = ocelot_gpio_get,
1019 .get_direction = ocelot_gpio_get_direction,
1020 .direction_input = ocelot_gpio_direction_input,
1021 .direction_output = ocelot_gpio_direction_output,
1022 .owner = THIS_MODULE,
1023};
1024
1025static void ocelot_irq_mask(struct irq_data *data)
1026{
1027 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
1028 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1029 unsigned int gpio = irqd_to_hwirq(data);
1030
1031 regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio),
1032 BIT(gpio % 32), 0);
1033}
1034
1035static void ocelot_irq_unmask(struct irq_data *data)
1036{
1037 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
1038 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1039 unsigned int gpio = irqd_to_hwirq(data);
1040
1041 regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio),
1042 BIT(gpio % 32), BIT(gpio % 32));
1043}
1044
1045static void ocelot_irq_ack(struct irq_data *data)
1046{
1047 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
1048 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1049 unsigned int gpio = irqd_to_hwirq(data);
1050
1051 regmap_write_bits(info->map, REG(OCELOT_GPIO_INTR, info, gpio),
1052 BIT(gpio % 32), BIT(gpio % 32));
1053}
1054
1055static int ocelot_irq_set_type(struct irq_data *data, unsigned int type);
1056
1057static struct irq_chip ocelot_eoi_irqchip = {
1058 .name = "gpio",
1059 .irq_mask = ocelot_irq_mask,
1060 .irq_eoi = ocelot_irq_ack,
1061 .irq_unmask = ocelot_irq_unmask,
1062 .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED,
1063 .irq_set_type = ocelot_irq_set_type,
1064};
1065
1066static struct irq_chip ocelot_irqchip = {
1067 .name = "gpio",
1068 .irq_mask = ocelot_irq_mask,
1069 .irq_ack = ocelot_irq_ack,
1070 .irq_unmask = ocelot_irq_unmask,
1071 .irq_set_type = ocelot_irq_set_type,
1072};
1073
1074static int ocelot_irq_set_type(struct irq_data *data, unsigned int type)
1075{
1076 type &= IRQ_TYPE_SENSE_MASK;
1077
1078 if (!(type & (IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_LEVEL_HIGH)))
1079 return -EINVAL;
1080
1081 if (type & IRQ_TYPE_LEVEL_HIGH)
1082 irq_set_chip_handler_name_locked(data, &ocelot_eoi_irqchip,
1083 handle_fasteoi_irq, NULL);
1084 if (type & IRQ_TYPE_EDGE_BOTH)
1085 irq_set_chip_handler_name_locked(data, &ocelot_irqchip,
1086 handle_edge_irq, NULL);
1087
1088 return 0;
1089}
1090
1091static void ocelot_irq_handler(struct irq_desc *desc)
1092{
1093 struct irq_chip *parent_chip = irq_desc_get_chip(desc);
1094 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
1095 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1096 unsigned int id_reg = OCELOT_GPIO_INTR_IDENT * info->stride;
1097 unsigned int reg = 0, irq, i;
1098 unsigned long irqs;
1099
1100 for (i = 0; i < info->stride; i++) {
1101 regmap_read(info->map, id_reg + 4 * i, ®);
1102 if (!reg)
1103 continue;
1104
1105 chained_irq_enter(parent_chip, desc);
1106
1107 irqs = reg;
1108
1109 for_each_set_bit(irq, &irqs,
1110 min(32U, info->desc->npins - 32 * i))
1111 generic_handle_irq(irq_linear_revmap(chip->irq.domain,
1112 irq + 32 * i));
1113
1114 chained_irq_exit(parent_chip, desc);
1115 }
1116}
1117
1118static int ocelot_gpiochip_register(struct platform_device *pdev,
1119 struct ocelot_pinctrl *info)
1120{
1121 struct gpio_chip *gc;
1122 struct gpio_irq_chip *girq;
1123 int ret, irq;
1124
1125 info->gpio_chip = ocelot_gpiolib_chip;
1126
1127 gc = &info->gpio_chip;
1128 gc->ngpio = info->desc->npins;
1129 gc->parent = &pdev->dev;
1130 gc->base = 0;
1131 gc->of_node = info->dev->of_node;
1132 gc->label = "ocelot-gpio";
1133
1134 irq = irq_of_parse_and_map(gc->of_node, 0);
1135 if (irq) {
1136 girq = &gc->irq;
1137 girq->chip = &ocelot_irqchip;
1138 girq->parent_handler = ocelot_irq_handler;
1139 girq->num_parents = 1;
1140 girq->parents = devm_kcalloc(&pdev->dev, 1,
1141 sizeof(*girq->parents),
1142 GFP_KERNEL);
1143 if (!girq->parents)
1144 return -ENOMEM;
1145 girq->parents[0] = irq;
1146 girq->default_type = IRQ_TYPE_NONE;
1147 girq->handler = handle_edge_irq;
1148 }
1149
1150 ret = devm_gpiochip_add_data(&pdev->dev, gc, info);
1151 if (ret)
1152 return ret;
1153
1154 return 0;
1155}
1156
1157static const struct of_device_id ocelot_pinctrl_of_match[] = {
1158 { .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc },
1159 { .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc },
1160 { .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc },
1161 {},
1162};
1163
1164static int ocelot_pinctrl_probe(struct platform_device *pdev)
1165{
1166 struct device *dev = &pdev->dev;
1167 struct ocelot_pinctrl *info;
1168 void __iomem *base;
1169 struct resource *res;
1170 int ret;
1171 struct regmap_config regmap_config = {
1172 .reg_bits = 32,
1173 .val_bits = 32,
1174 .reg_stride = 4,
1175 };
1176
1177 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
1178 if (!info)
1179 return -ENOMEM;
1180
1181 info->desc = (struct pinctrl_desc *)device_get_match_data(dev);
1182
1183 base = devm_ioremap_resource(dev,
1184 platform_get_resource(pdev, IORESOURCE_MEM, 0));
1185 if (IS_ERR(base)) {
1186 dev_err(dev, "Failed to ioremap registers\n");
1187 return PTR_ERR(base);
1188 }
1189
1190 info->stride = 1 + (info->desc->npins - 1) / 32;
1191
1192 regmap_config.max_register = OCELOT_GPIO_SD_MAP * info->stride + 15 * 4;
1193
1194 info->map = devm_regmap_init_mmio(dev, base, ®map_config);
1195 if (IS_ERR(info->map)) {
1196 dev_err(dev, "Failed to create regmap\n");
1197 return PTR_ERR(info->map);
1198 }
1199 dev_set_drvdata(dev, info->map);
1200 info->dev = dev;
1201
1202 /* Pinconf registers */
1203 if (info->desc->confops) {
1204 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1205 base = devm_ioremap_resource(dev, res);
1206 if (IS_ERR(base))
1207 dev_dbg(dev, "Failed to ioremap config registers (no extended pinconf)\n");
1208 else
1209 info->pincfg = base;
1210 }
1211
1212 ret = ocelot_pinctrl_register(pdev, info);
1213 if (ret)
1214 return ret;
1215
1216 ret = ocelot_gpiochip_register(pdev, info);
1217 if (ret)
1218 return ret;
1219
1220 dev_info(dev, "driver registered\n");
1221
1222 return 0;
1223}
1224
1225static struct platform_driver ocelot_pinctrl_driver = {
1226 .driver = {
1227 .name = "pinctrl-ocelot",
1228 .of_match_table = of_match_ptr(ocelot_pinctrl_of_match),
1229 .suppress_bind_attrs = true,
1230 },
1231 .probe = ocelot_pinctrl_probe,
1232};
1233builtin_platform_driver(ocelot_pinctrl_driver);
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Microsemi SoCs pinctrl driver
4 *
5 * Author: <alexandre.belloni@free-electrons.com>
6 * License: Dual MIT/GPL
7 * Copyright (c) 2017 Microsemi Corporation
8 */
9
10#include <linux/gpio/driver.h>
11#include <linux/interrupt.h>
12#include <linux/io.h>
13#include <linux/mfd/ocelot.h>
14#include <linux/of.h>
15#include <linux/platform_device.h>
16#include <linux/regmap.h>
17#include <linux/reset.h>
18#include <linux/slab.h>
19
20#include <linux/pinctrl/consumer.h>
21#include <linux/pinctrl/pinconf-generic.h>
22#include <linux/pinctrl/pinconf.h>
23#include <linux/pinctrl/pinctrl.h>
24#include <linux/pinctrl/pinmux.h>
25
26#include "core.h"
27#include "pinconf.h"
28#include "pinmux.h"
29
30#define ocelot_clrsetbits(addr, clear, set) \
31 writel((readl(addr) & ~(clear)) | (set), (addr))
32
33enum {
34 PINCONF_BIAS,
35 PINCONF_SCHMITT,
36 PINCONF_DRIVE_STRENGTH,
37};
38
39/* GPIO standard registers */
40#define OCELOT_GPIO_OUT_SET 0x0
41#define OCELOT_GPIO_OUT_CLR 0x4
42#define OCELOT_GPIO_OUT 0x8
43#define OCELOT_GPIO_IN 0xc
44#define OCELOT_GPIO_OE 0x10
45#define OCELOT_GPIO_INTR 0x14
46#define OCELOT_GPIO_INTR_ENA 0x18
47#define OCELOT_GPIO_INTR_IDENT 0x1c
48#define OCELOT_GPIO_ALT0 0x20
49#define OCELOT_GPIO_ALT1 0x24
50#define OCELOT_GPIO_SD_MAP 0x28
51
52#define OCELOT_FUNC_PER_PIN 4
53
54enum {
55 FUNC_CAN0_a,
56 FUNC_CAN0_b,
57 FUNC_CAN1,
58 FUNC_CLKMON,
59 FUNC_NONE,
60 FUNC_FC0_a,
61 FUNC_FC0_b,
62 FUNC_FC0_c,
63 FUNC_FC1_a,
64 FUNC_FC1_b,
65 FUNC_FC1_c,
66 FUNC_FC2_a,
67 FUNC_FC2_b,
68 FUNC_FC3_a,
69 FUNC_FC3_b,
70 FUNC_FC3_c,
71 FUNC_FC4_a,
72 FUNC_FC4_b,
73 FUNC_FC4_c,
74 FUNC_FC_SHRD0,
75 FUNC_FC_SHRD1,
76 FUNC_FC_SHRD2,
77 FUNC_FC_SHRD3,
78 FUNC_FC_SHRD4,
79 FUNC_FC_SHRD5,
80 FUNC_FC_SHRD6,
81 FUNC_FC_SHRD7,
82 FUNC_FC_SHRD8,
83 FUNC_FC_SHRD9,
84 FUNC_FC_SHRD10,
85 FUNC_FC_SHRD11,
86 FUNC_FC_SHRD12,
87 FUNC_FC_SHRD13,
88 FUNC_FC_SHRD14,
89 FUNC_FC_SHRD15,
90 FUNC_FC_SHRD16,
91 FUNC_FC_SHRD17,
92 FUNC_FC_SHRD18,
93 FUNC_FC_SHRD19,
94 FUNC_FC_SHRD20,
95 FUNC_GPIO,
96 FUNC_IB_TRG_a,
97 FUNC_IB_TRG_b,
98 FUNC_IB_TRG_c,
99 FUNC_IRQ0,
100 FUNC_IRQ_IN_a,
101 FUNC_IRQ_IN_b,
102 FUNC_IRQ_IN_c,
103 FUNC_IRQ0_IN,
104 FUNC_IRQ_OUT_a,
105 FUNC_IRQ_OUT_b,
106 FUNC_IRQ_OUT_c,
107 FUNC_IRQ0_OUT,
108 FUNC_IRQ1,
109 FUNC_IRQ1_IN,
110 FUNC_IRQ1_OUT,
111 FUNC_EXT_IRQ,
112 FUNC_MIIM,
113 FUNC_MIIM_a,
114 FUNC_MIIM_b,
115 FUNC_MIIM_c,
116 FUNC_MIIM_Sa,
117 FUNC_MIIM_Sb,
118 FUNC_OB_TRG,
119 FUNC_OB_TRG_a,
120 FUNC_OB_TRG_b,
121 FUNC_PHY_LED,
122 FUNC_PCI_WAKE,
123 FUNC_MD,
124 FUNC_PTP0,
125 FUNC_PTP1,
126 FUNC_PTP2,
127 FUNC_PTP3,
128 FUNC_PTPSYNC_0,
129 FUNC_PTPSYNC_1,
130 FUNC_PTPSYNC_2,
131 FUNC_PTPSYNC_3,
132 FUNC_PTPSYNC_4,
133 FUNC_PTPSYNC_5,
134 FUNC_PTPSYNC_6,
135 FUNC_PTPSYNC_7,
136 FUNC_PWM,
137 FUNC_PWM_a,
138 FUNC_PWM_b,
139 FUNC_QSPI1,
140 FUNC_QSPI2,
141 FUNC_R,
142 FUNC_RECO_a,
143 FUNC_RECO_b,
144 FUNC_RECO_CLK,
145 FUNC_SD,
146 FUNC_SFP,
147 FUNC_SFP_SD,
148 FUNC_SG0,
149 FUNC_SG1,
150 FUNC_SG2,
151 FUNC_SGPIO_a,
152 FUNC_SGPIO_b,
153 FUNC_SI,
154 FUNC_SI2,
155 FUNC_TACHO,
156 FUNC_TACHO_a,
157 FUNC_TACHO_b,
158 FUNC_TWI,
159 FUNC_TWI2,
160 FUNC_TWI3,
161 FUNC_TWI_SCL_M,
162 FUNC_TWI_SLC_GATE,
163 FUNC_TWI_SLC_GATE_AD,
164 FUNC_UART,
165 FUNC_UART2,
166 FUNC_UART3,
167 FUNC_USB_H_a,
168 FUNC_USB_H_b,
169 FUNC_USB_H_c,
170 FUNC_USB_S_a,
171 FUNC_USB_S_b,
172 FUNC_USB_S_c,
173 FUNC_PLL_STAT,
174 FUNC_EMMC,
175 FUNC_EMMC_SD,
176 FUNC_REF_CLK,
177 FUNC_RCVRD_CLK,
178 FUNC_MAX
179};
180
181static const char *const ocelot_function_names[] = {
182 [FUNC_CAN0_a] = "can0_a",
183 [FUNC_CAN0_b] = "can0_b",
184 [FUNC_CAN1] = "can1",
185 [FUNC_CLKMON] = "clkmon",
186 [FUNC_NONE] = "none",
187 [FUNC_FC0_a] = "fc0_a",
188 [FUNC_FC0_b] = "fc0_b",
189 [FUNC_FC0_c] = "fc0_c",
190 [FUNC_FC1_a] = "fc1_a",
191 [FUNC_FC1_b] = "fc1_b",
192 [FUNC_FC1_c] = "fc1_c",
193 [FUNC_FC2_a] = "fc2_a",
194 [FUNC_FC2_b] = "fc2_b",
195 [FUNC_FC3_a] = "fc3_a",
196 [FUNC_FC3_b] = "fc3_b",
197 [FUNC_FC3_c] = "fc3_c",
198 [FUNC_FC4_a] = "fc4_a",
199 [FUNC_FC4_b] = "fc4_b",
200 [FUNC_FC4_c] = "fc4_c",
201 [FUNC_FC_SHRD0] = "fc_shrd0",
202 [FUNC_FC_SHRD1] = "fc_shrd1",
203 [FUNC_FC_SHRD2] = "fc_shrd2",
204 [FUNC_FC_SHRD3] = "fc_shrd3",
205 [FUNC_FC_SHRD4] = "fc_shrd4",
206 [FUNC_FC_SHRD5] = "fc_shrd5",
207 [FUNC_FC_SHRD6] = "fc_shrd6",
208 [FUNC_FC_SHRD7] = "fc_shrd7",
209 [FUNC_FC_SHRD8] = "fc_shrd8",
210 [FUNC_FC_SHRD9] = "fc_shrd9",
211 [FUNC_FC_SHRD10] = "fc_shrd10",
212 [FUNC_FC_SHRD11] = "fc_shrd11",
213 [FUNC_FC_SHRD12] = "fc_shrd12",
214 [FUNC_FC_SHRD13] = "fc_shrd13",
215 [FUNC_FC_SHRD14] = "fc_shrd14",
216 [FUNC_FC_SHRD15] = "fc_shrd15",
217 [FUNC_FC_SHRD16] = "fc_shrd16",
218 [FUNC_FC_SHRD17] = "fc_shrd17",
219 [FUNC_FC_SHRD18] = "fc_shrd18",
220 [FUNC_FC_SHRD19] = "fc_shrd19",
221 [FUNC_FC_SHRD20] = "fc_shrd20",
222 [FUNC_GPIO] = "gpio",
223 [FUNC_IB_TRG_a] = "ib_trig_a",
224 [FUNC_IB_TRG_b] = "ib_trig_b",
225 [FUNC_IB_TRG_c] = "ib_trig_c",
226 [FUNC_IRQ0] = "irq0",
227 [FUNC_IRQ_IN_a] = "irq_in_a",
228 [FUNC_IRQ_IN_b] = "irq_in_b",
229 [FUNC_IRQ_IN_c] = "irq_in_c",
230 [FUNC_IRQ0_IN] = "irq0_in",
231 [FUNC_IRQ_OUT_a] = "irq_out_a",
232 [FUNC_IRQ_OUT_b] = "irq_out_b",
233 [FUNC_IRQ_OUT_c] = "irq_out_c",
234 [FUNC_IRQ0_OUT] = "irq0_out",
235 [FUNC_IRQ1] = "irq1",
236 [FUNC_IRQ1_IN] = "irq1_in",
237 [FUNC_IRQ1_OUT] = "irq1_out",
238 [FUNC_EXT_IRQ] = "ext_irq",
239 [FUNC_MIIM] = "miim",
240 [FUNC_MIIM_a] = "miim_a",
241 [FUNC_MIIM_b] = "miim_b",
242 [FUNC_MIIM_c] = "miim_c",
243 [FUNC_MIIM_Sa] = "miim_slave_a",
244 [FUNC_MIIM_Sb] = "miim_slave_b",
245 [FUNC_PHY_LED] = "phy_led",
246 [FUNC_PCI_WAKE] = "pci_wake",
247 [FUNC_MD] = "md",
248 [FUNC_OB_TRG] = "ob_trig",
249 [FUNC_OB_TRG_a] = "ob_trig_a",
250 [FUNC_OB_TRG_b] = "ob_trig_b",
251 [FUNC_PTP0] = "ptp0",
252 [FUNC_PTP1] = "ptp1",
253 [FUNC_PTP2] = "ptp2",
254 [FUNC_PTP3] = "ptp3",
255 [FUNC_PTPSYNC_0] = "ptpsync_0",
256 [FUNC_PTPSYNC_1] = "ptpsync_1",
257 [FUNC_PTPSYNC_2] = "ptpsync_2",
258 [FUNC_PTPSYNC_3] = "ptpsync_3",
259 [FUNC_PTPSYNC_4] = "ptpsync_4",
260 [FUNC_PTPSYNC_5] = "ptpsync_5",
261 [FUNC_PTPSYNC_6] = "ptpsync_6",
262 [FUNC_PTPSYNC_7] = "ptpsync_7",
263 [FUNC_PWM] = "pwm",
264 [FUNC_PWM_a] = "pwm_a",
265 [FUNC_PWM_b] = "pwm_b",
266 [FUNC_QSPI1] = "qspi1",
267 [FUNC_QSPI2] = "qspi2",
268 [FUNC_R] = "reserved",
269 [FUNC_RECO_a] = "reco_a",
270 [FUNC_RECO_b] = "reco_b",
271 [FUNC_RECO_CLK] = "reco_clk",
272 [FUNC_SD] = "sd",
273 [FUNC_SFP] = "sfp",
274 [FUNC_SFP_SD] = "sfp_sd",
275 [FUNC_SG0] = "sg0",
276 [FUNC_SG1] = "sg1",
277 [FUNC_SG2] = "sg2",
278 [FUNC_SGPIO_a] = "sgpio_a",
279 [FUNC_SGPIO_b] = "sgpio_b",
280 [FUNC_SI] = "si",
281 [FUNC_SI2] = "si2",
282 [FUNC_TACHO] = "tacho",
283 [FUNC_TACHO_a] = "tacho_a",
284 [FUNC_TACHO_b] = "tacho_b",
285 [FUNC_TWI] = "twi",
286 [FUNC_TWI2] = "twi2",
287 [FUNC_TWI3] = "twi3",
288 [FUNC_TWI_SCL_M] = "twi_scl_m",
289 [FUNC_TWI_SLC_GATE] = "twi_slc_gate",
290 [FUNC_TWI_SLC_GATE_AD] = "twi_slc_gate_ad",
291 [FUNC_USB_H_a] = "usb_host_a",
292 [FUNC_USB_H_b] = "usb_host_b",
293 [FUNC_USB_H_c] = "usb_host_c",
294 [FUNC_USB_S_a] = "usb_slave_a",
295 [FUNC_USB_S_b] = "usb_slave_b",
296 [FUNC_USB_S_c] = "usb_slave_c",
297 [FUNC_UART] = "uart",
298 [FUNC_UART2] = "uart2",
299 [FUNC_UART3] = "uart3",
300 [FUNC_PLL_STAT] = "pll_stat",
301 [FUNC_EMMC] = "emmc",
302 [FUNC_EMMC_SD] = "emmc_sd",
303 [FUNC_REF_CLK] = "ref_clk",
304 [FUNC_RCVRD_CLK] = "rcvrd_clk",
305};
306
307struct ocelot_pmx_func {
308 const char **groups;
309 unsigned int ngroups;
310};
311
312struct ocelot_pin_caps {
313 unsigned int pin;
314 unsigned char functions[OCELOT_FUNC_PER_PIN];
315 unsigned char a_functions[OCELOT_FUNC_PER_PIN]; /* Additional functions */
316};
317
318struct ocelot_pincfg_data {
319 u8 pd_bit;
320 u8 pu_bit;
321 u8 drive_bits;
322 u8 schmitt_bit;
323};
324
325struct ocelot_pinctrl {
326 struct device *dev;
327 struct pinctrl_dev *pctl;
328 struct gpio_chip gpio_chip;
329 struct regmap *map;
330 struct regmap *pincfg;
331 struct pinctrl_desc *desc;
332 const struct ocelot_pincfg_data *pincfg_data;
333 struct ocelot_pmx_func func[FUNC_MAX];
334 u8 stride;
335 struct workqueue_struct *wq;
336};
337
338struct ocelot_match_data {
339 struct pinctrl_desc desc;
340 struct ocelot_pincfg_data pincfg_data;
341};
342
343struct ocelot_irq_work {
344 struct work_struct irq_work;
345 struct irq_desc *irq_desc;
346};
347
348#define LUTON_P(p, f0, f1) \
349static struct ocelot_pin_caps luton_pin_##p = { \
350 .pin = p, \
351 .functions = { \
352 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE, \
353 }, \
354}
355
356LUTON_P(0, SG0, NONE);
357LUTON_P(1, SG0, NONE);
358LUTON_P(2, SG0, NONE);
359LUTON_P(3, SG0, NONE);
360LUTON_P(4, TACHO, NONE);
361LUTON_P(5, TWI, PHY_LED);
362LUTON_P(6, TWI, PHY_LED);
363LUTON_P(7, NONE, PHY_LED);
364LUTON_P(8, EXT_IRQ, PHY_LED);
365LUTON_P(9, EXT_IRQ, PHY_LED);
366LUTON_P(10, SFP, PHY_LED);
367LUTON_P(11, SFP, PHY_LED);
368LUTON_P(12, SFP, PHY_LED);
369LUTON_P(13, SFP, PHY_LED);
370LUTON_P(14, SI, PHY_LED);
371LUTON_P(15, SI, PHY_LED);
372LUTON_P(16, SI, PHY_LED);
373LUTON_P(17, SFP, PHY_LED);
374LUTON_P(18, SFP, PHY_LED);
375LUTON_P(19, SFP, PHY_LED);
376LUTON_P(20, SFP, PHY_LED);
377LUTON_P(21, SFP, PHY_LED);
378LUTON_P(22, SFP, PHY_LED);
379LUTON_P(23, SFP, PHY_LED);
380LUTON_P(24, SFP, PHY_LED);
381LUTON_P(25, SFP, PHY_LED);
382LUTON_P(26, SFP, PHY_LED);
383LUTON_P(27, SFP, PHY_LED);
384LUTON_P(28, SFP, PHY_LED);
385LUTON_P(29, PWM, NONE);
386LUTON_P(30, UART, NONE);
387LUTON_P(31, UART, NONE);
388
389#define LUTON_PIN(n) { \
390 .number = n, \
391 .name = "GPIO_"#n, \
392 .drv_data = &luton_pin_##n \
393}
394
395static const struct pinctrl_pin_desc luton_pins[] = {
396 LUTON_PIN(0),
397 LUTON_PIN(1),
398 LUTON_PIN(2),
399 LUTON_PIN(3),
400 LUTON_PIN(4),
401 LUTON_PIN(5),
402 LUTON_PIN(6),
403 LUTON_PIN(7),
404 LUTON_PIN(8),
405 LUTON_PIN(9),
406 LUTON_PIN(10),
407 LUTON_PIN(11),
408 LUTON_PIN(12),
409 LUTON_PIN(13),
410 LUTON_PIN(14),
411 LUTON_PIN(15),
412 LUTON_PIN(16),
413 LUTON_PIN(17),
414 LUTON_PIN(18),
415 LUTON_PIN(19),
416 LUTON_PIN(20),
417 LUTON_PIN(21),
418 LUTON_PIN(22),
419 LUTON_PIN(23),
420 LUTON_PIN(24),
421 LUTON_PIN(25),
422 LUTON_PIN(26),
423 LUTON_PIN(27),
424 LUTON_PIN(28),
425 LUTON_PIN(29),
426 LUTON_PIN(30),
427 LUTON_PIN(31),
428};
429
430#define SERVAL_P(p, f0, f1, f2) \
431static struct ocelot_pin_caps serval_pin_##p = { \
432 .pin = p, \
433 .functions = { \
434 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \
435 }, \
436}
437
438SERVAL_P(0, SG0, NONE, NONE);
439SERVAL_P(1, SG0, NONE, NONE);
440SERVAL_P(2, SG0, NONE, NONE);
441SERVAL_P(3, SG0, NONE, NONE);
442SERVAL_P(4, TACHO, NONE, NONE);
443SERVAL_P(5, PWM, NONE, NONE);
444SERVAL_P(6, TWI, NONE, NONE);
445SERVAL_P(7, TWI, NONE, NONE);
446SERVAL_P(8, SI, NONE, NONE);
447SERVAL_P(9, SI, MD, NONE);
448SERVAL_P(10, SI, MD, NONE);
449SERVAL_P(11, SFP, MD, TWI_SCL_M);
450SERVAL_P(12, SFP, MD, TWI_SCL_M);
451SERVAL_P(13, SFP, UART2, TWI_SCL_M);
452SERVAL_P(14, SFP, UART2, TWI_SCL_M);
453SERVAL_P(15, SFP, PTP0, TWI_SCL_M);
454SERVAL_P(16, SFP, PTP0, TWI_SCL_M);
455SERVAL_P(17, SFP, PCI_WAKE, TWI_SCL_M);
456SERVAL_P(18, SFP, NONE, TWI_SCL_M);
457SERVAL_P(19, SFP, NONE, TWI_SCL_M);
458SERVAL_P(20, SFP, NONE, TWI_SCL_M);
459SERVAL_P(21, SFP, NONE, TWI_SCL_M);
460SERVAL_P(22, NONE, NONE, NONE);
461SERVAL_P(23, NONE, NONE, NONE);
462SERVAL_P(24, NONE, NONE, NONE);
463SERVAL_P(25, NONE, NONE, NONE);
464SERVAL_P(26, UART, NONE, NONE);
465SERVAL_P(27, UART, NONE, NONE);
466SERVAL_P(28, IRQ0, NONE, NONE);
467SERVAL_P(29, IRQ1, NONE, NONE);
468SERVAL_P(30, PTP0, NONE, NONE);
469SERVAL_P(31, PTP0, NONE, NONE);
470
471#define SERVAL_PIN(n) { \
472 .number = n, \
473 .name = "GPIO_"#n, \
474 .drv_data = &serval_pin_##n \
475}
476
477static const struct pinctrl_pin_desc serval_pins[] = {
478 SERVAL_PIN(0),
479 SERVAL_PIN(1),
480 SERVAL_PIN(2),
481 SERVAL_PIN(3),
482 SERVAL_PIN(4),
483 SERVAL_PIN(5),
484 SERVAL_PIN(6),
485 SERVAL_PIN(7),
486 SERVAL_PIN(8),
487 SERVAL_PIN(9),
488 SERVAL_PIN(10),
489 SERVAL_PIN(11),
490 SERVAL_PIN(12),
491 SERVAL_PIN(13),
492 SERVAL_PIN(14),
493 SERVAL_PIN(15),
494 SERVAL_PIN(16),
495 SERVAL_PIN(17),
496 SERVAL_PIN(18),
497 SERVAL_PIN(19),
498 SERVAL_PIN(20),
499 SERVAL_PIN(21),
500 SERVAL_PIN(22),
501 SERVAL_PIN(23),
502 SERVAL_PIN(24),
503 SERVAL_PIN(25),
504 SERVAL_PIN(26),
505 SERVAL_PIN(27),
506 SERVAL_PIN(28),
507 SERVAL_PIN(29),
508 SERVAL_PIN(30),
509 SERVAL_PIN(31),
510};
511
512#define OCELOT_P(p, f0, f1, f2) \
513static struct ocelot_pin_caps ocelot_pin_##p = { \
514 .pin = p, \
515 .functions = { \
516 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \
517 }, \
518}
519
520OCELOT_P(0, SG0, NONE, NONE);
521OCELOT_P(1, SG0, NONE, NONE);
522OCELOT_P(2, SG0, NONE, NONE);
523OCELOT_P(3, SG0, NONE, NONE);
524OCELOT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M);
525OCELOT_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE);
526OCELOT_P(6, UART, TWI_SCL_M, NONE);
527OCELOT_P(7, UART, TWI_SCL_M, NONE);
528OCELOT_P(8, SI, TWI_SCL_M, IRQ0_OUT);
529OCELOT_P(9, SI, TWI_SCL_M, IRQ1_OUT);
530OCELOT_P(10, PTP2, TWI_SCL_M, SFP);
531OCELOT_P(11, PTP3, TWI_SCL_M, SFP);
532OCELOT_P(12, UART2, TWI_SCL_M, SFP);
533OCELOT_P(13, UART2, TWI_SCL_M, SFP);
534OCELOT_P(14, MIIM, TWI_SCL_M, SFP);
535OCELOT_P(15, MIIM, TWI_SCL_M, SFP);
536OCELOT_P(16, TWI, NONE, SI);
537OCELOT_P(17, TWI, TWI_SCL_M, SI);
538OCELOT_P(18, PTP0, TWI_SCL_M, NONE);
539OCELOT_P(19, PTP1, TWI_SCL_M, NONE);
540OCELOT_P(20, RECO_CLK, TACHO, TWI_SCL_M);
541OCELOT_P(21, RECO_CLK, PWM, TWI_SCL_M);
542
543#define OCELOT_PIN(n) { \
544 .number = n, \
545 .name = "GPIO_"#n, \
546 .drv_data = &ocelot_pin_##n \
547}
548
549static const struct pinctrl_pin_desc ocelot_pins[] = {
550 OCELOT_PIN(0),
551 OCELOT_PIN(1),
552 OCELOT_PIN(2),
553 OCELOT_PIN(3),
554 OCELOT_PIN(4),
555 OCELOT_PIN(5),
556 OCELOT_PIN(6),
557 OCELOT_PIN(7),
558 OCELOT_PIN(8),
559 OCELOT_PIN(9),
560 OCELOT_PIN(10),
561 OCELOT_PIN(11),
562 OCELOT_PIN(12),
563 OCELOT_PIN(13),
564 OCELOT_PIN(14),
565 OCELOT_PIN(15),
566 OCELOT_PIN(16),
567 OCELOT_PIN(17),
568 OCELOT_PIN(18),
569 OCELOT_PIN(19),
570 OCELOT_PIN(20),
571 OCELOT_PIN(21),
572};
573
574#define JAGUAR2_P(p, f0, f1) \
575static struct ocelot_pin_caps jaguar2_pin_##p = { \
576 .pin = p, \
577 .functions = { \
578 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE \
579 }, \
580}
581
582JAGUAR2_P(0, SG0, NONE);
583JAGUAR2_P(1, SG0, NONE);
584JAGUAR2_P(2, SG0, NONE);
585JAGUAR2_P(3, SG0, NONE);
586JAGUAR2_P(4, SG1, NONE);
587JAGUAR2_P(5, SG1, NONE);
588JAGUAR2_P(6, IRQ0_IN, IRQ0_OUT);
589JAGUAR2_P(7, IRQ1_IN, IRQ1_OUT);
590JAGUAR2_P(8, PTP0, NONE);
591JAGUAR2_P(9, PTP1, NONE);
592JAGUAR2_P(10, UART, NONE);
593JAGUAR2_P(11, UART, NONE);
594JAGUAR2_P(12, SG1, NONE);
595JAGUAR2_P(13, SG1, NONE);
596JAGUAR2_P(14, TWI, TWI_SCL_M);
597JAGUAR2_P(15, TWI, NONE);
598JAGUAR2_P(16, SI, TWI_SCL_M);
599JAGUAR2_P(17, SI, TWI_SCL_M);
600JAGUAR2_P(18, SI, TWI_SCL_M);
601JAGUAR2_P(19, PCI_WAKE, NONE);
602JAGUAR2_P(20, IRQ0_OUT, TWI_SCL_M);
603JAGUAR2_P(21, IRQ1_OUT, TWI_SCL_M);
604JAGUAR2_P(22, TACHO, NONE);
605JAGUAR2_P(23, PWM, NONE);
606JAGUAR2_P(24, UART2, NONE);
607JAGUAR2_P(25, UART2, SI);
608JAGUAR2_P(26, PTP2, SI);
609JAGUAR2_P(27, PTP3, SI);
610JAGUAR2_P(28, TWI2, SI);
611JAGUAR2_P(29, TWI2, SI);
612JAGUAR2_P(30, SG2, SI);
613JAGUAR2_P(31, SG2, SI);
614JAGUAR2_P(32, SG2, SI);
615JAGUAR2_P(33, SG2, SI);
616JAGUAR2_P(34, NONE, TWI_SCL_M);
617JAGUAR2_P(35, NONE, TWI_SCL_M);
618JAGUAR2_P(36, NONE, TWI_SCL_M);
619JAGUAR2_P(37, NONE, TWI_SCL_M);
620JAGUAR2_P(38, NONE, TWI_SCL_M);
621JAGUAR2_P(39, NONE, TWI_SCL_M);
622JAGUAR2_P(40, NONE, TWI_SCL_M);
623JAGUAR2_P(41, NONE, TWI_SCL_M);
624JAGUAR2_P(42, NONE, TWI_SCL_M);
625JAGUAR2_P(43, NONE, TWI_SCL_M);
626JAGUAR2_P(44, NONE, SFP);
627JAGUAR2_P(45, NONE, SFP);
628JAGUAR2_P(46, NONE, SFP);
629JAGUAR2_P(47, NONE, SFP);
630JAGUAR2_P(48, SFP, NONE);
631JAGUAR2_P(49, SFP, SI);
632JAGUAR2_P(50, SFP, SI);
633JAGUAR2_P(51, SFP, SI);
634JAGUAR2_P(52, SFP, NONE);
635JAGUAR2_P(53, SFP, NONE);
636JAGUAR2_P(54, SFP, NONE);
637JAGUAR2_P(55, SFP, NONE);
638JAGUAR2_P(56, MIIM, SFP);
639JAGUAR2_P(57, MIIM, SFP);
640JAGUAR2_P(58, MIIM, SFP);
641JAGUAR2_P(59, MIIM, SFP);
642JAGUAR2_P(60, NONE, NONE);
643JAGUAR2_P(61, NONE, NONE);
644JAGUAR2_P(62, NONE, NONE);
645JAGUAR2_P(63, NONE, NONE);
646
647#define JAGUAR2_PIN(n) { \
648 .number = n, \
649 .name = "GPIO_"#n, \
650 .drv_data = &jaguar2_pin_##n \
651}
652
653static const struct pinctrl_pin_desc jaguar2_pins[] = {
654 JAGUAR2_PIN(0),
655 JAGUAR2_PIN(1),
656 JAGUAR2_PIN(2),
657 JAGUAR2_PIN(3),
658 JAGUAR2_PIN(4),
659 JAGUAR2_PIN(5),
660 JAGUAR2_PIN(6),
661 JAGUAR2_PIN(7),
662 JAGUAR2_PIN(8),
663 JAGUAR2_PIN(9),
664 JAGUAR2_PIN(10),
665 JAGUAR2_PIN(11),
666 JAGUAR2_PIN(12),
667 JAGUAR2_PIN(13),
668 JAGUAR2_PIN(14),
669 JAGUAR2_PIN(15),
670 JAGUAR2_PIN(16),
671 JAGUAR2_PIN(17),
672 JAGUAR2_PIN(18),
673 JAGUAR2_PIN(19),
674 JAGUAR2_PIN(20),
675 JAGUAR2_PIN(21),
676 JAGUAR2_PIN(22),
677 JAGUAR2_PIN(23),
678 JAGUAR2_PIN(24),
679 JAGUAR2_PIN(25),
680 JAGUAR2_PIN(26),
681 JAGUAR2_PIN(27),
682 JAGUAR2_PIN(28),
683 JAGUAR2_PIN(29),
684 JAGUAR2_PIN(30),
685 JAGUAR2_PIN(31),
686 JAGUAR2_PIN(32),
687 JAGUAR2_PIN(33),
688 JAGUAR2_PIN(34),
689 JAGUAR2_PIN(35),
690 JAGUAR2_PIN(36),
691 JAGUAR2_PIN(37),
692 JAGUAR2_PIN(38),
693 JAGUAR2_PIN(39),
694 JAGUAR2_PIN(40),
695 JAGUAR2_PIN(41),
696 JAGUAR2_PIN(42),
697 JAGUAR2_PIN(43),
698 JAGUAR2_PIN(44),
699 JAGUAR2_PIN(45),
700 JAGUAR2_PIN(46),
701 JAGUAR2_PIN(47),
702 JAGUAR2_PIN(48),
703 JAGUAR2_PIN(49),
704 JAGUAR2_PIN(50),
705 JAGUAR2_PIN(51),
706 JAGUAR2_PIN(52),
707 JAGUAR2_PIN(53),
708 JAGUAR2_PIN(54),
709 JAGUAR2_PIN(55),
710 JAGUAR2_PIN(56),
711 JAGUAR2_PIN(57),
712 JAGUAR2_PIN(58),
713 JAGUAR2_PIN(59),
714 JAGUAR2_PIN(60),
715 JAGUAR2_PIN(61),
716 JAGUAR2_PIN(62),
717 JAGUAR2_PIN(63),
718};
719
720#define SERVALT_P(p, f0, f1, f2) \
721static struct ocelot_pin_caps servalt_pin_##p = { \
722 .pin = p, \
723 .functions = { \
724 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \
725 }, \
726}
727
728SERVALT_P(0, SG0, NONE, NONE);
729SERVALT_P(1, SG0, NONE, NONE);
730SERVALT_P(2, SG0, NONE, NONE);
731SERVALT_P(3, SG0, NONE, NONE);
732SERVALT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M);
733SERVALT_P(5, IRQ1_IN, IRQ1_OUT, TWI_SCL_M);
734SERVALT_P(6, UART, NONE, NONE);
735SERVALT_P(7, UART, NONE, NONE);
736SERVALT_P(8, SI, SFP, TWI_SCL_M);
737SERVALT_P(9, PCI_WAKE, SFP, SI);
738SERVALT_P(10, PTP0, SFP, TWI_SCL_M);
739SERVALT_P(11, PTP1, SFP, TWI_SCL_M);
740SERVALT_P(12, REF_CLK, SFP, TWI_SCL_M);
741SERVALT_P(13, REF_CLK, SFP, TWI_SCL_M);
742SERVALT_P(14, REF_CLK, IRQ0_OUT, SI);
743SERVALT_P(15, REF_CLK, IRQ1_OUT, SI);
744SERVALT_P(16, TACHO, SFP, SI);
745SERVALT_P(17, PWM, NONE, TWI_SCL_M);
746SERVALT_P(18, PTP2, SFP, SI);
747SERVALT_P(19, PTP3, SFP, SI);
748SERVALT_P(20, UART2, SFP, SI);
749SERVALT_P(21, UART2, NONE, NONE);
750SERVALT_P(22, MIIM, SFP, TWI2);
751SERVALT_P(23, MIIM, SFP, TWI2);
752SERVALT_P(24, TWI, NONE, NONE);
753SERVALT_P(25, TWI, SFP, TWI_SCL_M);
754SERVALT_P(26, TWI_SCL_M, SFP, SI);
755SERVALT_P(27, TWI_SCL_M, SFP, SI);
756SERVALT_P(28, TWI_SCL_M, SFP, SI);
757SERVALT_P(29, TWI_SCL_M, NONE, NONE);
758SERVALT_P(30, TWI_SCL_M, NONE, NONE);
759SERVALT_P(31, TWI_SCL_M, NONE, NONE);
760SERVALT_P(32, TWI_SCL_M, NONE, NONE);
761SERVALT_P(33, RCVRD_CLK, NONE, NONE);
762SERVALT_P(34, RCVRD_CLK, NONE, NONE);
763SERVALT_P(35, RCVRD_CLK, NONE, NONE);
764SERVALT_P(36, RCVRD_CLK, NONE, NONE);
765
766#define SERVALT_PIN(n) { \
767 .number = n, \
768 .name = "GPIO_"#n, \
769 .drv_data = &servalt_pin_##n \
770}
771
772static const struct pinctrl_pin_desc servalt_pins[] = {
773 SERVALT_PIN(0),
774 SERVALT_PIN(1),
775 SERVALT_PIN(2),
776 SERVALT_PIN(3),
777 SERVALT_PIN(4),
778 SERVALT_PIN(5),
779 SERVALT_PIN(6),
780 SERVALT_PIN(7),
781 SERVALT_PIN(8),
782 SERVALT_PIN(9),
783 SERVALT_PIN(10),
784 SERVALT_PIN(11),
785 SERVALT_PIN(12),
786 SERVALT_PIN(13),
787 SERVALT_PIN(14),
788 SERVALT_PIN(15),
789 SERVALT_PIN(16),
790 SERVALT_PIN(17),
791 SERVALT_PIN(18),
792 SERVALT_PIN(19),
793 SERVALT_PIN(20),
794 SERVALT_PIN(21),
795 SERVALT_PIN(22),
796 SERVALT_PIN(23),
797 SERVALT_PIN(24),
798 SERVALT_PIN(25),
799 SERVALT_PIN(26),
800 SERVALT_PIN(27),
801 SERVALT_PIN(28),
802 SERVALT_PIN(29),
803 SERVALT_PIN(30),
804 SERVALT_PIN(31),
805 SERVALT_PIN(32),
806 SERVALT_PIN(33),
807 SERVALT_PIN(34),
808 SERVALT_PIN(35),
809 SERVALT_PIN(36),
810};
811
812#define SPARX5_P(p, f0, f1, f2) \
813static struct ocelot_pin_caps sparx5_pin_##p = { \
814 .pin = p, \
815 .functions = { \
816 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \
817 }, \
818}
819
820SPARX5_P(0, SG0, PLL_STAT, NONE);
821SPARX5_P(1, SG0, NONE, NONE);
822SPARX5_P(2, SG0, NONE, NONE);
823SPARX5_P(3, SG0, NONE, NONE);
824SPARX5_P(4, SG1, NONE, NONE);
825SPARX5_P(5, SG1, NONE, NONE);
826SPARX5_P(6, IRQ0_IN, IRQ0_OUT, SFP);
827SPARX5_P(7, IRQ1_IN, IRQ1_OUT, SFP);
828SPARX5_P(8, PTP0, NONE, SFP);
829SPARX5_P(9, PTP1, SFP, TWI_SCL_M);
830SPARX5_P(10, UART, NONE, NONE);
831SPARX5_P(11, UART, NONE, NONE);
832SPARX5_P(12, SG1, NONE, NONE);
833SPARX5_P(13, SG1, NONE, NONE);
834SPARX5_P(14, TWI, TWI_SCL_M, NONE);
835SPARX5_P(15, TWI, NONE, NONE);
836SPARX5_P(16, SI, TWI_SCL_M, SFP);
837SPARX5_P(17, SI, TWI_SCL_M, SFP);
838SPARX5_P(18, SI, TWI_SCL_M, SFP);
839SPARX5_P(19, PCI_WAKE, TWI_SCL_M, SFP);
840SPARX5_P(20, IRQ0_OUT, TWI_SCL_M, SFP);
841SPARX5_P(21, IRQ1_OUT, TACHO, SFP);
842SPARX5_P(22, TACHO, IRQ0_OUT, TWI_SCL_M);
843SPARX5_P(23, PWM, UART3, TWI_SCL_M);
844SPARX5_P(24, PTP2, UART3, TWI_SCL_M);
845SPARX5_P(25, PTP3, SI, TWI_SCL_M);
846SPARX5_P(26, UART2, SI, TWI_SCL_M);
847SPARX5_P(27, UART2, SI, TWI_SCL_M);
848SPARX5_P(28, TWI2, SI, SFP);
849SPARX5_P(29, TWI2, SI, SFP);
850SPARX5_P(30, SG2, SI, PWM);
851SPARX5_P(31, SG2, SI, TWI_SCL_M);
852SPARX5_P(32, SG2, SI, TWI_SCL_M);
853SPARX5_P(33, SG2, SI, SFP);
854SPARX5_P(34, NONE, TWI_SCL_M, EMMC);
855SPARX5_P(35, SFP, TWI_SCL_M, EMMC);
856SPARX5_P(36, SFP, TWI_SCL_M, EMMC);
857SPARX5_P(37, SFP, NONE, EMMC);
858SPARX5_P(38, NONE, TWI_SCL_M, EMMC);
859SPARX5_P(39, SI2, TWI_SCL_M, EMMC);
860SPARX5_P(40, SI2, TWI_SCL_M, EMMC);
861SPARX5_P(41, SI2, TWI_SCL_M, EMMC);
862SPARX5_P(42, SI2, TWI_SCL_M, EMMC);
863SPARX5_P(43, SI2, TWI_SCL_M, EMMC);
864SPARX5_P(44, SI, SFP, EMMC);
865SPARX5_P(45, SI, SFP, EMMC);
866SPARX5_P(46, NONE, SFP, EMMC);
867SPARX5_P(47, NONE, SFP, EMMC);
868SPARX5_P(48, TWI3, SI, SFP);
869SPARX5_P(49, TWI3, NONE, SFP);
870SPARX5_P(50, SFP, NONE, TWI_SCL_M);
871SPARX5_P(51, SFP, SI, TWI_SCL_M);
872SPARX5_P(52, SFP, MIIM, TWI_SCL_M);
873SPARX5_P(53, SFP, MIIM, TWI_SCL_M);
874SPARX5_P(54, SFP, PTP2, TWI_SCL_M);
875SPARX5_P(55, SFP, PTP3, PCI_WAKE);
876SPARX5_P(56, MIIM, SFP, TWI_SCL_M);
877SPARX5_P(57, MIIM, SFP, TWI_SCL_M);
878SPARX5_P(58, MIIM, SFP, TWI_SCL_M);
879SPARX5_P(59, MIIM, SFP, NONE);
880SPARX5_P(60, RECO_CLK, NONE, NONE);
881SPARX5_P(61, RECO_CLK, NONE, NONE);
882SPARX5_P(62, RECO_CLK, PLL_STAT, NONE);
883SPARX5_P(63, RECO_CLK, NONE, NONE);
884
885#define SPARX5_PIN(n) { \
886 .number = n, \
887 .name = "GPIO_"#n, \
888 .drv_data = &sparx5_pin_##n \
889}
890
891static const struct pinctrl_pin_desc sparx5_pins[] = {
892 SPARX5_PIN(0),
893 SPARX5_PIN(1),
894 SPARX5_PIN(2),
895 SPARX5_PIN(3),
896 SPARX5_PIN(4),
897 SPARX5_PIN(5),
898 SPARX5_PIN(6),
899 SPARX5_PIN(7),
900 SPARX5_PIN(8),
901 SPARX5_PIN(9),
902 SPARX5_PIN(10),
903 SPARX5_PIN(11),
904 SPARX5_PIN(12),
905 SPARX5_PIN(13),
906 SPARX5_PIN(14),
907 SPARX5_PIN(15),
908 SPARX5_PIN(16),
909 SPARX5_PIN(17),
910 SPARX5_PIN(18),
911 SPARX5_PIN(19),
912 SPARX5_PIN(20),
913 SPARX5_PIN(21),
914 SPARX5_PIN(22),
915 SPARX5_PIN(23),
916 SPARX5_PIN(24),
917 SPARX5_PIN(25),
918 SPARX5_PIN(26),
919 SPARX5_PIN(27),
920 SPARX5_PIN(28),
921 SPARX5_PIN(29),
922 SPARX5_PIN(30),
923 SPARX5_PIN(31),
924 SPARX5_PIN(32),
925 SPARX5_PIN(33),
926 SPARX5_PIN(34),
927 SPARX5_PIN(35),
928 SPARX5_PIN(36),
929 SPARX5_PIN(37),
930 SPARX5_PIN(38),
931 SPARX5_PIN(39),
932 SPARX5_PIN(40),
933 SPARX5_PIN(41),
934 SPARX5_PIN(42),
935 SPARX5_PIN(43),
936 SPARX5_PIN(44),
937 SPARX5_PIN(45),
938 SPARX5_PIN(46),
939 SPARX5_PIN(47),
940 SPARX5_PIN(48),
941 SPARX5_PIN(49),
942 SPARX5_PIN(50),
943 SPARX5_PIN(51),
944 SPARX5_PIN(52),
945 SPARX5_PIN(53),
946 SPARX5_PIN(54),
947 SPARX5_PIN(55),
948 SPARX5_PIN(56),
949 SPARX5_PIN(57),
950 SPARX5_PIN(58),
951 SPARX5_PIN(59),
952 SPARX5_PIN(60),
953 SPARX5_PIN(61),
954 SPARX5_PIN(62),
955 SPARX5_PIN(63),
956};
957
958#define LAN966X_P(p, f0, f1, f2, f3, f4, f5, f6, f7) \
959static struct ocelot_pin_caps lan966x_pin_##p = { \
960 .pin = p, \
961 .functions = { \
962 FUNC_##f0, FUNC_##f1, FUNC_##f2, \
963 FUNC_##f3 \
964 }, \
965 .a_functions = { \
966 FUNC_##f4, FUNC_##f5, FUNC_##f6, \
967 FUNC_##f7 \
968 }, \
969}
970
971/* Pinmuxing table taken from data sheet */
972/* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 */
973LAN966X_P(0, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);
974LAN966X_P(1, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);
975LAN966X_P(2, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);
976LAN966X_P(3, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);
977LAN966X_P(4, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);
978LAN966X_P(5, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);
979LAN966X_P(6, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);
980LAN966X_P(7, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);
981LAN966X_P(8, GPIO, FC0_a, USB_H_b, NONE, USB_S_b, NONE, NONE, R);
982LAN966X_P(9, GPIO, FC0_a, USB_H_b, NONE, NONE, NONE, NONE, R);
983LAN966X_P(10, GPIO, FC0_a, NONE, NONE, NONE, NONE, NONE, R);
984LAN966X_P(11, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R);
985LAN966X_P(12, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R);
986LAN966X_P(13, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R);
987LAN966X_P(14, GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R);
988LAN966X_P(15, GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R);
989LAN966X_P(16, GPIO, FC2_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R);
990LAN966X_P(17, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R);
991LAN966X_P(18, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R);
992LAN966X_P(19, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R);
993LAN966X_P(20, GPIO, FC4_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, NONE, R);
994LAN966X_P(21, GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R);
995LAN966X_P(22, GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R);
996LAN966X_P(23, GPIO, NONE, NONE, NONE, OB_TRG_a, NONE, NONE, R);
997LAN966X_P(24, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_IN_c, TACHO_a, R);
998LAN966X_P(25, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_OUT_c, SFP_SD, R);
999LAN966X_P(26, GPIO, FC0_b, IB_TRG_a, USB_S_c, OB_TRG_a, CAN0_a, SFP_SD, R);
1000LAN966X_P(27, GPIO, NONE, NONE, NONE, OB_TRG_a, CAN0_a, PWM_a, R);
1001LAN966X_P(28, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, IRQ_OUT_c, SFP_SD, R);
1002LAN966X_P(29, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, NONE, NONE, R);
1003LAN966X_P(30, GPIO, FC3_c, CAN1, CLKMON, OB_TRG, RECO_b, NONE, R);
1004LAN966X_P(31, GPIO, FC3_c, CAN1, CLKMON, OB_TRG, RECO_b, NONE, R);
1005LAN966X_P(32, GPIO, FC3_c, NONE, SGPIO_a, NONE, MIIM_Sa, NONE, R);
1006LAN966X_P(33, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R);
1007LAN966X_P(34, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R);
1008LAN966X_P(35, GPIO, FC1_b, PTPSYNC_0, SGPIO_a, CAN0_b, NONE, NONE, R);
1009LAN966X_P(36, GPIO, NONE, PTPSYNC_1, NONE, CAN0_b, NONE, NONE, R);
1010LAN966X_P(37, GPIO, FC_SHRD0, PTPSYNC_2, TWI_SLC_GATE_AD, NONE, NONE, NONE, R);
1011LAN966X_P(38, GPIO, NONE, PTPSYNC_3, NONE, NONE, NONE, NONE, R);
1012LAN966X_P(39, GPIO, NONE, PTPSYNC_4, NONE, NONE, NONE, NONE, R);
1013LAN966X_P(40, GPIO, FC_SHRD1, PTPSYNC_5, NONE, NONE, NONE, NONE, R);
1014LAN966X_P(41, GPIO, FC_SHRD2, PTPSYNC_6, TWI_SLC_GATE_AD, NONE, NONE, NONE, R);
1015LAN966X_P(42, GPIO, FC_SHRD3, PTPSYNC_7, TWI_SLC_GATE_AD, NONE, NONE, NONE, R);
1016LAN966X_P(43, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R);
1017LAN966X_P(44, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R);
1018LAN966X_P(45, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, NONE, IRQ_IN_a, R);
1019LAN966X_P(46, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD4, IRQ_IN_a, R);
1020LAN966X_P(47, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD5, IRQ_IN_a, R);
1021LAN966X_P(48, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD6, IRQ_IN_a, R);
1022LAN966X_P(49, GPIO, FC_SHRD7, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, IRQ_IN_a, R);
1023LAN966X_P(50, GPIO, FC_SHRD16, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, NONE, R);
1024LAN966X_P(51, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, PWM_b, IRQ_IN_b, R);
1025LAN966X_P(52, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TACHO_b, IRQ_IN_b, R);
1026LAN966X_P(53, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, NONE, IRQ_IN_b, R);
1027LAN966X_P(54, GPIO, FC_SHRD8, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R);
1028LAN966X_P(55, GPIO, FC_SHRD9, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R);
1029LAN966X_P(56, GPIO, FC4_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, FC_SHRD10, IRQ_IN_b, R);
1030LAN966X_P(57, GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD11, IRQ_IN_b, R);
1031LAN966X_P(58, GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD12, IRQ_IN_b, R);
1032LAN966X_P(59, GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R);
1033LAN966X_P(60, GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R);
1034LAN966X_P(61, GPIO, QSPI1, NONE, SGPIO_b, FC0_c, MIIM_Sb, NONE, R);
1035LAN966X_P(62, GPIO, QSPI1, FC_SHRD13, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R);
1036LAN966X_P(63, GPIO, QSPI1, FC_SHRD14, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R);
1037LAN966X_P(64, GPIO, QSPI1, FC4_c, SGPIO_b, FC_SHRD15, TWI_SLC_GATE, SFP_SD, R);
1038LAN966X_P(65, GPIO, USB_H_a, FC4_c, NONE, IRQ_OUT_c, TWI_SLC_GATE_AD, NONE, R);
1039LAN966X_P(66, GPIO, USB_H_a, FC4_c, USB_S_a, IRQ_OUT_c, IRQ_IN_c, NONE, R);
1040LAN966X_P(67, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R);
1041LAN966X_P(68, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R);
1042LAN966X_P(69, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R);
1043LAN966X_P(70, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R);
1044LAN966X_P(71, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R);
1045LAN966X_P(72, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R);
1046LAN966X_P(73, GPIO, EMMC, NONE, NONE, SD, NONE, NONE, R);
1047LAN966X_P(74, GPIO, EMMC, NONE, FC_SHRD17, SD, TWI_SLC_GATE, NONE, R);
1048LAN966X_P(75, GPIO, EMMC, NONE, FC_SHRD18, SD, TWI_SLC_GATE, NONE, R);
1049LAN966X_P(76, GPIO, EMMC, NONE, FC_SHRD19, SD, TWI_SLC_GATE, NONE, R);
1050LAN966X_P(77, GPIO, EMMC_SD, NONE, FC_SHRD20, NONE, TWI_SLC_GATE, NONE, R);
1051
1052#define LAN966X_PIN(n) { \
1053 .number = n, \
1054 .name = "GPIO_"#n, \
1055 .drv_data = &lan966x_pin_##n \
1056}
1057
1058static const struct pinctrl_pin_desc lan966x_pins[] = {
1059 LAN966X_PIN(0),
1060 LAN966X_PIN(1),
1061 LAN966X_PIN(2),
1062 LAN966X_PIN(3),
1063 LAN966X_PIN(4),
1064 LAN966X_PIN(5),
1065 LAN966X_PIN(6),
1066 LAN966X_PIN(7),
1067 LAN966X_PIN(8),
1068 LAN966X_PIN(9),
1069 LAN966X_PIN(10),
1070 LAN966X_PIN(11),
1071 LAN966X_PIN(12),
1072 LAN966X_PIN(13),
1073 LAN966X_PIN(14),
1074 LAN966X_PIN(15),
1075 LAN966X_PIN(16),
1076 LAN966X_PIN(17),
1077 LAN966X_PIN(18),
1078 LAN966X_PIN(19),
1079 LAN966X_PIN(20),
1080 LAN966X_PIN(21),
1081 LAN966X_PIN(22),
1082 LAN966X_PIN(23),
1083 LAN966X_PIN(24),
1084 LAN966X_PIN(25),
1085 LAN966X_PIN(26),
1086 LAN966X_PIN(27),
1087 LAN966X_PIN(28),
1088 LAN966X_PIN(29),
1089 LAN966X_PIN(30),
1090 LAN966X_PIN(31),
1091 LAN966X_PIN(32),
1092 LAN966X_PIN(33),
1093 LAN966X_PIN(34),
1094 LAN966X_PIN(35),
1095 LAN966X_PIN(36),
1096 LAN966X_PIN(37),
1097 LAN966X_PIN(38),
1098 LAN966X_PIN(39),
1099 LAN966X_PIN(40),
1100 LAN966X_PIN(41),
1101 LAN966X_PIN(42),
1102 LAN966X_PIN(43),
1103 LAN966X_PIN(44),
1104 LAN966X_PIN(45),
1105 LAN966X_PIN(46),
1106 LAN966X_PIN(47),
1107 LAN966X_PIN(48),
1108 LAN966X_PIN(49),
1109 LAN966X_PIN(50),
1110 LAN966X_PIN(51),
1111 LAN966X_PIN(52),
1112 LAN966X_PIN(53),
1113 LAN966X_PIN(54),
1114 LAN966X_PIN(55),
1115 LAN966X_PIN(56),
1116 LAN966X_PIN(57),
1117 LAN966X_PIN(58),
1118 LAN966X_PIN(59),
1119 LAN966X_PIN(60),
1120 LAN966X_PIN(61),
1121 LAN966X_PIN(62),
1122 LAN966X_PIN(63),
1123 LAN966X_PIN(64),
1124 LAN966X_PIN(65),
1125 LAN966X_PIN(66),
1126 LAN966X_PIN(67),
1127 LAN966X_PIN(68),
1128 LAN966X_PIN(69),
1129 LAN966X_PIN(70),
1130 LAN966X_PIN(71),
1131 LAN966X_PIN(72),
1132 LAN966X_PIN(73),
1133 LAN966X_PIN(74),
1134 LAN966X_PIN(75),
1135 LAN966X_PIN(76),
1136 LAN966X_PIN(77),
1137};
1138
1139static int ocelot_get_functions_count(struct pinctrl_dev *pctldev)
1140{
1141 return ARRAY_SIZE(ocelot_function_names);
1142}
1143
1144static const char *ocelot_get_function_name(struct pinctrl_dev *pctldev,
1145 unsigned int function)
1146{
1147 return ocelot_function_names[function];
1148}
1149
1150static int ocelot_get_function_groups(struct pinctrl_dev *pctldev,
1151 unsigned int function,
1152 const char *const **groups,
1153 unsigned *const num_groups)
1154{
1155 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1156
1157 *groups = info->func[function].groups;
1158 *num_groups = info->func[function].ngroups;
1159
1160 return 0;
1161}
1162
1163static int ocelot_pin_function_idx(struct ocelot_pinctrl *info,
1164 unsigned int pin, unsigned int function)
1165{
1166 struct ocelot_pin_caps *p = info->desc->pins[pin].drv_data;
1167 int i;
1168
1169 for (i = 0; i < OCELOT_FUNC_PER_PIN; i++) {
1170 if (function == p->functions[i])
1171 return i;
1172
1173 if (function == p->a_functions[i])
1174 return i + OCELOT_FUNC_PER_PIN;
1175 }
1176
1177 return -1;
1178}
1179
1180#define REG_ALT(msb, info, p) (OCELOT_GPIO_ALT0 * (info)->stride + 4 * ((msb) + ((info)->stride * ((p) / 32))))
1181
1182static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev,
1183 unsigned int selector, unsigned int group)
1184{
1185 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1186 struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data;
1187 unsigned int p = pin->pin % 32;
1188 int f;
1189
1190 f = ocelot_pin_function_idx(info, group, selector);
1191 if (f < 0)
1192 return -EINVAL;
1193
1194 /*
1195 * f is encoded on two bits.
1196 * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of
1197 * ALT[1]
1198 * This is racy because both registers can't be updated at the same time
1199 * but it doesn't matter much for now.
1200 * Note: ALT0/ALT1 are organized specially for 64 gpio targets
1201 */
1202 regmap_update_bits(info->map, REG_ALT(0, info, pin->pin),
1203 BIT(p), f << p);
1204 regmap_update_bits(info->map, REG_ALT(1, info, pin->pin),
1205 BIT(p), (f >> 1) << p);
1206
1207 return 0;
1208}
1209
1210static int lan966x_pinmux_set_mux(struct pinctrl_dev *pctldev,
1211 unsigned int selector, unsigned int group)
1212{
1213 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1214 struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data;
1215 unsigned int p = pin->pin % 32;
1216 int f;
1217
1218 f = ocelot_pin_function_idx(info, group, selector);
1219 if (f < 0)
1220 return -EINVAL;
1221
1222 /*
1223 * f is encoded on three bits.
1224 * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of
1225 * ALT[1], bit 2 of f goes in BIT(pin) of ALT[2]
1226 * This is racy because three registers can't be updated at the same time
1227 * but it doesn't matter much for now.
1228 * Note: ALT0/ALT1/ALT2 are organized specially for 78 gpio targets
1229 */
1230 regmap_update_bits(info->map, REG_ALT(0, info, pin->pin),
1231 BIT(p), f << p);
1232 regmap_update_bits(info->map, REG_ALT(1, info, pin->pin),
1233 BIT(p), (f >> 1) << p);
1234 regmap_update_bits(info->map, REG_ALT(2, info, pin->pin),
1235 BIT(p), (f >> 2) << p);
1236
1237 return 0;
1238}
1239
1240#define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32)))
1241
1242static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev,
1243 struct pinctrl_gpio_range *range,
1244 unsigned int pin, bool input)
1245{
1246 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1247 unsigned int p = pin % 32;
1248
1249 regmap_update_bits(info->map, REG(OCELOT_GPIO_OE, info, pin), BIT(p),
1250 input ? 0 : BIT(p));
1251
1252 return 0;
1253}
1254
1255static int ocelot_gpio_request_enable(struct pinctrl_dev *pctldev,
1256 struct pinctrl_gpio_range *range,
1257 unsigned int offset)
1258{
1259 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1260 unsigned int p = offset % 32;
1261
1262 regmap_update_bits(info->map, REG_ALT(0, info, offset),
1263 BIT(p), 0);
1264 regmap_update_bits(info->map, REG_ALT(1, info, offset),
1265 BIT(p), 0);
1266
1267 return 0;
1268}
1269
1270static int lan966x_gpio_request_enable(struct pinctrl_dev *pctldev,
1271 struct pinctrl_gpio_range *range,
1272 unsigned int offset)
1273{
1274 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1275 unsigned int p = offset % 32;
1276
1277 regmap_update_bits(info->map, REG_ALT(0, info, offset),
1278 BIT(p), 0);
1279 regmap_update_bits(info->map, REG_ALT(1, info, offset),
1280 BIT(p), 0);
1281 regmap_update_bits(info->map, REG_ALT(2, info, offset),
1282 BIT(p), 0);
1283
1284 return 0;
1285}
1286
1287static const struct pinmux_ops ocelot_pmx_ops = {
1288 .get_functions_count = ocelot_get_functions_count,
1289 .get_function_name = ocelot_get_function_name,
1290 .get_function_groups = ocelot_get_function_groups,
1291 .set_mux = ocelot_pinmux_set_mux,
1292 .gpio_set_direction = ocelot_gpio_set_direction,
1293 .gpio_request_enable = ocelot_gpio_request_enable,
1294};
1295
1296static const struct pinmux_ops lan966x_pmx_ops = {
1297 .get_functions_count = ocelot_get_functions_count,
1298 .get_function_name = ocelot_get_function_name,
1299 .get_function_groups = ocelot_get_function_groups,
1300 .set_mux = lan966x_pinmux_set_mux,
1301 .gpio_set_direction = ocelot_gpio_set_direction,
1302 .gpio_request_enable = lan966x_gpio_request_enable,
1303};
1304
1305static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev)
1306{
1307 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1308
1309 return info->desc->npins;
1310}
1311
1312static const char *ocelot_pctl_get_group_name(struct pinctrl_dev *pctldev,
1313 unsigned int group)
1314{
1315 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1316
1317 return info->desc->pins[group].name;
1318}
1319
1320static int ocelot_pctl_get_group_pins(struct pinctrl_dev *pctldev,
1321 unsigned int group,
1322 const unsigned int **pins,
1323 unsigned int *num_pins)
1324{
1325 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1326
1327 *pins = &info->desc->pins[group].number;
1328 *num_pins = 1;
1329
1330 return 0;
1331}
1332
1333static int ocelot_hw_get_value(struct ocelot_pinctrl *info,
1334 unsigned int pin,
1335 unsigned int reg,
1336 int *val)
1337{
1338 int ret = -EOPNOTSUPP;
1339
1340 if (info->pincfg) {
1341 const struct ocelot_pincfg_data *opd = info->pincfg_data;
1342 u32 regcfg;
1343
1344 ret = regmap_read(info->pincfg,
1345 pin * regmap_get_reg_stride(info->pincfg),
1346 ®cfg);
1347 if (ret)
1348 return ret;
1349
1350 ret = 0;
1351 switch (reg) {
1352 case PINCONF_BIAS:
1353 *val = regcfg & (opd->pd_bit | opd->pu_bit);
1354 break;
1355
1356 case PINCONF_SCHMITT:
1357 *val = regcfg & opd->schmitt_bit;
1358 break;
1359
1360 case PINCONF_DRIVE_STRENGTH:
1361 *val = regcfg & opd->drive_bits;
1362 break;
1363
1364 default:
1365 ret = -EOPNOTSUPP;
1366 break;
1367 }
1368 }
1369 return ret;
1370}
1371
1372static int ocelot_pincfg_clrsetbits(struct ocelot_pinctrl *info, u32 regaddr,
1373 u32 clrbits, u32 setbits)
1374{
1375 u32 val;
1376 int ret;
1377
1378 ret = regmap_read(info->pincfg,
1379 regaddr * regmap_get_reg_stride(info->pincfg),
1380 &val);
1381 if (ret)
1382 return ret;
1383
1384 val &= ~clrbits;
1385 val |= setbits;
1386
1387 ret = regmap_write(info->pincfg,
1388 regaddr * regmap_get_reg_stride(info->pincfg),
1389 val);
1390
1391 return ret;
1392}
1393
1394static int ocelot_hw_set_value(struct ocelot_pinctrl *info,
1395 unsigned int pin,
1396 unsigned int reg,
1397 int val)
1398{
1399 int ret = -EOPNOTSUPP;
1400
1401 if (info->pincfg) {
1402 const struct ocelot_pincfg_data *opd = info->pincfg_data;
1403
1404 ret = 0;
1405 switch (reg) {
1406 case PINCONF_BIAS:
1407 ret = ocelot_pincfg_clrsetbits(info, pin,
1408 opd->pd_bit | opd->pu_bit,
1409 val);
1410 break;
1411
1412 case PINCONF_SCHMITT:
1413 ret = ocelot_pincfg_clrsetbits(info, pin,
1414 opd->schmitt_bit,
1415 val);
1416 break;
1417
1418 case PINCONF_DRIVE_STRENGTH:
1419 if (val <= 3)
1420 ret = ocelot_pincfg_clrsetbits(info, pin,
1421 opd->drive_bits,
1422 val);
1423 else
1424 ret = -EINVAL;
1425 break;
1426
1427 default:
1428 ret = -EOPNOTSUPP;
1429 break;
1430 }
1431 }
1432 return ret;
1433}
1434
1435static int ocelot_pinconf_get(struct pinctrl_dev *pctldev,
1436 unsigned int pin, unsigned long *config)
1437{
1438 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1439 u32 param = pinconf_to_config_param(*config);
1440 int val, err;
1441
1442 switch (param) {
1443 case PIN_CONFIG_BIAS_DISABLE:
1444 case PIN_CONFIG_BIAS_PULL_UP:
1445 case PIN_CONFIG_BIAS_PULL_DOWN:
1446 err = ocelot_hw_get_value(info, pin, PINCONF_BIAS, &val);
1447 if (err)
1448 return err;
1449 if (param == PIN_CONFIG_BIAS_DISABLE)
1450 val = (val == 0);
1451 else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
1452 val = !!(val & info->pincfg_data->pd_bit);
1453 else /* PIN_CONFIG_BIAS_PULL_UP */
1454 val = !!(val & info->pincfg_data->pu_bit);
1455 break;
1456
1457 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1458 if (!info->pincfg_data->schmitt_bit)
1459 return -EOPNOTSUPP;
1460
1461 err = ocelot_hw_get_value(info, pin, PINCONF_SCHMITT, &val);
1462 if (err)
1463 return err;
1464
1465 val = !!(val & info->pincfg_data->schmitt_bit);
1466 break;
1467
1468 case PIN_CONFIG_DRIVE_STRENGTH:
1469 err = ocelot_hw_get_value(info, pin, PINCONF_DRIVE_STRENGTH,
1470 &val);
1471 if (err)
1472 return err;
1473 break;
1474
1475 case PIN_CONFIG_OUTPUT:
1476 err = regmap_read(info->map, REG(OCELOT_GPIO_OUT, info, pin),
1477 &val);
1478 if (err)
1479 return err;
1480 val = !!(val & BIT(pin % 32));
1481 break;
1482
1483 case PIN_CONFIG_INPUT_ENABLE:
1484 case PIN_CONFIG_OUTPUT_ENABLE:
1485 err = regmap_read(info->map, REG(OCELOT_GPIO_OE, info, pin),
1486 &val);
1487 if (err)
1488 return err;
1489 val = val & BIT(pin % 32);
1490 if (param == PIN_CONFIG_OUTPUT_ENABLE)
1491 val = !!val;
1492 else
1493 val = !val;
1494 break;
1495
1496 default:
1497 return -EOPNOTSUPP;
1498 }
1499
1500 *config = pinconf_to_config_packed(param, val);
1501
1502 return 0;
1503}
1504
1505static int ocelot_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1506 unsigned long *configs, unsigned int num_configs)
1507{
1508 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1509 const struct ocelot_pincfg_data *opd = info->pincfg_data;
1510 u32 param, arg, p;
1511 int cfg, err = 0;
1512
1513 for (cfg = 0; cfg < num_configs; cfg++) {
1514 param = pinconf_to_config_param(configs[cfg]);
1515 arg = pinconf_to_config_argument(configs[cfg]);
1516
1517 switch (param) {
1518 case PIN_CONFIG_BIAS_DISABLE:
1519 case PIN_CONFIG_BIAS_PULL_UP:
1520 case PIN_CONFIG_BIAS_PULL_DOWN:
1521 arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 :
1522 (param == PIN_CONFIG_BIAS_PULL_UP) ?
1523 opd->pu_bit : opd->pd_bit;
1524
1525 err = ocelot_hw_set_value(info, pin, PINCONF_BIAS, arg);
1526 if (err)
1527 goto err;
1528
1529 break;
1530
1531 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1532 if (!opd->schmitt_bit)
1533 return -EOPNOTSUPP;
1534
1535 arg = arg ? opd->schmitt_bit : 0;
1536 err = ocelot_hw_set_value(info, pin, PINCONF_SCHMITT,
1537 arg);
1538 if (err)
1539 goto err;
1540
1541 break;
1542
1543 case PIN_CONFIG_DRIVE_STRENGTH:
1544 err = ocelot_hw_set_value(info, pin,
1545 PINCONF_DRIVE_STRENGTH,
1546 arg);
1547 if (err)
1548 goto err;
1549
1550 break;
1551
1552 case PIN_CONFIG_OUTPUT_ENABLE:
1553 case PIN_CONFIG_INPUT_ENABLE:
1554 case PIN_CONFIG_OUTPUT:
1555 p = pin % 32;
1556 if (arg)
1557 regmap_write(info->map,
1558 REG(OCELOT_GPIO_OUT_SET, info,
1559 pin),
1560 BIT(p));
1561 else
1562 regmap_write(info->map,
1563 REG(OCELOT_GPIO_OUT_CLR, info,
1564 pin),
1565 BIT(p));
1566 regmap_update_bits(info->map,
1567 REG(OCELOT_GPIO_OE, info, pin),
1568 BIT(p),
1569 param == PIN_CONFIG_INPUT_ENABLE ?
1570 0 : BIT(p));
1571 break;
1572
1573 default:
1574 err = -EOPNOTSUPP;
1575 }
1576 }
1577err:
1578 return err;
1579}
1580
1581static const struct pinconf_ops ocelot_confops = {
1582 .is_generic = true,
1583 .pin_config_get = ocelot_pinconf_get,
1584 .pin_config_set = ocelot_pinconf_set,
1585 .pin_config_config_dbg_show = pinconf_generic_dump_config,
1586};
1587
1588static const struct pinctrl_ops ocelot_pctl_ops = {
1589 .get_groups_count = ocelot_pctl_get_groups_count,
1590 .get_group_name = ocelot_pctl_get_group_name,
1591 .get_group_pins = ocelot_pctl_get_group_pins,
1592 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
1593 .dt_free_map = pinconf_generic_dt_free_map,
1594};
1595
1596static struct ocelot_match_data luton_desc = {
1597 .desc = {
1598 .name = "luton-pinctrl",
1599 .pins = luton_pins,
1600 .npins = ARRAY_SIZE(luton_pins),
1601 .pctlops = &ocelot_pctl_ops,
1602 .pmxops = &ocelot_pmx_ops,
1603 .owner = THIS_MODULE,
1604 },
1605};
1606
1607static struct ocelot_match_data serval_desc = {
1608 .desc = {
1609 .name = "serval-pinctrl",
1610 .pins = serval_pins,
1611 .npins = ARRAY_SIZE(serval_pins),
1612 .pctlops = &ocelot_pctl_ops,
1613 .pmxops = &ocelot_pmx_ops,
1614 .owner = THIS_MODULE,
1615 },
1616};
1617
1618static struct ocelot_match_data ocelot_desc = {
1619 .desc = {
1620 .name = "ocelot-pinctrl",
1621 .pins = ocelot_pins,
1622 .npins = ARRAY_SIZE(ocelot_pins),
1623 .pctlops = &ocelot_pctl_ops,
1624 .pmxops = &ocelot_pmx_ops,
1625 .owner = THIS_MODULE,
1626 },
1627};
1628
1629static struct ocelot_match_data jaguar2_desc = {
1630 .desc = {
1631 .name = "jaguar2-pinctrl",
1632 .pins = jaguar2_pins,
1633 .npins = ARRAY_SIZE(jaguar2_pins),
1634 .pctlops = &ocelot_pctl_ops,
1635 .pmxops = &ocelot_pmx_ops,
1636 .owner = THIS_MODULE,
1637 },
1638};
1639
1640static struct ocelot_match_data servalt_desc = {
1641 .desc = {
1642 .name = "servalt-pinctrl",
1643 .pins = servalt_pins,
1644 .npins = ARRAY_SIZE(servalt_pins),
1645 .pctlops = &ocelot_pctl_ops,
1646 .pmxops = &ocelot_pmx_ops,
1647 .owner = THIS_MODULE,
1648 },
1649};
1650
1651static struct ocelot_match_data sparx5_desc = {
1652 .desc = {
1653 .name = "sparx5-pinctrl",
1654 .pins = sparx5_pins,
1655 .npins = ARRAY_SIZE(sparx5_pins),
1656 .pctlops = &ocelot_pctl_ops,
1657 .pmxops = &ocelot_pmx_ops,
1658 .confops = &ocelot_confops,
1659 .owner = THIS_MODULE,
1660 },
1661 .pincfg_data = {
1662 .pd_bit = BIT(4),
1663 .pu_bit = BIT(3),
1664 .drive_bits = GENMASK(1, 0),
1665 .schmitt_bit = BIT(2),
1666 },
1667};
1668
1669static struct ocelot_match_data lan966x_desc = {
1670 .desc = {
1671 .name = "lan966x-pinctrl",
1672 .pins = lan966x_pins,
1673 .npins = ARRAY_SIZE(lan966x_pins),
1674 .pctlops = &ocelot_pctl_ops,
1675 .pmxops = &lan966x_pmx_ops,
1676 .confops = &ocelot_confops,
1677 .owner = THIS_MODULE,
1678 },
1679 .pincfg_data = {
1680 .pd_bit = BIT(3),
1681 .pu_bit = BIT(2),
1682 .drive_bits = GENMASK(1, 0),
1683 },
1684};
1685
1686static int ocelot_create_group_func_map(struct device *dev,
1687 struct ocelot_pinctrl *info)
1688{
1689 int f, npins, i;
1690 u8 *pins = kcalloc(info->desc->npins, sizeof(u8), GFP_KERNEL);
1691
1692 if (!pins)
1693 return -ENOMEM;
1694
1695 for (f = 0; f < FUNC_MAX; f++) {
1696 for (npins = 0, i = 0; i < info->desc->npins; i++) {
1697 if (ocelot_pin_function_idx(info, i, f) >= 0)
1698 pins[npins++] = i;
1699 }
1700
1701 if (!npins)
1702 continue;
1703
1704 info->func[f].ngroups = npins;
1705 info->func[f].groups = devm_kcalloc(dev, npins, sizeof(char *),
1706 GFP_KERNEL);
1707 if (!info->func[f].groups) {
1708 kfree(pins);
1709 return -ENOMEM;
1710 }
1711
1712 for (i = 0; i < npins; i++)
1713 info->func[f].groups[i] =
1714 info->desc->pins[pins[i]].name;
1715 }
1716
1717 kfree(pins);
1718
1719 return 0;
1720}
1721
1722static int ocelot_pinctrl_register(struct platform_device *pdev,
1723 struct ocelot_pinctrl *info)
1724{
1725 int ret;
1726
1727 ret = ocelot_create_group_func_map(&pdev->dev, info);
1728 if (ret) {
1729 dev_err(&pdev->dev, "Unable to create group func map.\n");
1730 return ret;
1731 }
1732
1733 info->pctl = devm_pinctrl_register(&pdev->dev, info->desc, info);
1734 if (IS_ERR(info->pctl)) {
1735 dev_err(&pdev->dev, "Failed to register pinctrl\n");
1736 return PTR_ERR(info->pctl);
1737 }
1738
1739 return 0;
1740}
1741
1742static int ocelot_gpio_get(struct gpio_chip *chip, unsigned int offset)
1743{
1744 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1745 unsigned int val;
1746
1747 regmap_read(info->map, REG(OCELOT_GPIO_IN, info, offset), &val);
1748
1749 return !!(val & BIT(offset % 32));
1750}
1751
1752static void ocelot_gpio_set(struct gpio_chip *chip, unsigned int offset,
1753 int value)
1754{
1755 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1756
1757 if (value)
1758 regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset),
1759 BIT(offset % 32));
1760 else
1761 regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset),
1762 BIT(offset % 32));
1763}
1764
1765static int ocelot_gpio_get_direction(struct gpio_chip *chip,
1766 unsigned int offset)
1767{
1768 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1769 unsigned int val;
1770
1771 regmap_read(info->map, REG(OCELOT_GPIO_OE, info, offset), &val);
1772
1773 if (val & BIT(offset % 32))
1774 return GPIO_LINE_DIRECTION_OUT;
1775
1776 return GPIO_LINE_DIRECTION_IN;
1777}
1778
1779static int ocelot_gpio_direction_output(struct gpio_chip *chip,
1780 unsigned int offset, int value)
1781{
1782 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1783 unsigned int pin = BIT(offset % 32);
1784
1785 if (value)
1786 regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset),
1787 pin);
1788 else
1789 regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset),
1790 pin);
1791
1792 return pinctrl_gpio_direction_output(chip, offset);
1793}
1794
1795static const struct gpio_chip ocelot_gpiolib_chip = {
1796 .request = gpiochip_generic_request,
1797 .free = gpiochip_generic_free,
1798 .set = ocelot_gpio_set,
1799 .get = ocelot_gpio_get,
1800 .get_direction = ocelot_gpio_get_direction,
1801 .direction_input = pinctrl_gpio_direction_input,
1802 .direction_output = ocelot_gpio_direction_output,
1803 .owner = THIS_MODULE,
1804};
1805
1806static void ocelot_irq_mask(struct irq_data *data)
1807{
1808 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
1809 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1810 unsigned int gpio = irqd_to_hwirq(data);
1811
1812 regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio),
1813 BIT(gpio % 32), 0);
1814 gpiochip_disable_irq(chip, gpio);
1815}
1816
1817static void ocelot_irq_work(struct work_struct *work)
1818{
1819 struct ocelot_irq_work *w = container_of(work, struct ocelot_irq_work, irq_work);
1820 struct irq_chip *parent_chip = irq_desc_get_chip(w->irq_desc);
1821 struct gpio_chip *chip = irq_desc_get_chip_data(w->irq_desc);
1822 struct irq_data *data = irq_desc_get_irq_data(w->irq_desc);
1823 unsigned int gpio = irqd_to_hwirq(data);
1824
1825 local_irq_disable();
1826 chained_irq_enter(parent_chip, w->irq_desc);
1827 generic_handle_domain_irq(chip->irq.domain, gpio);
1828 chained_irq_exit(parent_chip, w->irq_desc);
1829 local_irq_enable();
1830
1831 kfree(w);
1832}
1833
1834static void ocelot_irq_unmask_level(struct irq_data *data)
1835{
1836 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
1837 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1838 struct irq_desc *desc = irq_data_to_desc(data);
1839 unsigned int gpio = irqd_to_hwirq(data);
1840 unsigned int bit = BIT(gpio % 32);
1841 bool ack = false, active = false;
1842 u8 trigger_level;
1843 int val;
1844
1845 trigger_level = irqd_get_trigger_type(data);
1846
1847 /* Check if the interrupt line is still active. */
1848 regmap_read(info->map, REG(OCELOT_GPIO_IN, info, gpio), &val);
1849 if ((!(val & bit) && trigger_level == IRQ_TYPE_LEVEL_LOW) ||
1850 (val & bit && trigger_level == IRQ_TYPE_LEVEL_HIGH))
1851 active = true;
1852
1853 /*
1854 * Check if the interrupt controller has seen any changes in the
1855 * interrupt line.
1856 */
1857 regmap_read(info->map, REG(OCELOT_GPIO_INTR, info, gpio), &val);
1858 if (val & bit)
1859 ack = true;
1860
1861 /* Try to clear any rising edges */
1862 if (!active && ack)
1863 regmap_write_bits(info->map, REG(OCELOT_GPIO_INTR, info, gpio),
1864 bit, bit);
1865
1866 /* Enable the interrupt now */
1867 gpiochip_enable_irq(chip, gpio);
1868 regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio),
1869 bit, bit);
1870
1871 /*
1872 * In case the interrupt line is still active then it means that
1873 * there happen another interrupt while the line was active.
1874 * So we missed that one, so we need to kick the interrupt again
1875 * handler.
1876 */
1877 regmap_read(info->map, REG(OCELOT_GPIO_IN, info, gpio), &val);
1878 if ((!(val & bit) && trigger_level == IRQ_TYPE_LEVEL_LOW) ||
1879 (val & bit && trigger_level == IRQ_TYPE_LEVEL_HIGH))
1880 active = true;
1881
1882 if (active) {
1883 struct ocelot_irq_work *work;
1884
1885 work = kmalloc(sizeof(*work), GFP_ATOMIC);
1886 if (!work)
1887 return;
1888
1889 work->irq_desc = desc;
1890 INIT_WORK(&work->irq_work, ocelot_irq_work);
1891 queue_work(info->wq, &work->irq_work);
1892 }
1893}
1894
1895static void ocelot_irq_unmask(struct irq_data *data)
1896{
1897 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
1898 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1899 unsigned int gpio = irqd_to_hwirq(data);
1900
1901 gpiochip_enable_irq(chip, gpio);
1902 regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio),
1903 BIT(gpio % 32), BIT(gpio % 32));
1904}
1905
1906static void ocelot_irq_ack(struct irq_data *data)
1907{
1908 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
1909 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1910 unsigned int gpio = irqd_to_hwirq(data);
1911
1912 regmap_write_bits(info->map, REG(OCELOT_GPIO_INTR, info, gpio),
1913 BIT(gpio % 32), BIT(gpio % 32));
1914}
1915
1916static int ocelot_irq_set_type(struct irq_data *data, unsigned int type);
1917
1918static struct irq_chip ocelot_level_irqchip = {
1919 .name = "gpio",
1920 .irq_mask = ocelot_irq_mask,
1921 .irq_ack = ocelot_irq_ack,
1922 .irq_unmask = ocelot_irq_unmask_level,
1923 .flags = IRQCHIP_IMMUTABLE,
1924 .irq_set_type = ocelot_irq_set_type,
1925 GPIOCHIP_IRQ_RESOURCE_HELPERS
1926};
1927
1928static struct irq_chip ocelot_irqchip = {
1929 .name = "gpio",
1930 .irq_mask = ocelot_irq_mask,
1931 .irq_ack = ocelot_irq_ack,
1932 .irq_unmask = ocelot_irq_unmask,
1933 .irq_set_type = ocelot_irq_set_type,
1934 .flags = IRQCHIP_IMMUTABLE,
1935 GPIOCHIP_IRQ_RESOURCE_HELPERS
1936};
1937
1938static int ocelot_irq_set_type(struct irq_data *data, unsigned int type)
1939{
1940 if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
1941 irq_set_chip_handler_name_locked(data, &ocelot_level_irqchip,
1942 handle_level_irq, NULL);
1943 if (type & IRQ_TYPE_EDGE_BOTH)
1944 irq_set_chip_handler_name_locked(data, &ocelot_irqchip,
1945 handle_edge_irq, NULL);
1946
1947 return 0;
1948}
1949
1950static void ocelot_irq_handler(struct irq_desc *desc)
1951{
1952 struct irq_chip *parent_chip = irq_desc_get_chip(desc);
1953 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
1954 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1955 unsigned int id_reg = OCELOT_GPIO_INTR_IDENT * info->stride;
1956 unsigned int reg = 0, irq, i;
1957 unsigned long irqs;
1958
1959 for (i = 0; i < info->stride; i++) {
1960 regmap_read(info->map, id_reg + 4 * i, ®);
1961 if (!reg)
1962 continue;
1963
1964 chained_irq_enter(parent_chip, desc);
1965
1966 irqs = reg;
1967
1968 for_each_set_bit(irq, &irqs,
1969 min(32U, info->desc->npins - 32 * i))
1970 generic_handle_domain_irq(chip->irq.domain, irq + 32 * i);
1971
1972 chained_irq_exit(parent_chip, desc);
1973 }
1974}
1975
1976static int ocelot_gpiochip_register(struct platform_device *pdev,
1977 struct ocelot_pinctrl *info)
1978{
1979 struct gpio_chip *gc;
1980 struct gpio_irq_chip *girq;
1981 int irq;
1982
1983 info->gpio_chip = ocelot_gpiolib_chip;
1984
1985 gc = &info->gpio_chip;
1986 gc->ngpio = info->desc->npins;
1987 gc->parent = &pdev->dev;
1988 gc->base = -1;
1989 gc->label = "ocelot-gpio";
1990
1991 irq = platform_get_irq_optional(pdev, 0);
1992 if (irq > 0) {
1993 girq = &gc->irq;
1994 gpio_irq_chip_set_chip(girq, &ocelot_irqchip);
1995 girq->parent_handler = ocelot_irq_handler;
1996 girq->num_parents = 1;
1997 girq->parents = devm_kcalloc(&pdev->dev, 1,
1998 sizeof(*girq->parents),
1999 GFP_KERNEL);
2000 if (!girq->parents)
2001 return -ENOMEM;
2002 girq->parents[0] = irq;
2003 girq->default_type = IRQ_TYPE_NONE;
2004 girq->handler = handle_edge_irq;
2005 }
2006
2007 return devm_gpiochip_add_data(&pdev->dev, gc, info);
2008}
2009
2010static const struct of_device_id ocelot_pinctrl_of_match[] = {
2011 { .compatible = "mscc,luton-pinctrl", .data = &luton_desc },
2012 { .compatible = "mscc,serval-pinctrl", .data = &serval_desc },
2013 { .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc },
2014 { .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc },
2015 { .compatible = "mscc,servalt-pinctrl", .data = &servalt_desc },
2016 { .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc },
2017 { .compatible = "microchip,lan966x-pinctrl", .data = &lan966x_desc },
2018 {},
2019};
2020MODULE_DEVICE_TABLE(of, ocelot_pinctrl_of_match);
2021
2022static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device *pdev,
2023 const struct ocelot_pinctrl *info)
2024{
2025 void __iomem *base;
2026
2027 const struct regmap_config regmap_config = {
2028 .reg_bits = 32,
2029 .val_bits = 32,
2030 .reg_stride = 4,
2031 .max_register = info->desc->npins * 4,
2032 .name = "pincfg",
2033 };
2034
2035 base = devm_platform_ioremap_resource(pdev, 1);
2036 if (IS_ERR(base)) {
2037 dev_dbg(&pdev->dev, "Failed to ioremap config registers (no extended pinconf)\n");
2038 return NULL;
2039 }
2040
2041 return devm_regmap_init_mmio(&pdev->dev, base, ®map_config);
2042}
2043
2044static void ocelot_destroy_workqueue(void *data)
2045{
2046 destroy_workqueue(data);
2047}
2048
2049static int ocelot_pinctrl_probe(struct platform_device *pdev)
2050{
2051 const struct ocelot_match_data *data;
2052 struct device *dev = &pdev->dev;
2053 struct ocelot_pinctrl *info;
2054 struct reset_control *reset;
2055 struct regmap *pincfg;
2056 int ret;
2057 struct regmap_config regmap_config = {
2058 .reg_bits = 32,
2059 .val_bits = 32,
2060 .reg_stride = 4,
2061 };
2062
2063 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
2064 if (!info)
2065 return -ENOMEM;
2066
2067 data = device_get_match_data(dev);
2068 if (!data)
2069 return -EINVAL;
2070
2071 info->desc = devm_kmemdup(dev, &data->desc, sizeof(*info->desc),
2072 GFP_KERNEL);
2073 if (!info->desc)
2074 return -ENOMEM;
2075
2076 info->wq = alloc_ordered_workqueue("ocelot_ordered", 0);
2077 if (!info->wq)
2078 return -ENOMEM;
2079
2080 ret = devm_add_action_or_reset(dev, ocelot_destroy_workqueue,
2081 info->wq);
2082 if (ret)
2083 return ret;
2084
2085 info->pincfg_data = &data->pincfg_data;
2086
2087 reset = devm_reset_control_get_optional_shared(dev, "switch");
2088 if (IS_ERR(reset))
2089 return dev_err_probe(dev, PTR_ERR(reset),
2090 "Failed to get reset\n");
2091 reset_control_reset(reset);
2092
2093 info->stride = 1 + (info->desc->npins - 1) / 32;
2094
2095 regmap_config.max_register = OCELOT_GPIO_SD_MAP * info->stride + 15 * 4;
2096
2097 info->map = ocelot_regmap_from_resource(pdev, 0, ®map_config);
2098 if (IS_ERR(info->map))
2099 return dev_err_probe(dev, PTR_ERR(info->map),
2100 "Failed to create regmap\n");
2101 dev_set_drvdata(dev, info);
2102 info->dev = dev;
2103
2104 /* Pinconf registers */
2105 if (info->desc->confops) {
2106 pincfg = ocelot_pinctrl_create_pincfg(pdev, info);
2107 if (IS_ERR(pincfg))
2108 dev_dbg(dev, "Failed to create pincfg regmap\n");
2109 else
2110 info->pincfg = pincfg;
2111 }
2112
2113 ret = ocelot_pinctrl_register(pdev, info);
2114 if (ret)
2115 return ret;
2116
2117 ret = ocelot_gpiochip_register(pdev, info);
2118 if (ret)
2119 return ret;
2120
2121 dev_info(dev, "driver registered\n");
2122
2123 return 0;
2124}
2125
2126static struct platform_driver ocelot_pinctrl_driver = {
2127 .driver = {
2128 .name = "pinctrl-ocelot",
2129 .of_match_table = of_match_ptr(ocelot_pinctrl_of_match),
2130 .suppress_bind_attrs = true,
2131 },
2132 .probe = ocelot_pinctrl_probe,
2133};
2134module_platform_driver(ocelot_pinctrl_driver);
2135
2136MODULE_DESCRIPTION("Ocelot Chip Pinctrl Driver");
2137MODULE_LICENSE("Dual MIT/GPL");