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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * MAX77620 pin control driver.
4 *
5 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
6 *
7 * Author:
8 * Chaitanya Bandi <bandik@nvidia.com>
9 * Laxman Dewangan <ldewangan@nvidia.com>
10 */
11
12#include <linux/mfd/max77620.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/pinctrl/pinctrl.h>
16#include <linux/pinctrl/pinconf-generic.h>
17#include <linux/pinctrl/pinconf.h>
18#include <linux/pinctrl/pinmux.h>
19#include <linux/platform_device.h>
20#include <linux/regmap.h>
21
22#include "core.h"
23#include "pinconf.h"
24#include "pinctrl-utils.h"
25
26#define MAX77620_PIN_NUM 8
27
28enum max77620_pin_ppdrv {
29 MAX77620_PIN_UNCONFIG_DRV,
30 MAX77620_PIN_OD_DRV,
31 MAX77620_PIN_PP_DRV,
32};
33
34#define MAX77620_ACTIVE_FPS_SOURCE (PIN_CONFIG_END + 1)
35#define MAX77620_ACTIVE_FPS_POWER_ON_SLOTS (PIN_CONFIG_END + 2)
36#define MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS (PIN_CONFIG_END + 3)
37#define MAX77620_SUSPEND_FPS_SOURCE (PIN_CONFIG_END + 4)
38#define MAX77620_SUSPEND_FPS_POWER_ON_SLOTS (PIN_CONFIG_END + 5)
39#define MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS (PIN_CONFIG_END + 6)
40
41struct max77620_pin_function {
42 const char *name;
43 const char * const *groups;
44 unsigned int ngroups;
45 int mux_option;
46};
47
48static const struct pinconf_generic_params max77620_cfg_params[] = {
49 {
50 .property = "maxim,active-fps-source",
51 .param = MAX77620_ACTIVE_FPS_SOURCE,
52 }, {
53 .property = "maxim,active-fps-power-up-slot",
54 .param = MAX77620_ACTIVE_FPS_POWER_ON_SLOTS,
55 }, {
56 .property = "maxim,active-fps-power-down-slot",
57 .param = MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS,
58 }, {
59 .property = "maxim,suspend-fps-source",
60 .param = MAX77620_SUSPEND_FPS_SOURCE,
61 }, {
62 .property = "maxim,suspend-fps-power-up-slot",
63 .param = MAX77620_SUSPEND_FPS_POWER_ON_SLOTS,
64 }, {
65 .property = "maxim,suspend-fps-power-down-slot",
66 .param = MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS,
67 },
68};
69
70enum max77620_alternate_pinmux_option {
71 MAX77620_PINMUX_GPIO = 0,
72 MAX77620_PINMUX_LOW_POWER_MODE_CONTROL_IN = 1,
73 MAX77620_PINMUX_FLEXIBLE_POWER_SEQUENCER_OUT = 2,
74 MAX77620_PINMUX_32K_OUT1 = 3,
75 MAX77620_PINMUX_SD0_DYNAMIC_VOLTAGE_SCALING_IN = 4,
76 MAX77620_PINMUX_SD1_DYNAMIC_VOLTAGE_SCALING_IN = 5,
77 MAX77620_PINMUX_REFERENCE_OUT = 6,
78};
79
80struct max77620_pingroup {
81 const char *name;
82 const unsigned int pins[1];
83 unsigned int npins;
84 enum max77620_alternate_pinmux_option alt_option;
85};
86
87struct max77620_pin_info {
88 enum max77620_pin_ppdrv drv_type;
89 int pull_config;
90};
91
92struct max77620_fps_config {
93 int active_fps_src;
94 int active_power_up_slots;
95 int active_power_down_slots;
96 int suspend_fps_src;
97 int suspend_power_up_slots;
98 int suspend_power_down_slots;
99};
100
101struct max77620_pctrl_info {
102 struct device *dev;
103 struct pinctrl_dev *pctl;
104 struct regmap *rmap;
105 int pins_current_opt[MAX77620_GPIO_NR];
106 const struct max77620_pin_function *functions;
107 unsigned int num_functions;
108 const struct max77620_pingroup *pin_groups;
109 int num_pin_groups;
110 const struct pinctrl_pin_desc *pins;
111 unsigned int num_pins;
112 struct max77620_pin_info pin_info[MAX77620_PIN_NUM];
113 struct max77620_fps_config fps_config[MAX77620_PIN_NUM];
114};
115
116static const struct pinctrl_pin_desc max77620_pins_desc[] = {
117 PINCTRL_PIN(MAX77620_GPIO0, "gpio0"),
118 PINCTRL_PIN(MAX77620_GPIO1, "gpio1"),
119 PINCTRL_PIN(MAX77620_GPIO2, "gpio2"),
120 PINCTRL_PIN(MAX77620_GPIO3, "gpio3"),
121 PINCTRL_PIN(MAX77620_GPIO4, "gpio4"),
122 PINCTRL_PIN(MAX77620_GPIO5, "gpio5"),
123 PINCTRL_PIN(MAX77620_GPIO6, "gpio6"),
124 PINCTRL_PIN(MAX77620_GPIO7, "gpio7"),
125};
126
127static const char * const gpio_groups[] = {
128 "gpio0",
129 "gpio1",
130 "gpio2",
131 "gpio3",
132 "gpio4",
133 "gpio5",
134 "gpio6",
135 "gpio7",
136};
137
138#define FUNCTION_GROUP(fname, mux) \
139 { \
140 .name = fname, \
141 .groups = gpio_groups, \
142 .ngroups = ARRAY_SIZE(gpio_groups), \
143 .mux_option = MAX77620_PINMUX_##mux, \
144 }
145
146static const struct max77620_pin_function max77620_pin_function[] = {
147 FUNCTION_GROUP("gpio", GPIO),
148 FUNCTION_GROUP("lpm-control-in", LOW_POWER_MODE_CONTROL_IN),
149 FUNCTION_GROUP("fps-out", FLEXIBLE_POWER_SEQUENCER_OUT),
150 FUNCTION_GROUP("32k-out1", 32K_OUT1),
151 FUNCTION_GROUP("sd0-dvs-in", SD0_DYNAMIC_VOLTAGE_SCALING_IN),
152 FUNCTION_GROUP("sd1-dvs-in", SD1_DYNAMIC_VOLTAGE_SCALING_IN),
153 FUNCTION_GROUP("reference-out", REFERENCE_OUT),
154};
155
156#define MAX77620_PINGROUP(pg_name, pin_id, option) \
157 { \
158 .name = #pg_name, \
159 .pins = {MAX77620_##pin_id}, \
160 .npins = 1, \
161 .alt_option = MAX77620_PINMUX_##option, \
162 }
163
164static const struct max77620_pingroup max77620_pingroups[] = {
165 MAX77620_PINGROUP(gpio0, GPIO0, LOW_POWER_MODE_CONTROL_IN),
166 MAX77620_PINGROUP(gpio1, GPIO1, FLEXIBLE_POWER_SEQUENCER_OUT),
167 MAX77620_PINGROUP(gpio2, GPIO2, FLEXIBLE_POWER_SEQUENCER_OUT),
168 MAX77620_PINGROUP(gpio3, GPIO3, FLEXIBLE_POWER_SEQUENCER_OUT),
169 MAX77620_PINGROUP(gpio4, GPIO4, 32K_OUT1),
170 MAX77620_PINGROUP(gpio5, GPIO5, SD0_DYNAMIC_VOLTAGE_SCALING_IN),
171 MAX77620_PINGROUP(gpio6, GPIO6, SD1_DYNAMIC_VOLTAGE_SCALING_IN),
172 MAX77620_PINGROUP(gpio7, GPIO7, REFERENCE_OUT),
173};
174
175static int max77620_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
176{
177 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
178
179 return mpci->num_pin_groups;
180}
181
182static const char *max77620_pinctrl_get_group_name(
183 struct pinctrl_dev *pctldev, unsigned int group)
184{
185 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
186
187 return mpci->pin_groups[group].name;
188}
189
190static int max77620_pinctrl_get_group_pins(
191 struct pinctrl_dev *pctldev, unsigned int group,
192 const unsigned int **pins, unsigned int *num_pins)
193{
194 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
195
196 *pins = mpci->pin_groups[group].pins;
197 *num_pins = mpci->pin_groups[group].npins;
198
199 return 0;
200}
201
202static const struct pinctrl_ops max77620_pinctrl_ops = {
203 .get_groups_count = max77620_pinctrl_get_groups_count,
204 .get_group_name = max77620_pinctrl_get_group_name,
205 .get_group_pins = max77620_pinctrl_get_group_pins,
206 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
207 .dt_free_map = pinctrl_utils_free_map,
208};
209
210static int max77620_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
211{
212 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
213
214 return mpci->num_functions;
215}
216
217static const char *max77620_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
218 unsigned int function)
219{
220 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
221
222 return mpci->functions[function].name;
223}
224
225static int max77620_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
226 unsigned int function,
227 const char * const **groups,
228 unsigned int * const num_groups)
229{
230 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
231
232 *groups = mpci->functions[function].groups;
233 *num_groups = mpci->functions[function].ngroups;
234
235 return 0;
236}
237
238static int max77620_pinctrl_enable(struct pinctrl_dev *pctldev,
239 unsigned int function, unsigned int group)
240{
241 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
242 u8 val;
243 int ret;
244
245 if (function == MAX77620_PINMUX_GPIO) {
246 val = 0;
247 } else if (function == mpci->pin_groups[group].alt_option) {
248 val = 1 << group;
249 } else {
250 dev_err(mpci->dev, "GPIO %u doesn't have function %u\n",
251 group, function);
252 return -EINVAL;
253 }
254 ret = regmap_update_bits(mpci->rmap, MAX77620_REG_AME_GPIO,
255 BIT(group), val);
256 if (ret < 0)
257 dev_err(mpci->dev, "REG AME GPIO update failed: %d\n", ret);
258
259 return ret;
260}
261
262static const struct pinmux_ops max77620_pinmux_ops = {
263 .get_functions_count = max77620_pinctrl_get_funcs_count,
264 .get_function_name = max77620_pinctrl_get_func_name,
265 .get_function_groups = max77620_pinctrl_get_func_groups,
266 .set_mux = max77620_pinctrl_enable,
267};
268
269static int max77620_pinconf_get(struct pinctrl_dev *pctldev,
270 unsigned int pin, unsigned long *config)
271{
272 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
273 struct device *dev = mpci->dev;
274 enum pin_config_param param = pinconf_to_config_param(*config);
275 unsigned int val;
276 int arg = 0;
277 int ret;
278
279 switch (param) {
280 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
281 if (mpci->pin_info[pin].drv_type == MAX77620_PIN_OD_DRV)
282 arg = 1;
283 break;
284
285 case PIN_CONFIG_DRIVE_PUSH_PULL:
286 if (mpci->pin_info[pin].drv_type == MAX77620_PIN_PP_DRV)
287 arg = 1;
288 break;
289
290 case PIN_CONFIG_BIAS_PULL_UP:
291 ret = regmap_read(mpci->rmap, MAX77620_REG_PUE_GPIO, &val);
292 if (ret < 0) {
293 dev_err(dev, "Reg PUE_GPIO read failed: %d\n", ret);
294 return ret;
295 }
296 if (val & BIT(pin))
297 arg = 1;
298 break;
299
300 case PIN_CONFIG_BIAS_PULL_DOWN:
301 ret = regmap_read(mpci->rmap, MAX77620_REG_PDE_GPIO, &val);
302 if (ret < 0) {
303 dev_err(dev, "Reg PDE_GPIO read failed: %d\n", ret);
304 return ret;
305 }
306 if (val & BIT(pin))
307 arg = 1;
308 break;
309
310 default:
311 dev_err(dev, "Properties not supported\n");
312 return -ENOTSUPP;
313 }
314
315 *config = pinconf_to_config_packed(param, (u16)arg);
316
317 return 0;
318}
319
320static int max77620_get_default_fps(struct max77620_pctrl_info *mpci,
321 int addr, int *fps)
322{
323 unsigned int val;
324 int ret;
325
326 ret = regmap_read(mpci->rmap, addr, &val);
327 if (ret < 0) {
328 dev_err(mpci->dev, "Reg PUE_GPIO read failed: %d\n", ret);
329 return ret;
330 }
331 *fps = (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT;
332
333 return 0;
334}
335
336static int max77620_set_fps_param(struct max77620_pctrl_info *mpci,
337 int pin, int param)
338{
339 struct max77620_fps_config *fps_config = &mpci->fps_config[pin];
340 int addr, ret;
341 int param_val;
342 int mask, shift;
343
344 if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
345 return 0;
346
347 addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
348 switch (param) {
349 case MAX77620_ACTIVE_FPS_SOURCE:
350 case MAX77620_SUSPEND_FPS_SOURCE:
351 mask = MAX77620_FPS_SRC_MASK;
352 shift = MAX77620_FPS_SRC_SHIFT;
353 param_val = fps_config->active_fps_src;
354 if (param == MAX77620_SUSPEND_FPS_SOURCE)
355 param_val = fps_config->suspend_fps_src;
356 break;
357
358 case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS:
359 case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS:
360 mask = MAX77620_FPS_PU_PERIOD_MASK;
361 shift = MAX77620_FPS_PU_PERIOD_SHIFT;
362 param_val = fps_config->active_power_up_slots;
363 if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS)
364 param_val = fps_config->suspend_power_up_slots;
365 break;
366
367 case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS:
368 case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS:
369 mask = MAX77620_FPS_PD_PERIOD_MASK;
370 shift = MAX77620_FPS_PD_PERIOD_SHIFT;
371 param_val = fps_config->active_power_down_slots;
372 if (param == MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS)
373 param_val = fps_config->suspend_power_down_slots;
374 break;
375
376 default:
377 dev_err(mpci->dev, "Invalid parameter %d for pin %d\n",
378 param, pin);
379 return -EINVAL;
380 }
381
382 if (param_val < 0)
383 return 0;
384
385 ret = regmap_update_bits(mpci->rmap, addr, mask, param_val << shift);
386 if (ret < 0)
387 dev_err(mpci->dev, "Reg 0x%02x update failed %d\n", addr, ret);
388
389 return ret;
390}
391
392static int max77620_pinconf_set(struct pinctrl_dev *pctldev,
393 unsigned int pin, unsigned long *configs,
394 unsigned int num_configs)
395{
396 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
397 struct device *dev = mpci->dev;
398 struct max77620_fps_config *fps_config;
399 int param;
400 u32 param_val;
401 unsigned int val;
402 unsigned int pu_val;
403 unsigned int pd_val;
404 int addr, ret;
405 int i;
406
407 for (i = 0; i < num_configs; i++) {
408 param = pinconf_to_config_param(configs[i]);
409 param_val = pinconf_to_config_argument(configs[i]);
410
411 switch (param) {
412 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
413 val = param_val ? 0 : 1;
414 ret = regmap_update_bits(mpci->rmap,
415 MAX77620_REG_GPIO0 + pin,
416 MAX77620_CNFG_GPIO_DRV_MASK,
417 val);
418 if (ret)
419 goto report_update_failure;
420
421 mpci->pin_info[pin].drv_type = val ?
422 MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV;
423 break;
424
425 case PIN_CONFIG_DRIVE_PUSH_PULL:
426 val = param_val ? 1 : 0;
427 ret = regmap_update_bits(mpci->rmap,
428 MAX77620_REG_GPIO0 + pin,
429 MAX77620_CNFG_GPIO_DRV_MASK,
430 val);
431 if (ret)
432 goto report_update_failure;
433
434 mpci->pin_info[pin].drv_type = val ?
435 MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV;
436 break;
437
438 case MAX77620_ACTIVE_FPS_SOURCE:
439 case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS:
440 case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS:
441 if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
442 return -EINVAL;
443
444 fps_config = &mpci->fps_config[pin];
445
446 if ((param == MAX77620_ACTIVE_FPS_SOURCE) &&
447 (param_val == MAX77620_FPS_SRC_DEF)) {
448 addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
449 ret = max77620_get_default_fps(
450 mpci, addr,
451 &fps_config->active_fps_src);
452 if (ret < 0)
453 return ret;
454 break;
455 }
456
457 if (param == MAX77620_ACTIVE_FPS_SOURCE)
458 fps_config->active_fps_src = param_val;
459 else if (param == MAX77620_ACTIVE_FPS_POWER_ON_SLOTS)
460 fps_config->active_power_up_slots = param_val;
461 else
462 fps_config->active_power_down_slots = param_val;
463
464 ret = max77620_set_fps_param(mpci, pin, param);
465 if (ret < 0)
466 return ret;
467 break;
468
469 case MAX77620_SUSPEND_FPS_SOURCE:
470 case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS:
471 case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS:
472 if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
473 return -EINVAL;
474
475 fps_config = &mpci->fps_config[pin];
476
477 if ((param == MAX77620_SUSPEND_FPS_SOURCE) &&
478 (param_val == MAX77620_FPS_SRC_DEF)) {
479 addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
480 ret = max77620_get_default_fps(
481 mpci, addr,
482 &fps_config->suspend_fps_src);
483 if (ret < 0)
484 return ret;
485 break;
486 }
487
488 if (param == MAX77620_SUSPEND_FPS_SOURCE)
489 fps_config->suspend_fps_src = param_val;
490 else if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS)
491 fps_config->suspend_power_up_slots = param_val;
492 else
493 fps_config->suspend_power_down_slots =
494 param_val;
495 break;
496
497 case PIN_CONFIG_BIAS_PULL_UP:
498 case PIN_CONFIG_BIAS_PULL_DOWN:
499 pu_val = (param == PIN_CONFIG_BIAS_PULL_UP) ?
500 BIT(pin) : 0;
501 pd_val = (param == PIN_CONFIG_BIAS_PULL_DOWN) ?
502 BIT(pin) : 0;
503
504 ret = regmap_update_bits(mpci->rmap,
505 MAX77620_REG_PUE_GPIO,
506 BIT(pin), pu_val);
507 if (ret < 0) {
508 dev_err(dev, "PUE_GPIO update failed: %d\n",
509 ret);
510 return ret;
511 }
512
513 ret = regmap_update_bits(mpci->rmap,
514 MAX77620_REG_PDE_GPIO,
515 BIT(pin), pd_val);
516 if (ret < 0) {
517 dev_err(dev, "PDE_GPIO update failed: %d\n",
518 ret);
519 return ret;
520 }
521 break;
522
523 default:
524 dev_err(dev, "Properties not supported\n");
525 return -ENOTSUPP;
526 }
527 }
528
529 return 0;
530
531report_update_failure:
532 dev_err(dev, "Reg 0x%02x update failed %d\n",
533 MAX77620_REG_GPIO0 + pin, ret);
534 return ret;
535}
536
537static const struct pinconf_ops max77620_pinconf_ops = {
538 .pin_config_get = max77620_pinconf_get,
539 .pin_config_set = max77620_pinconf_set,
540};
541
542static struct pinctrl_desc max77620_pinctrl_desc = {
543 .pctlops = &max77620_pinctrl_ops,
544 .pmxops = &max77620_pinmux_ops,
545 .confops = &max77620_pinconf_ops,
546};
547
548static int max77620_pinctrl_probe(struct platform_device *pdev)
549{
550 struct max77620_chip *max77620 = dev_get_drvdata(pdev->dev.parent);
551 struct max77620_pctrl_info *mpci;
552 int i;
553
554 mpci = devm_kzalloc(&pdev->dev, sizeof(*mpci), GFP_KERNEL);
555 if (!mpci)
556 return -ENOMEM;
557
558 mpci->dev = &pdev->dev;
559 mpci->dev->of_node = pdev->dev.parent->of_node;
560 mpci->rmap = max77620->rmap;
561
562 mpci->pins = max77620_pins_desc;
563 mpci->num_pins = ARRAY_SIZE(max77620_pins_desc);
564 mpci->functions = max77620_pin_function;
565 mpci->num_functions = ARRAY_SIZE(max77620_pin_function);
566 mpci->pin_groups = max77620_pingroups;
567 mpci->num_pin_groups = ARRAY_SIZE(max77620_pingroups);
568 platform_set_drvdata(pdev, mpci);
569
570 max77620_pinctrl_desc.name = dev_name(&pdev->dev);
571 max77620_pinctrl_desc.pins = max77620_pins_desc;
572 max77620_pinctrl_desc.npins = ARRAY_SIZE(max77620_pins_desc);
573 max77620_pinctrl_desc.num_custom_params =
574 ARRAY_SIZE(max77620_cfg_params);
575 max77620_pinctrl_desc.custom_params = max77620_cfg_params;
576
577 for (i = 0; i < MAX77620_PIN_NUM; ++i) {
578 mpci->fps_config[i].active_fps_src = -1;
579 mpci->fps_config[i].active_power_up_slots = -1;
580 mpci->fps_config[i].active_power_down_slots = -1;
581 mpci->fps_config[i].suspend_fps_src = -1;
582 mpci->fps_config[i].suspend_power_up_slots = -1;
583 mpci->fps_config[i].suspend_power_down_slots = -1;
584 }
585
586 mpci->pctl = devm_pinctrl_register(&pdev->dev, &max77620_pinctrl_desc,
587 mpci);
588 if (IS_ERR(mpci->pctl)) {
589 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
590 return PTR_ERR(mpci->pctl);
591 }
592
593 return 0;
594}
595
596#ifdef CONFIG_PM_SLEEP
597static int max77620_suspend_fps_param[] = {
598 MAX77620_SUSPEND_FPS_SOURCE,
599 MAX77620_SUSPEND_FPS_POWER_ON_SLOTS,
600 MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS,
601};
602
603static int max77620_active_fps_param[] = {
604 MAX77620_ACTIVE_FPS_SOURCE,
605 MAX77620_ACTIVE_FPS_POWER_ON_SLOTS,
606 MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS,
607};
608
609static int max77620_pinctrl_suspend(struct device *dev)
610{
611 struct max77620_pctrl_info *mpci = dev_get_drvdata(dev);
612 int pin, p;
613
614 for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) {
615 if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
616 continue;
617 for (p = 0; p < 3; ++p)
618 max77620_set_fps_param(
619 mpci, pin, max77620_suspend_fps_param[p]);
620 }
621
622 return 0;
623};
624
625static int max77620_pinctrl_resume(struct device *dev)
626{
627 struct max77620_pctrl_info *mpci = dev_get_drvdata(dev);
628 int pin, p;
629
630 for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) {
631 if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
632 continue;
633 for (p = 0; p < 3; ++p)
634 max77620_set_fps_param(
635 mpci, pin, max77620_active_fps_param[p]);
636 }
637
638 return 0;
639}
640#endif
641
642static const struct dev_pm_ops max77620_pinctrl_pm_ops = {
643 SET_SYSTEM_SLEEP_PM_OPS(
644 max77620_pinctrl_suspend, max77620_pinctrl_resume)
645};
646
647static const struct platform_device_id max77620_pinctrl_devtype[] = {
648 { .name = "max77620-pinctrl", },
649 { .name = "max20024-pinctrl", },
650 {},
651};
652MODULE_DEVICE_TABLE(platform, max77620_pinctrl_devtype);
653
654static struct platform_driver max77620_pinctrl_driver = {
655 .driver = {
656 .name = "max77620-pinctrl",
657 .pm = &max77620_pinctrl_pm_ops,
658 },
659 .probe = max77620_pinctrl_probe,
660 .id_table = max77620_pinctrl_devtype,
661};
662
663module_platform_driver(max77620_pinctrl_driver);
664
665MODULE_DESCRIPTION("MAX77620/MAX20024 pin control driver");
666MODULE_AUTHOR("Chaitanya Bandi<bandik@nvidia.com>");
667MODULE_AUTHOR("Laxman Dewangan<ldewangan@nvidia.com>");
668MODULE_ALIAS("platform:max77620-pinctrl");
669MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * MAX77620 pin control driver.
4 *
5 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
6 *
7 * Author:
8 * Chaitanya Bandi <bandik@nvidia.com>
9 * Laxman Dewangan <ldewangan@nvidia.com>
10 */
11
12#include <linux/mfd/max77620.h>
13#include <linux/mod_devicetable.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/property.h>
17#include <linux/regmap.h>
18
19#include <linux/pinctrl/pinctrl.h>
20#include <linux/pinctrl/pinconf-generic.h>
21#include <linux/pinctrl/pinconf.h>
22#include <linux/pinctrl/pinmux.h>
23
24#include "core.h"
25#include "pinconf.h"
26#include "pinctrl-utils.h"
27
28#define MAX77620_PIN_NUM 8
29
30enum max77620_pin_ppdrv {
31 MAX77620_PIN_UNCONFIG_DRV,
32 MAX77620_PIN_OD_DRV,
33 MAX77620_PIN_PP_DRV,
34};
35
36#define MAX77620_ACTIVE_FPS_SOURCE (PIN_CONFIG_END + 1)
37#define MAX77620_ACTIVE_FPS_POWER_ON_SLOTS (PIN_CONFIG_END + 2)
38#define MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS (PIN_CONFIG_END + 3)
39#define MAX77620_SUSPEND_FPS_SOURCE (PIN_CONFIG_END + 4)
40#define MAX77620_SUSPEND_FPS_POWER_ON_SLOTS (PIN_CONFIG_END + 5)
41#define MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS (PIN_CONFIG_END + 6)
42
43struct max77620_pin_function {
44 const char *name;
45 const char * const *groups;
46 unsigned int ngroups;
47 int mux_option;
48};
49
50static const struct pinconf_generic_params max77620_cfg_params[] = {
51 {
52 .property = "maxim,active-fps-source",
53 .param = MAX77620_ACTIVE_FPS_SOURCE,
54 }, {
55 .property = "maxim,active-fps-power-up-slot",
56 .param = MAX77620_ACTIVE_FPS_POWER_ON_SLOTS,
57 }, {
58 .property = "maxim,active-fps-power-down-slot",
59 .param = MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS,
60 }, {
61 .property = "maxim,suspend-fps-source",
62 .param = MAX77620_SUSPEND_FPS_SOURCE,
63 }, {
64 .property = "maxim,suspend-fps-power-up-slot",
65 .param = MAX77620_SUSPEND_FPS_POWER_ON_SLOTS,
66 }, {
67 .property = "maxim,suspend-fps-power-down-slot",
68 .param = MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS,
69 },
70};
71
72enum max77620_alternate_pinmux_option {
73 MAX77620_PINMUX_GPIO = 0,
74 MAX77620_PINMUX_LOW_POWER_MODE_CONTROL_IN = 1,
75 MAX77620_PINMUX_FLEXIBLE_POWER_SEQUENCER_OUT = 2,
76 MAX77620_PINMUX_32K_OUT1 = 3,
77 MAX77620_PINMUX_SD0_DYNAMIC_VOLTAGE_SCALING_IN = 4,
78 MAX77620_PINMUX_SD1_DYNAMIC_VOLTAGE_SCALING_IN = 5,
79 MAX77620_PINMUX_REFERENCE_OUT = 6,
80};
81
82struct max77620_pingroup {
83 const char *name;
84 const unsigned int pins[1];
85 unsigned int npins;
86 enum max77620_alternate_pinmux_option alt_option;
87};
88
89struct max77620_pin_info {
90 enum max77620_pin_ppdrv drv_type;
91 int pull_config;
92};
93
94struct max77620_fps_config {
95 int active_fps_src;
96 int active_power_up_slots;
97 int active_power_down_slots;
98 int suspend_fps_src;
99 int suspend_power_up_slots;
100 int suspend_power_down_slots;
101};
102
103struct max77620_pctrl_info {
104 struct device *dev;
105 struct pinctrl_dev *pctl;
106 struct regmap *rmap;
107 int pins_current_opt[MAX77620_GPIO_NR];
108 const struct max77620_pin_function *functions;
109 unsigned int num_functions;
110 const struct max77620_pingroup *pin_groups;
111 int num_pin_groups;
112 const struct pinctrl_pin_desc *pins;
113 unsigned int num_pins;
114 struct max77620_pin_info pin_info[MAX77620_PIN_NUM];
115 struct max77620_fps_config fps_config[MAX77620_PIN_NUM];
116};
117
118static const struct pinctrl_pin_desc max77620_pins_desc[] = {
119 PINCTRL_PIN(MAX77620_GPIO0, "gpio0"),
120 PINCTRL_PIN(MAX77620_GPIO1, "gpio1"),
121 PINCTRL_PIN(MAX77620_GPIO2, "gpio2"),
122 PINCTRL_PIN(MAX77620_GPIO3, "gpio3"),
123 PINCTRL_PIN(MAX77620_GPIO4, "gpio4"),
124 PINCTRL_PIN(MAX77620_GPIO5, "gpio5"),
125 PINCTRL_PIN(MAX77620_GPIO6, "gpio6"),
126 PINCTRL_PIN(MAX77620_GPIO7, "gpio7"),
127};
128
129static const char * const gpio_groups[] = {
130 "gpio0",
131 "gpio1",
132 "gpio2",
133 "gpio3",
134 "gpio4",
135 "gpio5",
136 "gpio6",
137 "gpio7",
138};
139
140#define FUNCTION_GROUP(fname, mux) \
141 { \
142 .name = fname, \
143 .groups = gpio_groups, \
144 .ngroups = ARRAY_SIZE(gpio_groups), \
145 .mux_option = MAX77620_PINMUX_##mux, \
146 }
147
148static const struct max77620_pin_function max77620_pin_function[] = {
149 FUNCTION_GROUP("gpio", GPIO),
150 FUNCTION_GROUP("lpm-control-in", LOW_POWER_MODE_CONTROL_IN),
151 FUNCTION_GROUP("fps-out", FLEXIBLE_POWER_SEQUENCER_OUT),
152 FUNCTION_GROUP("32k-out1", 32K_OUT1),
153 FUNCTION_GROUP("sd0-dvs-in", SD0_DYNAMIC_VOLTAGE_SCALING_IN),
154 FUNCTION_GROUP("sd1-dvs-in", SD1_DYNAMIC_VOLTAGE_SCALING_IN),
155 FUNCTION_GROUP("reference-out", REFERENCE_OUT),
156};
157
158#define MAX77620_PINGROUP(pg_name, pin_id, option) \
159 { \
160 .name = #pg_name, \
161 .pins = {MAX77620_##pin_id}, \
162 .npins = 1, \
163 .alt_option = MAX77620_PINMUX_##option, \
164 }
165
166static const struct max77620_pingroup max77620_pingroups[] = {
167 MAX77620_PINGROUP(gpio0, GPIO0, LOW_POWER_MODE_CONTROL_IN),
168 MAX77620_PINGROUP(gpio1, GPIO1, FLEXIBLE_POWER_SEQUENCER_OUT),
169 MAX77620_PINGROUP(gpio2, GPIO2, FLEXIBLE_POWER_SEQUENCER_OUT),
170 MAX77620_PINGROUP(gpio3, GPIO3, FLEXIBLE_POWER_SEQUENCER_OUT),
171 MAX77620_PINGROUP(gpio4, GPIO4, 32K_OUT1),
172 MAX77620_PINGROUP(gpio5, GPIO5, SD0_DYNAMIC_VOLTAGE_SCALING_IN),
173 MAX77620_PINGROUP(gpio6, GPIO6, SD1_DYNAMIC_VOLTAGE_SCALING_IN),
174 MAX77620_PINGROUP(gpio7, GPIO7, REFERENCE_OUT),
175};
176
177static int max77620_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
178{
179 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
180
181 return mpci->num_pin_groups;
182}
183
184static const char *max77620_pinctrl_get_group_name(
185 struct pinctrl_dev *pctldev, unsigned int group)
186{
187 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
188
189 return mpci->pin_groups[group].name;
190}
191
192static int max77620_pinctrl_get_group_pins(
193 struct pinctrl_dev *pctldev, unsigned int group,
194 const unsigned int **pins, unsigned int *num_pins)
195{
196 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
197
198 *pins = mpci->pin_groups[group].pins;
199 *num_pins = mpci->pin_groups[group].npins;
200
201 return 0;
202}
203
204static const struct pinctrl_ops max77620_pinctrl_ops = {
205 .get_groups_count = max77620_pinctrl_get_groups_count,
206 .get_group_name = max77620_pinctrl_get_group_name,
207 .get_group_pins = max77620_pinctrl_get_group_pins,
208 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
209 .dt_free_map = pinctrl_utils_free_map,
210};
211
212static int max77620_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
213{
214 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
215
216 return mpci->num_functions;
217}
218
219static const char *max77620_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
220 unsigned int function)
221{
222 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
223
224 return mpci->functions[function].name;
225}
226
227static int max77620_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
228 unsigned int function,
229 const char * const **groups,
230 unsigned int * const num_groups)
231{
232 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
233
234 *groups = mpci->functions[function].groups;
235 *num_groups = mpci->functions[function].ngroups;
236
237 return 0;
238}
239
240static int max77620_pinctrl_enable(struct pinctrl_dev *pctldev,
241 unsigned int function, unsigned int group)
242{
243 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
244 u8 val;
245 int ret;
246
247 if (function == MAX77620_PINMUX_GPIO) {
248 val = 0;
249 } else if (function == mpci->pin_groups[group].alt_option) {
250 val = 1 << group;
251 } else {
252 dev_err(mpci->dev, "GPIO %u doesn't have function %u\n",
253 group, function);
254 return -EINVAL;
255 }
256 ret = regmap_update_bits(mpci->rmap, MAX77620_REG_AME_GPIO,
257 BIT(group), val);
258 if (ret < 0)
259 dev_err(mpci->dev, "REG AME GPIO update failed: %d\n", ret);
260
261 return ret;
262}
263
264static const struct pinmux_ops max77620_pinmux_ops = {
265 .get_functions_count = max77620_pinctrl_get_funcs_count,
266 .get_function_name = max77620_pinctrl_get_func_name,
267 .get_function_groups = max77620_pinctrl_get_func_groups,
268 .set_mux = max77620_pinctrl_enable,
269};
270
271static int max77620_pinconf_get(struct pinctrl_dev *pctldev,
272 unsigned int pin, unsigned long *config)
273{
274 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
275 struct device *dev = mpci->dev;
276 enum pin_config_param param = pinconf_to_config_param(*config);
277 unsigned int val;
278 int arg = 0;
279 int ret;
280
281 switch (param) {
282 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
283 if (mpci->pin_info[pin].drv_type == MAX77620_PIN_OD_DRV)
284 arg = 1;
285 break;
286
287 case PIN_CONFIG_DRIVE_PUSH_PULL:
288 if (mpci->pin_info[pin].drv_type == MAX77620_PIN_PP_DRV)
289 arg = 1;
290 break;
291
292 case PIN_CONFIG_BIAS_PULL_UP:
293 ret = regmap_read(mpci->rmap, MAX77620_REG_PUE_GPIO, &val);
294 if (ret < 0) {
295 dev_err(dev, "Reg PUE_GPIO read failed: %d\n", ret);
296 return ret;
297 }
298 if (val & BIT(pin))
299 arg = 1;
300 break;
301
302 case PIN_CONFIG_BIAS_PULL_DOWN:
303 ret = regmap_read(mpci->rmap, MAX77620_REG_PDE_GPIO, &val);
304 if (ret < 0) {
305 dev_err(dev, "Reg PDE_GPIO read failed: %d\n", ret);
306 return ret;
307 }
308 if (val & BIT(pin))
309 arg = 1;
310 break;
311
312 default:
313 dev_err(dev, "Properties not supported\n");
314 return -ENOTSUPP;
315 }
316
317 *config = pinconf_to_config_packed(param, (u16)arg);
318
319 return 0;
320}
321
322static int max77620_get_default_fps(struct max77620_pctrl_info *mpci,
323 int addr, int *fps)
324{
325 unsigned int val;
326 int ret;
327
328 ret = regmap_read(mpci->rmap, addr, &val);
329 if (ret < 0) {
330 dev_err(mpci->dev, "Reg PUE_GPIO read failed: %d\n", ret);
331 return ret;
332 }
333 *fps = (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT;
334
335 return 0;
336}
337
338static int max77620_set_fps_param(struct max77620_pctrl_info *mpci,
339 int pin, int param)
340{
341 struct max77620_fps_config *fps_config = &mpci->fps_config[pin];
342 int addr, ret;
343 int param_val;
344 int mask, shift;
345
346 if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
347 return 0;
348
349 addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
350 switch (param) {
351 case MAX77620_ACTIVE_FPS_SOURCE:
352 case MAX77620_SUSPEND_FPS_SOURCE:
353 mask = MAX77620_FPS_SRC_MASK;
354 shift = MAX77620_FPS_SRC_SHIFT;
355 param_val = fps_config->active_fps_src;
356 if (param == MAX77620_SUSPEND_FPS_SOURCE)
357 param_val = fps_config->suspend_fps_src;
358 break;
359
360 case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS:
361 case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS:
362 mask = MAX77620_FPS_PU_PERIOD_MASK;
363 shift = MAX77620_FPS_PU_PERIOD_SHIFT;
364 param_val = fps_config->active_power_up_slots;
365 if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS)
366 param_val = fps_config->suspend_power_up_slots;
367 break;
368
369 case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS:
370 case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS:
371 mask = MAX77620_FPS_PD_PERIOD_MASK;
372 shift = MAX77620_FPS_PD_PERIOD_SHIFT;
373 param_val = fps_config->active_power_down_slots;
374 if (param == MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS)
375 param_val = fps_config->suspend_power_down_slots;
376 break;
377
378 default:
379 dev_err(mpci->dev, "Invalid parameter %d for pin %d\n",
380 param, pin);
381 return -EINVAL;
382 }
383
384 if (param_val < 0)
385 return 0;
386
387 ret = regmap_update_bits(mpci->rmap, addr, mask, param_val << shift);
388 if (ret < 0)
389 dev_err(mpci->dev, "Reg 0x%02x update failed %d\n", addr, ret);
390
391 return ret;
392}
393
394static int max77620_pinconf_set(struct pinctrl_dev *pctldev,
395 unsigned int pin, unsigned long *configs,
396 unsigned int num_configs)
397{
398 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
399 struct device *dev = mpci->dev;
400 struct max77620_fps_config *fps_config;
401 int param;
402 u32 param_val;
403 unsigned int val;
404 unsigned int pu_val;
405 unsigned int pd_val;
406 int addr, ret;
407 int i;
408
409 for (i = 0; i < num_configs; i++) {
410 param = pinconf_to_config_param(configs[i]);
411 param_val = pinconf_to_config_argument(configs[i]);
412
413 switch (param) {
414 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
415 val = param_val ? 0 : 1;
416 ret = regmap_update_bits(mpci->rmap,
417 MAX77620_REG_GPIO0 + pin,
418 MAX77620_CNFG_GPIO_DRV_MASK,
419 val);
420 if (ret)
421 goto report_update_failure;
422
423 mpci->pin_info[pin].drv_type = val ?
424 MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV;
425 break;
426
427 case PIN_CONFIG_DRIVE_PUSH_PULL:
428 val = param_val ? 1 : 0;
429 ret = regmap_update_bits(mpci->rmap,
430 MAX77620_REG_GPIO0 + pin,
431 MAX77620_CNFG_GPIO_DRV_MASK,
432 val);
433 if (ret)
434 goto report_update_failure;
435
436 mpci->pin_info[pin].drv_type = val ?
437 MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV;
438 break;
439
440 case MAX77620_ACTIVE_FPS_SOURCE:
441 case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS:
442 case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS:
443 if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
444 return -EINVAL;
445
446 fps_config = &mpci->fps_config[pin];
447
448 if ((param == MAX77620_ACTIVE_FPS_SOURCE) &&
449 (param_val == MAX77620_FPS_SRC_DEF)) {
450 addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
451 ret = max77620_get_default_fps(
452 mpci, addr,
453 &fps_config->active_fps_src);
454 if (ret < 0)
455 return ret;
456 break;
457 }
458
459 if (param == MAX77620_ACTIVE_FPS_SOURCE)
460 fps_config->active_fps_src = param_val;
461 else if (param == MAX77620_ACTIVE_FPS_POWER_ON_SLOTS)
462 fps_config->active_power_up_slots = param_val;
463 else
464 fps_config->active_power_down_slots = param_val;
465
466 ret = max77620_set_fps_param(mpci, pin, param);
467 if (ret < 0)
468 return ret;
469 break;
470
471 case MAX77620_SUSPEND_FPS_SOURCE:
472 case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS:
473 case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS:
474 if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
475 return -EINVAL;
476
477 fps_config = &mpci->fps_config[pin];
478
479 if ((param == MAX77620_SUSPEND_FPS_SOURCE) &&
480 (param_val == MAX77620_FPS_SRC_DEF)) {
481 addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
482 ret = max77620_get_default_fps(
483 mpci, addr,
484 &fps_config->suspend_fps_src);
485 if (ret < 0)
486 return ret;
487 break;
488 }
489
490 if (param == MAX77620_SUSPEND_FPS_SOURCE)
491 fps_config->suspend_fps_src = param_val;
492 else if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS)
493 fps_config->suspend_power_up_slots = param_val;
494 else
495 fps_config->suspend_power_down_slots =
496 param_val;
497 break;
498
499 case PIN_CONFIG_BIAS_PULL_UP:
500 case PIN_CONFIG_BIAS_PULL_DOWN:
501 pu_val = (param == PIN_CONFIG_BIAS_PULL_UP) ?
502 BIT(pin) : 0;
503 pd_val = (param == PIN_CONFIG_BIAS_PULL_DOWN) ?
504 BIT(pin) : 0;
505
506 ret = regmap_update_bits(mpci->rmap,
507 MAX77620_REG_PUE_GPIO,
508 BIT(pin), pu_val);
509 if (ret < 0) {
510 dev_err(dev, "PUE_GPIO update failed: %d\n",
511 ret);
512 return ret;
513 }
514
515 ret = regmap_update_bits(mpci->rmap,
516 MAX77620_REG_PDE_GPIO,
517 BIT(pin), pd_val);
518 if (ret < 0) {
519 dev_err(dev, "PDE_GPIO update failed: %d\n",
520 ret);
521 return ret;
522 }
523 break;
524
525 default:
526 dev_err(dev, "Properties not supported\n");
527 return -ENOTSUPP;
528 }
529 }
530
531 return 0;
532
533report_update_failure:
534 dev_err(dev, "Reg 0x%02x update failed %d\n",
535 MAX77620_REG_GPIO0 + pin, ret);
536 return ret;
537}
538
539static const struct pinconf_ops max77620_pinconf_ops = {
540 .pin_config_get = max77620_pinconf_get,
541 .pin_config_set = max77620_pinconf_set,
542};
543
544static struct pinctrl_desc max77620_pinctrl_desc = {
545 .pctlops = &max77620_pinctrl_ops,
546 .pmxops = &max77620_pinmux_ops,
547 .confops = &max77620_pinconf_ops,
548};
549
550static int max77620_pinctrl_probe(struct platform_device *pdev)
551{
552 struct max77620_chip *max77620 = dev_get_drvdata(pdev->dev.parent);
553 struct max77620_pctrl_info *mpci;
554 int i;
555
556 device_set_node(&pdev->dev, dev_fwnode(pdev->dev.parent));
557
558 mpci = devm_kzalloc(&pdev->dev, sizeof(*mpci), GFP_KERNEL);
559 if (!mpci)
560 return -ENOMEM;
561
562 mpci->dev = &pdev->dev;
563 mpci->rmap = max77620->rmap;
564
565 mpci->pins = max77620_pins_desc;
566 mpci->num_pins = ARRAY_SIZE(max77620_pins_desc);
567 mpci->functions = max77620_pin_function;
568 mpci->num_functions = ARRAY_SIZE(max77620_pin_function);
569 mpci->pin_groups = max77620_pingroups;
570 mpci->num_pin_groups = ARRAY_SIZE(max77620_pingroups);
571 platform_set_drvdata(pdev, mpci);
572
573 max77620_pinctrl_desc.name = dev_name(&pdev->dev);
574 max77620_pinctrl_desc.pins = max77620_pins_desc;
575 max77620_pinctrl_desc.npins = ARRAY_SIZE(max77620_pins_desc);
576 max77620_pinctrl_desc.num_custom_params =
577 ARRAY_SIZE(max77620_cfg_params);
578 max77620_pinctrl_desc.custom_params = max77620_cfg_params;
579
580 for (i = 0; i < MAX77620_PIN_NUM; ++i) {
581 mpci->fps_config[i].active_fps_src = -1;
582 mpci->fps_config[i].active_power_up_slots = -1;
583 mpci->fps_config[i].active_power_down_slots = -1;
584 mpci->fps_config[i].suspend_fps_src = -1;
585 mpci->fps_config[i].suspend_power_up_slots = -1;
586 mpci->fps_config[i].suspend_power_down_slots = -1;
587 }
588
589 mpci->pctl = devm_pinctrl_register(&pdev->dev, &max77620_pinctrl_desc,
590 mpci);
591 if (IS_ERR(mpci->pctl)) {
592 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
593 return PTR_ERR(mpci->pctl);
594 }
595
596 return 0;
597}
598
599#ifdef CONFIG_PM_SLEEP
600static int max77620_suspend_fps_param[] = {
601 MAX77620_SUSPEND_FPS_SOURCE,
602 MAX77620_SUSPEND_FPS_POWER_ON_SLOTS,
603 MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS,
604};
605
606static int max77620_active_fps_param[] = {
607 MAX77620_ACTIVE_FPS_SOURCE,
608 MAX77620_ACTIVE_FPS_POWER_ON_SLOTS,
609 MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS,
610};
611
612static int max77620_pinctrl_suspend(struct device *dev)
613{
614 struct max77620_pctrl_info *mpci = dev_get_drvdata(dev);
615 int pin, p;
616
617 for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) {
618 if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
619 continue;
620 for (p = 0; p < 3; ++p)
621 max77620_set_fps_param(
622 mpci, pin, max77620_suspend_fps_param[p]);
623 }
624
625 return 0;
626};
627
628static int max77620_pinctrl_resume(struct device *dev)
629{
630 struct max77620_pctrl_info *mpci = dev_get_drvdata(dev);
631 int pin, p;
632
633 for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) {
634 if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
635 continue;
636 for (p = 0; p < 3; ++p)
637 max77620_set_fps_param(
638 mpci, pin, max77620_active_fps_param[p]);
639 }
640
641 return 0;
642}
643#endif
644
645static const struct dev_pm_ops max77620_pinctrl_pm_ops = {
646 SET_SYSTEM_SLEEP_PM_OPS(
647 max77620_pinctrl_suspend, max77620_pinctrl_resume)
648};
649
650static const struct platform_device_id max77620_pinctrl_devtype[] = {
651 { .name = "max77620-pinctrl", },
652 { .name = "max20024-pinctrl", },
653 {},
654};
655MODULE_DEVICE_TABLE(platform, max77620_pinctrl_devtype);
656
657static struct platform_driver max77620_pinctrl_driver = {
658 .driver = {
659 .name = "max77620-pinctrl",
660 .pm = &max77620_pinctrl_pm_ops,
661 },
662 .probe = max77620_pinctrl_probe,
663 .id_table = max77620_pinctrl_devtype,
664};
665
666module_platform_driver(max77620_pinctrl_driver);
667
668MODULE_DESCRIPTION("MAX77620/MAX20024 pin control driver");
669MODULE_AUTHOR("Chaitanya Bandi<bandik@nvidia.com>");
670MODULE_AUTHOR("Laxman Dewangan<ldewangan@nvidia.com>");
671MODULE_LICENSE("GPL v2");