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1// SPDX-License-Identifier: GPL-2.0
2/**
3 * PCIe SERDES driver for AM654x SoC
4 *
5 * Copyright (C) 2018 - 2019 Texas Instruments Incorporated - http://www.ti.com/
6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
7 */
8
9#include <dt-bindings/phy/phy.h>
10#include <linux/clk.h>
11#include <linux/clk-provider.h>
12#include <linux/delay.h>
13#include <linux/module.h>
14#include <linux/mfd/syscon.h>
15#include <linux/mux/consumer.h>
16#include <linux/of_address.h>
17#include <linux/phy/phy.h>
18#include <linux/platform_device.h>
19#include <linux/pm_runtime.h>
20#include <linux/regmap.h>
21
22#define CMU_R07C 0x7c
23
24#define COMLANE_R138 0xb38
25#define VERSION 0x70
26
27#define COMLANE_R190 0xb90
28
29#define COMLANE_R194 0xb94
30
31#define SERDES_CTRL 0x1fd0
32
33#define WIZ_LANEXCTL_STS 0x1fe0
34#define TX0_DISABLE_STATE 0x4
35#define TX0_SLEEP_STATE 0x5
36#define TX0_SNOOZE_STATE 0x6
37#define TX0_ENABLE_STATE 0x7
38
39#define RX0_DISABLE_STATE 0x4
40#define RX0_SLEEP_STATE 0x5
41#define RX0_SNOOZE_STATE 0x6
42#define RX0_ENABLE_STATE 0x7
43
44#define WIZ_PLL_CTRL 0x1ff4
45#define PLL_DISABLE_STATE 0x4
46#define PLL_SLEEP_STATE 0x5
47#define PLL_SNOOZE_STATE 0x6
48#define PLL_ENABLE_STATE 0x7
49
50#define PLL_LOCK_TIME 100000 /* in microseconds */
51#define SLEEP_TIME 100 /* in microseconds */
52
53#define LANE_USB3 0x0
54#define LANE_PCIE0_LANE0 0x1
55
56#define LANE_PCIE1_LANE0 0x0
57#define LANE_PCIE0_LANE1 0x1
58
59#define SERDES_NUM_CLOCKS 3
60
61#define AM654_SERDES_CTRL_CLKSEL_MASK GENMASK(7, 4)
62#define AM654_SERDES_CTRL_CLKSEL_SHIFT 4
63
64struct serdes_am654_clk_mux {
65 struct clk_hw hw;
66 struct regmap *regmap;
67 unsigned int reg;
68 int clk_id;
69 struct clk_init_data clk_data;
70};
71
72#define to_serdes_am654_clk_mux(_hw) \
73 container_of(_hw, struct serdes_am654_clk_mux, hw)
74
75static const struct regmap_config serdes_am654_regmap_config = {
76 .reg_bits = 32,
77 .val_bits = 32,
78 .reg_stride = 4,
79 .fast_io = true,
80 .max_register = 0x1ffc,
81};
82
83static const struct reg_field cmu_master_cdn_o = REG_FIELD(CMU_R07C, 24, 24);
84static const struct reg_field config_version = REG_FIELD(COMLANE_R138, 16, 23);
85static const struct reg_field l1_master_cdn_o = REG_FIELD(COMLANE_R190, 9, 9);
86static const struct reg_field cmu_ok_i_0 = REG_FIELD(COMLANE_R194, 19, 19);
87static const struct reg_field por_en = REG_FIELD(SERDES_CTRL, 29, 29);
88static const struct reg_field tx0_enable = REG_FIELD(WIZ_LANEXCTL_STS, 29, 31);
89static const struct reg_field rx0_enable = REG_FIELD(WIZ_LANEXCTL_STS, 13, 15);
90static const struct reg_field pll_enable = REG_FIELD(WIZ_PLL_CTRL, 29, 31);
91static const struct reg_field pll_ok = REG_FIELD(WIZ_PLL_CTRL, 28, 28);
92
93struct serdes_am654 {
94 struct regmap *regmap;
95 struct regmap_field *cmu_master_cdn_o;
96 struct regmap_field *config_version;
97 struct regmap_field *l1_master_cdn_o;
98 struct regmap_field *cmu_ok_i_0;
99 struct regmap_field *por_en;
100 struct regmap_field *tx0_enable;
101 struct regmap_field *rx0_enable;
102 struct regmap_field *pll_enable;
103 struct regmap_field *pll_ok;
104
105 struct device *dev;
106 struct mux_control *control;
107 bool busy;
108 u32 type;
109 struct device_node *of_node;
110 struct clk_onecell_data clk_data;
111 struct clk *clks[SERDES_NUM_CLOCKS];
112};
113
114static int serdes_am654_enable_pll(struct serdes_am654 *phy)
115{
116 int ret;
117 u32 val;
118
119 ret = regmap_field_write(phy->pll_enable, PLL_ENABLE_STATE);
120 if (ret)
121 return ret;
122
123 return regmap_field_read_poll_timeout(phy->pll_ok, val, val, 1000,
124 PLL_LOCK_TIME);
125}
126
127static void serdes_am654_disable_pll(struct serdes_am654 *phy)
128{
129 struct device *dev = phy->dev;
130 int ret;
131
132 ret = regmap_field_write(phy->pll_enable, PLL_DISABLE_STATE);
133 if (ret)
134 dev_err(dev, "Failed to disable PLL\n");
135}
136
137static int serdes_am654_enable_txrx(struct serdes_am654 *phy)
138{
139 int ret;
140
141 /* Enable TX */
142 ret = regmap_field_write(phy->tx0_enable, TX0_ENABLE_STATE);
143 if (ret)
144 return ret;
145
146 /* Enable RX */
147 ret = regmap_field_write(phy->rx0_enable, RX0_ENABLE_STATE);
148 if (ret)
149 return ret;
150
151 return 0;
152}
153
154static int serdes_am654_disable_txrx(struct serdes_am654 *phy)
155{
156 int ret;
157
158 /* Disable TX */
159 ret = regmap_field_write(phy->tx0_enable, TX0_DISABLE_STATE);
160 if (ret)
161 return ret;
162
163 /* Disable RX */
164 ret = regmap_field_write(phy->rx0_enable, RX0_DISABLE_STATE);
165 if (ret)
166 return ret;
167
168 return 0;
169}
170
171static int serdes_am654_power_on(struct phy *x)
172{
173 struct serdes_am654 *phy = phy_get_drvdata(x);
174 struct device *dev = phy->dev;
175 int ret;
176 u32 val;
177
178 ret = serdes_am654_enable_pll(phy);
179 if (ret) {
180 dev_err(dev, "Failed to enable PLL\n");
181 return ret;
182 }
183
184 ret = serdes_am654_enable_txrx(phy);
185 if (ret) {
186 dev_err(dev, "Failed to enable TX RX\n");
187 return ret;
188 }
189
190 return regmap_field_read_poll_timeout(phy->cmu_ok_i_0, val, val,
191 SLEEP_TIME, PLL_LOCK_TIME);
192}
193
194static int serdes_am654_power_off(struct phy *x)
195{
196 struct serdes_am654 *phy = phy_get_drvdata(x);
197
198 serdes_am654_disable_txrx(phy);
199 serdes_am654_disable_pll(phy);
200
201 return 0;
202}
203
204#define SERDES_AM654_CFG(offset, a, b, val) \
205 regmap_update_bits(phy->regmap, (offset),\
206 GENMASK((a), (b)), (val) << (b))
207
208static int serdes_am654_usb3_init(struct serdes_am654 *phy)
209{
210 SERDES_AM654_CFG(0x0000, 31, 24, 0x17);
211 SERDES_AM654_CFG(0x0004, 15, 8, 0x02);
212 SERDES_AM654_CFG(0x0004, 7, 0, 0x0e);
213 SERDES_AM654_CFG(0x0008, 23, 16, 0x2e);
214 SERDES_AM654_CFG(0x0008, 31, 24, 0x2e);
215 SERDES_AM654_CFG(0x0060, 7, 0, 0x4b);
216 SERDES_AM654_CFG(0x0060, 15, 8, 0x98);
217 SERDES_AM654_CFG(0x0060, 23, 16, 0x60);
218 SERDES_AM654_CFG(0x00d0, 31, 24, 0x45);
219 SERDES_AM654_CFG(0x00e8, 15, 8, 0x0e);
220 SERDES_AM654_CFG(0x0220, 7, 0, 0x34);
221 SERDES_AM654_CFG(0x0220, 15, 8, 0x34);
222 SERDES_AM654_CFG(0x0220, 31, 24, 0x37);
223 SERDES_AM654_CFG(0x0224, 7, 0, 0x37);
224 SERDES_AM654_CFG(0x0224, 15, 8, 0x37);
225 SERDES_AM654_CFG(0x0228, 23, 16, 0x37);
226 SERDES_AM654_CFG(0x0228, 31, 24, 0x37);
227 SERDES_AM654_CFG(0x022c, 7, 0, 0x37);
228 SERDES_AM654_CFG(0x022c, 15, 8, 0x37);
229 SERDES_AM654_CFG(0x0230, 15, 8, 0x2a);
230 SERDES_AM654_CFG(0x0230, 23, 16, 0x2a);
231 SERDES_AM654_CFG(0x0240, 23, 16, 0x10);
232 SERDES_AM654_CFG(0x0240, 31, 24, 0x34);
233 SERDES_AM654_CFG(0x0244, 7, 0, 0x40);
234 SERDES_AM654_CFG(0x0244, 23, 16, 0x34);
235 SERDES_AM654_CFG(0x0248, 15, 8, 0x0d);
236 SERDES_AM654_CFG(0x0258, 15, 8, 0x16);
237 SERDES_AM654_CFG(0x0258, 23, 16, 0x84);
238 SERDES_AM654_CFG(0x0258, 31, 24, 0xf2);
239 SERDES_AM654_CFG(0x025c, 7, 0, 0x21);
240 SERDES_AM654_CFG(0x0260, 7, 0, 0x27);
241 SERDES_AM654_CFG(0x0260, 15, 8, 0x04);
242 SERDES_AM654_CFG(0x0268, 15, 8, 0x04);
243 SERDES_AM654_CFG(0x0288, 15, 8, 0x2c);
244 SERDES_AM654_CFG(0x0330, 31, 24, 0xa0);
245 SERDES_AM654_CFG(0x0338, 23, 16, 0x03);
246 SERDES_AM654_CFG(0x0338, 31, 24, 0x00);
247 SERDES_AM654_CFG(0x033c, 7, 0, 0x00);
248 SERDES_AM654_CFG(0x0344, 31, 24, 0x18);
249 SERDES_AM654_CFG(0x034c, 7, 0, 0x18);
250 SERDES_AM654_CFG(0x039c, 23, 16, 0x3b);
251 SERDES_AM654_CFG(0x0a04, 7, 0, 0x03);
252 SERDES_AM654_CFG(0x0a14, 31, 24, 0x3c);
253 SERDES_AM654_CFG(0x0a18, 15, 8, 0x3c);
254 SERDES_AM654_CFG(0x0a38, 7, 0, 0x3e);
255 SERDES_AM654_CFG(0x0a38, 15, 8, 0x3e);
256 SERDES_AM654_CFG(0x0ae0, 7, 0, 0x07);
257 SERDES_AM654_CFG(0x0b6c, 23, 16, 0xcd);
258 SERDES_AM654_CFG(0x0b6c, 31, 24, 0x04);
259 SERDES_AM654_CFG(0x0b98, 23, 16, 0x03);
260 SERDES_AM654_CFG(0x1400, 7, 0, 0x3f);
261 SERDES_AM654_CFG(0x1404, 23, 16, 0x6f);
262 SERDES_AM654_CFG(0x1404, 31, 24, 0x6f);
263 SERDES_AM654_CFG(0x140c, 7, 0, 0x6f);
264 SERDES_AM654_CFG(0x140c, 15, 8, 0x6f);
265 SERDES_AM654_CFG(0x1410, 15, 8, 0x27);
266 SERDES_AM654_CFG(0x1414, 7, 0, 0x0c);
267 SERDES_AM654_CFG(0x1414, 23, 16, 0x07);
268 SERDES_AM654_CFG(0x1418, 23, 16, 0x40);
269 SERDES_AM654_CFG(0x141c, 7, 0, 0x00);
270 SERDES_AM654_CFG(0x141c, 15, 8, 0x1f);
271 SERDES_AM654_CFG(0x1428, 31, 24, 0x08);
272 SERDES_AM654_CFG(0x1434, 31, 24, 0x00);
273 SERDES_AM654_CFG(0x1444, 7, 0, 0x94);
274 SERDES_AM654_CFG(0x1460, 31, 24, 0x7f);
275 SERDES_AM654_CFG(0x1464, 7, 0, 0x43);
276 SERDES_AM654_CFG(0x1464, 23, 16, 0x6f);
277 SERDES_AM654_CFG(0x1464, 31, 24, 0x43);
278 SERDES_AM654_CFG(0x1484, 23, 16, 0x8f);
279 SERDES_AM654_CFG(0x1498, 7, 0, 0x4f);
280 SERDES_AM654_CFG(0x1498, 23, 16, 0x4f);
281 SERDES_AM654_CFG(0x007c, 31, 24, 0x0d);
282 SERDES_AM654_CFG(0x0b90, 15, 8, 0x0f);
283
284 return 0;
285}
286
287static int serdes_am654_pcie_init(struct serdes_am654 *phy)
288{
289 int ret;
290
291 ret = regmap_field_write(phy->config_version, VERSION);
292 if (ret)
293 return ret;
294
295 ret = regmap_field_write(phy->cmu_master_cdn_o, 0x1);
296 if (ret)
297 return ret;
298
299 ret = regmap_field_write(phy->l1_master_cdn_o, 0x1);
300 if (ret)
301 return ret;
302
303 return 0;
304}
305
306static int serdes_am654_init(struct phy *x)
307{
308 struct serdes_am654 *phy = phy_get_drvdata(x);
309
310 switch (phy->type) {
311 case PHY_TYPE_PCIE:
312 return serdes_am654_pcie_init(phy);
313 case PHY_TYPE_USB3:
314 return serdes_am654_usb3_init(phy);
315 default:
316 return -EINVAL;
317 }
318}
319
320static int serdes_am654_reset(struct phy *x)
321{
322 struct serdes_am654 *phy = phy_get_drvdata(x);
323 int ret;
324
325 serdes_am654_disable_pll(phy);
326 serdes_am654_disable_txrx(phy);
327
328 ret = regmap_field_write(phy->por_en, 0x1);
329 if (ret)
330 return ret;
331
332 mdelay(1);
333
334 ret = regmap_field_write(phy->por_en, 0x0);
335 if (ret)
336 return ret;
337
338 return 0;
339}
340
341static void serdes_am654_release(struct phy *x)
342{
343 struct serdes_am654 *phy = phy_get_drvdata(x);
344
345 phy->type = PHY_NONE;
346 phy->busy = false;
347 mux_control_deselect(phy->control);
348}
349
350static struct phy *serdes_am654_xlate(struct device *dev,
351 struct of_phandle_args *args)
352{
353 struct serdes_am654 *am654_phy;
354 struct phy *phy;
355 int ret;
356
357 phy = of_phy_simple_xlate(dev, args);
358 if (IS_ERR(phy))
359 return phy;
360
361 am654_phy = phy_get_drvdata(phy);
362 if (am654_phy->busy)
363 return ERR_PTR(-EBUSY);
364
365 ret = mux_control_select(am654_phy->control, args->args[1]);
366 if (ret) {
367 dev_err(dev, "Failed to select SERDES Lane Function\n");
368 return ERR_PTR(ret);
369 }
370
371 am654_phy->busy = true;
372 am654_phy->type = args->args[0];
373
374 return phy;
375}
376
377static const struct phy_ops ops = {
378 .reset = serdes_am654_reset,
379 .init = serdes_am654_init,
380 .power_on = serdes_am654_power_on,
381 .power_off = serdes_am654_power_off,
382 .release = serdes_am654_release,
383 .owner = THIS_MODULE,
384};
385
386#define SERDES_NUM_MUX_COMBINATIONS 16
387
388#define LICLK 0
389#define EXT_REFCLK 1
390#define RICLK 2
391
392static const int
393serdes_am654_mux_table[SERDES_NUM_MUX_COMBINATIONS][SERDES_NUM_CLOCKS] = {
394 /*
395 * Each combination maps to one of
396 * "Figure 12-1986. SerDes Reference Clock Distribution"
397 * in TRM.
398 */
399 /* Parent of CMU refclk, Left output, Right output
400 * either of EXT_REFCLK, LICLK, RICLK
401 */
402 { EXT_REFCLK, EXT_REFCLK, EXT_REFCLK }, /* 0000 */
403 { RICLK, EXT_REFCLK, EXT_REFCLK }, /* 0001 */
404 { EXT_REFCLK, RICLK, LICLK }, /* 0010 */
405 { RICLK, RICLK, EXT_REFCLK }, /* 0011 */
406 { LICLK, EXT_REFCLK, EXT_REFCLK }, /* 0100 */
407 { EXT_REFCLK, EXT_REFCLK, EXT_REFCLK }, /* 0101 */
408 { LICLK, RICLK, LICLK }, /* 0110 */
409 { EXT_REFCLK, RICLK, LICLK }, /* 0111 */
410 { EXT_REFCLK, EXT_REFCLK, LICLK }, /* 1000 */
411 { RICLK, EXT_REFCLK, LICLK }, /* 1001 */
412 { EXT_REFCLK, RICLK, EXT_REFCLK }, /* 1010 */
413 { RICLK, RICLK, EXT_REFCLK }, /* 1011 */
414 { LICLK, EXT_REFCLK, LICLK }, /* 1100 */
415 { EXT_REFCLK, EXT_REFCLK, LICLK }, /* 1101 */
416 { LICLK, RICLK, EXT_REFCLK }, /* 1110 */
417 { EXT_REFCLK, RICLK, EXT_REFCLK }, /* 1111 */
418};
419
420static u8 serdes_am654_clk_mux_get_parent(struct clk_hw *hw)
421{
422 struct serdes_am654_clk_mux *mux = to_serdes_am654_clk_mux(hw);
423 struct regmap *regmap = mux->regmap;
424 unsigned int reg = mux->reg;
425 unsigned int val;
426
427 regmap_read(regmap, reg, &val);
428 val &= AM654_SERDES_CTRL_CLKSEL_MASK;
429 val >>= AM654_SERDES_CTRL_CLKSEL_SHIFT;
430
431 return serdes_am654_mux_table[val][mux->clk_id];
432}
433
434static int serdes_am654_clk_mux_set_parent(struct clk_hw *hw, u8 index)
435{
436 struct serdes_am654_clk_mux *mux = to_serdes_am654_clk_mux(hw);
437 struct regmap *regmap = mux->regmap;
438 const char *name = clk_hw_get_name(hw);
439 unsigned int reg = mux->reg;
440 int clk_id = mux->clk_id;
441 int parents[SERDES_NUM_CLOCKS];
442 const int *p;
443 u32 val;
444 int found, i;
445 int ret;
446
447 /* get existing setting */
448 regmap_read(regmap, reg, &val);
449 val &= AM654_SERDES_CTRL_CLKSEL_MASK;
450 val >>= AM654_SERDES_CTRL_CLKSEL_SHIFT;
451
452 for (i = 0; i < SERDES_NUM_CLOCKS; i++)
453 parents[i] = serdes_am654_mux_table[val][i];
454
455 /* change parent of this clock. others left intact */
456 parents[clk_id] = index;
457
458 /* Find the match */
459 for (val = 0; val < SERDES_NUM_MUX_COMBINATIONS; val++) {
460 p = serdes_am654_mux_table[val];
461 found = 1;
462 for (i = 0; i < SERDES_NUM_CLOCKS; i++) {
463 if (parents[i] != p[i]) {
464 found = 0;
465 break;
466 }
467 }
468
469 if (found)
470 break;
471 }
472
473 if (!found) {
474 /*
475 * This can never happen, unless we missed
476 * a valid combination in serdes_am654_mux_table.
477 */
478 WARN(1, "Failed to find the parent of %s clock\n", name);
479 return -EINVAL;
480 }
481
482 val <<= AM654_SERDES_CTRL_CLKSEL_SHIFT;
483 ret = regmap_update_bits(regmap, reg, AM654_SERDES_CTRL_CLKSEL_MASK,
484 val);
485
486 return ret;
487}
488
489static const struct clk_ops serdes_am654_clk_mux_ops = {
490 .set_parent = serdes_am654_clk_mux_set_parent,
491 .get_parent = serdes_am654_clk_mux_get_parent,
492};
493
494static int serdes_am654_clk_register(struct serdes_am654 *am654_phy,
495 const char *clock_name, int clock_num)
496{
497 struct device_node *node = am654_phy->of_node;
498 struct device *dev = am654_phy->dev;
499 struct serdes_am654_clk_mux *mux;
500 struct device_node *regmap_node;
501 const char **parent_names;
502 struct clk_init_data *init;
503 unsigned int num_parents;
504 struct regmap *regmap;
505 const __be32 *addr;
506 unsigned int reg;
507 struct clk *clk;
508 int ret = 0;
509
510 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
511 if (!mux)
512 return -ENOMEM;
513
514 init = &mux->clk_data;
515
516 regmap_node = of_parse_phandle(node, "ti,serdes-clk", 0);
517 if (!regmap_node) {
518 dev_err(dev, "Fail to get serdes-clk node\n");
519 ret = -ENODEV;
520 goto out_put_node;
521 }
522
523 regmap = syscon_node_to_regmap(regmap_node->parent);
524 if (IS_ERR(regmap)) {
525 dev_err(dev, "Fail to get Syscon regmap\n");
526 ret = PTR_ERR(regmap);
527 goto out_put_node;
528 }
529
530 num_parents = of_clk_get_parent_count(node);
531 if (num_parents < 2) {
532 dev_err(dev, "SERDES clock must have parents\n");
533 ret = -EINVAL;
534 goto out_put_node;
535 }
536
537 parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents),
538 GFP_KERNEL);
539 if (!parent_names) {
540 ret = -ENOMEM;
541 goto out_put_node;
542 }
543
544 of_clk_parent_fill(node, parent_names, num_parents);
545
546 addr = of_get_address(regmap_node, 0, NULL, NULL);
547 if (!addr) {
548 ret = -EINVAL;
549 goto out_put_node;
550 }
551
552 reg = be32_to_cpu(*addr);
553
554 init->ops = &serdes_am654_clk_mux_ops;
555 init->flags = CLK_SET_RATE_NO_REPARENT;
556 init->parent_names = parent_names;
557 init->num_parents = num_parents;
558 init->name = clock_name;
559
560 mux->regmap = regmap;
561 mux->reg = reg;
562 mux->clk_id = clock_num;
563 mux->hw.init = init;
564
565 clk = devm_clk_register(dev, &mux->hw);
566 if (IS_ERR(clk)) {
567 ret = PTR_ERR(clk);
568 goto out_put_node;
569 }
570
571 am654_phy->clks[clock_num] = clk;
572
573out_put_node:
574 of_node_put(regmap_node);
575 return ret;
576}
577
578static const struct of_device_id serdes_am654_id_table[] = {
579 {
580 .compatible = "ti,phy-am654-serdes",
581 },
582 {}
583};
584MODULE_DEVICE_TABLE(of, serdes_am654_id_table);
585
586static int serdes_am654_regfield_init(struct serdes_am654 *am654_phy)
587{
588 struct regmap *regmap = am654_phy->regmap;
589 struct device *dev = am654_phy->dev;
590
591 am654_phy->cmu_master_cdn_o = devm_regmap_field_alloc(dev, regmap,
592 cmu_master_cdn_o);
593 if (IS_ERR(am654_phy->cmu_master_cdn_o)) {
594 dev_err(dev, "CMU_MASTER_CDN_O reg field init failed\n");
595 return PTR_ERR(am654_phy->cmu_master_cdn_o);
596 }
597
598 am654_phy->config_version = devm_regmap_field_alloc(dev, regmap,
599 config_version);
600 if (IS_ERR(am654_phy->config_version)) {
601 dev_err(dev, "CONFIG_VERSION reg field init failed\n");
602 return PTR_ERR(am654_phy->config_version);
603 }
604
605 am654_phy->l1_master_cdn_o = devm_regmap_field_alloc(dev, regmap,
606 l1_master_cdn_o);
607 if (IS_ERR(am654_phy->l1_master_cdn_o)) {
608 dev_err(dev, "L1_MASTER_CDN_O reg field init failed\n");
609 return PTR_ERR(am654_phy->l1_master_cdn_o);
610 }
611
612 am654_phy->cmu_ok_i_0 = devm_regmap_field_alloc(dev, regmap,
613 cmu_ok_i_0);
614 if (IS_ERR(am654_phy->cmu_ok_i_0)) {
615 dev_err(dev, "CMU_OK_I_0 reg field init failed\n");
616 return PTR_ERR(am654_phy->cmu_ok_i_0);
617 }
618
619 am654_phy->por_en = devm_regmap_field_alloc(dev, regmap, por_en);
620 if (IS_ERR(am654_phy->por_en)) {
621 dev_err(dev, "POR_EN reg field init failed\n");
622 return PTR_ERR(am654_phy->por_en);
623 }
624
625 am654_phy->tx0_enable = devm_regmap_field_alloc(dev, regmap,
626 tx0_enable);
627 if (IS_ERR(am654_phy->tx0_enable)) {
628 dev_err(dev, "TX0_ENABLE reg field init failed\n");
629 return PTR_ERR(am654_phy->tx0_enable);
630 }
631
632 am654_phy->rx0_enable = devm_regmap_field_alloc(dev, regmap,
633 rx0_enable);
634 if (IS_ERR(am654_phy->rx0_enable)) {
635 dev_err(dev, "RX0_ENABLE reg field init failed\n");
636 return PTR_ERR(am654_phy->rx0_enable);
637 }
638
639 am654_phy->pll_enable = devm_regmap_field_alloc(dev, regmap,
640 pll_enable);
641 if (IS_ERR(am654_phy->pll_enable)) {
642 dev_err(dev, "PLL_ENABLE reg field init failed\n");
643 return PTR_ERR(am654_phy->pll_enable);
644 }
645
646 am654_phy->pll_ok = devm_regmap_field_alloc(dev, regmap, pll_ok);
647 if (IS_ERR(am654_phy->pll_ok)) {
648 dev_err(dev, "PLL_OK reg field init failed\n");
649 return PTR_ERR(am654_phy->pll_ok);
650 }
651
652 return 0;
653}
654
655static int serdes_am654_probe(struct platform_device *pdev)
656{
657 struct phy_provider *phy_provider;
658 struct device *dev = &pdev->dev;
659 struct device_node *node = dev->of_node;
660 struct clk_onecell_data *clk_data;
661 struct serdes_am654 *am654_phy;
662 struct mux_control *control;
663 const char *clock_name;
664 struct regmap *regmap;
665 void __iomem *base;
666 struct phy *phy;
667 int ret;
668 int i;
669
670 am654_phy = devm_kzalloc(dev, sizeof(*am654_phy), GFP_KERNEL);
671 if (!am654_phy)
672 return -ENOMEM;
673
674 base = devm_platform_ioremap_resource(pdev, 0);
675 if (IS_ERR(base))
676 return PTR_ERR(base);
677
678 regmap = devm_regmap_init_mmio(dev, base, &serdes_am654_regmap_config);
679 if (IS_ERR(regmap)) {
680 dev_err(dev, "Failed to initialize regmap\n");
681 return PTR_ERR(regmap);
682 }
683
684 control = devm_mux_control_get(dev, NULL);
685 if (IS_ERR(control))
686 return PTR_ERR(control);
687
688 am654_phy->dev = dev;
689 am654_phy->of_node = node;
690 am654_phy->regmap = regmap;
691 am654_phy->control = control;
692 am654_phy->type = PHY_NONE;
693
694 ret = serdes_am654_regfield_init(am654_phy);
695 if (ret) {
696 dev_err(dev, "Failed to initialize regfields\n");
697 return ret;
698 }
699
700 platform_set_drvdata(pdev, am654_phy);
701
702 for (i = 0; i < SERDES_NUM_CLOCKS; i++) {
703 ret = of_property_read_string_index(node, "clock-output-names",
704 i, &clock_name);
705 if (ret) {
706 dev_err(dev, "Failed to get clock name\n");
707 return ret;
708 }
709
710 ret = serdes_am654_clk_register(am654_phy, clock_name, i);
711 if (ret) {
712 dev_err(dev, "Failed to initialize clock %s\n",
713 clock_name);
714 return ret;
715 }
716 }
717
718 clk_data = &am654_phy->clk_data;
719 clk_data->clks = am654_phy->clks;
720 clk_data->clk_num = SERDES_NUM_CLOCKS;
721 ret = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
722 if (ret)
723 return ret;
724
725 pm_runtime_enable(dev);
726
727 phy = devm_phy_create(dev, NULL, &ops);
728 if (IS_ERR(phy)) {
729 ret = PTR_ERR(phy);
730 goto clk_err;
731 }
732
733 phy_set_drvdata(phy, am654_phy);
734 phy_provider = devm_of_phy_provider_register(dev, serdes_am654_xlate);
735 if (IS_ERR(phy_provider)) {
736 ret = PTR_ERR(phy_provider);
737 goto clk_err;
738 }
739
740 return 0;
741
742clk_err:
743 of_clk_del_provider(node);
744
745 return ret;
746}
747
748static int serdes_am654_remove(struct platform_device *pdev)
749{
750 struct serdes_am654 *am654_phy = platform_get_drvdata(pdev);
751 struct device_node *node = am654_phy->of_node;
752
753 pm_runtime_disable(&pdev->dev);
754 of_clk_del_provider(node);
755
756 return 0;
757}
758
759static struct platform_driver serdes_am654_driver = {
760 .probe = serdes_am654_probe,
761 .remove = serdes_am654_remove,
762 .driver = {
763 .name = "phy-am654",
764 .of_match_table = serdes_am654_id_table,
765 },
766};
767module_platform_driver(serdes_am654_driver);
768
769MODULE_AUTHOR("Texas Instruments Inc.");
770MODULE_DESCRIPTION("TI AM654x SERDES driver");
771MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * PCIe SERDES driver for AM654x SoC
4 *
5 * Copyright (C) 2018 - 2019 Texas Instruments Incorporated - http://www.ti.com/
6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
7 */
8
9#include <dt-bindings/phy/phy.h>
10#include <linux/clk.h>
11#include <linux/clk-provider.h>
12#include <linux/delay.h>
13#include <linux/module.h>
14#include <linux/mfd/syscon.h>
15#include <linux/mux/consumer.h>
16#include <linux/of_address.h>
17#include <linux/phy/phy.h>
18#include <linux/platform_device.h>
19#include <linux/pm_runtime.h>
20#include <linux/regmap.h>
21
22#define CMU_R004 0x4
23#define CMU_R060 0x60
24#define CMU_R07C 0x7c
25#define CMU_R088 0x88
26#define CMU_R0D0 0xd0
27#define CMU_R0E8 0xe8
28
29#define LANE_R048 0x248
30#define LANE_R058 0x258
31#define LANE_R06c 0x26c
32#define LANE_R070 0x270
33#define LANE_R070 0x270
34#define LANE_R19C 0x39c
35
36#define COMLANE_R004 0xa04
37#define COMLANE_R138 0xb38
38#define VERSION_VAL 0x70
39
40#define COMLANE_R190 0xb90
41#define COMLANE_R194 0xb94
42
43#define COMRXEQ_R004 0x1404
44#define COMRXEQ_R008 0x1408
45#define COMRXEQ_R00C 0x140c
46#define COMRXEQ_R014 0x1414
47#define COMRXEQ_R018 0x1418
48#define COMRXEQ_R01C 0x141c
49#define COMRXEQ_R04C 0x144c
50#define COMRXEQ_R088 0x1488
51#define COMRXEQ_R094 0x1494
52#define COMRXEQ_R098 0x1498
53
54#define SERDES_CTRL 0x1fd0
55
56#define WIZ_LANEXCTL_STS 0x1fe0
57#define TX0_DISABLE_STATE 0x4
58#define TX0_SLEEP_STATE 0x5
59#define TX0_SNOOZE_STATE 0x6
60#define TX0_ENABLE_STATE 0x7
61
62#define RX0_DISABLE_STATE 0x4
63#define RX0_SLEEP_STATE 0x5
64#define RX0_SNOOZE_STATE 0x6
65#define RX0_ENABLE_STATE 0x7
66
67#define WIZ_PLL_CTRL 0x1ff4
68#define PLL_DISABLE_STATE 0x4
69#define PLL_SLEEP_STATE 0x5
70#define PLL_SNOOZE_STATE 0x6
71#define PLL_ENABLE_STATE 0x7
72
73#define PLL_LOCK_TIME 100000 /* in microseconds */
74#define SLEEP_TIME 100 /* in microseconds */
75
76#define LANE_USB3 0x0
77#define LANE_PCIE0_LANE0 0x1
78
79#define LANE_PCIE1_LANE0 0x0
80#define LANE_PCIE0_LANE1 0x1
81
82#define SERDES_NUM_CLOCKS 3
83
84#define AM654_SERDES_CTRL_CLKSEL_MASK GENMASK(7, 4)
85#define AM654_SERDES_CTRL_CLKSEL_SHIFT 4
86
87struct serdes_am654_clk_mux {
88 struct clk_hw hw;
89 struct regmap *regmap;
90 unsigned int reg;
91 int clk_id;
92 struct clk_init_data clk_data;
93};
94
95#define to_serdes_am654_clk_mux(_hw) \
96 container_of(_hw, struct serdes_am654_clk_mux, hw)
97
98static const struct regmap_config serdes_am654_regmap_config = {
99 .reg_bits = 32,
100 .val_bits = 32,
101 .reg_stride = 4,
102 .fast_io = true,
103 .max_register = 0x1ffc,
104};
105
106enum serdes_am654_fields {
107 /* CMU PLL Control */
108 CMU_PLL_CTRL,
109
110 LANE_PLL_CTRL_RXEQ_RXIDLE,
111
112 /* CMU VCO bias current and VREG setting */
113 AHB_PMA_CM_VCO_VBIAS_VREG,
114 AHB_PMA_CM_VCO_BIAS_VREG,
115
116 AHB_PMA_CM_SR,
117 AHB_SSC_GEN_Z_O_20_13,
118
119 /* AHB PMA Lane Configuration */
120 AHB_PMA_LN_AGC_THSEL_VREGH,
121
122 /* AGC and Signal detect threshold for Gen3 */
123 AHB_PMA_LN_GEN3_AGC_SD_THSEL,
124
125 AHB_PMA_LN_RX_SELR_GEN3,
126 AHB_PMA_LN_TX_DRV,
127
128 /* CMU Master Reset */
129 CMU_MASTER_CDN,
130
131 /* P2S ring buffer initial startup pointer difference */
132 P2S_RBUF_PTR_DIFF,
133
134 CONFIG_VERSION,
135
136 /* Lane 1 Master Reset */
137 L1_MASTER_CDN,
138
139 /* CMU OK Status */
140 CMU_OK_I_0,
141
142 /* Mid-speed initial calibration control */
143 COMRXEQ_MS_INIT_CTRL_7_0,
144
145 /* High-speed initial calibration control */
146 COMRXEQ_HS_INIT_CAL_7_0,
147
148 /* Mid-speed recalibration control */
149 COMRXEQ_MS_RECAL_CTRL_7_0,
150
151 /* High-speed recalibration control */
152 COMRXEQ_HS_RECAL_CTRL_7_0,
153
154 /* ATT configuration */
155 COMRXEQ_CSR_ATT_CONFIG,
156
157 /* Edge based boost adaptation window length */
158 COMRXEQ_CSR_EBSTADAPT_WIN_LEN,
159
160 /* COMRXEQ control 3 & 4 */
161 COMRXEQ_CTRL_3_4,
162
163 /* COMRXEQ control 14, 15 and 16*/
164 COMRXEQ_CTRL_14_15_16,
165
166 /* Threshold for errors in pattern data */
167 COMRXEQ_CSR_DLEV_ERR_THRESH,
168
169 /* COMRXEQ control 25 */
170 COMRXEQ_CTRL_25,
171
172 /* Mid-speed rate change calibration control */
173 CSR_RXEQ_RATE_CHANGE_CAL_RUN_RATE2_O,
174
175 /* High-speed rate change calibration control */
176 COMRXEQ_HS_RCHANGE_CTRL_7_0,
177
178 /* Serdes reset */
179 POR_EN,
180
181 /* Tx Enable Value */
182 TX0_ENABLE,
183
184 /* Rx Enable Value */
185 RX0_ENABLE,
186
187 /* PLL Enable Value */
188 PLL_ENABLE,
189
190 /* PLL ready for use */
191 PLL_OK,
192
193 /* sentinel */
194 MAX_FIELDS
195
196};
197
198static const struct reg_field serdes_am654_reg_fields[] = {
199 [CMU_PLL_CTRL] = REG_FIELD(CMU_R004, 8, 15),
200 [AHB_PMA_CM_VCO_VBIAS_VREG] = REG_FIELD(CMU_R060, 8, 15),
201 [CMU_MASTER_CDN] = REG_FIELD(CMU_R07C, 24, 31),
202 [AHB_PMA_CM_VCO_BIAS_VREG] = REG_FIELD(CMU_R088, 24, 31),
203 [AHB_PMA_CM_SR] = REG_FIELD(CMU_R0D0, 24, 31),
204 [AHB_SSC_GEN_Z_O_20_13] = REG_FIELD(CMU_R0E8, 8, 15),
205 [LANE_PLL_CTRL_RXEQ_RXIDLE] = REG_FIELD(LANE_R048, 8, 15),
206 [AHB_PMA_LN_AGC_THSEL_VREGH] = REG_FIELD(LANE_R058, 16, 23),
207 [AHB_PMA_LN_GEN3_AGC_SD_THSEL] = REG_FIELD(LANE_R06c, 0, 7),
208 [AHB_PMA_LN_RX_SELR_GEN3] = REG_FIELD(LANE_R070, 16, 23),
209 [AHB_PMA_LN_TX_DRV] = REG_FIELD(LANE_R19C, 16, 23),
210 [P2S_RBUF_PTR_DIFF] = REG_FIELD(COMLANE_R004, 0, 7),
211 [CONFIG_VERSION] = REG_FIELD(COMLANE_R138, 16, 23),
212 [L1_MASTER_CDN] = REG_FIELD(COMLANE_R190, 8, 15),
213 [CMU_OK_I_0] = REG_FIELD(COMLANE_R194, 19, 19),
214 [COMRXEQ_MS_INIT_CTRL_7_0] = REG_FIELD(COMRXEQ_R004, 24, 31),
215 [COMRXEQ_HS_INIT_CAL_7_0] = REG_FIELD(COMRXEQ_R008, 0, 7),
216 [COMRXEQ_MS_RECAL_CTRL_7_0] = REG_FIELD(COMRXEQ_R00C, 8, 15),
217 [COMRXEQ_HS_RECAL_CTRL_7_0] = REG_FIELD(COMRXEQ_R00C, 16, 23),
218 [COMRXEQ_CSR_ATT_CONFIG] = REG_FIELD(COMRXEQ_R014, 16, 23),
219 [COMRXEQ_CSR_EBSTADAPT_WIN_LEN] = REG_FIELD(COMRXEQ_R018, 16, 23),
220 [COMRXEQ_CTRL_3_4] = REG_FIELD(COMRXEQ_R01C, 8, 15),
221 [COMRXEQ_CTRL_14_15_16] = REG_FIELD(COMRXEQ_R04C, 0, 7),
222 [COMRXEQ_CSR_DLEV_ERR_THRESH] = REG_FIELD(COMRXEQ_R088, 16, 23),
223 [COMRXEQ_CTRL_25] = REG_FIELD(COMRXEQ_R094, 24, 31),
224 [CSR_RXEQ_RATE_CHANGE_CAL_RUN_RATE2_O] = REG_FIELD(COMRXEQ_R098, 8, 15),
225 [COMRXEQ_HS_RCHANGE_CTRL_7_0] = REG_FIELD(COMRXEQ_R098, 16, 23),
226 [POR_EN] = REG_FIELD(SERDES_CTRL, 29, 29),
227 [TX0_ENABLE] = REG_FIELD(WIZ_LANEXCTL_STS, 29, 31),
228 [RX0_ENABLE] = REG_FIELD(WIZ_LANEXCTL_STS, 13, 15),
229 [PLL_ENABLE] = REG_FIELD(WIZ_PLL_CTRL, 29, 31),
230 [PLL_OK] = REG_FIELD(WIZ_PLL_CTRL, 28, 28),
231};
232
233struct serdes_am654 {
234 struct regmap *regmap;
235 struct regmap_field *fields[MAX_FIELDS];
236
237 struct device *dev;
238 struct mux_control *control;
239 bool busy;
240 u32 type;
241 struct device_node *of_node;
242 struct clk_onecell_data clk_data;
243 struct clk *clks[SERDES_NUM_CLOCKS];
244};
245
246static int serdes_am654_enable_pll(struct serdes_am654 *phy)
247{
248 int ret;
249 u32 val;
250
251 ret = regmap_field_write(phy->fields[PLL_ENABLE], PLL_ENABLE_STATE);
252 if (ret)
253 return ret;
254
255 return regmap_field_read_poll_timeout(phy->fields[PLL_OK], val, val,
256 1000, PLL_LOCK_TIME);
257}
258
259static void serdes_am654_disable_pll(struct serdes_am654 *phy)
260{
261 struct device *dev = phy->dev;
262 int ret;
263
264 ret = regmap_field_write(phy->fields[PLL_ENABLE], PLL_DISABLE_STATE);
265 if (ret)
266 dev_err(dev, "Failed to disable PLL\n");
267}
268
269static int serdes_am654_enable_txrx(struct serdes_am654 *phy)
270{
271 int ret = 0;
272
273 /* Enable TX */
274 ret |= regmap_field_write(phy->fields[TX0_ENABLE], TX0_ENABLE_STATE);
275
276 /* Enable RX */
277 ret |= regmap_field_write(phy->fields[RX0_ENABLE], RX0_ENABLE_STATE);
278
279 if (ret)
280 return -EIO;
281
282 return 0;
283}
284
285static int serdes_am654_disable_txrx(struct serdes_am654 *phy)
286{
287 int ret = 0;
288
289 /* Disable TX */
290 ret |= regmap_field_write(phy->fields[TX0_ENABLE], TX0_DISABLE_STATE);
291
292 /* Disable RX */
293 ret |= regmap_field_write(phy->fields[RX0_ENABLE], RX0_DISABLE_STATE);
294
295 if (ret)
296 return -EIO;
297
298 return 0;
299}
300
301static int serdes_am654_power_on(struct phy *x)
302{
303 struct serdes_am654 *phy = phy_get_drvdata(x);
304 struct device *dev = phy->dev;
305 int ret;
306 u32 val;
307
308 ret = serdes_am654_enable_pll(phy);
309 if (ret) {
310 dev_err(dev, "Failed to enable PLL\n");
311 return ret;
312 }
313
314 ret = serdes_am654_enable_txrx(phy);
315 if (ret) {
316 dev_err(dev, "Failed to enable TX RX\n");
317 return ret;
318 }
319
320 return regmap_field_read_poll_timeout(phy->fields[CMU_OK_I_0], val,
321 val, SLEEP_TIME, PLL_LOCK_TIME);
322}
323
324static int serdes_am654_power_off(struct phy *x)
325{
326 struct serdes_am654 *phy = phy_get_drvdata(x);
327
328 serdes_am654_disable_txrx(phy);
329 serdes_am654_disable_pll(phy);
330
331 return 0;
332}
333
334#define SERDES_AM654_CFG(offset, a, b, val) \
335 regmap_update_bits(phy->regmap, (offset),\
336 GENMASK((a), (b)), (val) << (b))
337
338static int serdes_am654_usb3_init(struct serdes_am654 *phy)
339{
340 SERDES_AM654_CFG(0x0000, 31, 24, 0x17);
341 SERDES_AM654_CFG(0x0004, 15, 8, 0x02);
342 SERDES_AM654_CFG(0x0004, 7, 0, 0x0e);
343 SERDES_AM654_CFG(0x0008, 23, 16, 0x2e);
344 SERDES_AM654_CFG(0x0008, 31, 24, 0x2e);
345 SERDES_AM654_CFG(0x0060, 7, 0, 0x4b);
346 SERDES_AM654_CFG(0x0060, 15, 8, 0x98);
347 SERDES_AM654_CFG(0x0060, 23, 16, 0x60);
348 SERDES_AM654_CFG(0x00d0, 31, 24, 0x45);
349 SERDES_AM654_CFG(0x00e8, 15, 8, 0x0e);
350 SERDES_AM654_CFG(0x0220, 7, 0, 0x34);
351 SERDES_AM654_CFG(0x0220, 15, 8, 0x34);
352 SERDES_AM654_CFG(0x0220, 31, 24, 0x37);
353 SERDES_AM654_CFG(0x0224, 7, 0, 0x37);
354 SERDES_AM654_CFG(0x0224, 15, 8, 0x37);
355 SERDES_AM654_CFG(0x0228, 23, 16, 0x37);
356 SERDES_AM654_CFG(0x0228, 31, 24, 0x37);
357 SERDES_AM654_CFG(0x022c, 7, 0, 0x37);
358 SERDES_AM654_CFG(0x022c, 15, 8, 0x37);
359 SERDES_AM654_CFG(0x0230, 15, 8, 0x2a);
360 SERDES_AM654_CFG(0x0230, 23, 16, 0x2a);
361 SERDES_AM654_CFG(0x0240, 23, 16, 0x10);
362 SERDES_AM654_CFG(0x0240, 31, 24, 0x34);
363 SERDES_AM654_CFG(0x0244, 7, 0, 0x40);
364 SERDES_AM654_CFG(0x0244, 23, 16, 0x34);
365 SERDES_AM654_CFG(0x0248, 15, 8, 0x0d);
366 SERDES_AM654_CFG(0x0258, 15, 8, 0x16);
367 SERDES_AM654_CFG(0x0258, 23, 16, 0x84);
368 SERDES_AM654_CFG(0x0258, 31, 24, 0xf2);
369 SERDES_AM654_CFG(0x025c, 7, 0, 0x21);
370 SERDES_AM654_CFG(0x0260, 7, 0, 0x27);
371 SERDES_AM654_CFG(0x0260, 15, 8, 0x04);
372 SERDES_AM654_CFG(0x0268, 15, 8, 0x04);
373 SERDES_AM654_CFG(0x0288, 15, 8, 0x2c);
374 SERDES_AM654_CFG(0x0330, 31, 24, 0xa0);
375 SERDES_AM654_CFG(0x0338, 23, 16, 0x03);
376 SERDES_AM654_CFG(0x0338, 31, 24, 0x00);
377 SERDES_AM654_CFG(0x033c, 7, 0, 0x00);
378 SERDES_AM654_CFG(0x0344, 31, 24, 0x18);
379 SERDES_AM654_CFG(0x034c, 7, 0, 0x18);
380 SERDES_AM654_CFG(0x039c, 23, 16, 0x3b);
381 SERDES_AM654_CFG(0x0a04, 7, 0, 0x03);
382 SERDES_AM654_CFG(0x0a14, 31, 24, 0x3c);
383 SERDES_AM654_CFG(0x0a18, 15, 8, 0x3c);
384 SERDES_AM654_CFG(0x0a38, 7, 0, 0x3e);
385 SERDES_AM654_CFG(0x0a38, 15, 8, 0x3e);
386 SERDES_AM654_CFG(0x0ae0, 7, 0, 0x07);
387 SERDES_AM654_CFG(0x0b6c, 23, 16, 0xcd);
388 SERDES_AM654_CFG(0x0b6c, 31, 24, 0x04);
389 SERDES_AM654_CFG(0x0b98, 23, 16, 0x03);
390 SERDES_AM654_CFG(0x1400, 7, 0, 0x3f);
391 SERDES_AM654_CFG(0x1404, 23, 16, 0x6f);
392 SERDES_AM654_CFG(0x1404, 31, 24, 0x6f);
393 SERDES_AM654_CFG(0x140c, 7, 0, 0x6f);
394 SERDES_AM654_CFG(0x140c, 15, 8, 0x6f);
395 SERDES_AM654_CFG(0x1410, 15, 8, 0x27);
396 SERDES_AM654_CFG(0x1414, 7, 0, 0x0c);
397 SERDES_AM654_CFG(0x1414, 23, 16, 0x07);
398 SERDES_AM654_CFG(0x1418, 23, 16, 0x40);
399 SERDES_AM654_CFG(0x141c, 7, 0, 0x00);
400 SERDES_AM654_CFG(0x141c, 15, 8, 0x1f);
401 SERDES_AM654_CFG(0x1428, 31, 24, 0x08);
402 SERDES_AM654_CFG(0x1434, 31, 24, 0x00);
403 SERDES_AM654_CFG(0x1444, 7, 0, 0x94);
404 SERDES_AM654_CFG(0x1460, 31, 24, 0x7f);
405 SERDES_AM654_CFG(0x1464, 7, 0, 0x43);
406 SERDES_AM654_CFG(0x1464, 23, 16, 0x6f);
407 SERDES_AM654_CFG(0x1464, 31, 24, 0x43);
408 SERDES_AM654_CFG(0x1484, 23, 16, 0x8f);
409 SERDES_AM654_CFG(0x1498, 7, 0, 0x4f);
410 SERDES_AM654_CFG(0x1498, 23, 16, 0x4f);
411 SERDES_AM654_CFG(0x007c, 31, 24, 0x0d);
412 SERDES_AM654_CFG(0x0b90, 15, 8, 0x0f);
413
414 return 0;
415}
416
417static int serdes_am654_pcie_init(struct serdes_am654 *phy)
418{
419 int ret = 0;
420
421 ret |= regmap_field_write(phy->fields[CMU_PLL_CTRL], 0x2);
422 ret |= regmap_field_write(phy->fields[AHB_PMA_CM_VCO_VBIAS_VREG], 0x98);
423 ret |= regmap_field_write(phy->fields[AHB_PMA_CM_VCO_BIAS_VREG], 0x98);
424 ret |= regmap_field_write(phy->fields[AHB_PMA_CM_SR], 0x45);
425 ret |= regmap_field_write(phy->fields[AHB_SSC_GEN_Z_O_20_13], 0xe);
426 ret |= regmap_field_write(phy->fields[LANE_PLL_CTRL_RXEQ_RXIDLE], 0x5);
427 ret |= regmap_field_write(phy->fields[AHB_PMA_LN_AGC_THSEL_VREGH], 0x83);
428 ret |= regmap_field_write(phy->fields[AHB_PMA_LN_GEN3_AGC_SD_THSEL], 0x83);
429 ret |= regmap_field_write(phy->fields[AHB_PMA_LN_RX_SELR_GEN3], 0x81);
430 ret |= regmap_field_write(phy->fields[AHB_PMA_LN_TX_DRV], 0x3b);
431 ret |= regmap_field_write(phy->fields[P2S_RBUF_PTR_DIFF], 0x3);
432 ret |= regmap_field_write(phy->fields[CONFIG_VERSION], VERSION_VAL);
433 ret |= regmap_field_write(phy->fields[COMRXEQ_MS_INIT_CTRL_7_0], 0xf);
434 ret |= regmap_field_write(phy->fields[COMRXEQ_HS_INIT_CAL_7_0], 0x4f);
435 ret |= regmap_field_write(phy->fields[COMRXEQ_MS_RECAL_CTRL_7_0], 0xf);
436 ret |= regmap_field_write(phy->fields[COMRXEQ_HS_RECAL_CTRL_7_0], 0x4f);
437 ret |= regmap_field_write(phy->fields[COMRXEQ_CSR_ATT_CONFIG], 0x7);
438 ret |= regmap_field_write(phy->fields[COMRXEQ_CSR_EBSTADAPT_WIN_LEN], 0x7f);
439 ret |= regmap_field_write(phy->fields[COMRXEQ_CTRL_3_4], 0xf);
440 ret |= regmap_field_write(phy->fields[COMRXEQ_CTRL_14_15_16], 0x9a);
441 ret |= regmap_field_write(phy->fields[COMRXEQ_CSR_DLEV_ERR_THRESH], 0x32);
442 ret |= regmap_field_write(phy->fields[COMRXEQ_CTRL_25], 0x80);
443 ret |= regmap_field_write(phy->fields[CSR_RXEQ_RATE_CHANGE_CAL_RUN_RATE2_O], 0xf);
444 ret |= regmap_field_write(phy->fields[COMRXEQ_HS_RCHANGE_CTRL_7_0], 0x4f);
445 ret |= regmap_field_write(phy->fields[CMU_MASTER_CDN], 0x1);
446 ret |= regmap_field_write(phy->fields[L1_MASTER_CDN], 0x2);
447
448 if (ret)
449 return -EIO;
450
451 return 0;
452}
453
454static int serdes_am654_init(struct phy *x)
455{
456 struct serdes_am654 *phy = phy_get_drvdata(x);
457
458 switch (phy->type) {
459 case PHY_TYPE_PCIE:
460 return serdes_am654_pcie_init(phy);
461 case PHY_TYPE_USB3:
462 return serdes_am654_usb3_init(phy);
463 default:
464 return -EINVAL;
465 }
466}
467
468static int serdes_am654_reset(struct phy *x)
469{
470 struct serdes_am654 *phy = phy_get_drvdata(x);
471 int ret = 0;
472
473 serdes_am654_disable_pll(phy);
474 serdes_am654_disable_txrx(phy);
475
476 ret |= regmap_field_write(phy->fields[POR_EN], 0x1);
477
478 mdelay(1);
479
480 ret |= regmap_field_write(phy->fields[POR_EN], 0x0);
481
482 if (ret)
483 return -EIO;
484
485 return 0;
486}
487
488static void serdes_am654_release(struct phy *x)
489{
490 struct serdes_am654 *phy = phy_get_drvdata(x);
491
492 phy->type = PHY_NONE;
493 phy->busy = false;
494 mux_control_deselect(phy->control);
495}
496
497static struct phy *serdes_am654_xlate(struct device *dev,
498 struct of_phandle_args *args)
499{
500 struct serdes_am654 *am654_phy;
501 struct phy *phy;
502 int ret;
503
504 phy = of_phy_simple_xlate(dev, args);
505 if (IS_ERR(phy))
506 return phy;
507
508 am654_phy = phy_get_drvdata(phy);
509 if (am654_phy->busy)
510 return ERR_PTR(-EBUSY);
511
512 ret = mux_control_select(am654_phy->control, args->args[1]);
513 if (ret) {
514 dev_err(dev, "Failed to select SERDES Lane Function\n");
515 return ERR_PTR(ret);
516 }
517
518 am654_phy->busy = true;
519 am654_phy->type = args->args[0];
520
521 return phy;
522}
523
524static const struct phy_ops ops = {
525 .reset = serdes_am654_reset,
526 .init = serdes_am654_init,
527 .power_on = serdes_am654_power_on,
528 .power_off = serdes_am654_power_off,
529 .release = serdes_am654_release,
530 .owner = THIS_MODULE,
531};
532
533#define SERDES_NUM_MUX_COMBINATIONS 16
534
535#define LICLK 0
536#define EXT_REFCLK 1
537#define RICLK 2
538
539static const int
540serdes_am654_mux_table[SERDES_NUM_MUX_COMBINATIONS][SERDES_NUM_CLOCKS] = {
541 /*
542 * Each combination maps to one of
543 * "Figure 12-1986. SerDes Reference Clock Distribution"
544 * in TRM.
545 */
546 /* Parent of CMU refclk, Left output, Right output
547 * either of EXT_REFCLK, LICLK, RICLK
548 */
549 { EXT_REFCLK, EXT_REFCLK, EXT_REFCLK }, /* 0000 */
550 { RICLK, EXT_REFCLK, EXT_REFCLK }, /* 0001 */
551 { EXT_REFCLK, RICLK, LICLK }, /* 0010 */
552 { RICLK, RICLK, EXT_REFCLK }, /* 0011 */
553 { LICLK, EXT_REFCLK, EXT_REFCLK }, /* 0100 */
554 { EXT_REFCLK, EXT_REFCLK, EXT_REFCLK }, /* 0101 */
555 { LICLK, RICLK, LICLK }, /* 0110 */
556 { EXT_REFCLK, RICLK, LICLK }, /* 0111 */
557 { EXT_REFCLK, EXT_REFCLK, LICLK }, /* 1000 */
558 { RICLK, EXT_REFCLK, LICLK }, /* 1001 */
559 { EXT_REFCLK, RICLK, EXT_REFCLK }, /* 1010 */
560 { RICLK, RICLK, EXT_REFCLK }, /* 1011 */
561 { LICLK, EXT_REFCLK, LICLK }, /* 1100 */
562 { EXT_REFCLK, EXT_REFCLK, LICLK }, /* 1101 */
563 { LICLK, RICLK, EXT_REFCLK }, /* 1110 */
564 { EXT_REFCLK, RICLK, EXT_REFCLK }, /* 1111 */
565};
566
567static u8 serdes_am654_clk_mux_get_parent(struct clk_hw *hw)
568{
569 struct serdes_am654_clk_mux *mux = to_serdes_am654_clk_mux(hw);
570 struct regmap *regmap = mux->regmap;
571 unsigned int reg = mux->reg;
572 unsigned int val;
573
574 regmap_read(regmap, reg, &val);
575 val &= AM654_SERDES_CTRL_CLKSEL_MASK;
576 val >>= AM654_SERDES_CTRL_CLKSEL_SHIFT;
577
578 return serdes_am654_mux_table[val][mux->clk_id];
579}
580
581static int serdes_am654_clk_mux_set_parent(struct clk_hw *hw, u8 index)
582{
583 struct serdes_am654_clk_mux *mux = to_serdes_am654_clk_mux(hw);
584 struct regmap *regmap = mux->regmap;
585 const char *name = clk_hw_get_name(hw);
586 unsigned int reg = mux->reg;
587 int clk_id = mux->clk_id;
588 int parents[SERDES_NUM_CLOCKS];
589 const int *p;
590 u32 val;
591 int found, i;
592 int ret;
593
594 /* get existing setting */
595 regmap_read(regmap, reg, &val);
596 val &= AM654_SERDES_CTRL_CLKSEL_MASK;
597 val >>= AM654_SERDES_CTRL_CLKSEL_SHIFT;
598
599 for (i = 0; i < SERDES_NUM_CLOCKS; i++)
600 parents[i] = serdes_am654_mux_table[val][i];
601
602 /* change parent of this clock. others left intact */
603 parents[clk_id] = index;
604
605 /* Find the match */
606 for (val = 0; val < SERDES_NUM_MUX_COMBINATIONS; val++) {
607 p = serdes_am654_mux_table[val];
608 found = 1;
609 for (i = 0; i < SERDES_NUM_CLOCKS; i++) {
610 if (parents[i] != p[i]) {
611 found = 0;
612 break;
613 }
614 }
615
616 if (found)
617 break;
618 }
619
620 if (!found) {
621 /*
622 * This can never happen, unless we missed
623 * a valid combination in serdes_am654_mux_table.
624 */
625 WARN(1, "Failed to find the parent of %s clock\n", name);
626 return -EINVAL;
627 }
628
629 val <<= AM654_SERDES_CTRL_CLKSEL_SHIFT;
630 ret = regmap_update_bits(regmap, reg, AM654_SERDES_CTRL_CLKSEL_MASK,
631 val);
632
633 return ret;
634}
635
636static const struct clk_ops serdes_am654_clk_mux_ops = {
637 .determine_rate = __clk_mux_determine_rate,
638 .set_parent = serdes_am654_clk_mux_set_parent,
639 .get_parent = serdes_am654_clk_mux_get_parent,
640};
641
642static int serdes_am654_clk_register(struct serdes_am654 *am654_phy,
643 const char *clock_name, int clock_num)
644{
645 struct device_node *node = am654_phy->of_node;
646 struct device *dev = am654_phy->dev;
647 struct serdes_am654_clk_mux *mux;
648 struct device_node *regmap_node;
649 const char **parent_names;
650 struct clk_init_data *init;
651 unsigned int num_parents;
652 struct regmap *regmap;
653 const __be32 *addr;
654 unsigned int reg;
655 struct clk *clk;
656 int ret = 0;
657
658 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
659 if (!mux)
660 return -ENOMEM;
661
662 init = &mux->clk_data;
663
664 regmap_node = of_parse_phandle(node, "ti,serdes-clk", 0);
665 if (!regmap_node) {
666 dev_err(dev, "Fail to get serdes-clk node\n");
667 ret = -ENODEV;
668 goto out_put_node;
669 }
670
671 regmap = syscon_node_to_regmap(regmap_node->parent);
672 if (IS_ERR(regmap)) {
673 dev_err(dev, "Fail to get Syscon regmap\n");
674 ret = PTR_ERR(regmap);
675 goto out_put_node;
676 }
677
678 num_parents = of_clk_get_parent_count(node);
679 if (num_parents < 2) {
680 dev_err(dev, "SERDES clock must have parents\n");
681 ret = -EINVAL;
682 goto out_put_node;
683 }
684
685 parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents),
686 GFP_KERNEL);
687 if (!parent_names) {
688 ret = -ENOMEM;
689 goto out_put_node;
690 }
691
692 of_clk_parent_fill(node, parent_names, num_parents);
693
694 addr = of_get_address(regmap_node, 0, NULL, NULL);
695 if (!addr) {
696 ret = -EINVAL;
697 goto out_put_node;
698 }
699
700 reg = be32_to_cpu(*addr);
701
702 init->ops = &serdes_am654_clk_mux_ops;
703 init->flags = CLK_SET_RATE_NO_REPARENT;
704 init->parent_names = parent_names;
705 init->num_parents = num_parents;
706 init->name = clock_name;
707
708 mux->regmap = regmap;
709 mux->reg = reg;
710 mux->clk_id = clock_num;
711 mux->hw.init = init;
712
713 clk = devm_clk_register(dev, &mux->hw);
714 if (IS_ERR(clk)) {
715 ret = PTR_ERR(clk);
716 goto out_put_node;
717 }
718
719 am654_phy->clks[clock_num] = clk;
720
721out_put_node:
722 of_node_put(regmap_node);
723 return ret;
724}
725
726static const struct of_device_id serdes_am654_id_table[] = {
727 {
728 .compatible = "ti,phy-am654-serdes",
729 },
730 {}
731};
732MODULE_DEVICE_TABLE(of, serdes_am654_id_table);
733
734static int serdes_am654_regfield_init(struct serdes_am654 *am654_phy)
735{
736 struct regmap *regmap = am654_phy->regmap;
737 struct device *dev = am654_phy->dev;
738 int i;
739
740 for (i = 0; i < MAX_FIELDS; i++) {
741 am654_phy->fields[i] = devm_regmap_field_alloc(dev,
742 regmap,
743 serdes_am654_reg_fields[i]);
744 if (IS_ERR(am654_phy->fields[i])) {
745 dev_err(dev, "Unable to allocate regmap field %d\n", i);
746 return PTR_ERR(am654_phy->fields[i]);
747 }
748 }
749
750 return 0;
751}
752
753static int serdes_am654_probe(struct platform_device *pdev)
754{
755 struct phy_provider *phy_provider;
756 struct device *dev = &pdev->dev;
757 struct device_node *node = dev->of_node;
758 struct clk_onecell_data *clk_data;
759 struct serdes_am654 *am654_phy;
760 struct mux_control *control;
761 const char *clock_name;
762 struct regmap *regmap;
763 void __iomem *base;
764 struct phy *phy;
765 int ret;
766 int i;
767
768 am654_phy = devm_kzalloc(dev, sizeof(*am654_phy), GFP_KERNEL);
769 if (!am654_phy)
770 return -ENOMEM;
771
772 base = devm_platform_ioremap_resource(pdev, 0);
773 if (IS_ERR(base))
774 return PTR_ERR(base);
775
776 regmap = devm_regmap_init_mmio(dev, base, &serdes_am654_regmap_config);
777 if (IS_ERR(regmap)) {
778 dev_err(dev, "Failed to initialize regmap\n");
779 return PTR_ERR(regmap);
780 }
781
782 control = devm_mux_control_get(dev, NULL);
783 if (IS_ERR(control))
784 return PTR_ERR(control);
785
786 am654_phy->dev = dev;
787 am654_phy->of_node = node;
788 am654_phy->regmap = regmap;
789 am654_phy->control = control;
790 am654_phy->type = PHY_NONE;
791
792 ret = serdes_am654_regfield_init(am654_phy);
793 if (ret) {
794 dev_err(dev, "Failed to initialize regfields\n");
795 return ret;
796 }
797
798 platform_set_drvdata(pdev, am654_phy);
799
800 for (i = 0; i < SERDES_NUM_CLOCKS; i++) {
801 ret = of_property_read_string_index(node, "clock-output-names",
802 i, &clock_name);
803 if (ret) {
804 dev_err(dev, "Failed to get clock name\n");
805 return ret;
806 }
807
808 ret = serdes_am654_clk_register(am654_phy, clock_name, i);
809 if (ret) {
810 dev_err(dev, "Failed to initialize clock %s\n",
811 clock_name);
812 return ret;
813 }
814 }
815
816 clk_data = &am654_phy->clk_data;
817 clk_data->clks = am654_phy->clks;
818 clk_data->clk_num = SERDES_NUM_CLOCKS;
819 ret = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
820 if (ret)
821 return ret;
822
823 pm_runtime_enable(dev);
824
825 phy = devm_phy_create(dev, NULL, &ops);
826 if (IS_ERR(phy)) {
827 ret = PTR_ERR(phy);
828 goto clk_err;
829 }
830
831 phy_set_drvdata(phy, am654_phy);
832 phy_provider = devm_of_phy_provider_register(dev, serdes_am654_xlate);
833 if (IS_ERR(phy_provider)) {
834 ret = PTR_ERR(phy_provider);
835 goto clk_err;
836 }
837
838 return 0;
839
840clk_err:
841 of_clk_del_provider(node);
842 pm_runtime_disable(dev);
843 return ret;
844}
845
846static void serdes_am654_remove(struct platform_device *pdev)
847{
848 struct serdes_am654 *am654_phy = platform_get_drvdata(pdev);
849 struct device_node *node = am654_phy->of_node;
850
851 pm_runtime_disable(&pdev->dev);
852 of_clk_del_provider(node);
853}
854
855static struct platform_driver serdes_am654_driver = {
856 .probe = serdes_am654_probe,
857 .remove_new = serdes_am654_remove,
858 .driver = {
859 .name = "phy-am654",
860 .of_match_table = serdes_am654_id_table,
861 },
862};
863module_platform_driver(serdes_am654_driver);
864
865MODULE_AUTHOR("Texas Instruments Inc.");
866MODULE_DESCRIPTION("TI AM654x SERDES driver");
867MODULE_LICENSE("GPL v2");