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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * platform_device probing code for ARM performance counters.
4 *
5 * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
6 * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
7 */
8#define pr_fmt(fmt) "hw perfevents: " fmt
9
10#include <linux/bug.h>
11#include <linux/cpumask.h>
12#include <linux/device.h>
13#include <linux/errno.h>
14#include <linux/irq.h>
15#include <linux/irqdesc.h>
16#include <linux/kconfig.h>
17#include <linux/of.h>
18#include <linux/of_device.h>
19#include <linux/percpu.h>
20#include <linux/perf/arm_pmu.h>
21#include <linux/platform_device.h>
22#include <linux/printk.h>
23#include <linux/smp.h>
24
25static int probe_current_pmu(struct arm_pmu *pmu,
26 const struct pmu_probe_info *info)
27{
28 int cpu = get_cpu();
29 unsigned int cpuid = read_cpuid_id();
30 int ret = -ENODEV;
31
32 pr_info("probing PMU on CPU %d\n", cpu);
33
34 for (; info->init != NULL; info++) {
35 if ((cpuid & info->mask) != info->cpuid)
36 continue;
37 ret = info->init(pmu);
38 break;
39 }
40
41 put_cpu();
42 return ret;
43}
44
45static int pmu_parse_percpu_irq(struct arm_pmu *pmu, int irq)
46{
47 int cpu, ret;
48 struct pmu_hw_events __percpu *hw_events = pmu->hw_events;
49
50 ret = irq_get_percpu_devid_partition(irq, &pmu->supported_cpus);
51 if (ret)
52 return ret;
53
54 for_each_cpu(cpu, &pmu->supported_cpus)
55 per_cpu(hw_events->irq, cpu) = irq;
56
57 return 0;
58}
59
60static bool pmu_has_irq_affinity(struct device_node *node)
61{
62 return !!of_find_property(node, "interrupt-affinity", NULL);
63}
64
65static int pmu_parse_irq_affinity(struct device_node *node, int i)
66{
67 struct device_node *dn;
68 int cpu;
69
70 /*
71 * If we don't have an interrupt-affinity property, we guess irq
72 * affinity matches our logical CPU order, as we used to assume.
73 * This is fragile, so we'll warn in pmu_parse_irqs().
74 */
75 if (!pmu_has_irq_affinity(node))
76 return i;
77
78 dn = of_parse_phandle(node, "interrupt-affinity", i);
79 if (!dn) {
80 pr_warn("failed to parse interrupt-affinity[%d] for %pOFn\n",
81 i, node);
82 return -EINVAL;
83 }
84
85 cpu = of_cpu_node_to_id(dn);
86 if (cpu < 0) {
87 pr_warn("failed to find logical CPU for %pOFn\n", dn);
88 cpu = nr_cpu_ids;
89 }
90
91 of_node_put(dn);
92
93 return cpu;
94}
95
96static int pmu_parse_irqs(struct arm_pmu *pmu)
97{
98 int i = 0, num_irqs;
99 struct platform_device *pdev = pmu->plat_device;
100 struct pmu_hw_events __percpu *hw_events = pmu->hw_events;
101
102 num_irqs = platform_irq_count(pdev);
103 if (num_irqs < 0) {
104 pr_err("unable to count PMU IRQs\n");
105 return num_irqs;
106 }
107
108 /*
109 * In this case we have no idea which CPUs are covered by the PMU.
110 * To match our prior behaviour, we assume all CPUs in this case.
111 */
112 if (num_irqs == 0) {
113 pr_warn("no irqs for PMU, sampling events not supported\n");
114 pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
115 cpumask_setall(&pmu->supported_cpus);
116 return 0;
117 }
118
119 if (num_irqs == 1) {
120 int irq = platform_get_irq(pdev, 0);
121 if (irq && irq_is_percpu_devid(irq))
122 return pmu_parse_percpu_irq(pmu, irq);
123 }
124
125 if (nr_cpu_ids != 1 && !pmu_has_irq_affinity(pdev->dev.of_node)) {
126 pr_warn("no interrupt-affinity property for %pOF, guessing.\n",
127 pdev->dev.of_node);
128 }
129
130 for (i = 0; i < num_irqs; i++) {
131 int cpu, irq;
132
133 irq = platform_get_irq(pdev, i);
134 if (WARN_ON(irq <= 0))
135 continue;
136
137 if (irq_is_percpu_devid(irq)) {
138 pr_warn("multiple PPIs or mismatched SPI/PPI detected\n");
139 return -EINVAL;
140 }
141
142 cpu = pmu_parse_irq_affinity(pdev->dev.of_node, i);
143 if (cpu < 0)
144 return cpu;
145 if (cpu >= nr_cpu_ids)
146 continue;
147
148 if (per_cpu(hw_events->irq, cpu)) {
149 pr_warn("multiple PMU IRQs for the same CPU detected\n");
150 return -EINVAL;
151 }
152
153 per_cpu(hw_events->irq, cpu) = irq;
154 cpumask_set_cpu(cpu, &pmu->supported_cpus);
155 }
156
157 return 0;
158}
159
160static int armpmu_request_irqs(struct arm_pmu *armpmu)
161{
162 struct pmu_hw_events __percpu *hw_events = armpmu->hw_events;
163 int cpu, err = 0;
164
165 for_each_cpu(cpu, &armpmu->supported_cpus) {
166 int irq = per_cpu(hw_events->irq, cpu);
167 if (!irq)
168 continue;
169
170 err = armpmu_request_irq(irq, cpu);
171 if (err)
172 break;
173 }
174
175 return err;
176}
177
178static void armpmu_free_irqs(struct arm_pmu *armpmu)
179{
180 int cpu;
181 struct pmu_hw_events __percpu *hw_events = armpmu->hw_events;
182
183 for_each_cpu(cpu, &armpmu->supported_cpus) {
184 int irq = per_cpu(hw_events->irq, cpu);
185
186 armpmu_free_irq(irq, cpu);
187 }
188}
189
190int arm_pmu_device_probe(struct platform_device *pdev,
191 const struct of_device_id *of_table,
192 const struct pmu_probe_info *probe_table)
193{
194 const struct of_device_id *of_id;
195 armpmu_init_fn init_fn;
196 struct device_node *node = pdev->dev.of_node;
197 struct arm_pmu *pmu;
198 int ret = -ENODEV;
199
200 pmu = armpmu_alloc();
201 if (!pmu)
202 return -ENOMEM;
203
204 pmu->plat_device = pdev;
205
206 ret = pmu_parse_irqs(pmu);
207 if (ret)
208 goto out_free;
209
210 if (node && (of_id = of_match_node(of_table, pdev->dev.of_node))) {
211 init_fn = of_id->data;
212
213 pmu->secure_access = of_property_read_bool(pdev->dev.of_node,
214 "secure-reg-access");
215
216 /* arm64 systems boot only as non-secure */
217 if (IS_ENABLED(CONFIG_ARM64) && pmu->secure_access) {
218 pr_warn("ignoring \"secure-reg-access\" property for arm64\n");
219 pmu->secure_access = false;
220 }
221
222 ret = init_fn(pmu);
223 } else if (probe_table) {
224 cpumask_setall(&pmu->supported_cpus);
225 ret = probe_current_pmu(pmu, probe_table);
226 }
227
228 if (ret) {
229 pr_info("%pOF: failed to probe PMU!\n", node);
230 goto out_free;
231 }
232
233 ret = armpmu_request_irqs(pmu);
234 if (ret)
235 goto out_free_irqs;
236
237 ret = armpmu_register(pmu);
238 if (ret)
239 goto out_free;
240
241 return 0;
242
243out_free_irqs:
244 armpmu_free_irqs(pmu);
245out_free:
246 pr_info("%pOF: failed to register PMU devices!\n", node);
247 armpmu_free(pmu);
248 return ret;
249}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * platform_device probing code for ARM performance counters.
4 *
5 * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
6 * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
7 */
8#define pr_fmt(fmt) "hw perfevents: " fmt
9#define dev_fmt pr_fmt
10
11#include <linux/bug.h>
12#include <linux/cpumask.h>
13#include <linux/device.h>
14#include <linux/errno.h>
15#include <linux/irq.h>
16#include <linux/irqdesc.h>
17#include <linux/kconfig.h>
18#include <linux/of.h>
19#include <linux/percpu.h>
20#include <linux/perf/arm_pmu.h>
21#include <linux/platform_device.h>
22#include <linux/printk.h>
23#include <linux/smp.h>
24
25static int probe_current_pmu(struct arm_pmu *pmu,
26 const struct pmu_probe_info *info)
27{
28 int cpu = get_cpu();
29 unsigned int cpuid = read_cpuid_id();
30 int ret = -ENODEV;
31
32 pr_info("probing PMU on CPU %d\n", cpu);
33
34 for (; info->init != NULL; info++) {
35 if ((cpuid & info->mask) != info->cpuid)
36 continue;
37 ret = info->init(pmu);
38 break;
39 }
40
41 put_cpu();
42 return ret;
43}
44
45static int pmu_parse_percpu_irq(struct arm_pmu *pmu, int irq)
46{
47 int cpu, ret;
48 struct pmu_hw_events __percpu *hw_events = pmu->hw_events;
49
50 ret = irq_get_percpu_devid_partition(irq, &pmu->supported_cpus);
51 if (ret)
52 return ret;
53
54 for_each_cpu(cpu, &pmu->supported_cpus)
55 per_cpu(hw_events->irq, cpu) = irq;
56
57 return 0;
58}
59
60static bool pmu_has_irq_affinity(struct device_node *node)
61{
62 return !!of_find_property(node, "interrupt-affinity", NULL);
63}
64
65static int pmu_parse_irq_affinity(struct device *dev, int i)
66{
67 struct device_node *dn;
68 int cpu;
69
70 /*
71 * If we don't have an interrupt-affinity property, we guess irq
72 * affinity matches our logical CPU order, as we used to assume.
73 * This is fragile, so we'll warn in pmu_parse_irqs().
74 */
75 if (!pmu_has_irq_affinity(dev->of_node))
76 return i;
77
78 dn = of_parse_phandle(dev->of_node, "interrupt-affinity", i);
79 if (!dn) {
80 dev_warn(dev, "failed to parse interrupt-affinity[%d]\n", i);
81 return -EINVAL;
82 }
83
84 cpu = of_cpu_node_to_id(dn);
85 if (cpu < 0) {
86 dev_warn(dev, "failed to find logical CPU for %pOFn\n", dn);
87 cpu = nr_cpu_ids;
88 }
89
90 of_node_put(dn);
91
92 return cpu;
93}
94
95static int pmu_parse_irqs(struct arm_pmu *pmu)
96{
97 int i = 0, num_irqs;
98 struct platform_device *pdev = pmu->plat_device;
99 struct pmu_hw_events __percpu *hw_events = pmu->hw_events;
100 struct device *dev = &pdev->dev;
101
102 num_irqs = platform_irq_count(pdev);
103 if (num_irqs < 0)
104 return dev_err_probe(dev, num_irqs, "unable to count PMU IRQs\n");
105
106 /*
107 * In this case we have no idea which CPUs are covered by the PMU.
108 * To match our prior behaviour, we assume all CPUs in this case.
109 */
110 if (num_irqs == 0) {
111 dev_warn(dev, "no irqs for PMU, sampling events not supported\n");
112 pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
113 cpumask_setall(&pmu->supported_cpus);
114 return 0;
115 }
116
117 if (num_irqs == 1) {
118 int irq = platform_get_irq(pdev, 0);
119 if ((irq > 0) && irq_is_percpu_devid(irq))
120 return pmu_parse_percpu_irq(pmu, irq);
121 }
122
123 if (nr_cpu_ids != 1 && !pmu_has_irq_affinity(dev->of_node))
124 dev_warn(dev, "no interrupt-affinity property, guessing.\n");
125
126 for (i = 0; i < num_irqs; i++) {
127 int cpu, irq;
128
129 irq = platform_get_irq(pdev, i);
130 if (WARN_ON(irq <= 0))
131 continue;
132
133 if (irq_is_percpu_devid(irq)) {
134 dev_warn(dev, "multiple PPIs or mismatched SPI/PPI detected\n");
135 return -EINVAL;
136 }
137
138 cpu = pmu_parse_irq_affinity(dev, i);
139 if (cpu < 0)
140 return cpu;
141 if (cpu >= nr_cpu_ids)
142 continue;
143
144 if (per_cpu(hw_events->irq, cpu)) {
145 dev_warn(dev, "multiple PMU IRQs for the same CPU detected\n");
146 return -EINVAL;
147 }
148
149 per_cpu(hw_events->irq, cpu) = irq;
150 cpumask_set_cpu(cpu, &pmu->supported_cpus);
151 }
152
153 return 0;
154}
155
156static int armpmu_request_irqs(struct arm_pmu *armpmu)
157{
158 struct pmu_hw_events __percpu *hw_events = armpmu->hw_events;
159 int cpu, err = 0;
160
161 for_each_cpu(cpu, &armpmu->supported_cpus) {
162 int irq = per_cpu(hw_events->irq, cpu);
163 if (!irq)
164 continue;
165
166 err = armpmu_request_irq(irq, cpu);
167 if (err)
168 break;
169 }
170
171 return err;
172}
173
174static void armpmu_free_irqs(struct arm_pmu *armpmu)
175{
176 int cpu;
177 struct pmu_hw_events __percpu *hw_events = armpmu->hw_events;
178
179 for_each_cpu(cpu, &armpmu->supported_cpus) {
180 int irq = per_cpu(hw_events->irq, cpu);
181
182 armpmu_free_irq(irq, cpu);
183 }
184}
185
186int arm_pmu_device_probe(struct platform_device *pdev,
187 const struct of_device_id *of_table,
188 const struct pmu_probe_info *probe_table)
189{
190 armpmu_init_fn init_fn;
191 struct device *dev = &pdev->dev;
192 struct arm_pmu *pmu;
193 int ret = -ENODEV;
194
195 pmu = armpmu_alloc();
196 if (!pmu)
197 return -ENOMEM;
198
199 pmu->plat_device = pdev;
200
201 ret = pmu_parse_irqs(pmu);
202 if (ret)
203 goto out_free;
204
205 init_fn = of_device_get_match_data(dev);
206 if (init_fn) {
207 pmu->secure_access = of_property_read_bool(dev->of_node,
208 "secure-reg-access");
209
210 /* arm64 systems boot only as non-secure */
211 if (IS_ENABLED(CONFIG_ARM64) && pmu->secure_access) {
212 dev_warn(dev, "ignoring \"secure-reg-access\" property for arm64\n");
213 pmu->secure_access = false;
214 }
215
216 ret = init_fn(pmu);
217 } else if (probe_table) {
218 cpumask_setall(&pmu->supported_cpus);
219 ret = probe_current_pmu(pmu, probe_table);
220 }
221
222 if (ret) {
223 dev_err(dev, "failed to probe PMU!\n");
224 goto out_free;
225 }
226
227 ret = armpmu_request_irqs(pmu);
228 if (ret)
229 goto out_free_irqs;
230
231 ret = armpmu_register(pmu);
232 if (ret) {
233 dev_err(dev, "failed to register PMU devices!\n");
234 goto out_free_irqs;
235 }
236
237 return 0;
238
239out_free_irqs:
240 armpmu_free_irqs(pmu);
241out_free:
242 armpmu_free(pmu);
243 return ret;
244}